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[media] gspca - zc3xx: Set the exposure at start of hv7131r
[deliverable/linux.git] / drivers / media / video / ov9640.c
CommitLineData
8d648271
MV		 1/*
2 * OmniVision OV96xx Camera Driver
3 *
4 * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com>
5 *
6 * Based on ov772x camera driver:
7 *
8 * Copyright (C) 2008 Renesas Solutions Corp.
9 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
10 *
11 * Based on ov7670 and soc_camera_platform driver,
12 *
13 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
14 * Copyright (C) 2008 Magnus Damm
15 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
21
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/i2c.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
95d20109 27#include <linux/v4l2-mediabus.h>
8d648271 28#include <linux/videodev2.h>
de2e388d
GL		 29
30#include <media/soc_camera.h>
8d648271
MV		 31#include <media/v4l2-chip-ident.h>
32#include <media/v4l2-common.h>
839b48df 33#include <media/v4l2-ctrls.h>
8d648271
MV		 34
35#include "ov9640.h"
36
f7b74f76
DC		 37#define to_ov9640_sensor(sd) container_of(sd, struct ov9640_priv, subdev)
38
8d648271
MV		 39/* default register setup */
40static const struct ov9640_reg ov9640_regs_dflt[] = {
41 { OV9640_COM5, OV9640_COM5_SYSCLK | OV9640_COM5_LONGEXP },
42 { OV9640_COM6, OV9640_COM6_OPT_BLC | OV9640_COM6_ADBLC_BIAS |
43 OV9640_COM6_FMT_RST | OV9640_COM6_ADBLC_OPTEN },
44 { OV9640_PSHFT, OV9640_PSHFT_VAL(0x01) },
45 { OV9640_ACOM, OV9640_ACOM_2X_ANALOG | OV9640_ACOM_RSVD },
46 { OV9640_TSLB, OV9640_TSLB_YUYV_UYVY },
47 { OV9640_COM16, OV9640_COM16_RB_AVG },
48
49 /* Gamma curve P */
50 { 0x6c, 0x40 }, { 0x6d, 0x30 }, { 0x6e, 0x4b }, { 0x6f, 0x60 },
51 { 0x70, 0x70 }, { 0x71, 0x70 }, { 0x72, 0x70 }, { 0x73, 0x70 },
52 { 0x74, 0x60 }, { 0x75, 0x60 }, { 0x76, 0x50 }, { 0x77, 0x48 },
53 { 0x78, 0x3a }, { 0x79, 0x2e }, { 0x7a, 0x28 }, { 0x7b, 0x22 },
54
55 /* Gamma curve T */
56 { 0x7c, 0x04 }, { 0x7d, 0x07 }, { 0x7e, 0x10 }, { 0x7f, 0x28 },
57 { 0x80, 0x36 }, { 0x81, 0x44 }, { 0x82, 0x52 }, { 0x83, 0x60 },
58 { 0x84, 0x6c }, { 0x85, 0x78 }, { 0x86, 0x8c }, { 0x87, 0x9e },
59 { 0x88, 0xbb }, { 0x89, 0xd2 }, { 0x8a, 0xe6 },
60};
61
62/* Configurations
63 * NOTE: for YUV, alter the following registers:
64 * COM12 |= OV9640_COM12_YUV_AVG
65 *
66 * for RGB, alter the following registers:
000f64ef
MCC		 67 * COM7 |= OV9640_COM7_RGB
68 * COM13 |= OV9640_COM13_RGB_AVG
69 * COM15 |= proper RGB color encoding mode
8d648271
MV		 70 */
71static const struct ov9640_reg ov9640_regs_qqcif[] = {
72 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x0f) },
73 { OV9640_COM1, OV9640_COM1_QQFMT | OV9640_COM1_HREF_2SKIP },
74 { OV9640_COM4, OV9640_COM4_QQ_VP | OV9640_COM4_RSVD },
75 { OV9640_COM7, OV9640_COM7_QCIF },
76 { OV9640_COM12, OV9640_COM12_RSVD },
77 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
78 { OV9640_COM15, OV9640_COM15_OR_10F0 },
79};
80
81static const struct ov9640_reg ov9640_regs_qqvga[] = {
82 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x07) },
83 { OV9640_COM1, OV9640_COM1_QQFMT | OV9640_COM1_HREF_2SKIP },
84 { OV9640_COM4, OV9640_COM4_QQ_VP | OV9640_COM4_RSVD },
85 { OV9640_COM7, OV9640_COM7_QVGA },
86 { OV9640_COM12, OV9640_COM12_RSVD },
87 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
88 { OV9640_COM15, OV9640_COM15_OR_10F0 },
89};
90
91static const struct ov9640_reg ov9640_regs_qcif[] = {
92 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x07) },
93 { OV9640_COM4, OV9640_COM4_QQ_VP | OV9640_COM4_RSVD },
94 { OV9640_COM7, OV9640_COM7_QCIF },
95 { OV9640_COM12, OV9640_COM12_RSVD },
96 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
97 { OV9640_COM15, OV9640_COM15_OR_10F0 },
98};
99
100static const struct ov9640_reg ov9640_regs_qvga[] = {
101 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x03) },
102 { OV9640_COM4, OV9640_COM4_QQ_VP | OV9640_COM4_RSVD },
103 { OV9640_COM7, OV9640_COM7_QVGA },
104 { OV9640_COM12, OV9640_COM12_RSVD },
105 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
106 { OV9640_COM15, OV9640_COM15_OR_10F0 },
107};
108
109static const struct ov9640_reg ov9640_regs_cif[] = {
110 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x03) },
111 { OV9640_COM3, OV9640_COM3_VP },
112 { OV9640_COM7, OV9640_COM7_CIF },
113 { OV9640_COM12, OV9640_COM12_RSVD },
114 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
115 { OV9640_COM15, OV9640_COM15_OR_10F0 },
116};
117
118static const struct ov9640_reg ov9640_regs_vga[] = {
119 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x01) },
120 { OV9640_COM3, OV9640_COM3_VP },
121 { OV9640_COM7, OV9640_COM7_VGA },
122 { OV9640_COM12, OV9640_COM12_RSVD },
123 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
124 { OV9640_COM15, OV9640_COM15_OR_10F0 },
125};
126
127static const struct ov9640_reg ov9640_regs_sxga[] = {
128 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x01) },
129 { OV9640_COM3, OV9640_COM3_VP },
130 { OV9640_COM7, 0 },
131 { OV9640_COM12, OV9640_COM12_RSVD },
132 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
133 { OV9640_COM15, OV9640_COM15_OR_10F0 },
134};
135
136static const struct ov9640_reg ov9640_regs_yuv[] = {
137 { OV9640_MTX1, 0x58 },
138 { OV9640_MTX2, 0x48 },
139 { OV9640_MTX3, 0x10 },
140 { OV9640_MTX4, 0x28 },
141 { OV9640_MTX5, 0x48 },
142 { OV9640_MTX6, 0x70 },
143 { OV9640_MTX7, 0x40 },
144 { OV9640_MTX8, 0x40 },
145 { OV9640_MTX9, 0x40 },
146 { OV9640_MTXS, 0x0f },
147};
148
149static const struct ov9640_reg ov9640_regs_rgb[] = {
150 { OV9640_MTX1, 0x71 },
151 { OV9640_MTX2, 0x3e },
152 { OV9640_MTX3, 0x0c },
153 { OV9640_MTX4, 0x33 },
154 { OV9640_MTX5, 0x72 },
155 { OV9640_MTX6, 0x00 },
156 { OV9640_MTX7, 0x2b },
157 { OV9640_MTX8, 0x66 },
158 { OV9640_MTX9, 0xd2 },
159 { OV9640_MTXS, 0x65 },
160};
161
760697be 162static enum v4l2_mbus_pixelcode ov9640_codes[] = {
ace6e979 163 V4L2_MBUS_FMT_UYVY8_2X8,
760697be
GL		 164 V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE,
165 V4L2_MBUS_FMT_RGB565_2X8_LE,
8d648271
MV		 166};
167
8d648271
MV		 168/* read a register */
169static int ov9640_reg_read(struct i2c_client *client, u8 reg, u8 *val)
170{
171 int ret;
172 u8 data = reg;
173 struct i2c_msg msg = {
174 .addr = client->addr,
175 .flags = 0,
176 .len = 1,
177 .buf = &data,
178 };
179
180 ret = i2c_transfer(client->adapter, &msg, 1);
181 if (ret < 0)
182 goto err;
183
184 msg.flags = I2C_M_RD;
185 ret = i2c_transfer(client->adapter, &msg, 1);
186 if (ret < 0)
187 goto err;
188
189 *val = data;
190 return 0;
191
192err:
193 dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg);
194 return ret;
195}
196
197/* write a register */
198static int ov9640_reg_write(struct i2c_client *client, u8 reg, u8 val)
199{
200 int ret;
201 u8 _val;
202 unsigned char data[2] = { reg, val };
203 struct i2c_msg msg = {
204 .addr = client->addr,
205 .flags = 0,
206 .len = 2,
207 .buf = data,
208 };
209
210 ret = i2c_transfer(client->adapter, &msg, 1);
211 if (ret < 0) {
212 dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg);
213 return ret;
214 }
215
216 /* we have to read the register back ... no idea why, maybe HW bug */
217 ret = ov9640_reg_read(client, reg, &_val);
218 if (ret)
219 dev_err(&client->dev,
220 "Failed reading back register 0x%02x!\n", reg);
221
222 return 0;
223}
224
225
226/* Read a register, alter its bits, write it back */
227static int ov9640_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 unset)
228{
229 u8 val;
230 int ret;
231
232 ret = ov9640_reg_read(client, reg, &val);
233 if (ret) {
234 dev_err(&client->dev,
235 "[Read]-Modify-Write of register %02x failed!\n", reg);
236 return val;
237 }
238
239 val |= set;
240 val &= ~unset;
241
242 ret = ov9640_reg_write(client, reg, val);
243 if (ret)
244 dev_err(&client->dev,
245 "Read-Modify-[Write] of register %02x failed!\n", reg);
246
247 return ret;
248}
249
250/* Soft reset the camera. This has nothing to do with the RESET pin! */
251static int ov9640_reset(struct i2c_client *client)
252{
253 int ret;
254
255 ret = ov9640_reg_write(client, OV9640_COM7, OV9640_COM7_SCCB_RESET);
256 if (ret)
257 dev_err(&client->dev,
25985edc 258 "An error occurred while entering soft reset!\n");
8d648271
MV		 259
260 return ret;
261}
262
263/* Start/Stop streaming from the device */
264static int ov9640_s_stream(struct v4l2_subdev *sd, int enable)
265{
266 return 0;
267}
268
8d648271 269/* Set status of additional camera capabilities */
839b48df 270static int ov9640_s_ctrl(struct v4l2_ctrl *ctrl)
8d648271 271{
839b48df
HV		 272 struct ov9640_priv *priv = container_of(ctrl->handler, struct ov9640_priv, hdl);
273 struct i2c_client *client = v4l2_get_subdevdata(&priv->subdev);
8d648271
MV		 274
275 switch (ctrl->id) {
276 case V4L2_CID_VFLIP:
839b48df
HV		 277 if (ctrl->val)
278 return ov9640_reg_rmw(client, OV9640_MVFP,
8d648271 279 OV9640_MVFP_V, 0);
839b48df 280 return ov9640_reg_rmw(client, OV9640_MVFP, 0, OV9640_MVFP_V);
8d648271 281 case V4L2_CID_HFLIP:
839b48df
HV		 282 if (ctrl->val)
283 return ov9640_reg_rmw(client, OV9640_MVFP,
8d648271 284 OV9640_MVFP_H, 0);
839b48df 285 return ov9640_reg_rmw(client, OV9640_MVFP, 0, OV9640_MVFP_H);
8d648271 286 }
839b48df 287 return -EINVAL;
8d648271
MV		 288}
289
290/* Get chip identification */
291static int ov9640_g_chip_ident(struct v4l2_subdev *sd,
292 struct v4l2_dbg_chip_ident *id)
293{
f7b74f76 294 struct ov9640_priv *priv = to_ov9640_sensor(sd);
8d648271
MV		 295
296 id->ident = priv->model;
297 id->revision = priv->revision;
298
299 return 0;
300}
301
302#ifdef CONFIG_VIDEO_ADV_DEBUG
303static int ov9640_get_register(struct v4l2_subdev *sd,
304 struct v4l2_dbg_register *reg)
305{
c4ce6d14 306 struct i2c_client *client = v4l2_get_subdevdata(sd);
8d648271
MV		 307 int ret;
308 u8 val;
309
310 if (reg->reg & ~0xff)
311 return -EINVAL;
312
313 reg->size = 1;
314
315 ret = ov9640_reg_read(client, reg->reg, &val);
316 if (ret)
317 return ret;
318
319 reg->val = (__u64)val;
320
321 return 0;
322}
323
324static int ov9640_set_register(struct v4l2_subdev *sd,
325 struct v4l2_dbg_register *reg)
326{
c4ce6d14 327 struct i2c_client *client = v4l2_get_subdevdata(sd);
8d648271
MV		 328
329 if (reg->reg & ~0xff || reg->val & ~0xff)
330 return -EINVAL;
331
332 return ov9640_reg_write(client, reg->reg, reg->val);
333}
334#endif
335
336/* select nearest higher resolution for capture */
337static void ov9640_res_roundup(u32 *width, u32 *height)
338{
339 int i;
340 enum { QQCIF, QQVGA, QCIF, QVGA, CIF, VGA, SXGA };
341 int res_x[] = { 88, 160, 176, 320, 352, 640, 1280 };
342 int res_y[] = { 72, 120, 144, 240, 288, 480, 960 };
343
344 for (i = 0; i < ARRAY_SIZE(res_x); i++) {
345 if (res_x[i] >= *width && res_y[i] >= *height) {
346 *width = res_x[i];
347 *height = res_y[i];
348 return;
349 }
350 }
351
352 *width = res_x[SXGA];
353 *height = res_y[SXGA];
354}
355
356/* Prepare necessary register changes depending on color encoding */
760697be
GL		 357static void ov9640_alter_regs(enum v4l2_mbus_pixelcode code,
358 struct ov9640_reg_alt *alt)
8d648271 359{
760697be
GL		 360 switch (code) {
361 default:
ace6e979 362 case V4L2_MBUS_FMT_UYVY8_2X8:
8d648271
MV		 363 alt->com12 = OV9640_COM12_YUV_AVG;
364 alt->com13 = OV9640_COM13_Y_DELAY_EN |
365 OV9640_COM13_YUV_DLY(0x01);
366 break;
760697be 367 case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE:
8d648271
MV		 368 alt->com7 = OV9640_COM7_RGB;
369 alt->com13 = OV9640_COM13_RGB_AVG;
370 alt->com15 = OV9640_COM15_RGB_555;
371 break;
760697be 372 case V4L2_MBUS_FMT_RGB565_2X8_LE:
8d648271
MV		 373 alt->com7 = OV9640_COM7_RGB;
374 alt->com13 = OV9640_COM13_RGB_AVG;
375 alt->com15 = OV9640_COM15_RGB_565;
376 break;
377 };
378}
379
380/* Setup registers according to resolution and color encoding */
760697be
GL		 381static int ov9640_write_regs(struct i2c_client *client, u32 width,
382 enum v4l2_mbus_pixelcode code, struct ov9640_reg_alt *alts)
8d648271
MV		 383{
384 const struct ov9640_reg *ov9640_regs, *matrix_regs;
385 int ov9640_regs_len, matrix_regs_len;
386 int i, ret;
387 u8 val;
388
389 /* select register configuration for given resolution */
390 switch (width) {
391 case W_QQCIF:
392 ov9640_regs = ov9640_regs_qqcif;
393 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qqcif);
394 break;
395 case W_QQVGA:
396 ov9640_regs = ov9640_regs_qqvga;
397 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qqvga);
398 break;
399 case W_QCIF:
400 ov9640_regs = ov9640_regs_qcif;
401 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qcif);
402 break;
403 case W_QVGA:
404 ov9640_regs = ov9640_regs_qvga;
405 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qvga);
406 break;
407 case W_CIF:
408 ov9640_regs = ov9640_regs_cif;
409 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_cif);
410 break;
411 case W_VGA:
412 ov9640_regs = ov9640_regs_vga;
413 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_vga);
414 break;
415 case W_SXGA:
416 ov9640_regs = ov9640_regs_sxga;
417 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_sxga);
418 break;
419 default:
420 dev_err(&client->dev, "Failed to select resolution!\n");
421 return -EINVAL;
422 }
423
424 /* select color matrix configuration for given color encoding */
ace6e979 425 if (code == V4L2_MBUS_FMT_UYVY8_2X8) {
8d648271
MV		 426 matrix_regs = ov9640_regs_yuv;
427 matrix_regs_len = ARRAY_SIZE(ov9640_regs_yuv);
428 } else {
429 matrix_regs = ov9640_regs_rgb;
430 matrix_regs_len = ARRAY_SIZE(ov9640_regs_rgb);
431 }
432
433 /* write register settings into the module */
434 for (i = 0; i < ov9640_regs_len; i++) {
435 val = ov9640_regs[i].val;
436
437 switch (ov9640_regs[i].reg) {
438 case OV9640_COM7:
439 val |= alts->com7;
440 break;
441 case OV9640_COM12:
442 val |= alts->com12;
443 break;
444 case OV9640_COM13:
445 val |= alts->com13;
446 break;
447 case OV9640_COM15:
448 val |= alts->com15;
449 break;
450 }
451
452 ret = ov9640_reg_write(client, ov9640_regs[i].reg, val);
453 if (ret)
454 return ret;
455 }
456
457 /* write color matrix configuration into the module */
458 for (i = 0; i < matrix_regs_len; i++) {
459 ret = ov9640_reg_write(client, matrix_regs[i].reg,
460 matrix_regs[i].val);
461 if (ret)
462 return ret;
463 }
464
465 return 0;
466}
467
468/* program default register values */
469static int ov9640_prog_dflt(struct i2c_client *client)
470{
471 int i, ret;
472
473 for (i = 0; i < ARRAY_SIZE(ov9640_regs_dflt); i++) {
474 ret = ov9640_reg_write(client, ov9640_regs_dflt[i].reg,
475 ov9640_regs_dflt[i].val);
476 if (ret)
477 return ret;
478 }
479
480 /* wait for the changes to actually happen, 140ms are not enough yet */
481 mdelay(150);
482
483 return 0;
484}
485
486/* set the format we will capture in */
760697be
GL		 487static int ov9640_s_fmt(struct v4l2_subdev *sd,
488 struct v4l2_mbus_framefmt *mf)
8d648271 489{
c4ce6d14 490 struct i2c_client *client = v4l2_get_subdevdata(sd);
8d648271 491 struct ov9640_reg_alt alts = {0};
760697be
GL		 492 enum v4l2_colorspace cspace;
493 enum v4l2_mbus_pixelcode code = mf->code;
8d648271
MV		 494 int ret;
495
760697be
GL		 496 ov9640_res_roundup(&mf->width, &mf->height);
497 ov9640_alter_regs(mf->code, &alts);
8d648271
MV		 498
499 ov9640_reset(client);
500
501 ret = ov9640_prog_dflt(client);
502 if (ret)
503 return ret;
504
760697be
GL		 505 switch (code) {
506 case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE:
507 case V4L2_MBUS_FMT_RGB565_2X8_LE:
508 cspace = V4L2_COLORSPACE_SRGB;
509 break;
510 default:
ace6e979
GL		 511 code = V4L2_MBUS_FMT_UYVY8_2X8;
512 case V4L2_MBUS_FMT_UYVY8_2X8:
760697be
GL		 513 cspace = V4L2_COLORSPACE_JPEG;
514 }
515
516 ret = ov9640_write_regs(client, mf->width, code, &alts);
517 if (!ret) {
518 mf->code = code;
519 mf->colorspace = cspace;
520 }
521
522 return ret;
8d648271
MV		 523}
524
760697be
GL		 525static int ov9640_try_fmt(struct v4l2_subdev *sd,
526 struct v4l2_mbus_framefmt *mf)
8d648271 527{
760697be 528 ov9640_res_roundup(&mf->width, &mf->height);
8d648271 529
760697be
GL		 530 mf->field = V4L2_FIELD_NONE;
531
532 switch (mf->code) {
533 case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE:
534 case V4L2_MBUS_FMT_RGB565_2X8_LE:
535 mf->colorspace = V4L2_COLORSPACE_SRGB;
536 break;
537 default:
ace6e979
GL		 538 mf->code = V4L2_MBUS_FMT_UYVY8_2X8;
539 case V4L2_MBUS_FMT_UYVY8_2X8:
760697be
GL		 540 mf->colorspace = V4L2_COLORSPACE_JPEG;
541 }
8d648271
MV		 542
543 return 0;
544}
545
3805f201 546static int ov9640_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
760697be
GL		 547 enum v4l2_mbus_pixelcode *code)
548{
3805f201 549 if (index >= ARRAY_SIZE(ov9640_codes))
760697be
GL		 550 return -EINVAL;
551
552 *code = ov9640_codes[index];
553 return 0;
554}
555
8d648271
MV		 556static int ov9640_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
557{
558 a->c.left = 0;
559 a->c.top = 0;
560 a->c.width = W_SXGA;
561 a->c.height = H_SXGA;
562 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
563
564 return 0;
565}
566
567static int ov9640_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
568{
569 a->bounds.left = 0;
570 a->bounds.top = 0;
571 a->bounds.width = W_SXGA;
572 a->bounds.height = H_SXGA;
573 a->defrect = a->bounds;
574 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
575 a->pixelaspect.numerator = 1;
576 a->pixelaspect.denominator = 1;
577
578 return 0;
579}
580
14178aa5 581static int ov9640_video_probe(struct i2c_client *client)
8d648271 582{
63c9718c
DC		 583 struct v4l2_subdev *sd = i2c_get_clientdata(client);
584 struct ov9640_priv *priv = to_ov9640_sensor(sd);
8d648271
MV		 585 u8 pid, ver, midh, midl;
586 const char *devname;
587 int ret = 0;
588
8d648271
MV		 589 /*
590 * check and show product ID and manufacturer ID
591 */
592
593 ret = ov9640_reg_read(client, OV9640_PID, &pid);
839b48df
HV		 594 if (!ret)
595 ret = ov9640_reg_read(client, OV9640_VER, &ver);
596 if (!ret)
597 ret = ov9640_reg_read(client, OV9640_MIDH, &midh);
598 if (!ret)
599 ret = ov9640_reg_read(client, OV9640_MIDL, &midl);
8d648271 600 if (ret)
839b48df 601 return ret;
8d648271
MV		 602
603 switch (VERSION(pid, ver)) {
604 case OV9640_V2:
605 devname = "ov9640";
606 priv->model = V4L2_IDENT_OV9640;
607 priv->revision = 2;
608 case OV9640_V3:
609 devname = "ov9640";
610 priv->model = V4L2_IDENT_OV9640;
611 priv->revision = 3;
612 break;
613 default:
614 dev_err(&client->dev, "Product ID error %x:%x\n", pid, ver);
839b48df 615 return -ENODEV;
8d648271
MV		 616 }
617
618 dev_info(&client->dev, "%s Product ID %0x:%0x Manufacturer ID %x:%x\n",
619 devname, pid, ver, midh, midl);
620
839b48df 621 return v4l2_ctrl_handler_setup(&priv->hdl);
8d648271
MV		 622}
623
839b48df
HV		 624static const struct v4l2_ctrl_ops ov9640_ctrl_ops = {
625 .s_ctrl = ov9640_s_ctrl,
8d648271
MV		 626};
627
628static struct v4l2_subdev_core_ops ov9640_core_ops = {
8d648271
MV		 629 .g_chip_ident = ov9640_g_chip_ident,
630#ifdef CONFIG_VIDEO_ADV_DEBUG
631 .g_register = ov9640_get_register,
632 .s_register = ov9640_set_register,
633#endif
634
635};
636
88e816a2 637/* Request bus settings on camera side */
de2e388d
GL		 638static int ov9640_g_mbus_config(struct v4l2_subdev *sd,
639 struct v4l2_mbus_config *cfg)
640{
641 struct i2c_client *client = v4l2_get_subdevdata(sd);
14178aa5 642 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
de2e388d
GL		 643
644 cfg->flags = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER |
645 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH |
646 V4L2_MBUS_DATA_ACTIVE_HIGH;
647 cfg->type = V4L2_MBUS_PARALLEL;
648 cfg->flags = soc_camera_apply_board_flags(icl, cfg);
649
650 return 0;
651}
652
8d648271 653static struct v4l2_subdev_video_ops ov9640_video_ops = {
760697be
GL		 654 .s_stream = ov9640_s_stream,
655 .s_mbus_fmt = ov9640_s_fmt,
656 .try_mbus_fmt = ov9640_try_fmt,
657 .enum_mbus_fmt = ov9640_enum_fmt,
658 .cropcap = ov9640_cropcap,
659 .g_crop = ov9640_g_crop,
de2e388d 660 .g_mbus_config = ov9640_g_mbus_config,
8d648271
MV		 661};
662
663static struct v4l2_subdev_ops ov9640_subdev_ops = {
664 .core = &ov9640_core_ops,
665 .video = &ov9640_video_ops,
666};
667
668/*
669 * i2c_driver function
670 */
671static int ov9640_probe(struct i2c_client *client,
672 const struct i2c_device_id *did)
673{
674 struct ov9640_priv *priv;
14178aa5 675 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
8d648271
MV		 676 int ret;
677
8d648271
MV		 678 if (!icl) {
679 dev_err(&client->dev, "Missing platform_data for driver\n");
680 return -EINVAL;
681 }
682
683 priv = kzalloc(sizeof(struct ov9640_priv), GFP_KERNEL);
684 if (!priv) {
685 dev_err(&client->dev,
686 "Failed to allocate memory for private data!\n");
687 return -ENOMEM;
688 }
689
690 v4l2_i2c_subdev_init(&priv->subdev, client, &ov9640_subdev_ops);
691
839b48df
HV		 692 v4l2_ctrl_handler_init(&priv->hdl, 2);
693 v4l2_ctrl_new_std(&priv->hdl, &ov9640_ctrl_ops,
694 V4L2_CID_VFLIP, 0, 1, 1, 0);
695 v4l2_ctrl_new_std(&priv->hdl, &ov9640_ctrl_ops,
696 V4L2_CID_HFLIP, 0, 1, 1, 0);
697 priv->subdev.ctrl_handler = &priv->hdl;
698 if (priv->hdl.error) {
699 int err = priv->hdl.error;
700
701 kfree(priv);
702 return err;
703 }
8d648271 704
14178aa5 705 ret = ov9640_video_probe(client);
8d648271
MV		 706
707 if (ret) {
839b48df 708 v4l2_ctrl_handler_free(&priv->hdl);
8d648271
MV		 709 kfree(priv);
710 }
711
712 return ret;
713}
714
715static int ov9640_remove(struct i2c_client *client)
716{
63c9718c
DC		 717 struct v4l2_subdev *sd = i2c_get_clientdata(client);
718 struct ov9640_priv *priv = to_ov9640_sensor(sd);
8d648271 719
839b48df
HV		 720 v4l2_device_unregister_subdev(&priv->subdev);
721 v4l2_ctrl_handler_free(&priv->hdl);
8d648271
MV		 722 kfree(priv);
723 return 0;
724}
725
726static const struct i2c_device_id ov9640_id[] = {
727 { "ov9640", 0 },
728 { }
729};
730MODULE_DEVICE_TABLE(i2c, ov9640_id);
731
732static struct i2c_driver ov9640_i2c_driver = {
733 .driver = {
734 .name = "ov9640",
735 },
736 .probe = ov9640_probe,
737 .remove = ov9640_remove,
738 .id_table = ov9640_id,
739};
740
741static int __init ov9640_module_init(void)
742{
743 return i2c_add_driver(&ov9640_i2c_driver);
744}
745
746static void __exit ov9640_module_exit(void)
747{
748 i2c_del_driver(&ov9640_i2c_driver);
749}
750
751module_init(ov9640_module_init);
752module_exit(ov9640_module_exit);
753
754MODULE_DESCRIPTION("SoC Camera driver for OmniVision OV96xx");
755MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");
756MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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