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3bc43840 GL |
1 | /* |
2 | * V4L2 Driver for PXA camera host | |
3 | * | |
4 | * Copyright (C) 2006, Sascha Hauer, Pengutronix | |
5 | * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
3bc43840 GL |
13 | #include <linux/init.h> |
14 | #include <linux/module.h> | |
7102b773 | 15 | #include <linux/io.h> |
3bc43840 GL |
16 | #include <linux/delay.h> |
17 | #include <linux/dma-mapping.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/fs.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/mm.h> | |
23 | #include <linux/moduleparam.h> | |
24 | #include <linux/time.h> | |
25 | #include <linux/version.h> | |
26 | #include <linux/device.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/mutex.h> | |
29 | #include <linux/clk.h> | |
30 | ||
31 | #include <media/v4l2-common.h> | |
32 | #include <media/v4l2-dev.h> | |
092d3921 | 33 | #include <media/videobuf-dma-sg.h> |
3bc43840 GL |
34 | #include <media/soc_camera.h> |
35 | ||
36 | #include <linux/videodev2.h> | |
37 | ||
38 | #include <asm/dma.h> | |
a09e64fb RK |
39 | #include <mach/pxa-regs.h> |
40 | #include <mach/camera.h> | |
3bc43840 GL |
41 | |
42 | #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5) | |
43 | #define PXA_CAM_DRV_NAME "pxa27x-camera" | |
44 | ||
5ca11fa3 EM |
45 | /* Camera Interface */ |
46 | #define CICR0 0x0000 | |
47 | #define CICR1 0x0004 | |
48 | #define CICR2 0x0008 | |
49 | #define CICR3 0x000C | |
50 | #define CICR4 0x0010 | |
51 | #define CISR 0x0014 | |
52 | #define CIFR 0x0018 | |
53 | #define CITOR 0x001C | |
54 | #define CIBR0 0x0028 | |
55 | #define CIBR1 0x0030 | |
56 | #define CIBR2 0x0038 | |
57 | ||
58 | #define CICR0_DMAEN (1 << 31) /* DMA request enable */ | |
59 | #define CICR0_PAR_EN (1 << 30) /* Parity enable */ | |
60 | #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */ | |
61 | #define CICR0_ENB (1 << 28) /* Camera interface enable */ | |
62 | #define CICR0_DIS (1 << 27) /* Camera interface disable */ | |
63 | #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */ | |
64 | #define CICR0_TOM (1 << 9) /* Time-out mask */ | |
65 | #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */ | |
66 | #define CICR0_FEM (1 << 7) /* FIFO-empty mask */ | |
67 | #define CICR0_EOLM (1 << 6) /* End-of-line mask */ | |
68 | #define CICR0_PERRM (1 << 5) /* Parity-error mask */ | |
69 | #define CICR0_QDM (1 << 4) /* Quick-disable mask */ | |
70 | #define CICR0_CDM (1 << 3) /* Disable-done mask */ | |
71 | #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */ | |
72 | #define CICR0_EOFM (1 << 1) /* End-of-frame mask */ | |
73 | #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */ | |
74 | ||
75 | #define CICR1_TBIT (1 << 31) /* Transparency bit */ | |
76 | #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */ | |
77 | #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */ | |
78 | #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */ | |
79 | #define CICR1_RGB_F (1 << 11) /* RGB format */ | |
80 | #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */ | |
81 | #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */ | |
82 | #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */ | |
83 | #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */ | |
84 | #define CICR1_DW (0x7 << 0) /* Data width mask */ | |
85 | ||
86 | #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock | |
87 | wait count mask */ | |
88 | #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock | |
89 | wait count mask */ | |
90 | #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */ | |
91 | #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock | |
92 | wait count mask */ | |
93 | #define CICR2_FSW (0x7 << 0) /* Frame stabilization | |
94 | wait count mask */ | |
95 | ||
96 | #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock | |
97 | wait count mask */ | |
98 | #define CICR3_EFW (0xff << 16) /* End-of-frame line clock | |
99 | wait count mask */ | |
100 | #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */ | |
101 | #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock | |
102 | wait count mask */ | |
103 | #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */ | |
104 | ||
105 | #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */ | |
106 | #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */ | |
107 | #define CICR4_PCP (1 << 22) /* Pixel clock polarity */ | |
108 | #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */ | |
109 | #define CICR4_VSP (1 << 20) /* Vertical sync polarity */ | |
110 | #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */ | |
111 | #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */ | |
112 | #define CICR4_DIV (0xff << 0) /* Clock divisor mask */ | |
113 | ||
114 | #define CISR_FTO (1 << 15) /* FIFO time-out */ | |
115 | #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */ | |
116 | #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */ | |
117 | #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */ | |
118 | #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */ | |
119 | #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */ | |
120 | #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */ | |
121 | #define CISR_EOL (1 << 8) /* End of line */ | |
122 | #define CISR_PAR_ERR (1 << 7) /* Parity error */ | |
123 | #define CISR_CQD (1 << 6) /* Camera interface quick disable */ | |
124 | #define CISR_CDD (1 << 5) /* Camera interface disable done */ | |
125 | #define CISR_SOF (1 << 4) /* Start of frame */ | |
126 | #define CISR_EOF (1 << 3) /* End of frame */ | |
127 | #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */ | |
128 | #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */ | |
129 | #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */ | |
130 | ||
131 | #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */ | |
132 | #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */ | |
133 | #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */ | |
134 | #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */ | |
135 | #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */ | |
136 | #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */ | |
137 | #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */ | |
138 | #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */ | |
139 | ||
7102b773 GL |
140 | #define CICR0_SIM_MP (0 << 24) |
141 | #define CICR0_SIM_SP (1 << 24) | |
142 | #define CICR0_SIM_MS (2 << 24) | |
143 | #define CICR0_SIM_EP (3 << 24) | |
144 | #define CICR0_SIM_ES (4 << 24) | |
145 | ||
146 | #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */ | |
147 | #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */ | |
a5462e5b MR |
148 | #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */ |
149 | #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */ | |
150 | #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */ | |
7102b773 GL |
151 | |
152 | #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */ | |
153 | #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */ | |
154 | #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */ | |
155 | #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */ | |
156 | #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */ | |
157 | ||
158 | #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */ | |
159 | #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */ | |
160 | #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */ | |
161 | #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */ | |
162 | ||
3bc43840 GL |
163 | #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \ |
164 | CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \ | |
165 | CICR0_EOFM | CICR0_FOM) | |
166 | ||
167 | static DEFINE_MUTEX(camera_lock); | |
168 | ||
169 | /* | |
170 | * Structures | |
171 | */ | |
a5462e5b MR |
172 | enum pxa_camera_active_dma { |
173 | DMA_Y = 0x1, | |
174 | DMA_U = 0x2, | |
175 | DMA_V = 0x4, | |
176 | }; | |
177 | ||
178 | /* descriptor needed for the PXA DMA engine */ | |
179 | struct pxa_cam_dma { | |
180 | dma_addr_t sg_dma; | |
181 | struct pxa_dma_desc *sg_cpu; | |
182 | size_t sg_size; | |
183 | int sglen; | |
184 | }; | |
3bc43840 GL |
185 | |
186 | /* buffer for one video frame */ | |
187 | struct pxa_buffer { | |
188 | /* common v4l buffer stuff -- must be first */ | |
189 | struct videobuf_buffer vb; | |
190 | ||
191 | const struct soc_camera_data_format *fmt; | |
192 | ||
a5462e5b MR |
193 | /* our descriptor lists for Y, U and V channels */ |
194 | struct pxa_cam_dma dmas[3]; | |
195 | ||
3bc43840 | 196 | int inwork; |
a5462e5b MR |
197 | |
198 | enum pxa_camera_active_dma active_dma; | |
3bc43840 GL |
199 | }; |
200 | ||
3bc43840 GL |
201 | struct pxa_camera_dev { |
202 | struct device *dev; | |
203 | /* PXA27x is only supposed to handle one camera on its Quick Capture | |
204 | * interface. If anyone ever builds hardware to enable more than | |
205 | * one camera, they will have to modify this driver too */ | |
206 | struct soc_camera_device *icd; | |
207 | struct clk *clk; | |
208 | ||
209 | unsigned int irq; | |
210 | void __iomem *base; | |
a5462e5b | 211 | |
e7c50688 | 212 | int channels; |
a5462e5b | 213 | unsigned int dma_chans[3]; |
3bc43840 | 214 | |
3bc43840 GL |
215 | struct pxacamera_platform_data *pdata; |
216 | struct resource *res; | |
217 | unsigned long platform_flags; | |
cf34cba7 GL |
218 | unsigned long ciclk; |
219 | unsigned long mclk; | |
220 | u32 mclk_divisor; | |
3bc43840 GL |
221 | |
222 | struct list_head capture; | |
223 | ||
224 | spinlock_t lock; | |
225 | ||
3bc43840 | 226 | struct pxa_buffer *active; |
5aa2110f | 227 | struct pxa_dma_desc *sg_tail[3]; |
3f6ac497 RJ |
228 | |
229 | u32 save_cicr[5]; | |
3bc43840 GL |
230 | }; |
231 | ||
232 | static const char *pxa_cam_driver_description = "PXA_Camera"; | |
233 | ||
234 | static unsigned int vid_limit = 16; /* Video memory limit, in Mb */ | |
235 | ||
236 | /* | |
237 | * Videobuf operations | |
238 | */ | |
7102b773 GL |
239 | static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count, |
240 | unsigned int *size) | |
3bc43840 GL |
241 | { |
242 | struct soc_camera_device *icd = vq->priv_data; | |
64f5905e | 243 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
5aa2110f | 244 | struct pxa_camera_dev *pcdev = ici->priv; |
3bc43840 GL |
245 | |
246 | dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size); | |
247 | ||
a5462e5b | 248 | /* planar capture requires Y, U and V buffers to be page aligned */ |
5aa2110f | 249 | if (pcdev->channels == 3) { |
a5462e5b MR |
250 | *size = PAGE_ALIGN(icd->width * icd->height); /* Y pages */ |
251 | *size += PAGE_ALIGN(icd->width * icd->height / 2); /* U pages */ | |
252 | *size += PAGE_ALIGN(icd->width * icd->height / 2); /* V pages */ | |
253 | } else { | |
254 | *size = icd->width * icd->height * | |
255 | ((icd->current_fmt->depth + 7) >> 3); | |
256 | } | |
3bc43840 GL |
257 | |
258 | if (0 == *count) | |
259 | *count = 32; | |
260 | while (*size * *count > vid_limit * 1024 * 1024) | |
261 | (*count)--; | |
262 | ||
263 | return 0; | |
264 | } | |
265 | ||
266 | static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf) | |
267 | { | |
268 | struct soc_camera_device *icd = vq->priv_data; | |
64f5905e | 269 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
3bc43840 GL |
270 | struct pxa_camera_dev *pcdev = ici->priv; |
271 | struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb); | |
a5462e5b | 272 | int i; |
3bc43840 GL |
273 | |
274 | BUG_ON(in_interrupt()); | |
275 | ||
7e28adb2 | 276 | dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
277 | &buf->vb, buf->vb.baddr, buf->vb.bsize); |
278 | ||
279 | /* This waits until this buffer is out of danger, i.e., until it is no | |
280 | * longer in STATE_QUEUED or STATE_ACTIVE */ | |
281 | videobuf_waiton(&buf->vb, 0, 0); | |
282 | videobuf_dma_unmap(vq, dma); | |
283 | videobuf_dma_free(dma); | |
284 | ||
a5462e5b MR |
285 | for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) { |
286 | if (buf->dmas[i].sg_cpu) | |
287 | dma_free_coherent(pcdev->dev, buf->dmas[i].sg_size, | |
288 | buf->dmas[i].sg_cpu, | |
289 | buf->dmas[i].sg_dma); | |
290 | buf->dmas[i].sg_cpu = NULL; | |
291 | } | |
3bc43840 GL |
292 | |
293 | buf->vb.state = VIDEOBUF_NEEDS_INIT; | |
294 | } | |
295 | ||
a5462e5b MR |
296 | static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev, |
297 | struct pxa_buffer *buf, | |
298 | struct videobuf_dmabuf *dma, int channel, | |
299 | int sglen, int sg_start, int cibr, | |
300 | unsigned int size) | |
301 | { | |
302 | struct pxa_cam_dma *pxa_dma = &buf->dmas[channel]; | |
303 | int i; | |
304 | ||
305 | if (pxa_dma->sg_cpu) | |
306 | dma_free_coherent(pcdev->dev, pxa_dma->sg_size, | |
307 | pxa_dma->sg_cpu, pxa_dma->sg_dma); | |
308 | ||
309 | pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc); | |
310 | pxa_dma->sg_cpu = dma_alloc_coherent(pcdev->dev, pxa_dma->sg_size, | |
311 | &pxa_dma->sg_dma, GFP_KERNEL); | |
312 | if (!pxa_dma->sg_cpu) | |
313 | return -ENOMEM; | |
314 | ||
315 | pxa_dma->sglen = sglen; | |
316 | ||
317 | for (i = 0; i < sglen; i++) { | |
318 | int sg_i = sg_start + i; | |
319 | struct scatterlist *sg = dma->sglist; | |
320 | unsigned int dma_len = sg_dma_len(&sg[sg_i]), xfer_len; | |
321 | ||
322 | pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr; | |
323 | pxa_dma->sg_cpu[i].dtadr = sg_dma_address(&sg[sg_i]); | |
324 | ||
325 | /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */ | |
326 | xfer_len = (min(dma_len, size) + 7) & ~7; | |
327 | ||
328 | pxa_dma->sg_cpu[i].dcmd = | |
329 | DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len; | |
330 | size -= dma_len; | |
331 | pxa_dma->sg_cpu[i].ddadr = | |
332 | pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc); | |
333 | } | |
334 | ||
335 | pxa_dma->sg_cpu[sglen - 1].ddadr = DDADR_STOP; | |
336 | pxa_dma->sg_cpu[sglen - 1].dcmd |= DCMD_ENDIRQEN; | |
337 | ||
338 | return 0; | |
339 | } | |
340 | ||
7102b773 GL |
341 | static int pxa_videobuf_prepare(struct videobuf_queue *vq, |
342 | struct videobuf_buffer *vb, enum v4l2_field field) | |
3bc43840 GL |
343 | { |
344 | struct soc_camera_device *icd = vq->priv_data; | |
64f5905e | 345 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
3bc43840 GL |
346 | struct pxa_camera_dev *pcdev = ici->priv; |
347 | struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); | |
a5462e5b MR |
348 | int ret; |
349 | int sglen_y, sglen_yu = 0, sglen_u = 0, sglen_v = 0; | |
350 | int size_y, size_u = 0, size_v = 0; | |
3bc43840 | 351 | |
7e28adb2 | 352 | dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
353 | vb, vb->baddr, vb->bsize); |
354 | ||
355 | /* Added list head initialization on alloc */ | |
356 | WARN_ON(!list_empty(&vb->queue)); | |
357 | ||
358 | #ifdef DEBUG | |
359 | /* This can be useful if you want to see if we actually fill | |
360 | * the buffer with something */ | |
361 | memset((void *)vb->baddr, 0xaa, vb->bsize); | |
362 | #endif | |
363 | ||
364 | BUG_ON(NULL == icd->current_fmt); | |
365 | ||
366 | /* I think, in buf_prepare you only have to protect global data, | |
367 | * the actual buffer is yours */ | |
368 | buf->inwork = 1; | |
369 | ||
370 | if (buf->fmt != icd->current_fmt || | |
371 | vb->width != icd->width || | |
372 | vb->height != icd->height || | |
373 | vb->field != field) { | |
374 | buf->fmt = icd->current_fmt; | |
375 | vb->width = icd->width; | |
376 | vb->height = icd->height; | |
377 | vb->field = field; | |
378 | vb->state = VIDEOBUF_NEEDS_INIT; | |
379 | } | |
380 | ||
381 | vb->size = vb->width * vb->height * ((buf->fmt->depth + 7) >> 3); | |
382 | if (0 != vb->baddr && vb->bsize < vb->size) { | |
383 | ret = -EINVAL; | |
384 | goto out; | |
385 | } | |
386 | ||
387 | if (vb->state == VIDEOBUF_NEEDS_INIT) { | |
388 | unsigned int size = vb->size; | |
389 | struct videobuf_dmabuf *dma = videobuf_to_dma(vb); | |
390 | ||
391 | ret = videobuf_iolock(vq, vb, NULL); | |
392 | if (ret) | |
393 | goto fail; | |
394 | ||
5aa2110f | 395 | if (pcdev->channels == 3) { |
a5462e5b MR |
396 | /* FIXME the calculations should be more precise */ |
397 | sglen_y = dma->sglen / 2; | |
398 | sglen_u = sglen_v = dma->sglen / 4 + 1; | |
399 | sglen_yu = sglen_y + sglen_u; | |
400 | size_y = size / 2; | |
401 | size_u = size_v = size / 4; | |
402 | } else { | |
403 | sglen_y = dma->sglen; | |
404 | size_y = size; | |
405 | } | |
406 | ||
407 | /* init DMA for Y channel */ | |
408 | ret = pxa_init_dma_channel(pcdev, buf, dma, 0, sglen_y, | |
409 | 0, 0x28, size_y); | |
3bc43840 | 410 | |
a5462e5b MR |
411 | if (ret) { |
412 | dev_err(pcdev->dev, | |
413 | "DMA initialization for Y/RGB failed\n"); | |
3bc43840 GL |
414 | goto fail; |
415 | } | |
416 | ||
5aa2110f | 417 | if (pcdev->channels == 3) { |
a5462e5b MR |
418 | /* init DMA for U channel */ |
419 | ret = pxa_init_dma_channel(pcdev, buf, dma, 1, sglen_u, | |
420 | sglen_y, 0x30, size_u); | |
421 | if (ret) { | |
422 | dev_err(pcdev->dev, | |
423 | "DMA initialization for U failed\n"); | |
424 | goto fail_u; | |
425 | } | |
426 | ||
427 | /* init DMA for V channel */ | |
428 | ret = pxa_init_dma_channel(pcdev, buf, dma, 2, sglen_v, | |
429 | sglen_yu, 0x38, size_v); | |
430 | if (ret) { | |
431 | dev_err(pcdev->dev, | |
432 | "DMA initialization for V failed\n"); | |
433 | goto fail_v; | |
434 | } | |
3bc43840 | 435 | } |
3bc43840 GL |
436 | |
437 | vb->state = VIDEOBUF_PREPARED; | |
438 | } | |
439 | ||
440 | buf->inwork = 0; | |
a5462e5b | 441 | buf->active_dma = DMA_Y; |
5aa2110f | 442 | if (pcdev->channels == 3) |
a5462e5b | 443 | buf->active_dma |= DMA_U | DMA_V; |
3bc43840 GL |
444 | |
445 | return 0; | |
446 | ||
a5462e5b MR |
447 | fail_v: |
448 | dma_free_coherent(pcdev->dev, buf->dmas[1].sg_size, | |
449 | buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma); | |
450 | fail_u: | |
451 | dma_free_coherent(pcdev->dev, buf->dmas[0].sg_size, | |
452 | buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma); | |
3bc43840 GL |
453 | fail: |
454 | free_buffer(vq, buf); | |
455 | out: | |
456 | buf->inwork = 0; | |
457 | return ret; | |
458 | } | |
459 | ||
7102b773 GL |
460 | static void pxa_videobuf_queue(struct videobuf_queue *vq, |
461 | struct videobuf_buffer *vb) | |
3bc43840 GL |
462 | { |
463 | struct soc_camera_device *icd = vq->priv_data; | |
64f5905e | 464 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
3bc43840 GL |
465 | struct pxa_camera_dev *pcdev = ici->priv; |
466 | struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); | |
7102b773 | 467 | struct pxa_buffer *active; |
3bc43840 | 468 | unsigned long flags; |
5aa2110f | 469 | int i; |
3bc43840 | 470 | |
7e28adb2 | 471 | dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
472 | vb, vb->baddr, vb->bsize); |
473 | spin_lock_irqsave(&pcdev->lock, flags); | |
474 | ||
475 | list_add_tail(&vb->queue, &pcdev->capture); | |
476 | ||
477 | vb->state = VIDEOBUF_ACTIVE; | |
7102b773 | 478 | active = pcdev->active; |
3bc43840 | 479 | |
7102b773 | 480 | if (!active) { |
5ca11fa3 EM |
481 | unsigned long cifr, cicr0; |
482 | ||
483 | cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F; | |
484 | __raw_writel(cifr, pcdev->base + CIFR); | |
a5462e5b | 485 | |
5aa2110f GL |
486 | for (i = 0; i < pcdev->channels; i++) { |
487 | DDADR(pcdev->dma_chans[i]) = buf->dmas[i].sg_dma; | |
488 | DCSR(pcdev->dma_chans[i]) = DCSR_RUN; | |
489 | pcdev->sg_tail[i] = buf->dmas[i].sg_cpu + buf->dmas[i].sglen - 1; | |
a5462e5b MR |
490 | } |
491 | ||
3bc43840 | 492 | pcdev->active = buf; |
5ca11fa3 EM |
493 | |
494 | cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB; | |
495 | __raw_writel(cicr0, pcdev->base + CICR0); | |
3bc43840 | 496 | } else { |
a5462e5b MR |
497 | struct pxa_cam_dma *buf_dma; |
498 | struct pxa_cam_dma *act_dma; | |
a5462e5b | 499 | int nents; |
a5462e5b | 500 | |
e7c50688 | 501 | for (i = 0; i < pcdev->channels; i++) { |
a5462e5b MR |
502 | buf_dma = &buf->dmas[i]; |
503 | act_dma = &active->dmas[i]; | |
504 | nents = buf_dma->sglen; | |
505 | ||
506 | /* Stop DMA engine */ | |
507 | DCSR(pcdev->dma_chans[i]) = 0; | |
508 | ||
509 | /* Add the descriptors we just initialized to | |
510 | the currently running chain */ | |
5aa2110f GL |
511 | pcdev->sg_tail[i]->ddadr = buf_dma->sg_dma; |
512 | pcdev->sg_tail[i] = buf_dma->sg_cpu + buf_dma->sglen - 1; | |
a5462e5b MR |
513 | |
514 | /* Setup a dummy descriptor with the DMA engines current | |
515 | * state | |
3bc43840 | 516 | */ |
a5462e5b MR |
517 | buf_dma->sg_cpu[nents].dsadr = |
518 | pcdev->res->start + 0x28 + i*8; /* CIBRx */ | |
519 | buf_dma->sg_cpu[nents].dtadr = | |
520 | DTADR(pcdev->dma_chans[i]); | |
521 | buf_dma->sg_cpu[nents].dcmd = | |
522 | DCMD(pcdev->dma_chans[i]); | |
523 | ||
524 | if (DDADR(pcdev->dma_chans[i]) == DDADR_STOP) { | |
525 | /* The DMA engine is on the last | |
526 | descriptor, set the next descriptors | |
527 | address to the descriptors we just | |
528 | initialized */ | |
529 | buf_dma->sg_cpu[nents].ddadr = buf_dma->sg_dma; | |
530 | } else { | |
531 | buf_dma->sg_cpu[nents].ddadr = | |
532 | DDADR(pcdev->dma_chans[i]); | |
533 | } | |
534 | ||
535 | /* The next descriptor is the dummy descriptor */ | |
536 | DDADR(pcdev->dma_chans[i]) = buf_dma->sg_dma + nents * | |
537 | sizeof(struct pxa_dma_desc); | |
538 | ||
539 | DCSR(pcdev->dma_chans[i]) = DCSR_RUN; | |
3bc43840 | 540 | } |
3bc43840 GL |
541 | } |
542 | ||
543 | spin_unlock_irqrestore(&pcdev->lock, flags); | |
3bc43840 GL |
544 | } |
545 | ||
546 | static void pxa_videobuf_release(struct videobuf_queue *vq, | |
547 | struct videobuf_buffer *vb) | |
548 | { | |
549 | struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); | |
550 | #ifdef DEBUG | |
551 | struct soc_camera_device *icd = vq->priv_data; | |
552 | ||
7e28adb2 | 553 | dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
554 | vb, vb->baddr, vb->bsize); |
555 | ||
556 | switch (vb->state) { | |
557 | case VIDEOBUF_ACTIVE: | |
7e28adb2 | 558 | dev_dbg(&icd->dev, "%s (active)\n", __func__); |
3bc43840 GL |
559 | break; |
560 | case VIDEOBUF_QUEUED: | |
7e28adb2 | 561 | dev_dbg(&icd->dev, "%s (queued)\n", __func__); |
3bc43840 GL |
562 | break; |
563 | case VIDEOBUF_PREPARED: | |
7e28adb2 | 564 | dev_dbg(&icd->dev, "%s (prepared)\n", __func__); |
3bc43840 GL |
565 | break; |
566 | default: | |
7e28adb2 | 567 | dev_dbg(&icd->dev, "%s (unknown)\n", __func__); |
3bc43840 GL |
568 | break; |
569 | } | |
570 | #endif | |
571 | ||
572 | free_buffer(vq, buf); | |
573 | } | |
574 | ||
a5462e5b MR |
575 | static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev, |
576 | struct videobuf_buffer *vb, | |
577 | struct pxa_buffer *buf) | |
578 | { | |
5ca11fa3 EM |
579 | unsigned long cicr0; |
580 | ||
a5462e5b MR |
581 | /* _init is used to debug races, see comment in pxa_camera_reqbufs() */ |
582 | list_del_init(&vb->queue); | |
583 | vb->state = VIDEOBUF_DONE; | |
584 | do_gettimeofday(&vb->ts); | |
585 | vb->field_count++; | |
586 | wake_up(&vb->done); | |
587 | ||
588 | if (list_empty(&pcdev->capture)) { | |
589 | pcdev->active = NULL; | |
590 | DCSR(pcdev->dma_chans[0]) = 0; | |
591 | DCSR(pcdev->dma_chans[1]) = 0; | |
592 | DCSR(pcdev->dma_chans[2]) = 0; | |
5ca11fa3 EM |
593 | |
594 | cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB; | |
595 | __raw_writel(cicr0, pcdev->base + CICR0); | |
a5462e5b MR |
596 | return; |
597 | } | |
598 | ||
599 | pcdev->active = list_entry(pcdev->capture.next, | |
600 | struct pxa_buffer, vb.queue); | |
601 | } | |
602 | ||
603 | static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev, | |
604 | enum pxa_camera_active_dma act_dma) | |
3bc43840 | 605 | { |
3bc43840 GL |
606 | struct pxa_buffer *buf; |
607 | unsigned long flags; | |
e7c50688 | 608 | u32 status, camera_status, overrun; |
3bc43840 | 609 | struct videobuf_buffer *vb; |
5ca11fa3 | 610 | unsigned long cifr, cicr0; |
3bc43840 GL |
611 | |
612 | spin_lock_irqsave(&pcdev->lock, flags); | |
613 | ||
a5462e5b MR |
614 | status = DCSR(channel); |
615 | DCSR(channel) = status | DCSR_ENDINTR; | |
7102b773 | 616 | |
3bc43840 | 617 | if (status & DCSR_BUSERR) { |
7102b773 | 618 | dev_err(pcdev->dev, "DMA Bus Error IRQ!\n"); |
3bc43840 GL |
619 | goto out; |
620 | } | |
621 | ||
622 | if (!(status & DCSR_ENDINTR)) { | |
7102b773 GL |
623 | dev_err(pcdev->dev, "Unknown DMA IRQ source, " |
624 | "status: 0x%08x\n", status); | |
3bc43840 GL |
625 | goto out; |
626 | } | |
627 | ||
3bc43840 | 628 | if (!pcdev->active) { |
7102b773 | 629 | dev_err(pcdev->dev, "DMA End IRQ with no active buffer!\n"); |
3bc43840 GL |
630 | goto out; |
631 | } | |
632 | ||
5ca11fa3 | 633 | camera_status = __raw_readl(pcdev->base + CISR); |
e7c50688 GL |
634 | overrun = CISR_IFO_0; |
635 | if (pcdev->channels == 3) | |
636 | overrun |= CISR_IFO_1 | CISR_IFO_2; | |
637 | if (camera_status & overrun) { | |
638 | dev_dbg(pcdev->dev, "FIFO overrun! CISR: %x\n", camera_status); | |
639 | /* Stop the Capture Interface */ | |
5ca11fa3 EM |
640 | cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB; |
641 | __raw_writel(cicr0, pcdev->base + CICR0); | |
642 | ||
e7c50688 GL |
643 | /* Stop DMA */ |
644 | DCSR(channel) = 0; | |
645 | /* Reset the FIFOs */ | |
5ca11fa3 EM |
646 | cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F; |
647 | __raw_writel(cifr, pcdev->base + CIFR); | |
e7c50688 | 648 | /* Enable End-Of-Frame Interrupt */ |
5ca11fa3 EM |
649 | cicr0 &= ~CICR0_EOFM; |
650 | __raw_writel(cicr0, pcdev->base + CICR0); | |
e7c50688 | 651 | /* Restart the Capture Interface */ |
5ca11fa3 | 652 | __raw_writel(cicr0 | CICR0_ENB, pcdev->base + CICR0); |
e7c50688 GL |
653 | goto out; |
654 | } | |
655 | ||
3bc43840 GL |
656 | vb = &pcdev->active->vb; |
657 | buf = container_of(vb, struct pxa_buffer, vb); | |
658 | WARN_ON(buf->inwork || list_empty(&vb->queue)); | |
7e28adb2 | 659 | dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
660 | vb, vb->baddr, vb->bsize); |
661 | ||
a5462e5b MR |
662 | buf->active_dma &= ~act_dma; |
663 | if (!buf->active_dma) | |
664 | pxa_camera_wakeup(pcdev, vb, buf); | |
3bc43840 GL |
665 | |
666 | out: | |
667 | spin_unlock_irqrestore(&pcdev->lock, flags); | |
668 | } | |
669 | ||
a5462e5b MR |
670 | static void pxa_camera_dma_irq_y(int channel, void *data) |
671 | { | |
672 | struct pxa_camera_dev *pcdev = data; | |
673 | pxa_camera_dma_irq(channel, pcdev, DMA_Y); | |
674 | } | |
675 | ||
676 | static void pxa_camera_dma_irq_u(int channel, void *data) | |
677 | { | |
678 | struct pxa_camera_dev *pcdev = data; | |
679 | pxa_camera_dma_irq(channel, pcdev, DMA_U); | |
680 | } | |
681 | ||
682 | static void pxa_camera_dma_irq_v(int channel, void *data) | |
683 | { | |
684 | struct pxa_camera_dev *pcdev = data; | |
685 | pxa_camera_dma_irq(channel, pcdev, DMA_V); | |
686 | } | |
687 | ||
7102b773 | 688 | static struct videobuf_queue_ops pxa_videobuf_ops = { |
3bc43840 GL |
689 | .buf_setup = pxa_videobuf_setup, |
690 | .buf_prepare = pxa_videobuf_prepare, | |
691 | .buf_queue = pxa_videobuf_queue, | |
692 | .buf_release = pxa_videobuf_release, | |
693 | }; | |
694 | ||
a034d1b7 | 695 | static void pxa_camera_init_videobuf(struct videobuf_queue *q, |
092d3921 PZ |
696 | struct soc_camera_device *icd) |
697 | { | |
a034d1b7 MD |
698 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
699 | struct pxa_camera_dev *pcdev = ici->priv; | |
700 | ||
092d3921 PZ |
701 | /* We must pass NULL as dev pointer, then all pci_* dma operations |
702 | * transform to normal dma_* ones. */ | |
a034d1b7 | 703 | videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock, |
092d3921 PZ |
704 | V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE, |
705 | sizeof(struct pxa_buffer), icd); | |
706 | } | |
707 | ||
cf34cba7 | 708 | static u32 mclk_get_divisor(struct pxa_camera_dev *pcdev) |
3bc43840 | 709 | { |
cf34cba7 GL |
710 | unsigned long mclk = pcdev->mclk; |
711 | u32 div; | |
3bc43840 GL |
712 | unsigned long lcdclk; |
713 | ||
cf34cba7 GL |
714 | lcdclk = clk_get_rate(pcdev->clk); |
715 | pcdev->ciclk = lcdclk; | |
3bc43840 | 716 | |
cf34cba7 GL |
717 | /* mclk <= ciclk / 4 (27.4.2) */ |
718 | if (mclk > lcdclk / 4) { | |
719 | mclk = lcdclk / 4; | |
720 | dev_warn(pcdev->dev, "Limiting master clock to %lu\n", mclk); | |
721 | } | |
722 | ||
723 | /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */ | |
724 | div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1; | |
725 | ||
726 | /* If we're not supplying MCLK, leave it at 0 */ | |
727 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
728 | pcdev->mclk = lcdclk / (2 * (div + 1)); | |
3bc43840 | 729 | |
cf34cba7 GL |
730 | dev_dbg(pcdev->dev, "LCD clock %luHz, target freq %luHz, " |
731 | "divisor %u\n", lcdclk, mclk, div); | |
3bc43840 GL |
732 | |
733 | return div; | |
734 | } | |
735 | ||
cf34cba7 GL |
736 | static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev, |
737 | unsigned long pclk) | |
738 | { | |
739 | /* We want a timeout > 1 pixel time, not ">=" */ | |
740 | u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1; | |
741 | ||
742 | __raw_writel(ciclk_per_pixel, pcdev->base + CITOR); | |
743 | } | |
744 | ||
7102b773 | 745 | static void pxa_camera_activate(struct pxa_camera_dev *pcdev) |
3bc43840 GL |
746 | { |
747 | struct pxacamera_platform_data *pdata = pcdev->pdata; | |
748 | u32 cicr4 = 0; | |
749 | ||
750 | dev_dbg(pcdev->dev, "Registered platform device at %p data %p\n", | |
751 | pcdev, pdata); | |
752 | ||
753 | if (pdata && pdata->init) { | |
7e28adb2 | 754 | dev_dbg(pcdev->dev, "%s: Init gpios\n", __func__); |
3bc43840 GL |
755 | pdata->init(pcdev->dev); |
756 | } | |
757 | ||
5ca11fa3 EM |
758 | /* disable all interrupts */ |
759 | __raw_writel(0x3ff, pcdev->base + CICR0); | |
3bc43840 GL |
760 | |
761 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
762 | cicr4 |= CICR4_PCLK_EN; | |
763 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
764 | cicr4 |= CICR4_MCLK_EN; | |
765 | if (pcdev->platform_flags & PXA_CAMERA_PCP) | |
766 | cicr4 |= CICR4_PCP; | |
767 | if (pcdev->platform_flags & PXA_CAMERA_HSP) | |
768 | cicr4 |= CICR4_HSP; | |
769 | if (pcdev->platform_flags & PXA_CAMERA_VSP) | |
770 | cicr4 |= CICR4_VSP; | |
771 | ||
cf34cba7 GL |
772 | __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4); |
773 | ||
774 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
775 | /* Initialise the timeout under the assumption pclk = mclk */ | |
776 | recalculate_fifo_timeout(pcdev, pcdev->mclk); | |
777 | else | |
778 | /* "Safe default" - 13MHz */ | |
779 | recalculate_fifo_timeout(pcdev, 13000000); | |
3bc43840 GL |
780 | |
781 | clk_enable(pcdev->clk); | |
782 | } | |
783 | ||
7102b773 | 784 | static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev) |
3bc43840 | 785 | { |
3bc43840 | 786 | clk_disable(pcdev->clk); |
3bc43840 GL |
787 | } |
788 | ||
789 | static irqreturn_t pxa_camera_irq(int irq, void *data) | |
790 | { | |
791 | struct pxa_camera_dev *pcdev = data; | |
5ca11fa3 | 792 | unsigned long status, cicr0; |
3bc43840 | 793 | |
5ca11fa3 EM |
794 | status = __raw_readl(pcdev->base + CISR); |
795 | dev_dbg(pcdev->dev, "Camera interrupt status 0x%lx\n", status); | |
3bc43840 | 796 | |
e7c50688 GL |
797 | if (!status) |
798 | return IRQ_NONE; | |
799 | ||
5ca11fa3 | 800 | __raw_writel(status, pcdev->base + CISR); |
e7c50688 GL |
801 | |
802 | if (status & CISR_EOF) { | |
803 | int i; | |
804 | for (i = 0; i < pcdev->channels; i++) { | |
805 | DDADR(pcdev->dma_chans[i]) = | |
806 | pcdev->active->dmas[i].sg_dma; | |
807 | DCSR(pcdev->dma_chans[i]) = DCSR_RUN; | |
808 | } | |
5ca11fa3 EM |
809 | cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM; |
810 | __raw_writel(cicr0, pcdev->base + CICR0); | |
e7c50688 GL |
811 | } |
812 | ||
3bc43840 GL |
813 | return IRQ_HANDLED; |
814 | } | |
815 | ||
816 | /* The following two functions absolutely depend on the fact, that | |
817 | * there can be only one camera on PXA quick capture interface */ | |
7102b773 | 818 | static int pxa_camera_add_device(struct soc_camera_device *icd) |
3bc43840 GL |
819 | { |
820 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
821 | struct pxa_camera_dev *pcdev = ici->priv; | |
822 | int ret; | |
823 | ||
824 | mutex_lock(&camera_lock); | |
825 | ||
826 | if (pcdev->icd) { | |
827 | ret = -EBUSY; | |
828 | goto ebusy; | |
829 | } | |
830 | ||
831 | dev_info(&icd->dev, "PXA Camera driver attached to camera %d\n", | |
832 | icd->devnum); | |
833 | ||
7102b773 | 834 | pxa_camera_activate(pcdev); |
3bc43840 GL |
835 | ret = icd->ops->init(icd); |
836 | ||
837 | if (!ret) | |
838 | pcdev->icd = icd; | |
839 | ||
840 | ebusy: | |
841 | mutex_unlock(&camera_lock); | |
842 | ||
843 | return ret; | |
844 | } | |
845 | ||
7102b773 | 846 | static void pxa_camera_remove_device(struct soc_camera_device *icd) |
3bc43840 GL |
847 | { |
848 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
849 | struct pxa_camera_dev *pcdev = ici->priv; | |
850 | ||
851 | BUG_ON(icd != pcdev->icd); | |
852 | ||
853 | dev_info(&icd->dev, "PXA Camera driver detached from camera %d\n", | |
854 | icd->devnum); | |
855 | ||
856 | /* disable capture, disable interrupts */ | |
5ca11fa3 | 857 | __raw_writel(0x3ff, pcdev->base + CICR0); |
a5462e5b | 858 | |
3bc43840 | 859 | /* Stop DMA engine */ |
a5462e5b MR |
860 | DCSR(pcdev->dma_chans[0]) = 0; |
861 | DCSR(pcdev->dma_chans[1]) = 0; | |
862 | DCSR(pcdev->dma_chans[2]) = 0; | |
3bc43840 GL |
863 | |
864 | icd->ops->release(icd); | |
865 | ||
7102b773 | 866 | pxa_camera_deactivate(pcdev); |
3bc43840 GL |
867 | |
868 | pcdev->icd = NULL; | |
869 | } | |
870 | ||
ad5f2e85 GL |
871 | static int test_platform_param(struct pxa_camera_dev *pcdev, |
872 | unsigned char buswidth, unsigned long *flags) | |
3bc43840 | 873 | { |
ad5f2e85 GL |
874 | /* |
875 | * Platform specified synchronization and pixel clock polarities are | |
876 | * only a recommendation and are only used during probing. The PXA270 | |
877 | * quick capture interface supports both. | |
878 | */ | |
879 | *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ? | |
880 | SOCAM_MASTER : SOCAM_SLAVE) | | |
881 | SOCAM_HSYNC_ACTIVE_HIGH | | |
882 | SOCAM_HSYNC_ACTIVE_LOW | | |
883 | SOCAM_VSYNC_ACTIVE_HIGH | | |
884 | SOCAM_VSYNC_ACTIVE_LOW | | |
885 | SOCAM_PCLK_SAMPLE_RISING | | |
886 | SOCAM_PCLK_SAMPLE_FALLING; | |
3bc43840 GL |
887 | |
888 | /* If requested data width is supported by the platform, use it */ | |
ad5f2e85 | 889 | switch (buswidth) { |
3bc43840 | 890 | case 10: |
ad5f2e85 GL |
891 | if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10)) |
892 | return -EINVAL; | |
893 | *flags |= SOCAM_DATAWIDTH_10; | |
3bc43840 GL |
894 | break; |
895 | case 9: | |
ad5f2e85 GL |
896 | if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9)) |
897 | return -EINVAL; | |
898 | *flags |= SOCAM_DATAWIDTH_9; | |
3bc43840 GL |
899 | break; |
900 | case 8: | |
ad5f2e85 GL |
901 | if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8)) |
902 | return -EINVAL; | |
903 | *flags |= SOCAM_DATAWIDTH_8; | |
2a48fc73 RJ |
904 | break; |
905 | default: | |
906 | return -EINVAL; | |
3bc43840 | 907 | } |
ad5f2e85 GL |
908 | |
909 | return 0; | |
910 | } | |
911 | ||
912 | static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt) | |
913 | { | |
64f5905e | 914 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
ad5f2e85 GL |
915 | struct pxa_camera_dev *pcdev = ici->priv; |
916 | unsigned long dw, bpp, bus_flags, camera_flags, common_flags; | |
5ca11fa3 | 917 | u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0; |
ad5f2e85 GL |
918 | int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags); |
919 | ||
920 | if (ret < 0) | |
921 | return ret; | |
922 | ||
923 | camera_flags = icd->ops->query_bus_param(icd); | |
924 | ||
925 | common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags); | |
926 | if (!common_flags) | |
3bc43840 GL |
927 | return -EINVAL; |
928 | ||
e7c50688 GL |
929 | pcdev->channels = 1; |
930 | ||
ad5f2e85 GL |
931 | /* Make choises, based on platform preferences */ |
932 | if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) && | |
933 | (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) { | |
934 | if (pcdev->platform_flags & PXA_CAMERA_HSP) | |
935 | common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH; | |
936 | else | |
937 | common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW; | |
938 | } | |
939 | ||
940 | if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) && | |
941 | (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) { | |
942 | if (pcdev->platform_flags & PXA_CAMERA_VSP) | |
943 | common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH; | |
944 | else | |
945 | common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW; | |
946 | } | |
947 | ||
948 | if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) && | |
949 | (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) { | |
950 | if (pcdev->platform_flags & PXA_CAMERA_PCP) | |
951 | common_flags &= ~SOCAM_PCLK_SAMPLE_RISING; | |
952 | else | |
953 | common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING; | |
954 | } | |
955 | ||
956 | ret = icd->ops->set_bus_param(icd, common_flags); | |
3bc43840 GL |
957 | if (ret < 0) |
958 | return ret; | |
959 | ||
960 | /* Datawidth is now guaranteed to be equal to one of the three values. | |
961 | * We fix bit-per-pixel equal to data-width... */ | |
ad5f2e85 GL |
962 | switch (common_flags & SOCAM_DATAWIDTH_MASK) { |
963 | case SOCAM_DATAWIDTH_10: | |
3bc43840 GL |
964 | dw = 4; |
965 | bpp = 0x40; | |
966 | break; | |
ad5f2e85 | 967 | case SOCAM_DATAWIDTH_9: |
3bc43840 GL |
968 | dw = 3; |
969 | bpp = 0x20; | |
970 | break; | |
971 | default: | |
972 | /* Actually it can only be 8 now, | |
973 | * default is just to silence compiler warnings */ | |
ad5f2e85 | 974 | case SOCAM_DATAWIDTH_8: |
3bc43840 GL |
975 | dw = 2; |
976 | bpp = 0; | |
977 | } | |
978 | ||
979 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
980 | cicr4 |= CICR4_PCLK_EN; | |
981 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
982 | cicr4 |= CICR4_MCLK_EN; | |
ad5f2e85 | 983 | if (common_flags & SOCAM_PCLK_SAMPLE_FALLING) |
3bc43840 | 984 | cicr4 |= CICR4_PCP; |
ad5f2e85 | 985 | if (common_flags & SOCAM_HSYNC_ACTIVE_LOW) |
3bc43840 | 986 | cicr4 |= CICR4_HSP; |
ad5f2e85 | 987 | if (common_flags & SOCAM_VSYNC_ACTIVE_LOW) |
3bc43840 GL |
988 | cicr4 |= CICR4_VSP; |
989 | ||
5ca11fa3 | 990 | cicr0 = __raw_readl(pcdev->base + CICR0); |
3bc43840 | 991 | if (cicr0 & CICR0_ENB) |
5ca11fa3 | 992 | __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0); |
a5462e5b MR |
993 | |
994 | cicr1 = CICR1_PPL_VAL(icd->width - 1) | bpp | dw; | |
995 | ||
996 | switch (pixfmt) { | |
997 | case V4L2_PIX_FMT_YUV422P: | |
e7c50688 | 998 | pcdev->channels = 3; |
a5462e5b | 999 | cicr1 |= CICR1_YCBCR_F; |
2a48fc73 RJ |
1000 | /* |
1001 | * Normally, pxa bus wants as input UYVY format. We allow all | |
1002 | * reorderings of the YUV422 format, as no processing is done, | |
1003 | * and the YUV stream is just passed through without any | |
1004 | * transformation. Note that UYVY is the only format that | |
1005 | * should be used if pxa framebuffer Overlay2 is used. | |
1006 | */ | |
1007 | case V4L2_PIX_FMT_UYVY: | |
1008 | case V4L2_PIX_FMT_VYUY: | |
a5462e5b | 1009 | case V4L2_PIX_FMT_YUYV: |
2a48fc73 | 1010 | case V4L2_PIX_FMT_YVYU: |
a5462e5b MR |
1011 | cicr1 |= CICR1_COLOR_SP_VAL(2); |
1012 | break; | |
1013 | case V4L2_PIX_FMT_RGB555: | |
1014 | cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) | | |
1015 | CICR1_TBIT | CICR1_COLOR_SP_VAL(1); | |
1016 | break; | |
1017 | case V4L2_PIX_FMT_RGB565: | |
1018 | cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2); | |
1019 | break; | |
1020 | } | |
1021 | ||
5ca11fa3 EM |
1022 | cicr2 = 0; |
1023 | cicr3 = CICR3_LPF_VAL(icd->height - 1) | | |
3bc43840 | 1024 | CICR3_BFW_VAL(min((unsigned short)255, icd->y_skip_top)); |
cf34cba7 | 1025 | cicr4 |= pcdev->mclk_divisor; |
5ca11fa3 EM |
1026 | |
1027 | __raw_writel(cicr1, pcdev->base + CICR1); | |
1028 | __raw_writel(cicr2, pcdev->base + CICR2); | |
1029 | __raw_writel(cicr3, pcdev->base + CICR3); | |
1030 | __raw_writel(cicr4, pcdev->base + CICR4); | |
3bc43840 GL |
1031 | |
1032 | /* CIF interrupts are not used, only DMA */ | |
5ca11fa3 EM |
1033 | cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ? |
1034 | CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP)); | |
1035 | cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK; | |
1036 | __raw_writel(cicr0, pcdev->base + CICR0); | |
3bc43840 GL |
1037 | |
1038 | return 0; | |
1039 | } | |
1040 | ||
2a48fc73 RJ |
1041 | static int pxa_camera_try_bus_param(struct soc_camera_device *icd, |
1042 | unsigned char buswidth) | |
ad5f2e85 | 1043 | { |
cf34cba7 | 1044 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
ad5f2e85 GL |
1045 | struct pxa_camera_dev *pcdev = ici->priv; |
1046 | unsigned long bus_flags, camera_flags; | |
2a48fc73 | 1047 | int ret = test_platform_param(pcdev, buswidth, &bus_flags); |
ad5f2e85 GL |
1048 | |
1049 | if (ret < 0) | |
1050 | return ret; | |
1051 | ||
1052 | camera_flags = icd->ops->query_bus_param(icd); | |
1053 | ||
1054 | return soc_camera_bus_param_compatible(camera_flags, bus_flags) ? 0 : -EINVAL; | |
1055 | } | |
1056 | ||
2a48fc73 RJ |
1057 | static const struct soc_camera_data_format pxa_camera_formats[] = { |
1058 | { | |
1059 | .name = "Planar YUV422 16 bit", | |
1060 | .depth = 16, | |
1061 | .fourcc = V4L2_PIX_FMT_YUV422P, | |
1062 | .colorspace = V4L2_COLORSPACE_JPEG, | |
1063 | }, | |
1064 | }; | |
1065 | ||
1066 | static bool buswidth_supported(struct soc_camera_device *icd, int depth) | |
1067 | { | |
1068 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
1069 | struct pxa_camera_dev *pcdev = ici->priv; | |
1070 | ||
1071 | switch (depth) { | |
1072 | case 8: | |
1073 | return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8); | |
1074 | case 9: | |
1075 | return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9); | |
1076 | case 10: | |
1077 | return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10); | |
1078 | } | |
1079 | return false; | |
1080 | } | |
1081 | ||
1082 | static int required_buswidth(const struct soc_camera_data_format *fmt) | |
1083 | { | |
1084 | switch (fmt->fourcc) { | |
1085 | case V4L2_PIX_FMT_UYVY: | |
1086 | case V4L2_PIX_FMT_VYUY: | |
1087 | case V4L2_PIX_FMT_YUYV: | |
1088 | case V4L2_PIX_FMT_YVYU: | |
1089 | case V4L2_PIX_FMT_RGB565: | |
1090 | case V4L2_PIX_FMT_RGB555: | |
1091 | return 8; | |
1092 | default: | |
1093 | return fmt->depth; | |
1094 | } | |
1095 | } | |
1096 | ||
1097 | static int pxa_camera_get_formats(struct soc_camera_device *icd, int idx, | |
1098 | struct soc_camera_format_xlate *xlate) | |
1099 | { | |
1100 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
1101 | int formats = 0, buswidth, ret; | |
1102 | ||
1103 | buswidth = required_buswidth(icd->formats + idx); | |
1104 | ||
1105 | if (!buswidth_supported(icd, buswidth)) | |
1106 | return 0; | |
1107 | ||
1108 | ret = pxa_camera_try_bus_param(icd, buswidth); | |
1109 | if (ret < 0) | |
1110 | return 0; | |
1111 | ||
1112 | switch (icd->formats[idx].fourcc) { | |
1113 | case V4L2_PIX_FMT_UYVY: | |
1114 | formats++; | |
1115 | if (xlate) { | |
1116 | xlate->host_fmt = &pxa_camera_formats[0]; | |
1117 | xlate->cam_fmt = icd->formats + idx; | |
1118 | xlate->buswidth = buswidth; | |
1119 | xlate++; | |
1120 | dev_dbg(&ici->dev, "Providing format %s using %s\n", | |
1121 | pxa_camera_formats[0].name, | |
1122 | icd->formats[idx].name); | |
1123 | } | |
1124 | case V4L2_PIX_FMT_VYUY: | |
1125 | case V4L2_PIX_FMT_YUYV: | |
1126 | case V4L2_PIX_FMT_YVYU: | |
1127 | case V4L2_PIX_FMT_RGB565: | |
1128 | case V4L2_PIX_FMT_RGB555: | |
1129 | formats++; | |
1130 | if (xlate) { | |
1131 | xlate->host_fmt = icd->formats + idx; | |
1132 | xlate->cam_fmt = icd->formats + idx; | |
1133 | xlate->buswidth = buswidth; | |
1134 | xlate++; | |
1135 | dev_dbg(&ici->dev, "Providing format %s packed\n", | |
1136 | icd->formats[idx].name); | |
1137 | } | |
1138 | break; | |
1139 | default: | |
1140 | /* Generic pass-through */ | |
1141 | formats++; | |
1142 | if (xlate) { | |
1143 | xlate->host_fmt = icd->formats + idx; | |
1144 | xlate->cam_fmt = icd->formats + idx; | |
1145 | xlate->buswidth = icd->formats[idx].depth; | |
1146 | xlate++; | |
1147 | dev_dbg(&ici->dev, | |
1148 | "Providing format %s in pass-through mode\n", | |
1149 | icd->formats[idx].name); | |
1150 | } | |
1151 | } | |
1152 | ||
1153 | return formats; | |
1154 | } | |
1155 | ||
d8fac217 GL |
1156 | static int pxa_camera_set_fmt(struct soc_camera_device *icd, |
1157 | __u32 pixfmt, struct v4l2_rect *rect) | |
ad5f2e85 | 1158 | { |
2a48fc73 | 1159 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
cf34cba7 | 1160 | struct pxa_camera_dev *pcdev = ici->priv; |
2a48fc73 RJ |
1161 | const struct soc_camera_data_format *host_fmt, *cam_fmt = NULL; |
1162 | const struct soc_camera_format_xlate *xlate; | |
cf34cba7 GL |
1163 | struct soc_camera_sense sense = { |
1164 | .master_clock = pcdev->mclk, | |
1165 | .pixel_clock_max = pcdev->ciclk / 4, | |
1166 | }; | |
2a48fc73 | 1167 | int ret, buswidth; |
25c4d74e | 1168 | |
2a48fc73 RJ |
1169 | xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); |
1170 | if (!xlate) { | |
1171 | dev_warn(&ici->dev, "Format %x not found\n", pixfmt); | |
1172 | return -EINVAL; | |
25c4d74e GL |
1173 | } |
1174 | ||
2a48fc73 RJ |
1175 | buswidth = xlate->buswidth; |
1176 | host_fmt = xlate->host_fmt; | |
1177 | cam_fmt = xlate->cam_fmt; | |
1178 | ||
cf34cba7 GL |
1179 | /* If PCLK is used to latch data from the sensor, check sense */ |
1180 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
1181 | icd->sense = &sense; | |
1182 | ||
2a48fc73 RJ |
1183 | switch (pixfmt) { |
1184 | case 0: /* Only geometry change */ | |
1185 | ret = icd->ops->set_fmt(icd, pixfmt, rect); | |
1186 | break; | |
1187 | default: | |
1188 | ret = icd->ops->set_fmt(icd, cam_fmt->fourcc, rect); | |
1189 | } | |
1190 | ||
cf34cba7 GL |
1191 | icd->sense = NULL; |
1192 | ||
1193 | if (ret < 0) { | |
2a48fc73 RJ |
1194 | dev_warn(&ici->dev, "Failed to configure for format %x\n", |
1195 | pixfmt); | |
cf34cba7 GL |
1196 | } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) { |
1197 | if (sense.pixel_clock > sense.pixel_clock_max) { | |
1198 | dev_err(&ici->dev, | |
1199 | "pixel clock %lu set by the camera too high!", | |
1200 | sense.pixel_clock); | |
1201 | return -EIO; | |
1202 | } | |
1203 | recalculate_fifo_timeout(pcdev, sense.pixel_clock); | |
1204 | } | |
2a48fc73 RJ |
1205 | |
1206 | if (pixfmt && !ret) { | |
1207 | icd->buswidth = buswidth; | |
1208 | icd->current_fmt = host_fmt; | |
1209 | } | |
25c4d74e GL |
1210 | |
1211 | return ret; | |
ad5f2e85 GL |
1212 | } |
1213 | ||
d8fac217 GL |
1214 | static int pxa_camera_try_fmt(struct soc_camera_device *icd, |
1215 | struct v4l2_format *f) | |
3bc43840 | 1216 | { |
2a48fc73 RJ |
1217 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
1218 | const struct soc_camera_format_xlate *xlate; | |
1219 | struct v4l2_pix_format *pix = &f->fmt.pix; | |
1220 | __u32 pixfmt = pix->pixelformat; | |
a2c8c68c | 1221 | |
2a48fc73 RJ |
1222 | xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); |
1223 | if (!xlate) { | |
1224 | dev_warn(&ici->dev, "Format %x not found\n", pixfmt); | |
25c4d74e | 1225 | return -EINVAL; |
2a48fc73 | 1226 | } |
25c4d74e | 1227 | |
3bc43840 | 1228 | /* limit to pxa hardware capabilities */ |
2a48fc73 RJ |
1229 | if (pix->height < 32) |
1230 | pix->height = 32; | |
1231 | if (pix->height > 2048) | |
1232 | pix->height = 2048; | |
1233 | if (pix->width < 48) | |
1234 | pix->width = 48; | |
1235 | if (pix->width > 2048) | |
1236 | pix->width = 2048; | |
1237 | pix->width &= ~0x01; | |
1238 | ||
1239 | pix->bytesperline = pix->width * | |
1240 | DIV_ROUND_UP(xlate->host_fmt->depth, 8); | |
1241 | pix->sizeimage = pix->height * pix->bytesperline; | |
25c4d74e | 1242 | |
ad5f2e85 | 1243 | /* limit to sensor capabilities */ |
d8fac217 | 1244 | return icd->ops->try_fmt(icd, f); |
3bc43840 GL |
1245 | } |
1246 | ||
7102b773 GL |
1247 | static int pxa_camera_reqbufs(struct soc_camera_file *icf, |
1248 | struct v4l2_requestbuffers *p) | |
3bc43840 GL |
1249 | { |
1250 | int i; | |
1251 | ||
1252 | /* This is for locking debugging only. I removed spinlocks and now I | |
1253 | * check whether .prepare is ever called on a linked buffer, or whether | |
1254 | * a dma IRQ can occur for an in-work or unlinked buffer. Until now | |
1255 | * it hadn't triggered */ | |
1256 | for (i = 0; i < p->count; i++) { | |
1257 | struct pxa_buffer *buf = container_of(icf->vb_vidq.bufs[i], | |
1258 | struct pxa_buffer, vb); | |
1259 | buf->inwork = 0; | |
1260 | INIT_LIST_HEAD(&buf->vb.queue); | |
1261 | } | |
1262 | ||
1263 | return 0; | |
1264 | } | |
1265 | ||
7102b773 | 1266 | static unsigned int pxa_camera_poll(struct file *file, poll_table *pt) |
3bc43840 GL |
1267 | { |
1268 | struct soc_camera_file *icf = file->private_data; | |
1269 | struct pxa_buffer *buf; | |
1270 | ||
1271 | buf = list_entry(icf->vb_vidq.stream.next, struct pxa_buffer, | |
1272 | vb.stream); | |
1273 | ||
1274 | poll_wait(file, &buf->vb.done, pt); | |
1275 | ||
1276 | if (buf->vb.state == VIDEOBUF_DONE || | |
1277 | buf->vb.state == VIDEOBUF_ERROR) | |
1278 | return POLLIN|POLLRDNORM; | |
1279 | ||
1280 | return 0; | |
1281 | } | |
1282 | ||
7102b773 GL |
1283 | static int pxa_camera_querycap(struct soc_camera_host *ici, |
1284 | struct v4l2_capability *cap) | |
3bc43840 GL |
1285 | { |
1286 | /* cap->name is set by the firendly caller:-> */ | |
1287 | strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card)); | |
1288 | cap->version = PXA_CAM_VERSION_CODE; | |
1289 | cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; | |
1290 | ||
1291 | return 0; | |
1292 | } | |
1293 | ||
3f6ac497 RJ |
1294 | static int pxa_camera_suspend(struct soc_camera_device *icd, pm_message_t state) |
1295 | { | |
64f5905e | 1296 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
3f6ac497 RJ |
1297 | struct pxa_camera_dev *pcdev = ici->priv; |
1298 | int i = 0, ret = 0; | |
1299 | ||
5ca11fa3 EM |
1300 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0); |
1301 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1); | |
1302 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2); | |
1303 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3); | |
1304 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4); | |
3f6ac497 RJ |
1305 | |
1306 | if ((pcdev->icd) && (pcdev->icd->ops->suspend)) | |
1307 | ret = pcdev->icd->ops->suspend(pcdev->icd, state); | |
1308 | ||
1309 | return ret; | |
1310 | } | |
1311 | ||
1312 | static int pxa_camera_resume(struct soc_camera_device *icd) | |
1313 | { | |
64f5905e | 1314 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
3f6ac497 RJ |
1315 | struct pxa_camera_dev *pcdev = ici->priv; |
1316 | int i = 0, ret = 0; | |
1317 | ||
87f3dd77 EM |
1318 | DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD; |
1319 | DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD; | |
1320 | DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD; | |
3f6ac497 | 1321 | |
5ca11fa3 EM |
1322 | __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0); |
1323 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1); | |
1324 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2); | |
1325 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3); | |
1326 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4); | |
3f6ac497 RJ |
1327 | |
1328 | if ((pcdev->icd) && (pcdev->icd->ops->resume)) | |
1329 | ret = pcdev->icd->ops->resume(pcdev->icd); | |
1330 | ||
1331 | /* Restart frame capture if active buffer exists */ | |
1332 | if (!ret && pcdev->active) { | |
5ca11fa3 EM |
1333 | unsigned long cifr, cicr0; |
1334 | ||
3f6ac497 | 1335 | /* Reset the FIFOs */ |
5ca11fa3 EM |
1336 | cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F; |
1337 | __raw_writel(cifr, pcdev->base + CIFR); | |
1338 | ||
1339 | cicr0 = __raw_readl(pcdev->base + CICR0); | |
1340 | cicr0 &= ~CICR0_EOFM; /* Enable End-Of-Frame Interrupt */ | |
1341 | cicr0 |= CICR0_ENB; /* Restart the Capture Interface */ | |
1342 | __raw_writel(cicr0, pcdev->base + CICR0); | |
3f6ac497 RJ |
1343 | } |
1344 | ||
1345 | return ret; | |
1346 | } | |
1347 | ||
b8d9904c GL |
1348 | static struct soc_camera_host_ops pxa_soc_camera_host_ops = { |
1349 | .owner = THIS_MODULE, | |
1350 | .add = pxa_camera_add_device, | |
1351 | .remove = pxa_camera_remove_device, | |
3f6ac497 RJ |
1352 | .suspend = pxa_camera_suspend, |
1353 | .resume = pxa_camera_resume, | |
2a48fc73 | 1354 | .get_formats = pxa_camera_get_formats, |
d8fac217 GL |
1355 | .set_fmt = pxa_camera_set_fmt, |
1356 | .try_fmt = pxa_camera_try_fmt, | |
092d3921 | 1357 | .init_videobuf = pxa_camera_init_videobuf, |
b8d9904c GL |
1358 | .reqbufs = pxa_camera_reqbufs, |
1359 | .poll = pxa_camera_poll, | |
1360 | .querycap = pxa_camera_querycap, | |
b8d9904c GL |
1361 | .set_bus_param = pxa_camera_set_bus_param, |
1362 | }; | |
1363 | ||
1364 | /* Should be allocated dynamically too, but we have only one. */ | |
3bc43840 GL |
1365 | static struct soc_camera_host pxa_soc_camera_host = { |
1366 | .drv_name = PXA_CAM_DRV_NAME, | |
b8d9904c | 1367 | .ops = &pxa_soc_camera_host_ops, |
3bc43840 GL |
1368 | }; |
1369 | ||
1370 | static int pxa_camera_probe(struct platform_device *pdev) | |
1371 | { | |
1372 | struct pxa_camera_dev *pcdev; | |
1373 | struct resource *res; | |
1374 | void __iomem *base; | |
02da4659 | 1375 | int irq; |
3bc43840 GL |
1376 | int err = 0; |
1377 | ||
1378 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1379 | irq = platform_get_irq(pdev, 0); | |
02da4659 | 1380 | if (!res || irq < 0) { |
3bc43840 GL |
1381 | err = -ENODEV; |
1382 | goto exit; | |
1383 | } | |
1384 | ||
1385 | pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL); | |
1386 | if (!pcdev) { | |
7102b773 | 1387 | dev_err(&pdev->dev, "Could not allocate pcdev\n"); |
3bc43840 GL |
1388 | err = -ENOMEM; |
1389 | goto exit; | |
1390 | } | |
1391 | ||
1392 | pcdev->clk = clk_get(&pdev->dev, "CAMCLK"); | |
1393 | if (IS_ERR(pcdev->clk)) { | |
1394 | err = PTR_ERR(pcdev->clk); | |
1395 | goto exit_kfree; | |
1396 | } | |
1397 | ||
1398 | dev_set_drvdata(&pdev->dev, pcdev); | |
1399 | pcdev->res = res; | |
1400 | ||
1401 | pcdev->pdata = pdev->dev.platform_data; | |
1402 | pcdev->platform_flags = pcdev->pdata->flags; | |
ad5f2e85 GL |
1403 | if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 | |
1404 | PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) { | |
3bc43840 GL |
1405 | /* Platform hasn't set available data widths. This is bad. |
1406 | * Warn and use a default. */ | |
1407 | dev_warn(&pdev->dev, "WARNING! Platform hasn't set available " | |
1408 | "data widths, using default 10 bit\n"); | |
1409 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10; | |
1410 | } | |
cf34cba7 GL |
1411 | pcdev->mclk = pcdev->pdata->mclk_10khz * 10000; |
1412 | if (!pcdev->mclk) { | |
3bc43840 | 1413 | dev_warn(&pdev->dev, |
cf34cba7 | 1414 | "mclk == 0! Please, fix your platform data. " |
3bc43840 | 1415 | "Using default 20MHz\n"); |
cf34cba7 | 1416 | pcdev->mclk = 20000000; |
3bc43840 GL |
1417 | } |
1418 | ||
cf34cba7 GL |
1419 | pcdev->dev = &pdev->dev; |
1420 | pcdev->mclk_divisor = mclk_get_divisor(pcdev); | |
1421 | ||
3bc43840 GL |
1422 | INIT_LIST_HEAD(&pcdev->capture); |
1423 | spin_lock_init(&pcdev->lock); | |
1424 | ||
1425 | /* | |
1426 | * Request the regions. | |
1427 | */ | |
1428 | if (!request_mem_region(res->start, res->end - res->start + 1, | |
1429 | PXA_CAM_DRV_NAME)) { | |
1430 | err = -EBUSY; | |
1431 | goto exit_clk; | |
1432 | } | |
1433 | ||
1434 | base = ioremap(res->start, res->end - res->start + 1); | |
1435 | if (!base) { | |
1436 | err = -ENOMEM; | |
1437 | goto exit_release; | |
1438 | } | |
1439 | pcdev->irq = irq; | |
1440 | pcdev->base = base; | |
3bc43840 GL |
1441 | |
1442 | /* request dma */ | |
de3e3b82 | 1443 | err = pxa_request_dma("CI_Y", DMA_PRIO_HIGH, |
1444 | pxa_camera_dma_irq_y, pcdev); | |
1445 | if (err < 0) { | |
3bc43840 | 1446 | dev_err(pcdev->dev, "Can't request DMA for Y\n"); |
3bc43840 GL |
1447 | goto exit_iounmap; |
1448 | } | |
de3e3b82 | 1449 | pcdev->dma_chans[0] = err; |
a5462e5b MR |
1450 | dev_dbg(pcdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]); |
1451 | ||
de3e3b82 | 1452 | err = pxa_request_dma("CI_U", DMA_PRIO_HIGH, |
1453 | pxa_camera_dma_irq_u, pcdev); | |
1454 | if (err < 0) { | |
a5462e5b | 1455 | dev_err(pcdev->dev, "Can't request DMA for U\n"); |
a5462e5b MR |
1456 | goto exit_free_dma_y; |
1457 | } | |
de3e3b82 | 1458 | pcdev->dma_chans[1] = err; |
a5462e5b MR |
1459 | dev_dbg(pcdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]); |
1460 | ||
de3e3b82 | 1461 | err = pxa_request_dma("CI_V", DMA_PRIO_HIGH, |
1462 | pxa_camera_dma_irq_v, pcdev); | |
1463 | if (err < 0) { | |
a5462e5b | 1464 | dev_err(pcdev->dev, "Can't request DMA for V\n"); |
a5462e5b MR |
1465 | goto exit_free_dma_u; |
1466 | } | |
de3e3b82 | 1467 | pcdev->dma_chans[2] = err; |
a5462e5b | 1468 | dev_dbg(pcdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]); |
3bc43840 | 1469 | |
87f3dd77 EM |
1470 | DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD; |
1471 | DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD; | |
1472 | DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD; | |
3bc43840 GL |
1473 | |
1474 | /* request irq */ | |
1475 | err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME, | |
1476 | pcdev); | |
1477 | if (err) { | |
1478 | dev_err(pcdev->dev, "Camera interrupt register failed \n"); | |
1479 | goto exit_free_dma; | |
1480 | } | |
1481 | ||
1482 | pxa_soc_camera_host.priv = pcdev; | |
1483 | pxa_soc_camera_host.dev.parent = &pdev->dev; | |
1484 | pxa_soc_camera_host.nr = pdev->id; | |
b8d9904c | 1485 | err = soc_camera_host_register(&pxa_soc_camera_host); |
3bc43840 GL |
1486 | if (err) |
1487 | goto exit_free_irq; | |
1488 | ||
1489 | return 0; | |
1490 | ||
1491 | exit_free_irq: | |
1492 | free_irq(pcdev->irq, pcdev); | |
1493 | exit_free_dma: | |
a5462e5b MR |
1494 | pxa_free_dma(pcdev->dma_chans[2]); |
1495 | exit_free_dma_u: | |
1496 | pxa_free_dma(pcdev->dma_chans[1]); | |
1497 | exit_free_dma_y: | |
1498 | pxa_free_dma(pcdev->dma_chans[0]); | |
3bc43840 GL |
1499 | exit_iounmap: |
1500 | iounmap(base); | |
1501 | exit_release: | |
1502 | release_mem_region(res->start, res->end - res->start + 1); | |
1503 | exit_clk: | |
1504 | clk_put(pcdev->clk); | |
1505 | exit_kfree: | |
1506 | kfree(pcdev); | |
1507 | exit: | |
1508 | return err; | |
1509 | } | |
1510 | ||
1511 | static int __devexit pxa_camera_remove(struct platform_device *pdev) | |
1512 | { | |
1513 | struct pxa_camera_dev *pcdev = platform_get_drvdata(pdev); | |
1514 | struct resource *res; | |
1515 | ||
1516 | clk_put(pcdev->clk); | |
1517 | ||
a5462e5b MR |
1518 | pxa_free_dma(pcdev->dma_chans[0]); |
1519 | pxa_free_dma(pcdev->dma_chans[1]); | |
1520 | pxa_free_dma(pcdev->dma_chans[2]); | |
3bc43840 GL |
1521 | free_irq(pcdev->irq, pcdev); |
1522 | ||
1523 | soc_camera_host_unregister(&pxa_soc_camera_host); | |
1524 | ||
1525 | iounmap(pcdev->base); | |
1526 | ||
1527 | res = pcdev->res; | |
1528 | release_mem_region(res->start, res->end - res->start + 1); | |
1529 | ||
1530 | kfree(pcdev); | |
1531 | ||
7102b773 | 1532 | dev_info(&pdev->dev, "PXA Camera driver unloaded\n"); |
3bc43840 | 1533 | |
3bc43840 GL |
1534 | return 0; |
1535 | } | |
1536 | ||
3bc43840 GL |
1537 | static struct platform_driver pxa_camera_driver = { |
1538 | .driver = { | |
1539 | .name = PXA_CAM_DRV_NAME, | |
1540 | }, | |
1541 | .probe = pxa_camera_probe, | |
1542 | .remove = __exit_p(pxa_camera_remove), | |
3bc43840 GL |
1543 | }; |
1544 | ||
1545 | ||
1546 | static int __devinit pxa_camera_init(void) | |
1547 | { | |
1548 | return platform_driver_register(&pxa_camera_driver); | |
1549 | } | |
1550 | ||
1551 | static void __exit pxa_camera_exit(void) | |
1552 | { | |
01c1e4ca | 1553 | platform_driver_unregister(&pxa_camera_driver); |
3bc43840 GL |
1554 | } |
1555 | ||
1556 | module_init(pxa_camera_init); | |
1557 | module_exit(pxa_camera_exit); | |
1558 | ||
1559 | MODULE_DESCRIPTION("PXA27x SoC Camera Host driver"); | |
1560 | MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>"); | |
1561 | MODULE_LICENSE("GPL"); |