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3bc43840 GL |
1 | /* |
2 | * V4L2 Driver for PXA camera host | |
3 | * | |
4 | * Copyright (C) 2006, Sascha Hauer, Pengutronix | |
5 | * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
3bc43840 GL |
13 | #include <linux/init.h> |
14 | #include <linux/module.h> | |
7102b773 | 15 | #include <linux/io.h> |
3bc43840 GL |
16 | #include <linux/delay.h> |
17 | #include <linux/dma-mapping.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/fs.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/mm.h> | |
23 | #include <linux/moduleparam.h> | |
24 | #include <linux/time.h> | |
3bc43840 GL |
25 | #include <linux/device.h> |
26 | #include <linux/platform_device.h> | |
3bc43840 | 27 | #include <linux/clk.h> |
d514edac | 28 | #include <linux/sched.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
3bc43840 GL |
30 | |
31 | #include <media/v4l2-common.h> | |
32 | #include <media/v4l2-dev.h> | |
092d3921 | 33 | #include <media/videobuf-dma-sg.h> |
3bc43840 | 34 | #include <media/soc_camera.h> |
760697be | 35 | #include <media/soc_mediabus.h> |
3bc43840 GL |
36 | |
37 | #include <linux/videodev2.h> | |
38 | ||
cfbaf4df | 39 | #include <mach/dma.h> |
a09e64fb | 40 | #include <mach/camera.h> |
3bc43840 | 41 | |
64dc3c1a | 42 | #define PXA_CAM_VERSION "0.0.6" |
3bc43840 GL |
43 | #define PXA_CAM_DRV_NAME "pxa27x-camera" |
44 | ||
5ca11fa3 EM |
45 | /* Camera Interface */ |
46 | #define CICR0 0x0000 | |
47 | #define CICR1 0x0004 | |
48 | #define CICR2 0x0008 | |
49 | #define CICR3 0x000C | |
50 | #define CICR4 0x0010 | |
51 | #define CISR 0x0014 | |
52 | #define CIFR 0x0018 | |
53 | #define CITOR 0x001C | |
54 | #define CIBR0 0x0028 | |
55 | #define CIBR1 0x0030 | |
56 | #define CIBR2 0x0038 | |
57 | ||
58 | #define CICR0_DMAEN (1 << 31) /* DMA request enable */ | |
59 | #define CICR0_PAR_EN (1 << 30) /* Parity enable */ | |
60 | #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */ | |
61 | #define CICR0_ENB (1 << 28) /* Camera interface enable */ | |
62 | #define CICR0_DIS (1 << 27) /* Camera interface disable */ | |
63 | #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */ | |
64 | #define CICR0_TOM (1 << 9) /* Time-out mask */ | |
65 | #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */ | |
66 | #define CICR0_FEM (1 << 7) /* FIFO-empty mask */ | |
67 | #define CICR0_EOLM (1 << 6) /* End-of-line mask */ | |
68 | #define CICR0_PERRM (1 << 5) /* Parity-error mask */ | |
69 | #define CICR0_QDM (1 << 4) /* Quick-disable mask */ | |
70 | #define CICR0_CDM (1 << 3) /* Disable-done mask */ | |
71 | #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */ | |
72 | #define CICR0_EOFM (1 << 1) /* End-of-frame mask */ | |
73 | #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */ | |
74 | ||
75 | #define CICR1_TBIT (1 << 31) /* Transparency bit */ | |
76 | #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */ | |
77 | #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */ | |
78 | #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */ | |
79 | #define CICR1_RGB_F (1 << 11) /* RGB format */ | |
80 | #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */ | |
81 | #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */ | |
82 | #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */ | |
83 | #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */ | |
84 | #define CICR1_DW (0x7 << 0) /* Data width mask */ | |
85 | ||
86 | #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock | |
87 | wait count mask */ | |
88 | #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock | |
89 | wait count mask */ | |
90 | #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */ | |
91 | #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock | |
92 | wait count mask */ | |
93 | #define CICR2_FSW (0x7 << 0) /* Frame stabilization | |
94 | wait count mask */ | |
95 | ||
96 | #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock | |
97 | wait count mask */ | |
98 | #define CICR3_EFW (0xff << 16) /* End-of-frame line clock | |
99 | wait count mask */ | |
100 | #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */ | |
101 | #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock | |
102 | wait count mask */ | |
103 | #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */ | |
104 | ||
105 | #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */ | |
106 | #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */ | |
107 | #define CICR4_PCP (1 << 22) /* Pixel clock polarity */ | |
108 | #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */ | |
109 | #define CICR4_VSP (1 << 20) /* Vertical sync polarity */ | |
110 | #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */ | |
111 | #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */ | |
112 | #define CICR4_DIV (0xff << 0) /* Clock divisor mask */ | |
113 | ||
114 | #define CISR_FTO (1 << 15) /* FIFO time-out */ | |
115 | #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */ | |
116 | #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */ | |
117 | #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */ | |
118 | #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */ | |
119 | #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */ | |
120 | #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */ | |
121 | #define CISR_EOL (1 << 8) /* End of line */ | |
122 | #define CISR_PAR_ERR (1 << 7) /* Parity error */ | |
123 | #define CISR_CQD (1 << 6) /* Camera interface quick disable */ | |
124 | #define CISR_CDD (1 << 5) /* Camera interface disable done */ | |
125 | #define CISR_SOF (1 << 4) /* Start of frame */ | |
126 | #define CISR_EOF (1 << 3) /* End of frame */ | |
127 | #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */ | |
128 | #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */ | |
129 | #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */ | |
130 | ||
131 | #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */ | |
132 | #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */ | |
133 | #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */ | |
134 | #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */ | |
135 | #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */ | |
136 | #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */ | |
137 | #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */ | |
138 | #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */ | |
139 | ||
7102b773 GL |
140 | #define CICR0_SIM_MP (0 << 24) |
141 | #define CICR0_SIM_SP (1 << 24) | |
142 | #define CICR0_SIM_MS (2 << 24) | |
143 | #define CICR0_SIM_EP (3 << 24) | |
144 | #define CICR0_SIM_ES (4 << 24) | |
145 | ||
146 | #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */ | |
147 | #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */ | |
a5462e5b MR |
148 | #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */ |
149 | #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */ | |
150 | #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */ | |
7102b773 GL |
151 | |
152 | #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */ | |
153 | #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */ | |
154 | #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */ | |
155 | #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */ | |
156 | #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */ | |
157 | ||
158 | #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */ | |
159 | #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */ | |
160 | #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */ | |
161 | #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */ | |
162 | ||
3bc43840 GL |
163 | #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \ |
164 | CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \ | |
165 | CICR0_EOFM | CICR0_FOM) | |
166 | ||
3bc43840 GL |
167 | /* |
168 | * Structures | |
169 | */ | |
a5462e5b MR |
170 | enum pxa_camera_active_dma { |
171 | DMA_Y = 0x1, | |
172 | DMA_U = 0x2, | |
173 | DMA_V = 0x4, | |
174 | }; | |
175 | ||
176 | /* descriptor needed for the PXA DMA engine */ | |
177 | struct pxa_cam_dma { | |
178 | dma_addr_t sg_dma; | |
179 | struct pxa_dma_desc *sg_cpu; | |
180 | size_t sg_size; | |
181 | int sglen; | |
182 | }; | |
3bc43840 GL |
183 | |
184 | /* buffer for one video frame */ | |
185 | struct pxa_buffer { | |
186 | /* common v4l buffer stuff -- must be first */ | |
760697be GL |
187 | struct videobuf_buffer vb; |
188 | enum v4l2_mbus_pixelcode code; | |
a5462e5b | 189 | /* our descriptor lists for Y, U and V channels */ |
760697be GL |
190 | struct pxa_cam_dma dmas[3]; |
191 | int inwork; | |
192 | enum pxa_camera_active_dma active_dma; | |
3bc43840 GL |
193 | }; |
194 | ||
3bc43840 | 195 | struct pxa_camera_dev { |
eb6c8558 | 196 | struct soc_camera_host soc_host; |
5d28d525 GL |
197 | /* |
198 | * PXA27x is only supposed to handle one camera on its Quick Capture | |
3bc43840 | 199 | * interface. If anyone ever builds hardware to enable more than |
5d28d525 GL |
200 | * one camera, they will have to modify this driver too |
201 | */ | |
3bc43840 GL |
202 | struct soc_camera_device *icd; |
203 | struct clk *clk; | |
204 | ||
205 | unsigned int irq; | |
206 | void __iomem *base; | |
a5462e5b | 207 | |
e7c50688 | 208 | int channels; |
a5462e5b | 209 | unsigned int dma_chans[3]; |
3bc43840 | 210 | |
3bc43840 GL |
211 | struct pxacamera_platform_data *pdata; |
212 | struct resource *res; | |
213 | unsigned long platform_flags; | |
cf34cba7 GL |
214 | unsigned long ciclk; |
215 | unsigned long mclk; | |
216 | u32 mclk_divisor; | |
3bc43840 GL |
217 | |
218 | struct list_head capture; | |
219 | ||
220 | spinlock_t lock; | |
221 | ||
3bc43840 | 222 | struct pxa_buffer *active; |
5aa2110f | 223 | struct pxa_dma_desc *sg_tail[3]; |
3f6ac497 RJ |
224 | |
225 | u32 save_cicr[5]; | |
3bc43840 GL |
226 | }; |
227 | ||
6a6c8786 GL |
228 | struct pxa_cam { |
229 | unsigned long flags; | |
230 | }; | |
231 | ||
3bc43840 GL |
232 | static const char *pxa_cam_driver_description = "PXA_Camera"; |
233 | ||
234 | static unsigned int vid_limit = 16; /* Video memory limit, in Mb */ | |
235 | ||
236 | /* | |
237 | * Videobuf operations | |
238 | */ | |
7102b773 GL |
239 | static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count, |
240 | unsigned int *size) | |
3bc43840 GL |
241 | { |
242 | struct soc_camera_device *icd = vq->priv_data; | |
760697be GL |
243 | int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width, |
244 | icd->current_fmt->host_fmt); | |
245 | ||
246 | if (bytes_per_line < 0) | |
247 | return bytes_per_line; | |
3bc43840 | 248 | |
0166b743 | 249 | dev_dbg(icd->dev.parent, "count=%d, size=%d\n", *count, *size); |
3bc43840 | 250 | |
760697be | 251 | *size = bytes_per_line * icd->user_height; |
3bc43840 GL |
252 | |
253 | if (0 == *count) | |
254 | *count = 32; | |
dab7e310 AB |
255 | if (*size * *count > vid_limit * 1024 * 1024) |
256 | *count = (vid_limit * 1024 * 1024) / *size; | |
3bc43840 GL |
257 | |
258 | return 0; | |
259 | } | |
260 | ||
261 | static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf) | |
262 | { | |
263 | struct soc_camera_device *icd = vq->priv_data; | |
64f5905e | 264 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
3bc43840 | 265 | struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb); |
a5462e5b | 266 | int i; |
3bc43840 GL |
267 | |
268 | BUG_ON(in_interrupt()); | |
269 | ||
0166b743 | 270 | dev_dbg(icd->dev.parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
271 | &buf->vb, buf->vb.baddr, buf->vb.bsize); |
272 | ||
5d28d525 GL |
273 | /* |
274 | * This waits until this buffer is out of danger, i.e., until it is no | |
275 | * longer in STATE_QUEUED or STATE_ACTIVE | |
276 | */ | |
0e0809a5 | 277 | videobuf_waiton(vq, &buf->vb, 0, 0); |
95268403 | 278 | videobuf_dma_unmap(vq->dev, dma); |
3bc43840 GL |
279 | videobuf_dma_free(dma); |
280 | ||
a5462e5b MR |
281 | for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) { |
282 | if (buf->dmas[i].sg_cpu) | |
96c75399 GL |
283 | dma_free_coherent(ici->v4l2_dev.dev, |
284 | buf->dmas[i].sg_size, | |
a5462e5b MR |
285 | buf->dmas[i].sg_cpu, |
286 | buf->dmas[i].sg_dma); | |
287 | buf->dmas[i].sg_cpu = NULL; | |
288 | } | |
3bc43840 GL |
289 | |
290 | buf->vb.state = VIDEOBUF_NEEDS_INIT; | |
291 | } | |
292 | ||
37f5aefd RJ |
293 | static int calculate_dma_sglen(struct scatterlist *sglist, int sglen, |
294 | int sg_first_ofs, int size) | |
295 | { | |
296 | int i, offset, dma_len, xfer_len; | |
297 | struct scatterlist *sg; | |
298 | ||
299 | offset = sg_first_ofs; | |
300 | for_each_sg(sglist, sg, sglen, i) { | |
301 | dma_len = sg_dma_len(sg); | |
302 | ||
303 | /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */ | |
304 | xfer_len = roundup(min(dma_len - offset, size), 8); | |
305 | ||
306 | size = max(0, size - xfer_len); | |
307 | offset = 0; | |
308 | if (size == 0) | |
309 | break; | |
310 | } | |
311 | ||
312 | BUG_ON(size != 0); | |
313 | return i + 1; | |
314 | } | |
315 | ||
316 | /** | |
317 | * pxa_init_dma_channel - init dma descriptors | |
318 | * @pcdev: pxa camera device | |
319 | * @buf: pxa buffer to find pxa dma channel | |
320 | * @dma: dma video buffer | |
321 | * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V') | |
322 | * @cibr: camera Receive Buffer Register | |
323 | * @size: bytes to transfer | |
324 | * @sg_first: first element of sg_list | |
325 | * @sg_first_ofs: offset in first element of sg_list | |
326 | * | |
327 | * Prepares the pxa dma descriptors to transfer one camera channel. | |
328 | * Beware sg_first and sg_first_ofs are both input and output parameters. | |
329 | * | |
330 | * Returns 0 or -ENOMEM if no coherent memory is available | |
331 | */ | |
a5462e5b MR |
332 | static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev, |
333 | struct pxa_buffer *buf, | |
334 | struct videobuf_dmabuf *dma, int channel, | |
37f5aefd RJ |
335 | int cibr, int size, |
336 | struct scatterlist **sg_first, int *sg_first_ofs) | |
a5462e5b MR |
337 | { |
338 | struct pxa_cam_dma *pxa_dma = &buf->dmas[channel]; | |
979ea1dd | 339 | struct device *dev = pcdev->soc_host.v4l2_dev.dev; |
37f5aefd RJ |
340 | struct scatterlist *sg; |
341 | int i, offset, sglen; | |
342 | int dma_len = 0, xfer_len = 0; | |
a5462e5b MR |
343 | |
344 | if (pxa_dma->sg_cpu) | |
979ea1dd | 345 | dma_free_coherent(dev, pxa_dma->sg_size, |
a5462e5b MR |
346 | pxa_dma->sg_cpu, pxa_dma->sg_dma); |
347 | ||
37f5aefd RJ |
348 | sglen = calculate_dma_sglen(*sg_first, dma->sglen, |
349 | *sg_first_ofs, size); | |
350 | ||
a5462e5b | 351 | pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc); |
979ea1dd | 352 | pxa_dma->sg_cpu = dma_alloc_coherent(dev, pxa_dma->sg_size, |
a5462e5b MR |
353 | &pxa_dma->sg_dma, GFP_KERNEL); |
354 | if (!pxa_dma->sg_cpu) | |
355 | return -ENOMEM; | |
356 | ||
357 | pxa_dma->sglen = sglen; | |
37f5aefd | 358 | offset = *sg_first_ofs; |
a5462e5b | 359 | |
979ea1dd | 360 | dev_dbg(dev, "DMA: sg_first=%p, sglen=%d, ofs=%d, dma.desc=%x\n", |
37f5aefd | 361 | *sg_first, sglen, *sg_first_ofs, pxa_dma->sg_dma); |
a5462e5b | 362 | |
37f5aefd RJ |
363 | |
364 | for_each_sg(*sg_first, sg, sglen, i) { | |
365 | dma_len = sg_dma_len(sg); | |
a5462e5b MR |
366 | |
367 | /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */ | |
37f5aefd | 368 | xfer_len = roundup(min(dma_len - offset, size), 8); |
a5462e5b | 369 | |
37f5aefd RJ |
370 | size = max(0, size - xfer_len); |
371 | ||
372 | pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr; | |
373 | pxa_dma->sg_cpu[i].dtadr = sg_dma_address(sg) + offset; | |
a5462e5b MR |
374 | pxa_dma->sg_cpu[i].dcmd = |
375 | DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len; | |
256b0233 RJ |
376 | #ifdef DEBUG |
377 | if (!i) | |
378 | pxa_dma->sg_cpu[i].dcmd |= DCMD_STARTIRQEN; | |
379 | #endif | |
a5462e5b MR |
380 | pxa_dma->sg_cpu[i].ddadr = |
381 | pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc); | |
37f5aefd | 382 | |
979ea1dd | 383 | dev_vdbg(dev, "DMA: desc.%08x->@phys=0x%08x, len=%d\n", |
37f5aefd RJ |
384 | pxa_dma->sg_dma + i * sizeof(struct pxa_dma_desc), |
385 | sg_dma_address(sg) + offset, xfer_len); | |
386 | offset = 0; | |
387 | ||
388 | if (size == 0) | |
389 | break; | |
a5462e5b MR |
390 | } |
391 | ||
256b0233 RJ |
392 | pxa_dma->sg_cpu[sglen].ddadr = DDADR_STOP; |
393 | pxa_dma->sg_cpu[sglen].dcmd = DCMD_FLOWSRC | DCMD_BURST8 | DCMD_ENDIRQEN; | |
a5462e5b | 394 | |
37f5aefd RJ |
395 | /* |
396 | * Handle 1 special case : | |
397 | * - in 3 planes (YUV422P format), we might finish with xfer_len equal | |
398 | * to dma_len (end on PAGE boundary). In this case, the sg element | |
399 | * for next plane should be the next after the last used to store the | |
400 | * last scatter gather RAM page | |
401 | */ | |
402 | if (xfer_len >= dma_len) { | |
403 | *sg_first_ofs = xfer_len - dma_len; | |
404 | *sg_first = sg_next(sg); | |
405 | } else { | |
406 | *sg_first_ofs = xfer_len; | |
407 | *sg_first = sg; | |
408 | } | |
409 | ||
a5462e5b MR |
410 | return 0; |
411 | } | |
412 | ||
256b0233 RJ |
413 | static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev, |
414 | struct pxa_buffer *buf) | |
415 | { | |
416 | buf->active_dma = DMA_Y; | |
417 | if (pcdev->channels == 3) | |
418 | buf->active_dma |= DMA_U | DMA_V; | |
419 | } | |
420 | ||
421 | /* | |
422 | * Please check the DMA prepared buffer structure in : | |
423 | * Documentation/video4linux/pxa_camera.txt | |
424 | * Please check also in pxa_camera_check_link_miss() to understand why DMA chain | |
425 | * modification while DMA chain is running will work anyway. | |
426 | */ | |
7102b773 GL |
427 | static int pxa_videobuf_prepare(struct videobuf_queue *vq, |
428 | struct videobuf_buffer *vb, enum v4l2_field field) | |
3bc43840 GL |
429 | { |
430 | struct soc_camera_device *icd = vq->priv_data; | |
64f5905e | 431 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
3bc43840 | 432 | struct pxa_camera_dev *pcdev = ici->priv; |
979ea1dd | 433 | struct device *dev = pcdev->soc_host.v4l2_dev.dev; |
3bc43840 | 434 | struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); |
a5462e5b | 435 | int ret; |
a5462e5b | 436 | int size_y, size_u = 0, size_v = 0; |
760697be GL |
437 | int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width, |
438 | icd->current_fmt->host_fmt); | |
439 | ||
440 | if (bytes_per_line < 0) | |
441 | return bytes_per_line; | |
3bc43840 | 442 | |
979ea1dd | 443 | dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
444 | vb, vb->baddr, vb->bsize); |
445 | ||
446 | /* Added list head initialization on alloc */ | |
447 | WARN_ON(!list_empty(&vb->queue)); | |
448 | ||
449 | #ifdef DEBUG | |
5d28d525 GL |
450 | /* |
451 | * This can be useful if you want to see if we actually fill | |
452 | * the buffer with something | |
453 | */ | |
3bc43840 GL |
454 | memset((void *)vb->baddr, 0xaa, vb->bsize); |
455 | #endif | |
456 | ||
457 | BUG_ON(NULL == icd->current_fmt); | |
458 | ||
5d28d525 GL |
459 | /* |
460 | * I think, in buf_prepare you only have to protect global data, | |
461 | * the actual buffer is yours | |
462 | */ | |
3bc43840 GL |
463 | buf->inwork = 1; |
464 | ||
760697be | 465 | if (buf->code != icd->current_fmt->code || |
6a6c8786 GL |
466 | vb->width != icd->user_width || |
467 | vb->height != icd->user_height || | |
3bc43840 | 468 | vb->field != field) { |
760697be | 469 | buf->code = icd->current_fmt->code; |
6a6c8786 GL |
470 | vb->width = icd->user_width; |
471 | vb->height = icd->user_height; | |
3bc43840 GL |
472 | vb->field = field; |
473 | vb->state = VIDEOBUF_NEEDS_INIT; | |
474 | } | |
475 | ||
760697be | 476 | vb->size = bytes_per_line * vb->height; |
3bc43840 GL |
477 | if (0 != vb->baddr && vb->bsize < vb->size) { |
478 | ret = -EINVAL; | |
479 | goto out; | |
480 | } | |
481 | ||
482 | if (vb->state == VIDEOBUF_NEEDS_INIT) { | |
37f5aefd RJ |
483 | int size = vb->size; |
484 | int next_ofs = 0; | |
3bc43840 | 485 | struct videobuf_dmabuf *dma = videobuf_to_dma(vb); |
37f5aefd | 486 | struct scatterlist *sg; |
3bc43840 GL |
487 | |
488 | ret = videobuf_iolock(vq, vb, NULL); | |
489 | if (ret) | |
490 | goto fail; | |
491 | ||
5aa2110f | 492 | if (pcdev->channels == 3) { |
a5462e5b MR |
493 | size_y = size / 2; |
494 | size_u = size_v = size / 4; | |
495 | } else { | |
a5462e5b MR |
496 | size_y = size; |
497 | } | |
498 | ||
37f5aefd | 499 | sg = dma->sglist; |
3bc43840 | 500 | |
37f5aefd RJ |
501 | /* init DMA for Y channel */ |
502 | ret = pxa_init_dma_channel(pcdev, buf, dma, 0, CIBR0, size_y, | |
503 | &sg, &next_ofs); | |
a5462e5b | 504 | if (ret) { |
979ea1dd | 505 | dev_err(dev, "DMA initialization for Y/RGB failed\n"); |
3bc43840 GL |
506 | goto fail; |
507 | } | |
508 | ||
37f5aefd RJ |
509 | /* init DMA for U channel */ |
510 | if (size_u) | |
511 | ret = pxa_init_dma_channel(pcdev, buf, dma, 1, CIBR1, | |
512 | size_u, &sg, &next_ofs); | |
513 | if (ret) { | |
979ea1dd | 514 | dev_err(dev, "DMA initialization for U failed\n"); |
37f5aefd RJ |
515 | goto fail_u; |
516 | } | |
517 | ||
518 | /* init DMA for V channel */ | |
519 | if (size_v) | |
520 | ret = pxa_init_dma_channel(pcdev, buf, dma, 2, CIBR2, | |
521 | size_v, &sg, &next_ofs); | |
522 | if (ret) { | |
979ea1dd | 523 | dev_err(dev, "DMA initialization for V failed\n"); |
37f5aefd | 524 | goto fail_v; |
3bc43840 | 525 | } |
3bc43840 GL |
526 | |
527 | vb->state = VIDEOBUF_PREPARED; | |
528 | } | |
529 | ||
530 | buf->inwork = 0; | |
256b0233 | 531 | pxa_videobuf_set_actdma(pcdev, buf); |
3bc43840 GL |
532 | |
533 | return 0; | |
534 | ||
a5462e5b | 535 | fail_v: |
979ea1dd | 536 | dma_free_coherent(dev, buf->dmas[1].sg_size, |
a5462e5b MR |
537 | buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma); |
538 | fail_u: | |
979ea1dd | 539 | dma_free_coherent(dev, buf->dmas[0].sg_size, |
a5462e5b | 540 | buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma); |
3bc43840 GL |
541 | fail: |
542 | free_buffer(vq, buf); | |
543 | out: | |
544 | buf->inwork = 0; | |
545 | return ret; | |
546 | } | |
547 | ||
256b0233 RJ |
548 | /** |
549 | * pxa_dma_start_channels - start DMA channel for active buffer | |
550 | * @pcdev: pxa camera device | |
551 | * | |
552 | * Initialize DMA channels to the beginning of the active video buffer, and | |
553 | * start these channels. | |
554 | */ | |
555 | static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev) | |
556 | { | |
557 | int i; | |
558 | struct pxa_buffer *active; | |
559 | ||
560 | active = pcdev->active; | |
561 | ||
562 | for (i = 0; i < pcdev->channels; i++) { | |
0166b743 GL |
563 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, |
564 | "%s (channel=%d) ddadr=%08x\n", __func__, | |
256b0233 RJ |
565 | i, active->dmas[i].sg_dma); |
566 | DDADR(pcdev->dma_chans[i]) = active->dmas[i].sg_dma; | |
567 | DCSR(pcdev->dma_chans[i]) = DCSR_RUN; | |
568 | } | |
569 | } | |
570 | ||
571 | static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev) | |
572 | { | |
573 | int i; | |
574 | ||
575 | for (i = 0; i < pcdev->channels; i++) { | |
0166b743 GL |
576 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, |
577 | "%s (channel=%d)\n", __func__, i); | |
256b0233 RJ |
578 | DCSR(pcdev->dma_chans[i]) = 0; |
579 | } | |
580 | } | |
581 | ||
256b0233 RJ |
582 | static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev, |
583 | struct pxa_buffer *buf) | |
584 | { | |
585 | int i; | |
586 | struct pxa_dma_desc *buf_last_desc; | |
587 | ||
588 | for (i = 0; i < pcdev->channels; i++) { | |
589 | buf_last_desc = buf->dmas[i].sg_cpu + buf->dmas[i].sglen; | |
590 | buf_last_desc->ddadr = DDADR_STOP; | |
591 | ||
ae7410e7 GL |
592 | if (pcdev->sg_tail[i]) |
593 | /* Link the new buffer to the old tail */ | |
594 | pcdev->sg_tail[i]->ddadr = buf->dmas[i].sg_dma; | |
256b0233 | 595 | |
ae7410e7 GL |
596 | /* Update the channel tail */ |
597 | pcdev->sg_tail[i] = buf_last_desc; | |
598 | } | |
256b0233 RJ |
599 | } |
600 | ||
601 | /** | |
602 | * pxa_camera_start_capture - start video capturing | |
603 | * @pcdev: camera device | |
604 | * | |
605 | * Launch capturing. DMA channels should not be active yet. They should get | |
606 | * activated at the end of frame interrupt, to capture only whole frames, and | |
607 | * never begin the capture of a partial frame. | |
608 | */ | |
609 | static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev) | |
610 | { | |
a47f6be4 | 611 | unsigned long cicr0; |
256b0233 | 612 | |
979ea1dd | 613 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__); |
256b0233 RJ |
614 | /* Enable End-Of-Frame Interrupt */ |
615 | cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB; | |
616 | cicr0 &= ~CICR0_EOFM; | |
617 | __raw_writel(cicr0, pcdev->base + CICR0); | |
618 | } | |
619 | ||
620 | static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev) | |
621 | { | |
622 | unsigned long cicr0; | |
623 | ||
624 | pxa_dma_stop_channels(pcdev); | |
625 | ||
626 | cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB; | |
627 | __raw_writel(cicr0, pcdev->base + CICR0); | |
628 | ||
8c62e221 | 629 | pcdev->active = NULL; |
979ea1dd | 630 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__); |
256b0233 RJ |
631 | } |
632 | ||
2dd54a54 | 633 | /* Called under spinlock_irqsave(&pcdev->lock, ...) */ |
7102b773 GL |
634 | static void pxa_videobuf_queue(struct videobuf_queue *vq, |
635 | struct videobuf_buffer *vb) | |
3bc43840 GL |
636 | { |
637 | struct soc_camera_device *icd = vq->priv_data; | |
64f5905e | 638 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
3bc43840 GL |
639 | struct pxa_camera_dev *pcdev = ici->priv; |
640 | struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); | |
3bc43840 | 641 | |
0166b743 GL |
642 | dev_dbg(icd->dev.parent, "%s (vb=0x%p) 0x%08lx %d active=%p\n", |
643 | __func__, vb, vb->baddr, vb->bsize, pcdev->active); | |
256b0233 | 644 | |
3bc43840 GL |
645 | list_add_tail(&vb->queue, &pcdev->capture); |
646 | ||
647 | vb->state = VIDEOBUF_ACTIVE; | |
256b0233 | 648 | pxa_dma_add_tail_buf(pcdev, buf); |
3bc43840 | 649 | |
256b0233 RJ |
650 | if (!pcdev->active) |
651 | pxa_camera_start_capture(pcdev); | |
3bc43840 GL |
652 | } |
653 | ||
654 | static void pxa_videobuf_release(struct videobuf_queue *vq, | |
655 | struct videobuf_buffer *vb) | |
656 | { | |
657 | struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); | |
658 | #ifdef DEBUG | |
659 | struct soc_camera_device *icd = vq->priv_data; | |
0166b743 | 660 | struct device *dev = icd->dev.parent; |
3bc43840 | 661 | |
0166b743 | 662 | dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
663 | vb, vb->baddr, vb->bsize); |
664 | ||
665 | switch (vb->state) { | |
666 | case VIDEOBUF_ACTIVE: | |
0166b743 | 667 | dev_dbg(dev, "%s (active)\n", __func__); |
3bc43840 GL |
668 | break; |
669 | case VIDEOBUF_QUEUED: | |
0166b743 | 670 | dev_dbg(dev, "%s (queued)\n", __func__); |
3bc43840 GL |
671 | break; |
672 | case VIDEOBUF_PREPARED: | |
0166b743 | 673 | dev_dbg(dev, "%s (prepared)\n", __func__); |
3bc43840 GL |
674 | break; |
675 | default: | |
0166b743 | 676 | dev_dbg(dev, "%s (unknown)\n", __func__); |
3bc43840 GL |
677 | break; |
678 | } | |
679 | #endif | |
680 | ||
681 | free_buffer(vq, buf); | |
682 | } | |
683 | ||
a5462e5b MR |
684 | static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev, |
685 | struct videobuf_buffer *vb, | |
686 | struct pxa_buffer *buf) | |
687 | { | |
256b0233 | 688 | int i; |
5ca11fa3 | 689 | |
a5462e5b MR |
690 | /* _init is used to debug races, see comment in pxa_camera_reqbufs() */ |
691 | list_del_init(&vb->queue); | |
692 | vb->state = VIDEOBUF_DONE; | |
693 | do_gettimeofday(&vb->ts); | |
694 | vb->field_count++; | |
695 | wake_up(&vb->done); | |
979ea1dd GL |
696 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s dequeud buffer (vb=0x%p)\n", |
697 | __func__, vb); | |
a5462e5b MR |
698 | |
699 | if (list_empty(&pcdev->capture)) { | |
256b0233 | 700 | pxa_camera_stop_capture(pcdev); |
256b0233 RJ |
701 | for (i = 0; i < pcdev->channels; i++) |
702 | pcdev->sg_tail[i] = NULL; | |
a5462e5b MR |
703 | return; |
704 | } | |
705 | ||
706 | pcdev->active = list_entry(pcdev->capture.next, | |
707 | struct pxa_buffer, vb.queue); | |
708 | } | |
709 | ||
256b0233 RJ |
710 | /** |
711 | * pxa_camera_check_link_miss - check missed DMA linking | |
712 | * @pcdev: camera device | |
713 | * | |
714 | * The DMA chaining is done with DMA running. This means a tiny temporal window | |
715 | * remains, where a buffer is queued on the chain, while the chain is already | |
25985edc | 716 | * stopped. This means the tailed buffer would never be transferred by DMA. |
256b0233 RJ |
717 | * This function restarts the capture for this corner case, where : |
718 | * - DADR() == DADDR_STOP | |
719 | * - a videobuffer is queued on the pcdev->capture list | |
720 | * | |
721 | * Please check the "DMA hot chaining timeslice issue" in | |
722 | * Documentation/video4linux/pxa_camera.txt | |
723 | * | |
724 | * Context: should only be called within the dma irq handler | |
725 | */ | |
726 | static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev) | |
727 | { | |
728 | int i, is_dma_stopped = 1; | |
729 | ||
730 | for (i = 0; i < pcdev->channels; i++) | |
731 | if (DDADR(pcdev->dma_chans[i]) != DDADR_STOP) | |
732 | is_dma_stopped = 0; | |
979ea1dd GL |
733 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, |
734 | "%s : top queued buffer=%p, dma_stopped=%d\n", | |
256b0233 RJ |
735 | __func__, pcdev->active, is_dma_stopped); |
736 | if (pcdev->active && is_dma_stopped) | |
737 | pxa_camera_start_capture(pcdev); | |
738 | } | |
739 | ||
a5462e5b MR |
740 | static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev, |
741 | enum pxa_camera_active_dma act_dma) | |
3bc43840 | 742 | { |
979ea1dd | 743 | struct device *dev = pcdev->soc_host.v4l2_dev.dev; |
3bc43840 GL |
744 | struct pxa_buffer *buf; |
745 | unsigned long flags; | |
e7c50688 | 746 | u32 status, camera_status, overrun; |
3bc43840 GL |
747 | struct videobuf_buffer *vb; |
748 | ||
749 | spin_lock_irqsave(&pcdev->lock, flags); | |
750 | ||
a5462e5b | 751 | status = DCSR(channel); |
256b0233 RJ |
752 | DCSR(channel) = status; |
753 | ||
754 | camera_status = __raw_readl(pcdev->base + CISR); | |
755 | overrun = CISR_IFO_0; | |
756 | if (pcdev->channels == 3) | |
757 | overrun |= CISR_IFO_1 | CISR_IFO_2; | |
7102b773 | 758 | |
3bc43840 | 759 | if (status & DCSR_BUSERR) { |
979ea1dd | 760 | dev_err(dev, "DMA Bus Error IRQ!\n"); |
3bc43840 GL |
761 | goto out; |
762 | } | |
763 | ||
256b0233 | 764 | if (!(status & (DCSR_ENDINTR | DCSR_STARTINTR))) { |
979ea1dd GL |
765 | dev_err(dev, "Unknown DMA IRQ source, status: 0x%08x\n", |
766 | status); | |
3bc43840 GL |
767 | goto out; |
768 | } | |
769 | ||
8c62e221 RJ |
770 | /* |
771 | * pcdev->active should not be NULL in DMA irq handler. | |
772 | * | |
773 | * But there is one corner case : if capture was stopped due to an | |
774 | * overrun of channel 1, and at that same channel 2 was completed. | |
775 | * | |
776 | * When handling the overrun in DMA irq for channel 1, we'll stop the | |
777 | * capture and restart it (and thus set pcdev->active to NULL). But the | |
778 | * DMA irq handler will already be pending for channel 2. So on entering | |
779 | * the DMA irq handler for channel 2 there will be no active buffer, yet | |
780 | * that is normal. | |
781 | */ | |
782 | if (!pcdev->active) | |
3bc43840 | 783 | goto out; |
3bc43840 GL |
784 | |
785 | vb = &pcdev->active->vb; | |
786 | buf = container_of(vb, struct pxa_buffer, vb); | |
787 | WARN_ON(buf->inwork || list_empty(&vb->queue)); | |
3bc43840 | 788 | |
979ea1dd | 789 | dev_dbg(dev, "%s channel=%d %s%s(vb=0x%p) dma.desc=%x\n", |
256b0233 RJ |
790 | __func__, channel, status & DCSR_STARTINTR ? "SOF " : "", |
791 | status & DCSR_ENDINTR ? "EOF " : "", vb, DDADR(channel)); | |
792 | ||
793 | if (status & DCSR_ENDINTR) { | |
8c62e221 RJ |
794 | /* |
795 | * It's normal if the last frame creates an overrun, as there | |
796 | * are no more DMA descriptors to fetch from QCI fifos | |
797 | */ | |
798 | if (camera_status & overrun && | |
799 | !list_is_last(pcdev->capture.next, &pcdev->capture)) { | |
979ea1dd | 800 | dev_dbg(dev, "FIFO overrun! CISR: %x\n", |
256b0233 RJ |
801 | camera_status); |
802 | pxa_camera_stop_capture(pcdev); | |
803 | pxa_camera_start_capture(pcdev); | |
804 | goto out; | |
805 | } | |
806 | buf->active_dma &= ~act_dma; | |
807 | if (!buf->active_dma) { | |
808 | pxa_camera_wakeup(pcdev, vb, buf); | |
809 | pxa_camera_check_link_miss(pcdev); | |
810 | } | |
811 | } | |
3bc43840 GL |
812 | |
813 | out: | |
814 | spin_unlock_irqrestore(&pcdev->lock, flags); | |
815 | } | |
816 | ||
a5462e5b MR |
817 | static void pxa_camera_dma_irq_y(int channel, void *data) |
818 | { | |
819 | struct pxa_camera_dev *pcdev = data; | |
820 | pxa_camera_dma_irq(channel, pcdev, DMA_Y); | |
821 | } | |
822 | ||
823 | static void pxa_camera_dma_irq_u(int channel, void *data) | |
824 | { | |
825 | struct pxa_camera_dev *pcdev = data; | |
826 | pxa_camera_dma_irq(channel, pcdev, DMA_U); | |
827 | } | |
828 | ||
829 | static void pxa_camera_dma_irq_v(int channel, void *data) | |
830 | { | |
831 | struct pxa_camera_dev *pcdev = data; | |
832 | pxa_camera_dma_irq(channel, pcdev, DMA_V); | |
833 | } | |
834 | ||
7102b773 | 835 | static struct videobuf_queue_ops pxa_videobuf_ops = { |
3bc43840 GL |
836 | .buf_setup = pxa_videobuf_setup, |
837 | .buf_prepare = pxa_videobuf_prepare, | |
838 | .buf_queue = pxa_videobuf_queue, | |
839 | .buf_release = pxa_videobuf_release, | |
840 | }; | |
841 | ||
a034d1b7 | 842 | static void pxa_camera_init_videobuf(struct videobuf_queue *q, |
092d3921 PZ |
843 | struct soc_camera_device *icd) |
844 | { | |
a034d1b7 MD |
845 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
846 | struct pxa_camera_dev *pcdev = ici->priv; | |
847 | ||
5d28d525 GL |
848 | /* |
849 | * We must pass NULL as dev pointer, then all pci_* dma operations | |
850 | * transform to normal dma_* ones. | |
851 | */ | |
a034d1b7 | 852 | videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock, |
092d3921 | 853 | V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE, |
b6a633c1 | 854 | sizeof(struct pxa_buffer), icd, &icd->video_lock); |
092d3921 PZ |
855 | } |
856 | ||
40e2e092 GL |
857 | static u32 mclk_get_divisor(struct platform_device *pdev, |
858 | struct pxa_camera_dev *pcdev) | |
3bc43840 | 859 | { |
cf34cba7 | 860 | unsigned long mclk = pcdev->mclk; |
6a6c8786 | 861 | struct device *dev = &pdev->dev; |
cf34cba7 | 862 | u32 div; |
3bc43840 GL |
863 | unsigned long lcdclk; |
864 | ||
cf34cba7 GL |
865 | lcdclk = clk_get_rate(pcdev->clk); |
866 | pcdev->ciclk = lcdclk; | |
3bc43840 | 867 | |
cf34cba7 GL |
868 | /* mclk <= ciclk / 4 (27.4.2) */ |
869 | if (mclk > lcdclk / 4) { | |
870 | mclk = lcdclk / 4; | |
979ea1dd | 871 | dev_warn(dev, "Limiting master clock to %lu\n", mclk); |
cf34cba7 GL |
872 | } |
873 | ||
874 | /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */ | |
875 | div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1; | |
3bc43840 | 876 | |
cf34cba7 GL |
877 | /* If we're not supplying MCLK, leave it at 0 */ |
878 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
879 | pcdev->mclk = lcdclk / (2 * (div + 1)); | |
3bc43840 | 880 | |
979ea1dd | 881 | dev_dbg(dev, "LCD clock %luHz, target freq %luHz, divisor %u\n", |
40e2e092 | 882 | lcdclk, mclk, div); |
3bc43840 GL |
883 | |
884 | return div; | |
885 | } | |
886 | ||
cf34cba7 GL |
887 | static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev, |
888 | unsigned long pclk) | |
889 | { | |
890 | /* We want a timeout > 1 pixel time, not ">=" */ | |
891 | u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1; | |
892 | ||
893 | __raw_writel(ciclk_per_pixel, pcdev->base + CITOR); | |
894 | } | |
895 | ||
7102b773 | 896 | static void pxa_camera_activate(struct pxa_camera_dev *pcdev) |
3bc43840 | 897 | { |
3bc43840 GL |
898 | u32 cicr4 = 0; |
899 | ||
5ca11fa3 EM |
900 | /* disable all interrupts */ |
901 | __raw_writel(0x3ff, pcdev->base + CICR0); | |
3bc43840 GL |
902 | |
903 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
904 | cicr4 |= CICR4_PCLK_EN; | |
905 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
906 | cicr4 |= CICR4_MCLK_EN; | |
907 | if (pcdev->platform_flags & PXA_CAMERA_PCP) | |
908 | cicr4 |= CICR4_PCP; | |
909 | if (pcdev->platform_flags & PXA_CAMERA_HSP) | |
910 | cicr4 |= CICR4_HSP; | |
911 | if (pcdev->platform_flags & PXA_CAMERA_VSP) | |
912 | cicr4 |= CICR4_VSP; | |
913 | ||
cf34cba7 GL |
914 | __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4); |
915 | ||
916 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
917 | /* Initialise the timeout under the assumption pclk = mclk */ | |
918 | recalculate_fifo_timeout(pcdev, pcdev->mclk); | |
919 | else | |
920 | /* "Safe default" - 13MHz */ | |
921 | recalculate_fifo_timeout(pcdev, 13000000); | |
3bc43840 GL |
922 | |
923 | clk_enable(pcdev->clk); | |
924 | } | |
925 | ||
7102b773 | 926 | static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev) |
3bc43840 | 927 | { |
3bc43840 | 928 | clk_disable(pcdev->clk); |
3bc43840 GL |
929 | } |
930 | ||
931 | static irqreturn_t pxa_camera_irq(int irq, void *data) | |
932 | { | |
933 | struct pxa_camera_dev *pcdev = data; | |
a47f6be4 | 934 | unsigned long status, cifr, cicr0; |
256b0233 RJ |
935 | struct pxa_buffer *buf; |
936 | struct videobuf_buffer *vb; | |
3bc43840 | 937 | |
5ca11fa3 | 938 | status = __raw_readl(pcdev->base + CISR); |
0166b743 GL |
939 | dev_dbg(pcdev->soc_host.v4l2_dev.dev, |
940 | "Camera interrupt status 0x%lx\n", status); | |
3bc43840 | 941 | |
e7c50688 GL |
942 | if (!status) |
943 | return IRQ_NONE; | |
944 | ||
5ca11fa3 | 945 | __raw_writel(status, pcdev->base + CISR); |
e7c50688 GL |
946 | |
947 | if (status & CISR_EOF) { | |
a47f6be4 SH |
948 | /* Reset the FIFOs */ |
949 | cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F; | |
950 | __raw_writel(cifr, pcdev->base + CIFR); | |
951 | ||
256b0233 RJ |
952 | pcdev->active = list_first_entry(&pcdev->capture, |
953 | struct pxa_buffer, vb.queue); | |
954 | vb = &pcdev->active->vb; | |
955 | buf = container_of(vb, struct pxa_buffer, vb); | |
956 | pxa_videobuf_set_actdma(pcdev, buf); | |
957 | ||
958 | pxa_dma_start_channels(pcdev); | |
959 | ||
5ca11fa3 EM |
960 | cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM; |
961 | __raw_writel(cicr0, pcdev->base + CICR0); | |
e7c50688 GL |
962 | } |
963 | ||
3bc43840 GL |
964 | return IRQ_HANDLED; |
965 | } | |
966 | ||
1c3bb743 GL |
967 | /* |
968 | * The following two functions absolutely depend on the fact, that | |
969 | * there can be only one camera on PXA quick capture interface | |
970 | * Called with .video_lock held | |
971 | */ | |
7102b773 | 972 | static int pxa_camera_add_device(struct soc_camera_device *icd) |
3bc43840 GL |
973 | { |
974 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
975 | struct pxa_camera_dev *pcdev = ici->priv; | |
3bc43840 | 976 | |
979ea1dd GL |
977 | if (pcdev->icd) |
978 | return -EBUSY; | |
3bc43840 | 979 | |
7102b773 | 980 | pxa_camera_activate(pcdev); |
40e2e092 GL |
981 | |
982 | pcdev->icd = icd; | |
3bc43840 | 983 | |
0166b743 | 984 | dev_info(icd->dev.parent, "PXA Camera driver attached to camera %d\n", |
40e2e092 | 985 | icd->devnum); |
3bc43840 | 986 | |
40e2e092 | 987 | return 0; |
3bc43840 GL |
988 | } |
989 | ||
1c3bb743 | 990 | /* Called with .video_lock held */ |
7102b773 | 991 | static void pxa_camera_remove_device(struct soc_camera_device *icd) |
3bc43840 GL |
992 | { |
993 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
994 | struct pxa_camera_dev *pcdev = ici->priv; | |
995 | ||
996 | BUG_ON(icd != pcdev->icd); | |
997 | ||
0166b743 | 998 | dev_info(icd->dev.parent, "PXA Camera driver detached from camera %d\n", |
3bc43840 GL |
999 | icd->devnum); |
1000 | ||
1001 | /* disable capture, disable interrupts */ | |
5ca11fa3 | 1002 | __raw_writel(0x3ff, pcdev->base + CICR0); |
a5462e5b | 1003 | |
3bc43840 | 1004 | /* Stop DMA engine */ |
a5462e5b MR |
1005 | DCSR(pcdev->dma_chans[0]) = 0; |
1006 | DCSR(pcdev->dma_chans[1]) = 0; | |
1007 | DCSR(pcdev->dma_chans[2]) = 0; | |
3bc43840 | 1008 | |
7102b773 | 1009 | pxa_camera_deactivate(pcdev); |
3bc43840 GL |
1010 | |
1011 | pcdev->icd = NULL; | |
1012 | } | |
1013 | ||
ad5f2e85 GL |
1014 | static int test_platform_param(struct pxa_camera_dev *pcdev, |
1015 | unsigned char buswidth, unsigned long *flags) | |
3bc43840 | 1016 | { |
ad5f2e85 GL |
1017 | /* |
1018 | * Platform specified synchronization and pixel clock polarities are | |
1019 | * only a recommendation and are only used during probing. The PXA270 | |
1020 | * quick capture interface supports both. | |
1021 | */ | |
1022 | *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ? | |
1023 | SOCAM_MASTER : SOCAM_SLAVE) | | |
1024 | SOCAM_HSYNC_ACTIVE_HIGH | | |
1025 | SOCAM_HSYNC_ACTIVE_LOW | | |
1026 | SOCAM_VSYNC_ACTIVE_HIGH | | |
1027 | SOCAM_VSYNC_ACTIVE_LOW | | |
2d9329f3 | 1028 | SOCAM_DATA_ACTIVE_HIGH | |
ad5f2e85 GL |
1029 | SOCAM_PCLK_SAMPLE_RISING | |
1030 | SOCAM_PCLK_SAMPLE_FALLING; | |
3bc43840 GL |
1031 | |
1032 | /* If requested data width is supported by the platform, use it */ | |
ad5f2e85 | 1033 | switch (buswidth) { |
3bc43840 | 1034 | case 10: |
ad5f2e85 GL |
1035 | if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10)) |
1036 | return -EINVAL; | |
1037 | *flags |= SOCAM_DATAWIDTH_10; | |
3bc43840 GL |
1038 | break; |
1039 | case 9: | |
ad5f2e85 GL |
1040 | if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9)) |
1041 | return -EINVAL; | |
1042 | *flags |= SOCAM_DATAWIDTH_9; | |
3bc43840 GL |
1043 | break; |
1044 | case 8: | |
ad5f2e85 GL |
1045 | if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8)) |
1046 | return -EINVAL; | |
1047 | *flags |= SOCAM_DATAWIDTH_8; | |
2a48fc73 RJ |
1048 | break; |
1049 | default: | |
1050 | return -EINVAL; | |
3bc43840 | 1051 | } |
ad5f2e85 GL |
1052 | |
1053 | return 0; | |
1054 | } | |
1055 | ||
6a6c8786 GL |
1056 | static void pxa_camera_setup_cicr(struct soc_camera_device *icd, |
1057 | unsigned long flags, __u32 pixfmt) | |
ad5f2e85 | 1058 | { |
64f5905e | 1059 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
ad5f2e85 | 1060 | struct pxa_camera_dev *pcdev = ici->priv; |
32536108 | 1061 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
6a6c8786 | 1062 | unsigned long dw, bpp; |
32536108 GL |
1063 | u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top; |
1064 | int ret = v4l2_subdev_call(sd, sensor, g_skip_top_lines, &y_skip_top); | |
1065 | ||
1066 | if (ret < 0) | |
1067 | y_skip_top = 0; | |
3bc43840 | 1068 | |
5d28d525 GL |
1069 | /* |
1070 | * Datawidth is now guaranteed to be equal to one of the three values. | |
1071 | * We fix bit-per-pixel equal to data-width... | |
1072 | */ | |
6a6c8786 | 1073 | switch (flags & SOCAM_DATAWIDTH_MASK) { |
ad5f2e85 | 1074 | case SOCAM_DATAWIDTH_10: |
3bc43840 GL |
1075 | dw = 4; |
1076 | bpp = 0x40; | |
1077 | break; | |
ad5f2e85 | 1078 | case SOCAM_DATAWIDTH_9: |
3bc43840 GL |
1079 | dw = 3; |
1080 | bpp = 0x20; | |
1081 | break; | |
1082 | default: | |
5d28d525 GL |
1083 | /* |
1084 | * Actually it can only be 8 now, | |
1085 | * default is just to silence compiler warnings | |
1086 | */ | |
ad5f2e85 | 1087 | case SOCAM_DATAWIDTH_8: |
3bc43840 GL |
1088 | dw = 2; |
1089 | bpp = 0; | |
1090 | } | |
1091 | ||
1092 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
1093 | cicr4 |= CICR4_PCLK_EN; | |
1094 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
1095 | cicr4 |= CICR4_MCLK_EN; | |
6a6c8786 | 1096 | if (flags & SOCAM_PCLK_SAMPLE_FALLING) |
3bc43840 | 1097 | cicr4 |= CICR4_PCP; |
6a6c8786 | 1098 | if (flags & SOCAM_HSYNC_ACTIVE_LOW) |
3bc43840 | 1099 | cicr4 |= CICR4_HSP; |
6a6c8786 | 1100 | if (flags & SOCAM_VSYNC_ACTIVE_LOW) |
3bc43840 GL |
1101 | cicr4 |= CICR4_VSP; |
1102 | ||
5ca11fa3 | 1103 | cicr0 = __raw_readl(pcdev->base + CICR0); |
3bc43840 | 1104 | if (cicr0 & CICR0_ENB) |
5ca11fa3 | 1105 | __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0); |
a5462e5b | 1106 | |
6a6c8786 | 1107 | cicr1 = CICR1_PPL_VAL(icd->user_width - 1) | bpp | dw; |
a5462e5b MR |
1108 | |
1109 | switch (pixfmt) { | |
1110 | case V4L2_PIX_FMT_YUV422P: | |
e7c50688 | 1111 | pcdev->channels = 3; |
a5462e5b | 1112 | cicr1 |= CICR1_YCBCR_F; |
2a48fc73 RJ |
1113 | /* |
1114 | * Normally, pxa bus wants as input UYVY format. We allow all | |
1115 | * reorderings of the YUV422 format, as no processing is done, | |
1116 | * and the YUV stream is just passed through without any | |
1117 | * transformation. Note that UYVY is the only format that | |
1118 | * should be used if pxa framebuffer Overlay2 is used. | |
1119 | */ | |
1120 | case V4L2_PIX_FMT_UYVY: | |
1121 | case V4L2_PIX_FMT_VYUY: | |
a5462e5b | 1122 | case V4L2_PIX_FMT_YUYV: |
2a48fc73 | 1123 | case V4L2_PIX_FMT_YVYU: |
a5462e5b MR |
1124 | cicr1 |= CICR1_COLOR_SP_VAL(2); |
1125 | break; | |
1126 | case V4L2_PIX_FMT_RGB555: | |
1127 | cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) | | |
1128 | CICR1_TBIT | CICR1_COLOR_SP_VAL(1); | |
1129 | break; | |
1130 | case V4L2_PIX_FMT_RGB565: | |
1131 | cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2); | |
1132 | break; | |
1133 | } | |
1134 | ||
5ca11fa3 | 1135 | cicr2 = 0; |
6a6c8786 | 1136 | cicr3 = CICR3_LPF_VAL(icd->user_height - 1) | |
32536108 | 1137 | CICR3_BFW_VAL(min((u32)255, y_skip_top)); |
cf34cba7 | 1138 | cicr4 |= pcdev->mclk_divisor; |
5ca11fa3 EM |
1139 | |
1140 | __raw_writel(cicr1, pcdev->base + CICR1); | |
1141 | __raw_writel(cicr2, pcdev->base + CICR2); | |
1142 | __raw_writel(cicr3, pcdev->base + CICR3); | |
1143 | __raw_writel(cicr4, pcdev->base + CICR4); | |
3bc43840 GL |
1144 | |
1145 | /* CIF interrupts are not used, only DMA */ | |
5ca11fa3 EM |
1146 | cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ? |
1147 | CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP)); | |
1148 | cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK; | |
1149 | __raw_writel(cicr0, pcdev->base + CICR0); | |
6a6c8786 GL |
1150 | } |
1151 | ||
1152 | static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt) | |
1153 | { | |
1154 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
1155 | struct pxa_camera_dev *pcdev = ici->priv; | |
1156 | unsigned long bus_flags, camera_flags, common_flags; | |
760697be | 1157 | int ret; |
6a6c8786 GL |
1158 | struct pxa_cam *cam = icd->host_priv; |
1159 | ||
d2dcad49 GL |
1160 | ret = test_platform_param(pcdev, icd->current_fmt->host_fmt->bits_per_sample, |
1161 | &bus_flags); | |
6a6c8786 GL |
1162 | if (ret < 0) |
1163 | return ret; | |
1164 | ||
1165 | camera_flags = icd->ops->query_bus_param(icd); | |
1166 | ||
1167 | common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags); | |
1168 | if (!common_flags) | |
1169 | return -EINVAL; | |
1170 | ||
1171 | pcdev->channels = 1; | |
1172 | ||
1173 | /* Make choises, based on platform preferences */ | |
1174 | if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) && | |
1175 | (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) { | |
1176 | if (pcdev->platform_flags & PXA_CAMERA_HSP) | |
1177 | common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH; | |
1178 | else | |
1179 | common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW; | |
1180 | } | |
1181 | ||
1182 | if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) && | |
1183 | (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) { | |
1184 | if (pcdev->platform_flags & PXA_CAMERA_VSP) | |
1185 | common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH; | |
1186 | else | |
1187 | common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW; | |
1188 | } | |
1189 | ||
1190 | if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) && | |
1191 | (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) { | |
1192 | if (pcdev->platform_flags & PXA_CAMERA_PCP) | |
1193 | common_flags &= ~SOCAM_PCLK_SAMPLE_RISING; | |
1194 | else | |
1195 | common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING; | |
1196 | } | |
1197 | ||
1198 | cam->flags = common_flags; | |
1199 | ||
1200 | ret = icd->ops->set_bus_param(icd, common_flags); | |
1201 | if (ret < 0) | |
1202 | return ret; | |
1203 | ||
1204 | pxa_camera_setup_cicr(icd, common_flags, pixfmt); | |
3bc43840 GL |
1205 | |
1206 | return 0; | |
1207 | } | |
1208 | ||
2a48fc73 RJ |
1209 | static int pxa_camera_try_bus_param(struct soc_camera_device *icd, |
1210 | unsigned char buswidth) | |
ad5f2e85 | 1211 | { |
cf34cba7 | 1212 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
ad5f2e85 GL |
1213 | struct pxa_camera_dev *pcdev = ici->priv; |
1214 | unsigned long bus_flags, camera_flags; | |
2a48fc73 | 1215 | int ret = test_platform_param(pcdev, buswidth, &bus_flags); |
ad5f2e85 GL |
1216 | |
1217 | if (ret < 0) | |
1218 | return ret; | |
1219 | ||
1220 | camera_flags = icd->ops->query_bus_param(icd); | |
1221 | ||
1222 | return soc_camera_bus_param_compatible(camera_flags, bus_flags) ? 0 : -EINVAL; | |
1223 | } | |
1224 | ||
760697be | 1225 | static const struct soc_mbus_pixelfmt pxa_camera_formats[] = { |
2a48fc73 | 1226 | { |
760697be GL |
1227 | .fourcc = V4L2_PIX_FMT_YUV422P, |
1228 | .name = "Planar YUV422 16 bit", | |
1229 | .bits_per_sample = 8, | |
1230 | .packing = SOC_MBUS_PACKING_2X8_PADHI, | |
1231 | .order = SOC_MBUS_ORDER_LE, | |
2a48fc73 RJ |
1232 | }, |
1233 | }; | |
1234 | ||
760697be GL |
1235 | /* This will be corrected as we get more formats */ |
1236 | static bool pxa_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt) | |
ad5f2e85 | 1237 | { |
760697be GL |
1238 | return fmt->packing == SOC_MBUS_PACKING_NONE || |
1239 | (fmt->bits_per_sample == 8 && | |
1240 | fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) || | |
1241 | (fmt->bits_per_sample > 8 && | |
1242 | fmt->packing == SOC_MBUS_PACKING_EXTEND16); | |
2a48fc73 RJ |
1243 | } |
1244 | ||
3805f201 | 1245 | static int pxa_camera_get_formats(struct soc_camera_device *icd, unsigned int idx, |
2a48fc73 RJ |
1246 | struct soc_camera_format_xlate *xlate) |
1247 | { | |
760697be | 1248 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
0166b743 | 1249 | struct device *dev = icd->dev.parent; |
760697be | 1250 | int formats = 0, ret; |
6a6c8786 | 1251 | struct pxa_cam *cam; |
760697be GL |
1252 | enum v4l2_mbus_pixelcode code; |
1253 | const struct soc_mbus_pixelfmt *fmt; | |
2a48fc73 | 1254 | |
760697be GL |
1255 | ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code); |
1256 | if (ret < 0) | |
1257 | /* No more formats */ | |
1258 | return 0; | |
2a48fc73 | 1259 | |
760697be GL |
1260 | fmt = soc_mbus_get_fmtdesc(code); |
1261 | if (!fmt) { | |
3805f201 | 1262 | dev_err(dev, "Invalid format code #%u: %d\n", idx, code); |
2a48fc73 | 1263 | return 0; |
760697be | 1264 | } |
3bc43840 | 1265 | |
760697be GL |
1266 | /* This also checks support for the requested bits-per-sample */ |
1267 | ret = pxa_camera_try_bus_param(icd, fmt->bits_per_sample); | |
2a48fc73 RJ |
1268 | if (ret < 0) |
1269 | return 0; | |
1270 | ||
6a6c8786 GL |
1271 | if (!icd->host_priv) { |
1272 | cam = kzalloc(sizeof(*cam), GFP_KERNEL); | |
1273 | if (!cam) | |
1274 | return -ENOMEM; | |
1275 | ||
1276 | icd->host_priv = cam; | |
1277 | } else { | |
1278 | cam = icd->host_priv; | |
1279 | } | |
1280 | ||
760697be | 1281 | switch (code) { |
ace6e979 | 1282 | case V4L2_MBUS_FMT_UYVY8_2X8: |
2a48fc73 RJ |
1283 | formats++; |
1284 | if (xlate) { | |
760697be GL |
1285 | xlate->host_fmt = &pxa_camera_formats[0]; |
1286 | xlate->code = code; | |
2a48fc73 | 1287 | xlate++; |
760697be GL |
1288 | dev_dbg(dev, "Providing format %s using code %d\n", |
1289 | pxa_camera_formats[0].name, code); | |
2a48fc73 | 1290 | } |
ace6e979 GL |
1291 | case V4L2_MBUS_FMT_VYUY8_2X8: |
1292 | case V4L2_MBUS_FMT_YUYV8_2X8: | |
1293 | case V4L2_MBUS_FMT_YVYU8_2X8: | |
760697be GL |
1294 | case V4L2_MBUS_FMT_RGB565_2X8_LE: |
1295 | case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE: | |
1296 | if (xlate) | |
0166b743 | 1297 | dev_dbg(dev, "Providing format %s packed\n", |
760697be | 1298 | fmt->name); |
2a48fc73 RJ |
1299 | break; |
1300 | default: | |
760697be GL |
1301 | if (!pxa_camera_packing_supported(fmt)) |
1302 | return 0; | |
1303 | if (xlate) | |
0166b743 | 1304 | dev_dbg(dev, |
2a48fc73 | 1305 | "Providing format %s in pass-through mode\n", |
760697be GL |
1306 | fmt->name); |
1307 | } | |
1308 | ||
1309 | /* Generic pass-through */ | |
1310 | formats++; | |
1311 | if (xlate) { | |
1312 | xlate->host_fmt = fmt; | |
1313 | xlate->code = code; | |
1314 | xlate++; | |
2a48fc73 RJ |
1315 | } |
1316 | ||
1317 | return formats; | |
1318 | } | |
1319 | ||
6a6c8786 GL |
1320 | static void pxa_camera_put_formats(struct soc_camera_device *icd) |
1321 | { | |
1322 | kfree(icd->host_priv); | |
1323 | icd->host_priv = NULL; | |
1324 | } | |
1325 | ||
760697be | 1326 | static int pxa_camera_check_frame(u32 width, u32 height) |
6a6c8786 GL |
1327 | { |
1328 | /* limit to pxa hardware capabilities */ | |
760697be GL |
1329 | return height < 32 || height > 2048 || width < 48 || width > 2048 || |
1330 | (width & 0x01); | |
6a6c8786 GL |
1331 | } |
1332 | ||
09e231b3 | 1333 | static int pxa_camera_set_crop(struct soc_camera_device *icd, |
08590b96 | 1334 | struct v4l2_crop *a) |
09e231b3 | 1335 | { |
08590b96 | 1336 | struct v4l2_rect *rect = &a->c; |
09e231b3 GL |
1337 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
1338 | struct pxa_camera_dev *pcdev = ici->priv; | |
0166b743 | 1339 | struct device *dev = icd->dev.parent; |
c9c1f1c0 | 1340 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
09e231b3 GL |
1341 | struct soc_camera_sense sense = { |
1342 | .master_clock = pcdev->mclk, | |
1343 | .pixel_clock_max = pcdev->ciclk / 4, | |
1344 | }; | |
760697be | 1345 | struct v4l2_mbus_framefmt mf; |
6a6c8786 | 1346 | struct pxa_cam *cam = icd->host_priv; |
760697be | 1347 | u32 fourcc = icd->current_fmt->host_fmt->fourcc; |
09e231b3 GL |
1348 | int ret; |
1349 | ||
1350 | /* If PCLK is used to latch data from the sensor, check sense */ | |
1351 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
1352 | icd->sense = &sense; | |
1353 | ||
08590b96 | 1354 | ret = v4l2_subdev_call(sd, video, s_crop, a); |
09e231b3 GL |
1355 | |
1356 | icd->sense = NULL; | |
1357 | ||
1358 | if (ret < 0) { | |
0166b743 | 1359 | dev_warn(dev, "Failed to crop to %ux%u@%u:%u\n", |
09e231b3 | 1360 | rect->width, rect->height, rect->left, rect->top); |
6a6c8786 GL |
1361 | return ret; |
1362 | } | |
1363 | ||
760697be | 1364 | ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf); |
6a6c8786 GL |
1365 | if (ret < 0) |
1366 | return ret; | |
1367 | ||
760697be | 1368 | if (pxa_camera_check_frame(mf.width, mf.height)) { |
6a6c8786 GL |
1369 | /* |
1370 | * Camera cropping produced a frame beyond our capabilities. | |
1371 | * FIXME: just extract a subframe, that we can process. | |
1372 | */ | |
760697be GL |
1373 | v4l_bound_align_image(&mf.width, 48, 2048, 1, |
1374 | &mf.height, 32, 2048, 0, | |
1375 | fourcc == V4L2_PIX_FMT_YUV422P ? 4 : 0); | |
1376 | ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf); | |
6a6c8786 GL |
1377 | if (ret < 0) |
1378 | return ret; | |
1379 | ||
760697be | 1380 | if (pxa_camera_check_frame(mf.width, mf.height)) { |
6a6c8786 GL |
1381 | dev_warn(icd->dev.parent, |
1382 | "Inconsistent state. Use S_FMT to repair\n"); | |
1383 | return -EINVAL; | |
1384 | } | |
1385 | } | |
1386 | ||
1387 | if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) { | |
09e231b3 | 1388 | if (sense.pixel_clock > sense.pixel_clock_max) { |
0166b743 | 1389 | dev_err(dev, |
09e231b3 GL |
1390 | "pixel clock %lu set by the camera too high!", |
1391 | sense.pixel_clock); | |
1392 | return -EIO; | |
1393 | } | |
1394 | recalculate_fifo_timeout(pcdev, sense.pixel_clock); | |
1395 | } | |
1396 | ||
760697be GL |
1397 | icd->user_width = mf.width; |
1398 | icd->user_height = mf.height; | |
6a6c8786 | 1399 | |
760697be | 1400 | pxa_camera_setup_cicr(icd, cam->flags, fourcc); |
6a6c8786 | 1401 | |
09e231b3 GL |
1402 | return ret; |
1403 | } | |
1404 | ||
d8fac217 | 1405 | static int pxa_camera_set_fmt(struct soc_camera_device *icd, |
09e231b3 | 1406 | struct v4l2_format *f) |
ad5f2e85 | 1407 | { |
2a48fc73 | 1408 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
cf34cba7 | 1409 | struct pxa_camera_dev *pcdev = ici->priv; |
0166b743 | 1410 | struct device *dev = icd->dev.parent; |
c9c1f1c0 | 1411 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
0ad675eb | 1412 | const struct soc_camera_format_xlate *xlate = NULL; |
cf34cba7 GL |
1413 | struct soc_camera_sense sense = { |
1414 | .master_clock = pcdev->mclk, | |
1415 | .pixel_clock_max = pcdev->ciclk / 4, | |
1416 | }; | |
09e231b3 | 1417 | struct v4l2_pix_format *pix = &f->fmt.pix; |
760697be | 1418 | struct v4l2_mbus_framefmt mf; |
0ad675eb | 1419 | int ret; |
25c4d74e | 1420 | |
09e231b3 GL |
1421 | xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); |
1422 | if (!xlate) { | |
0166b743 | 1423 | dev_warn(dev, "Format %x not found\n", pix->pixelformat); |
09e231b3 | 1424 | return -EINVAL; |
0ad675eb | 1425 | } |
2a48fc73 | 1426 | |
cf34cba7 GL |
1427 | /* If PCLK is used to latch data from the sensor, check sense */ |
1428 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
760697be | 1429 | /* The caller holds a mutex. */ |
cf34cba7 GL |
1430 | icd->sense = &sense; |
1431 | ||
760697be GL |
1432 | mf.width = pix->width; |
1433 | mf.height = pix->height; | |
1434 | mf.field = pix->field; | |
1435 | mf.colorspace = pix->colorspace; | |
1436 | mf.code = xlate->code; | |
1437 | ||
1438 | ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf); | |
1439 | ||
1440 | if (mf.code != xlate->code) | |
1441 | return -EINVAL; | |
2a48fc73 | 1442 | |
cf34cba7 GL |
1443 | icd->sense = NULL; |
1444 | ||
1445 | if (ret < 0) { | |
0166b743 | 1446 | dev_warn(dev, "Failed to configure for format %x\n", |
09e231b3 | 1447 | pix->pixelformat); |
760697be | 1448 | } else if (pxa_camera_check_frame(mf.width, mf.height)) { |
6a6c8786 GL |
1449 | dev_warn(dev, |
1450 | "Camera driver produced an unsupported frame %dx%d\n", | |
760697be | 1451 | mf.width, mf.height); |
6a6c8786 | 1452 | ret = -EINVAL; |
cf34cba7 GL |
1453 | } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) { |
1454 | if (sense.pixel_clock > sense.pixel_clock_max) { | |
0166b743 | 1455 | dev_err(dev, |
cf34cba7 GL |
1456 | "pixel clock %lu set by the camera too high!", |
1457 | sense.pixel_clock); | |
1458 | return -EIO; | |
1459 | } | |
1460 | recalculate_fifo_timeout(pcdev, sense.pixel_clock); | |
1461 | } | |
2a48fc73 | 1462 | |
760697be GL |
1463 | if (ret < 0) |
1464 | return ret; | |
1465 | ||
1466 | pix->width = mf.width; | |
1467 | pix->height = mf.height; | |
1468 | pix->field = mf.field; | |
1469 | pix->colorspace = mf.colorspace; | |
1470 | icd->current_fmt = xlate; | |
25c4d74e GL |
1471 | |
1472 | return ret; | |
ad5f2e85 GL |
1473 | } |
1474 | ||
d8fac217 GL |
1475 | static int pxa_camera_try_fmt(struct soc_camera_device *icd, |
1476 | struct v4l2_format *f) | |
3bc43840 | 1477 | { |
c9c1f1c0 | 1478 | struct v4l2_subdev *sd = soc_camera_to_subdev(icd); |
2a48fc73 RJ |
1479 | const struct soc_camera_format_xlate *xlate; |
1480 | struct v4l2_pix_format *pix = &f->fmt.pix; | |
760697be | 1481 | struct v4l2_mbus_framefmt mf; |
2a48fc73 | 1482 | __u32 pixfmt = pix->pixelformat; |
bf507158 | 1483 | int ret; |
a2c8c68c | 1484 | |
2a48fc73 RJ |
1485 | xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); |
1486 | if (!xlate) { | |
760697be | 1487 | dev_warn(icd->dev.parent, "Format %x not found\n", pixfmt); |
25c4d74e | 1488 | return -EINVAL; |
2a48fc73 | 1489 | } |
25c4d74e | 1490 | |
92a8337b | 1491 | /* |
4a6b8df2 TP |
1492 | * Limit to pxa hardware capabilities. YUV422P planar format requires |
1493 | * images size to be a multiple of 16 bytes. If not, zeros will be | |
1494 | * inserted between Y and U planes, and U and V planes, which violates | |
1495 | * the YUV422P standard. | |
92a8337b | 1496 | */ |
4a6b8df2 TP |
1497 | v4l_bound_align_image(&pix->width, 48, 2048, 1, |
1498 | &pix->height, 32, 2048, 0, | |
6a6c8786 | 1499 | pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0); |
92a8337b | 1500 | |
ad5f2e85 | 1501 | /* limit to sensor capabilities */ |
760697be GL |
1502 | mf.width = pix->width; |
1503 | mf.height = pix->height; | |
91401219 GL |
1504 | /* Only progressive video supported so far */ |
1505 | mf.field = V4L2_FIELD_NONE; | |
760697be GL |
1506 | mf.colorspace = pix->colorspace; |
1507 | mf.code = xlate->code; | |
bf507158 | 1508 | |
760697be GL |
1509 | ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf); |
1510 | if (ret < 0) | |
1511 | return ret; | |
06daa1af | 1512 | |
760697be GL |
1513 | pix->width = mf.width; |
1514 | pix->height = mf.height; | |
1515 | pix->colorspace = mf.colorspace; | |
1516 | ||
1517 | switch (mf.field) { | |
1518 | case V4L2_FIELD_ANY: | |
1519 | case V4L2_FIELD_NONE: | |
1520 | pix->field = V4L2_FIELD_NONE; | |
1521 | break; | |
1522 | default: | |
1523 | /* TODO: support interlaced at least in pass-through mode */ | |
1524 | dev_err(icd->dev.parent, "Field type %d unsupported.\n", | |
1525 | mf.field); | |
06daa1af GL |
1526 | return -EINVAL; |
1527 | } | |
1528 | ||
bf507158 | 1529 | return ret; |
3bc43840 GL |
1530 | } |
1531 | ||
57bee29d | 1532 | static int pxa_camera_reqbufs(struct soc_camera_device *icd, |
7102b773 | 1533 | struct v4l2_requestbuffers *p) |
3bc43840 GL |
1534 | { |
1535 | int i; | |
1536 | ||
5d28d525 GL |
1537 | /* |
1538 | * This is for locking debugging only. I removed spinlocks and now I | |
3bc43840 GL |
1539 | * check whether .prepare is ever called on a linked buffer, or whether |
1540 | * a dma IRQ can occur for an in-work or unlinked buffer. Until now | |
5d28d525 GL |
1541 | * it hadn't triggered |
1542 | */ | |
3bc43840 | 1543 | for (i = 0; i < p->count; i++) { |
57bee29d | 1544 | struct pxa_buffer *buf = container_of(icd->vb_vidq.bufs[i], |
3bc43840 GL |
1545 | struct pxa_buffer, vb); |
1546 | buf->inwork = 0; | |
1547 | INIT_LIST_HEAD(&buf->vb.queue); | |
1548 | } | |
1549 | ||
1550 | return 0; | |
1551 | } | |
1552 | ||
7102b773 | 1553 | static unsigned int pxa_camera_poll(struct file *file, poll_table *pt) |
3bc43840 | 1554 | { |
57bee29d | 1555 | struct soc_camera_device *icd = file->private_data; |
3bc43840 GL |
1556 | struct pxa_buffer *buf; |
1557 | ||
57bee29d | 1558 | buf = list_entry(icd->vb_vidq.stream.next, struct pxa_buffer, |
3bc43840 GL |
1559 | vb.stream); |
1560 | ||
1561 | poll_wait(file, &buf->vb.done, pt); | |
1562 | ||
1563 | if (buf->vb.state == VIDEOBUF_DONE || | |
1564 | buf->vb.state == VIDEOBUF_ERROR) | |
1565 | return POLLIN|POLLRDNORM; | |
1566 | ||
1567 | return 0; | |
1568 | } | |
1569 | ||
7102b773 GL |
1570 | static int pxa_camera_querycap(struct soc_camera_host *ici, |
1571 | struct v4l2_capability *cap) | |
3bc43840 GL |
1572 | { |
1573 | /* cap->name is set by the firendly caller:-> */ | |
1574 | strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card)); | |
3bc43840 GL |
1575 | cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; |
1576 | ||
1577 | return 0; | |
1578 | } | |
1579 | ||
3f6ac497 RJ |
1580 | static int pxa_camera_suspend(struct soc_camera_device *icd, pm_message_t state) |
1581 | { | |
64f5905e | 1582 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
3f6ac497 RJ |
1583 | struct pxa_camera_dev *pcdev = ici->priv; |
1584 | int i = 0, ret = 0; | |
1585 | ||
5ca11fa3 EM |
1586 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0); |
1587 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1); | |
1588 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2); | |
1589 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3); | |
1590 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4); | |
3f6ac497 RJ |
1591 | |
1592 | if ((pcdev->icd) && (pcdev->icd->ops->suspend)) | |
1593 | ret = pcdev->icd->ops->suspend(pcdev->icd, state); | |
1594 | ||
1595 | return ret; | |
1596 | } | |
1597 | ||
1598 | static int pxa_camera_resume(struct soc_camera_device *icd) | |
1599 | { | |
64f5905e | 1600 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
3f6ac497 RJ |
1601 | struct pxa_camera_dev *pcdev = ici->priv; |
1602 | int i = 0, ret = 0; | |
1603 | ||
87f3dd77 EM |
1604 | DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD; |
1605 | DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD; | |
1606 | DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD; | |
3f6ac497 | 1607 | |
5ca11fa3 EM |
1608 | __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0); |
1609 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1); | |
1610 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2); | |
1611 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3); | |
1612 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4); | |
3f6ac497 RJ |
1613 | |
1614 | if ((pcdev->icd) && (pcdev->icd->ops->resume)) | |
1615 | ret = pcdev->icd->ops->resume(pcdev->icd); | |
1616 | ||
1617 | /* Restart frame capture if active buffer exists */ | |
256b0233 RJ |
1618 | if (!ret && pcdev->active) |
1619 | pxa_camera_start_capture(pcdev); | |
3f6ac497 RJ |
1620 | |
1621 | return ret; | |
1622 | } | |
1623 | ||
b8d9904c GL |
1624 | static struct soc_camera_host_ops pxa_soc_camera_host_ops = { |
1625 | .owner = THIS_MODULE, | |
1626 | .add = pxa_camera_add_device, | |
1627 | .remove = pxa_camera_remove_device, | |
3f6ac497 RJ |
1628 | .suspend = pxa_camera_suspend, |
1629 | .resume = pxa_camera_resume, | |
09e231b3 | 1630 | .set_crop = pxa_camera_set_crop, |
2a48fc73 | 1631 | .get_formats = pxa_camera_get_formats, |
6a6c8786 | 1632 | .put_formats = pxa_camera_put_formats, |
d8fac217 GL |
1633 | .set_fmt = pxa_camera_set_fmt, |
1634 | .try_fmt = pxa_camera_try_fmt, | |
092d3921 | 1635 | .init_videobuf = pxa_camera_init_videobuf, |
b8d9904c GL |
1636 | .reqbufs = pxa_camera_reqbufs, |
1637 | .poll = pxa_camera_poll, | |
1638 | .querycap = pxa_camera_querycap, | |
b8d9904c GL |
1639 | .set_bus_param = pxa_camera_set_bus_param, |
1640 | }; | |
1641 | ||
e36bc31f | 1642 | static int __devinit pxa_camera_probe(struct platform_device *pdev) |
3bc43840 GL |
1643 | { |
1644 | struct pxa_camera_dev *pcdev; | |
1645 | struct resource *res; | |
1646 | void __iomem *base; | |
02da4659 | 1647 | int irq; |
3bc43840 GL |
1648 | int err = 0; |
1649 | ||
1650 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1651 | irq = platform_get_irq(pdev, 0); | |
02da4659 | 1652 | if (!res || irq < 0) { |
3bc43840 GL |
1653 | err = -ENODEV; |
1654 | goto exit; | |
1655 | } | |
1656 | ||
1657 | pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL); | |
1658 | if (!pcdev) { | |
7102b773 | 1659 | dev_err(&pdev->dev, "Could not allocate pcdev\n"); |
3bc43840 GL |
1660 | err = -ENOMEM; |
1661 | goto exit; | |
1662 | } | |
1663 | ||
e0d8b13a | 1664 | pcdev->clk = clk_get(&pdev->dev, NULL); |
3bc43840 GL |
1665 | if (IS_ERR(pcdev->clk)) { |
1666 | err = PTR_ERR(pcdev->clk); | |
1667 | goto exit_kfree; | |
1668 | } | |
1669 | ||
3bc43840 GL |
1670 | pcdev->res = res; |
1671 | ||
1672 | pcdev->pdata = pdev->dev.platform_data; | |
1673 | pcdev->platform_flags = pcdev->pdata->flags; | |
ad5f2e85 GL |
1674 | if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 | |
1675 | PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) { | |
5d28d525 GL |
1676 | /* |
1677 | * Platform hasn't set available data widths. This is bad. | |
1678 | * Warn and use a default. | |
1679 | */ | |
3bc43840 GL |
1680 | dev_warn(&pdev->dev, "WARNING! Platform hasn't set available " |
1681 | "data widths, using default 10 bit\n"); | |
1682 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10; | |
1683 | } | |
cf34cba7 GL |
1684 | pcdev->mclk = pcdev->pdata->mclk_10khz * 10000; |
1685 | if (!pcdev->mclk) { | |
3bc43840 | 1686 | dev_warn(&pdev->dev, |
cf34cba7 | 1687 | "mclk == 0! Please, fix your platform data. " |
3bc43840 | 1688 | "Using default 20MHz\n"); |
cf34cba7 | 1689 | pcdev->mclk = 20000000; |
3bc43840 GL |
1690 | } |
1691 | ||
40e2e092 | 1692 | pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev); |
cf34cba7 | 1693 | |
3bc43840 GL |
1694 | INIT_LIST_HEAD(&pcdev->capture); |
1695 | spin_lock_init(&pcdev->lock); | |
1696 | ||
1697 | /* | |
1698 | * Request the regions. | |
1699 | */ | |
eb6c8558 | 1700 | if (!request_mem_region(res->start, resource_size(res), |
3bc43840 GL |
1701 | PXA_CAM_DRV_NAME)) { |
1702 | err = -EBUSY; | |
1703 | goto exit_clk; | |
1704 | } | |
1705 | ||
eb6c8558 | 1706 | base = ioremap(res->start, resource_size(res)); |
3bc43840 GL |
1707 | if (!base) { |
1708 | err = -ENOMEM; | |
1709 | goto exit_release; | |
1710 | } | |
1711 | pcdev->irq = irq; | |
1712 | pcdev->base = base; | |
3bc43840 GL |
1713 | |
1714 | /* request dma */ | |
de3e3b82 | 1715 | err = pxa_request_dma("CI_Y", DMA_PRIO_HIGH, |
1716 | pxa_camera_dma_irq_y, pcdev); | |
1717 | if (err < 0) { | |
eff505fa | 1718 | dev_err(&pdev->dev, "Can't request DMA for Y\n"); |
3bc43840 GL |
1719 | goto exit_iounmap; |
1720 | } | |
de3e3b82 | 1721 | pcdev->dma_chans[0] = err; |
eff505fa | 1722 | dev_dbg(&pdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]); |
a5462e5b | 1723 | |
de3e3b82 | 1724 | err = pxa_request_dma("CI_U", DMA_PRIO_HIGH, |
1725 | pxa_camera_dma_irq_u, pcdev); | |
1726 | if (err < 0) { | |
eff505fa | 1727 | dev_err(&pdev->dev, "Can't request DMA for U\n"); |
a5462e5b MR |
1728 | goto exit_free_dma_y; |
1729 | } | |
de3e3b82 | 1730 | pcdev->dma_chans[1] = err; |
eff505fa | 1731 | dev_dbg(&pdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]); |
a5462e5b | 1732 | |
de3e3b82 | 1733 | err = pxa_request_dma("CI_V", DMA_PRIO_HIGH, |
1734 | pxa_camera_dma_irq_v, pcdev); | |
1735 | if (err < 0) { | |
eff505fa | 1736 | dev_err(&pdev->dev, "Can't request DMA for V\n"); |
a5462e5b MR |
1737 | goto exit_free_dma_u; |
1738 | } | |
de3e3b82 | 1739 | pcdev->dma_chans[2] = err; |
eff505fa | 1740 | dev_dbg(&pdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]); |
3bc43840 | 1741 | |
87f3dd77 EM |
1742 | DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD; |
1743 | DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD; | |
1744 | DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD; | |
3bc43840 GL |
1745 | |
1746 | /* request irq */ | |
1747 | err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME, | |
1748 | pcdev); | |
1749 | if (err) { | |
eff505fa | 1750 | dev_err(&pdev->dev, "Camera interrupt register failed \n"); |
3bc43840 GL |
1751 | goto exit_free_dma; |
1752 | } | |
1753 | ||
eb6c8558 GL |
1754 | pcdev->soc_host.drv_name = PXA_CAM_DRV_NAME; |
1755 | pcdev->soc_host.ops = &pxa_soc_camera_host_ops; | |
1756 | pcdev->soc_host.priv = pcdev; | |
979ea1dd | 1757 | pcdev->soc_host.v4l2_dev.dev = &pdev->dev; |
eb6c8558 | 1758 | pcdev->soc_host.nr = pdev->id; |
eff505fa | 1759 | |
eb6c8558 | 1760 | err = soc_camera_host_register(&pcdev->soc_host); |
3bc43840 GL |
1761 | if (err) |
1762 | goto exit_free_irq; | |
1763 | ||
1764 | return 0; | |
1765 | ||
1766 | exit_free_irq: | |
1767 | free_irq(pcdev->irq, pcdev); | |
1768 | exit_free_dma: | |
a5462e5b MR |
1769 | pxa_free_dma(pcdev->dma_chans[2]); |
1770 | exit_free_dma_u: | |
1771 | pxa_free_dma(pcdev->dma_chans[1]); | |
1772 | exit_free_dma_y: | |
1773 | pxa_free_dma(pcdev->dma_chans[0]); | |
3bc43840 GL |
1774 | exit_iounmap: |
1775 | iounmap(base); | |
1776 | exit_release: | |
eb6c8558 | 1777 | release_mem_region(res->start, resource_size(res)); |
3bc43840 GL |
1778 | exit_clk: |
1779 | clk_put(pcdev->clk); | |
1780 | exit_kfree: | |
1781 | kfree(pcdev); | |
1782 | exit: | |
1783 | return err; | |
1784 | } | |
1785 | ||
1786 | static int __devexit pxa_camera_remove(struct platform_device *pdev) | |
1787 | { | |
eff505fa GL |
1788 | struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev); |
1789 | struct pxa_camera_dev *pcdev = container_of(soc_host, | |
1790 | struct pxa_camera_dev, soc_host); | |
3bc43840 GL |
1791 | struct resource *res; |
1792 | ||
1793 | clk_put(pcdev->clk); | |
1794 | ||
a5462e5b MR |
1795 | pxa_free_dma(pcdev->dma_chans[0]); |
1796 | pxa_free_dma(pcdev->dma_chans[1]); | |
1797 | pxa_free_dma(pcdev->dma_chans[2]); | |
3bc43840 GL |
1798 | free_irq(pcdev->irq, pcdev); |
1799 | ||
eff505fa | 1800 | soc_camera_host_unregister(soc_host); |
3bc43840 GL |
1801 | |
1802 | iounmap(pcdev->base); | |
1803 | ||
1804 | res = pcdev->res; | |
eb6c8558 | 1805 | release_mem_region(res->start, resource_size(res)); |
3bc43840 GL |
1806 | |
1807 | kfree(pcdev); | |
1808 | ||
7102b773 | 1809 | dev_info(&pdev->dev, "PXA Camera driver unloaded\n"); |
3bc43840 | 1810 | |
3bc43840 GL |
1811 | return 0; |
1812 | } | |
1813 | ||
3bc43840 GL |
1814 | static struct platform_driver pxa_camera_driver = { |
1815 | .driver = { | |
1816 | .name = PXA_CAM_DRV_NAME, | |
1817 | }, | |
1818 | .probe = pxa_camera_probe, | |
e36bc31f | 1819 | .remove = __devexit_p(pxa_camera_remove), |
3bc43840 GL |
1820 | }; |
1821 | ||
1822 | ||
e36bc31f | 1823 | static int __init pxa_camera_init(void) |
3bc43840 GL |
1824 | { |
1825 | return platform_driver_register(&pxa_camera_driver); | |
1826 | } | |
1827 | ||
1828 | static void __exit pxa_camera_exit(void) | |
1829 | { | |
01c1e4ca | 1830 | platform_driver_unregister(&pxa_camera_driver); |
3bc43840 GL |
1831 | } |
1832 | ||
1833 | module_init(pxa_camera_init); | |
1834 | module_exit(pxa_camera_exit); | |
1835 | ||
1836 | MODULE_DESCRIPTION("PXA27x SoC Camera Host driver"); | |
1837 | MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>"); | |
1838 | MODULE_LICENSE("GPL"); | |
64dc3c1a | 1839 | MODULE_VERSION(PXA_CAM_VERSION); |
40e2e092 | 1840 | MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME); |