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3bc43840 GL |
1 | /* |
2 | * V4L2 Driver for PXA camera host | |
3 | * | |
4 | * Copyright (C) 2006, Sascha Hauer, Pengutronix | |
5 | * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
3bc43840 GL |
13 | #include <linux/init.h> |
14 | #include <linux/module.h> | |
7102b773 | 15 | #include <linux/io.h> |
3bc43840 GL |
16 | #include <linux/delay.h> |
17 | #include <linux/dma-mapping.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/fs.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/mm.h> | |
23 | #include <linux/moduleparam.h> | |
24 | #include <linux/time.h> | |
25 | #include <linux/version.h> | |
26 | #include <linux/device.h> | |
27 | #include <linux/platform_device.h> | |
3bc43840 GL |
28 | #include <linux/clk.h> |
29 | ||
30 | #include <media/v4l2-common.h> | |
31 | #include <media/v4l2-dev.h> | |
092d3921 | 32 | #include <media/videobuf-dma-sg.h> |
3bc43840 GL |
33 | #include <media/soc_camera.h> |
34 | ||
35 | #include <linux/videodev2.h> | |
36 | ||
cfbaf4df | 37 | #include <mach/dma.h> |
a09e64fb | 38 | #include <mach/camera.h> |
3bc43840 GL |
39 | |
40 | #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5) | |
41 | #define PXA_CAM_DRV_NAME "pxa27x-camera" | |
42 | ||
5ca11fa3 EM |
43 | /* Camera Interface */ |
44 | #define CICR0 0x0000 | |
45 | #define CICR1 0x0004 | |
46 | #define CICR2 0x0008 | |
47 | #define CICR3 0x000C | |
48 | #define CICR4 0x0010 | |
49 | #define CISR 0x0014 | |
50 | #define CIFR 0x0018 | |
51 | #define CITOR 0x001C | |
52 | #define CIBR0 0x0028 | |
53 | #define CIBR1 0x0030 | |
54 | #define CIBR2 0x0038 | |
55 | ||
56 | #define CICR0_DMAEN (1 << 31) /* DMA request enable */ | |
57 | #define CICR0_PAR_EN (1 << 30) /* Parity enable */ | |
58 | #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */ | |
59 | #define CICR0_ENB (1 << 28) /* Camera interface enable */ | |
60 | #define CICR0_DIS (1 << 27) /* Camera interface disable */ | |
61 | #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */ | |
62 | #define CICR0_TOM (1 << 9) /* Time-out mask */ | |
63 | #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */ | |
64 | #define CICR0_FEM (1 << 7) /* FIFO-empty mask */ | |
65 | #define CICR0_EOLM (1 << 6) /* End-of-line mask */ | |
66 | #define CICR0_PERRM (1 << 5) /* Parity-error mask */ | |
67 | #define CICR0_QDM (1 << 4) /* Quick-disable mask */ | |
68 | #define CICR0_CDM (1 << 3) /* Disable-done mask */ | |
69 | #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */ | |
70 | #define CICR0_EOFM (1 << 1) /* End-of-frame mask */ | |
71 | #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */ | |
72 | ||
73 | #define CICR1_TBIT (1 << 31) /* Transparency bit */ | |
74 | #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */ | |
75 | #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */ | |
76 | #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */ | |
77 | #define CICR1_RGB_F (1 << 11) /* RGB format */ | |
78 | #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */ | |
79 | #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */ | |
80 | #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */ | |
81 | #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */ | |
82 | #define CICR1_DW (0x7 << 0) /* Data width mask */ | |
83 | ||
84 | #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock | |
85 | wait count mask */ | |
86 | #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock | |
87 | wait count mask */ | |
88 | #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */ | |
89 | #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock | |
90 | wait count mask */ | |
91 | #define CICR2_FSW (0x7 << 0) /* Frame stabilization | |
92 | wait count mask */ | |
93 | ||
94 | #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock | |
95 | wait count mask */ | |
96 | #define CICR3_EFW (0xff << 16) /* End-of-frame line clock | |
97 | wait count mask */ | |
98 | #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */ | |
99 | #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock | |
100 | wait count mask */ | |
101 | #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */ | |
102 | ||
103 | #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */ | |
104 | #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */ | |
105 | #define CICR4_PCP (1 << 22) /* Pixel clock polarity */ | |
106 | #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */ | |
107 | #define CICR4_VSP (1 << 20) /* Vertical sync polarity */ | |
108 | #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */ | |
109 | #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */ | |
110 | #define CICR4_DIV (0xff << 0) /* Clock divisor mask */ | |
111 | ||
112 | #define CISR_FTO (1 << 15) /* FIFO time-out */ | |
113 | #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */ | |
114 | #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */ | |
115 | #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */ | |
116 | #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */ | |
117 | #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */ | |
118 | #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */ | |
119 | #define CISR_EOL (1 << 8) /* End of line */ | |
120 | #define CISR_PAR_ERR (1 << 7) /* Parity error */ | |
121 | #define CISR_CQD (1 << 6) /* Camera interface quick disable */ | |
122 | #define CISR_CDD (1 << 5) /* Camera interface disable done */ | |
123 | #define CISR_SOF (1 << 4) /* Start of frame */ | |
124 | #define CISR_EOF (1 << 3) /* End of frame */ | |
125 | #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */ | |
126 | #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */ | |
127 | #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */ | |
128 | ||
129 | #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */ | |
130 | #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */ | |
131 | #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */ | |
132 | #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */ | |
133 | #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */ | |
134 | #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */ | |
135 | #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */ | |
136 | #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */ | |
137 | ||
7102b773 GL |
138 | #define CICR0_SIM_MP (0 << 24) |
139 | #define CICR0_SIM_SP (1 << 24) | |
140 | #define CICR0_SIM_MS (2 << 24) | |
141 | #define CICR0_SIM_EP (3 << 24) | |
142 | #define CICR0_SIM_ES (4 << 24) | |
143 | ||
144 | #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */ | |
145 | #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */ | |
a5462e5b MR |
146 | #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */ |
147 | #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */ | |
148 | #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */ | |
7102b773 GL |
149 | |
150 | #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */ | |
151 | #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */ | |
152 | #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */ | |
153 | #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */ | |
154 | #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */ | |
155 | ||
156 | #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */ | |
157 | #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */ | |
158 | #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */ | |
159 | #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */ | |
160 | ||
3bc43840 GL |
161 | #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \ |
162 | CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \ | |
163 | CICR0_EOFM | CICR0_FOM) | |
164 | ||
92a8337b RJ |
165 | /* |
166 | * YUV422P picture size should be a multiple of 16, so the heuristic aligns | |
167 | * height, width on 4 byte boundaries to reach the 16 multiple for the size. | |
168 | */ | |
169 | #define YUV422P_X_Y_ALIGN 4 | |
170 | #define YUV422P_SIZE_ALIGN YUV422P_X_Y_ALIGN * YUV422P_X_Y_ALIGN | |
171 | ||
3bc43840 GL |
172 | /* |
173 | * Structures | |
174 | */ | |
a5462e5b MR |
175 | enum pxa_camera_active_dma { |
176 | DMA_Y = 0x1, | |
177 | DMA_U = 0x2, | |
178 | DMA_V = 0x4, | |
179 | }; | |
180 | ||
181 | /* descriptor needed for the PXA DMA engine */ | |
182 | struct pxa_cam_dma { | |
183 | dma_addr_t sg_dma; | |
184 | struct pxa_dma_desc *sg_cpu; | |
185 | size_t sg_size; | |
186 | int sglen; | |
187 | }; | |
3bc43840 GL |
188 | |
189 | /* buffer for one video frame */ | |
190 | struct pxa_buffer { | |
191 | /* common v4l buffer stuff -- must be first */ | |
192 | struct videobuf_buffer vb; | |
193 | ||
194 | const struct soc_camera_data_format *fmt; | |
195 | ||
a5462e5b MR |
196 | /* our descriptor lists for Y, U and V channels */ |
197 | struct pxa_cam_dma dmas[3]; | |
198 | ||
3bc43840 | 199 | int inwork; |
a5462e5b MR |
200 | |
201 | enum pxa_camera_active_dma active_dma; | |
3bc43840 GL |
202 | }; |
203 | ||
3bc43840 GL |
204 | struct pxa_camera_dev { |
205 | struct device *dev; | |
206 | /* PXA27x is only supposed to handle one camera on its Quick Capture | |
207 | * interface. If anyone ever builds hardware to enable more than | |
208 | * one camera, they will have to modify this driver too */ | |
209 | struct soc_camera_device *icd; | |
210 | struct clk *clk; | |
211 | ||
212 | unsigned int irq; | |
213 | void __iomem *base; | |
a5462e5b | 214 | |
e7c50688 | 215 | int channels; |
a5462e5b | 216 | unsigned int dma_chans[3]; |
3bc43840 | 217 | |
3bc43840 GL |
218 | struct pxacamera_platform_data *pdata; |
219 | struct resource *res; | |
220 | unsigned long platform_flags; | |
cf34cba7 GL |
221 | unsigned long ciclk; |
222 | unsigned long mclk; | |
223 | u32 mclk_divisor; | |
3bc43840 GL |
224 | |
225 | struct list_head capture; | |
226 | ||
227 | spinlock_t lock; | |
228 | ||
3bc43840 | 229 | struct pxa_buffer *active; |
5aa2110f | 230 | struct pxa_dma_desc *sg_tail[3]; |
3f6ac497 RJ |
231 | |
232 | u32 save_cicr[5]; | |
3bc43840 GL |
233 | }; |
234 | ||
235 | static const char *pxa_cam_driver_description = "PXA_Camera"; | |
236 | ||
237 | static unsigned int vid_limit = 16; /* Video memory limit, in Mb */ | |
238 | ||
239 | /* | |
240 | * Videobuf operations | |
241 | */ | |
7102b773 GL |
242 | static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count, |
243 | unsigned int *size) | |
3bc43840 GL |
244 | { |
245 | struct soc_camera_device *icd = vq->priv_data; | |
246 | ||
247 | dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size); | |
248 | ||
92a8337b RJ |
249 | *size = roundup(icd->width * icd->height * |
250 | ((icd->current_fmt->depth + 7) >> 3), 8); | |
3bc43840 GL |
251 | |
252 | if (0 == *count) | |
253 | *count = 32; | |
254 | while (*size * *count > vid_limit * 1024 * 1024) | |
255 | (*count)--; | |
256 | ||
257 | return 0; | |
258 | } | |
259 | ||
260 | static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf) | |
261 | { | |
262 | struct soc_camera_device *icd = vq->priv_data; | |
64f5905e | 263 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
3bc43840 GL |
264 | struct pxa_camera_dev *pcdev = ici->priv; |
265 | struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb); | |
a5462e5b | 266 | int i; |
3bc43840 GL |
267 | |
268 | BUG_ON(in_interrupt()); | |
269 | ||
7e28adb2 | 270 | dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
271 | &buf->vb, buf->vb.baddr, buf->vb.bsize); |
272 | ||
273 | /* This waits until this buffer is out of danger, i.e., until it is no | |
274 | * longer in STATE_QUEUED or STATE_ACTIVE */ | |
275 | videobuf_waiton(&buf->vb, 0, 0); | |
276 | videobuf_dma_unmap(vq, dma); | |
277 | videobuf_dma_free(dma); | |
278 | ||
a5462e5b MR |
279 | for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) { |
280 | if (buf->dmas[i].sg_cpu) | |
281 | dma_free_coherent(pcdev->dev, buf->dmas[i].sg_size, | |
282 | buf->dmas[i].sg_cpu, | |
283 | buf->dmas[i].sg_dma); | |
284 | buf->dmas[i].sg_cpu = NULL; | |
285 | } | |
3bc43840 GL |
286 | |
287 | buf->vb.state = VIDEOBUF_NEEDS_INIT; | |
288 | } | |
289 | ||
a5462e5b MR |
290 | static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev, |
291 | struct pxa_buffer *buf, | |
292 | struct videobuf_dmabuf *dma, int channel, | |
293 | int sglen, int sg_start, int cibr, | |
294 | unsigned int size) | |
295 | { | |
296 | struct pxa_cam_dma *pxa_dma = &buf->dmas[channel]; | |
297 | int i; | |
298 | ||
299 | if (pxa_dma->sg_cpu) | |
300 | dma_free_coherent(pcdev->dev, pxa_dma->sg_size, | |
301 | pxa_dma->sg_cpu, pxa_dma->sg_dma); | |
302 | ||
303 | pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc); | |
304 | pxa_dma->sg_cpu = dma_alloc_coherent(pcdev->dev, pxa_dma->sg_size, | |
305 | &pxa_dma->sg_dma, GFP_KERNEL); | |
306 | if (!pxa_dma->sg_cpu) | |
307 | return -ENOMEM; | |
308 | ||
309 | pxa_dma->sglen = sglen; | |
310 | ||
311 | for (i = 0; i < sglen; i++) { | |
312 | int sg_i = sg_start + i; | |
313 | struct scatterlist *sg = dma->sglist; | |
314 | unsigned int dma_len = sg_dma_len(&sg[sg_i]), xfer_len; | |
315 | ||
316 | pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr; | |
317 | pxa_dma->sg_cpu[i].dtadr = sg_dma_address(&sg[sg_i]); | |
318 | ||
319 | /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */ | |
320 | xfer_len = (min(dma_len, size) + 7) & ~7; | |
321 | ||
322 | pxa_dma->sg_cpu[i].dcmd = | |
323 | DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len; | |
324 | size -= dma_len; | |
325 | pxa_dma->sg_cpu[i].ddadr = | |
326 | pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc); | |
327 | } | |
328 | ||
329 | pxa_dma->sg_cpu[sglen - 1].ddadr = DDADR_STOP; | |
330 | pxa_dma->sg_cpu[sglen - 1].dcmd |= DCMD_ENDIRQEN; | |
331 | ||
332 | return 0; | |
333 | } | |
334 | ||
7102b773 GL |
335 | static int pxa_videobuf_prepare(struct videobuf_queue *vq, |
336 | struct videobuf_buffer *vb, enum v4l2_field field) | |
3bc43840 GL |
337 | { |
338 | struct soc_camera_device *icd = vq->priv_data; | |
64f5905e | 339 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
3bc43840 GL |
340 | struct pxa_camera_dev *pcdev = ici->priv; |
341 | struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); | |
a5462e5b MR |
342 | int ret; |
343 | int sglen_y, sglen_yu = 0, sglen_u = 0, sglen_v = 0; | |
344 | int size_y, size_u = 0, size_v = 0; | |
3bc43840 | 345 | |
7e28adb2 | 346 | dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
347 | vb, vb->baddr, vb->bsize); |
348 | ||
349 | /* Added list head initialization on alloc */ | |
350 | WARN_ON(!list_empty(&vb->queue)); | |
351 | ||
352 | #ifdef DEBUG | |
353 | /* This can be useful if you want to see if we actually fill | |
354 | * the buffer with something */ | |
355 | memset((void *)vb->baddr, 0xaa, vb->bsize); | |
356 | #endif | |
357 | ||
358 | BUG_ON(NULL == icd->current_fmt); | |
359 | ||
360 | /* I think, in buf_prepare you only have to protect global data, | |
361 | * the actual buffer is yours */ | |
362 | buf->inwork = 1; | |
363 | ||
364 | if (buf->fmt != icd->current_fmt || | |
365 | vb->width != icd->width || | |
366 | vb->height != icd->height || | |
367 | vb->field != field) { | |
368 | buf->fmt = icd->current_fmt; | |
369 | vb->width = icd->width; | |
370 | vb->height = icd->height; | |
371 | vb->field = field; | |
372 | vb->state = VIDEOBUF_NEEDS_INIT; | |
373 | } | |
374 | ||
375 | vb->size = vb->width * vb->height * ((buf->fmt->depth + 7) >> 3); | |
376 | if (0 != vb->baddr && vb->bsize < vb->size) { | |
377 | ret = -EINVAL; | |
378 | goto out; | |
379 | } | |
380 | ||
381 | if (vb->state == VIDEOBUF_NEEDS_INIT) { | |
382 | unsigned int size = vb->size; | |
383 | struct videobuf_dmabuf *dma = videobuf_to_dma(vb); | |
384 | ||
385 | ret = videobuf_iolock(vq, vb, NULL); | |
386 | if (ret) | |
387 | goto fail; | |
388 | ||
5aa2110f | 389 | if (pcdev->channels == 3) { |
a5462e5b MR |
390 | /* FIXME the calculations should be more precise */ |
391 | sglen_y = dma->sglen / 2; | |
392 | sglen_u = sglen_v = dma->sglen / 4 + 1; | |
393 | sglen_yu = sglen_y + sglen_u; | |
394 | size_y = size / 2; | |
395 | size_u = size_v = size / 4; | |
396 | } else { | |
397 | sglen_y = dma->sglen; | |
398 | size_y = size; | |
399 | } | |
400 | ||
401 | /* init DMA for Y channel */ | |
402 | ret = pxa_init_dma_channel(pcdev, buf, dma, 0, sglen_y, | |
403 | 0, 0x28, size_y); | |
3bc43840 | 404 | |
a5462e5b MR |
405 | if (ret) { |
406 | dev_err(pcdev->dev, | |
407 | "DMA initialization for Y/RGB failed\n"); | |
3bc43840 GL |
408 | goto fail; |
409 | } | |
410 | ||
5aa2110f | 411 | if (pcdev->channels == 3) { |
a5462e5b MR |
412 | /* init DMA for U channel */ |
413 | ret = pxa_init_dma_channel(pcdev, buf, dma, 1, sglen_u, | |
414 | sglen_y, 0x30, size_u); | |
415 | if (ret) { | |
416 | dev_err(pcdev->dev, | |
417 | "DMA initialization for U failed\n"); | |
418 | goto fail_u; | |
419 | } | |
420 | ||
421 | /* init DMA for V channel */ | |
422 | ret = pxa_init_dma_channel(pcdev, buf, dma, 2, sglen_v, | |
423 | sglen_yu, 0x38, size_v); | |
424 | if (ret) { | |
425 | dev_err(pcdev->dev, | |
426 | "DMA initialization for V failed\n"); | |
427 | goto fail_v; | |
428 | } | |
3bc43840 | 429 | } |
3bc43840 GL |
430 | |
431 | vb->state = VIDEOBUF_PREPARED; | |
432 | } | |
433 | ||
434 | buf->inwork = 0; | |
a5462e5b | 435 | buf->active_dma = DMA_Y; |
5aa2110f | 436 | if (pcdev->channels == 3) |
a5462e5b | 437 | buf->active_dma |= DMA_U | DMA_V; |
3bc43840 GL |
438 | |
439 | return 0; | |
440 | ||
a5462e5b MR |
441 | fail_v: |
442 | dma_free_coherent(pcdev->dev, buf->dmas[1].sg_size, | |
443 | buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma); | |
444 | fail_u: | |
445 | dma_free_coherent(pcdev->dev, buf->dmas[0].sg_size, | |
446 | buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma); | |
3bc43840 GL |
447 | fail: |
448 | free_buffer(vq, buf); | |
449 | out: | |
450 | buf->inwork = 0; | |
451 | return ret; | |
452 | } | |
453 | ||
7102b773 GL |
454 | static void pxa_videobuf_queue(struct videobuf_queue *vq, |
455 | struct videobuf_buffer *vb) | |
3bc43840 GL |
456 | { |
457 | struct soc_camera_device *icd = vq->priv_data; | |
64f5905e | 458 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
3bc43840 GL |
459 | struct pxa_camera_dev *pcdev = ici->priv; |
460 | struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); | |
7102b773 | 461 | struct pxa_buffer *active; |
3bc43840 | 462 | unsigned long flags; |
5aa2110f | 463 | int i; |
3bc43840 | 464 | |
7e28adb2 | 465 | dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
466 | vb, vb->baddr, vb->bsize); |
467 | spin_lock_irqsave(&pcdev->lock, flags); | |
468 | ||
469 | list_add_tail(&vb->queue, &pcdev->capture); | |
470 | ||
471 | vb->state = VIDEOBUF_ACTIVE; | |
7102b773 | 472 | active = pcdev->active; |
3bc43840 | 473 | |
7102b773 | 474 | if (!active) { |
5ca11fa3 EM |
475 | unsigned long cifr, cicr0; |
476 | ||
477 | cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F; | |
478 | __raw_writel(cifr, pcdev->base + CIFR); | |
a5462e5b | 479 | |
5aa2110f GL |
480 | for (i = 0; i < pcdev->channels; i++) { |
481 | DDADR(pcdev->dma_chans[i]) = buf->dmas[i].sg_dma; | |
482 | DCSR(pcdev->dma_chans[i]) = DCSR_RUN; | |
483 | pcdev->sg_tail[i] = buf->dmas[i].sg_cpu + buf->dmas[i].sglen - 1; | |
a5462e5b MR |
484 | } |
485 | ||
3bc43840 | 486 | pcdev->active = buf; |
5ca11fa3 EM |
487 | |
488 | cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB; | |
489 | __raw_writel(cicr0, pcdev->base + CICR0); | |
3bc43840 | 490 | } else { |
a5462e5b MR |
491 | struct pxa_cam_dma *buf_dma; |
492 | struct pxa_cam_dma *act_dma; | |
a5462e5b | 493 | int nents; |
a5462e5b | 494 | |
e7c50688 | 495 | for (i = 0; i < pcdev->channels; i++) { |
a5462e5b MR |
496 | buf_dma = &buf->dmas[i]; |
497 | act_dma = &active->dmas[i]; | |
498 | nents = buf_dma->sglen; | |
499 | ||
500 | /* Stop DMA engine */ | |
501 | DCSR(pcdev->dma_chans[i]) = 0; | |
502 | ||
503 | /* Add the descriptors we just initialized to | |
504 | the currently running chain */ | |
5aa2110f GL |
505 | pcdev->sg_tail[i]->ddadr = buf_dma->sg_dma; |
506 | pcdev->sg_tail[i] = buf_dma->sg_cpu + buf_dma->sglen - 1; | |
a5462e5b MR |
507 | |
508 | /* Setup a dummy descriptor with the DMA engines current | |
509 | * state | |
3bc43840 | 510 | */ |
a5462e5b MR |
511 | buf_dma->sg_cpu[nents].dsadr = |
512 | pcdev->res->start + 0x28 + i*8; /* CIBRx */ | |
513 | buf_dma->sg_cpu[nents].dtadr = | |
514 | DTADR(pcdev->dma_chans[i]); | |
515 | buf_dma->sg_cpu[nents].dcmd = | |
516 | DCMD(pcdev->dma_chans[i]); | |
517 | ||
518 | if (DDADR(pcdev->dma_chans[i]) == DDADR_STOP) { | |
519 | /* The DMA engine is on the last | |
520 | descriptor, set the next descriptors | |
521 | address to the descriptors we just | |
522 | initialized */ | |
523 | buf_dma->sg_cpu[nents].ddadr = buf_dma->sg_dma; | |
524 | } else { | |
525 | buf_dma->sg_cpu[nents].ddadr = | |
526 | DDADR(pcdev->dma_chans[i]); | |
527 | } | |
528 | ||
529 | /* The next descriptor is the dummy descriptor */ | |
530 | DDADR(pcdev->dma_chans[i]) = buf_dma->sg_dma + nents * | |
531 | sizeof(struct pxa_dma_desc); | |
532 | ||
533 | DCSR(pcdev->dma_chans[i]) = DCSR_RUN; | |
3bc43840 | 534 | } |
3bc43840 GL |
535 | } |
536 | ||
537 | spin_unlock_irqrestore(&pcdev->lock, flags); | |
3bc43840 GL |
538 | } |
539 | ||
540 | static void pxa_videobuf_release(struct videobuf_queue *vq, | |
541 | struct videobuf_buffer *vb) | |
542 | { | |
543 | struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); | |
544 | #ifdef DEBUG | |
545 | struct soc_camera_device *icd = vq->priv_data; | |
546 | ||
7e28adb2 | 547 | dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
548 | vb, vb->baddr, vb->bsize); |
549 | ||
550 | switch (vb->state) { | |
551 | case VIDEOBUF_ACTIVE: | |
7e28adb2 | 552 | dev_dbg(&icd->dev, "%s (active)\n", __func__); |
3bc43840 GL |
553 | break; |
554 | case VIDEOBUF_QUEUED: | |
7e28adb2 | 555 | dev_dbg(&icd->dev, "%s (queued)\n", __func__); |
3bc43840 GL |
556 | break; |
557 | case VIDEOBUF_PREPARED: | |
7e28adb2 | 558 | dev_dbg(&icd->dev, "%s (prepared)\n", __func__); |
3bc43840 GL |
559 | break; |
560 | default: | |
7e28adb2 | 561 | dev_dbg(&icd->dev, "%s (unknown)\n", __func__); |
3bc43840 GL |
562 | break; |
563 | } | |
564 | #endif | |
565 | ||
566 | free_buffer(vq, buf); | |
567 | } | |
568 | ||
a5462e5b MR |
569 | static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev, |
570 | struct videobuf_buffer *vb, | |
571 | struct pxa_buffer *buf) | |
572 | { | |
5ca11fa3 EM |
573 | unsigned long cicr0; |
574 | ||
a5462e5b MR |
575 | /* _init is used to debug races, see comment in pxa_camera_reqbufs() */ |
576 | list_del_init(&vb->queue); | |
577 | vb->state = VIDEOBUF_DONE; | |
578 | do_gettimeofday(&vb->ts); | |
579 | vb->field_count++; | |
580 | wake_up(&vb->done); | |
581 | ||
582 | if (list_empty(&pcdev->capture)) { | |
583 | pcdev->active = NULL; | |
584 | DCSR(pcdev->dma_chans[0]) = 0; | |
585 | DCSR(pcdev->dma_chans[1]) = 0; | |
586 | DCSR(pcdev->dma_chans[2]) = 0; | |
5ca11fa3 EM |
587 | |
588 | cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB; | |
589 | __raw_writel(cicr0, pcdev->base + CICR0); | |
a5462e5b MR |
590 | return; |
591 | } | |
592 | ||
593 | pcdev->active = list_entry(pcdev->capture.next, | |
594 | struct pxa_buffer, vb.queue); | |
595 | } | |
596 | ||
597 | static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev, | |
598 | enum pxa_camera_active_dma act_dma) | |
3bc43840 | 599 | { |
3bc43840 GL |
600 | struct pxa_buffer *buf; |
601 | unsigned long flags; | |
e7c50688 | 602 | u32 status, camera_status, overrun; |
3bc43840 | 603 | struct videobuf_buffer *vb; |
5ca11fa3 | 604 | unsigned long cifr, cicr0; |
3bc43840 GL |
605 | |
606 | spin_lock_irqsave(&pcdev->lock, flags); | |
607 | ||
a5462e5b MR |
608 | status = DCSR(channel); |
609 | DCSR(channel) = status | DCSR_ENDINTR; | |
7102b773 | 610 | |
3bc43840 | 611 | if (status & DCSR_BUSERR) { |
7102b773 | 612 | dev_err(pcdev->dev, "DMA Bus Error IRQ!\n"); |
3bc43840 GL |
613 | goto out; |
614 | } | |
615 | ||
616 | if (!(status & DCSR_ENDINTR)) { | |
7102b773 GL |
617 | dev_err(pcdev->dev, "Unknown DMA IRQ source, " |
618 | "status: 0x%08x\n", status); | |
3bc43840 GL |
619 | goto out; |
620 | } | |
621 | ||
3bc43840 | 622 | if (!pcdev->active) { |
7102b773 | 623 | dev_err(pcdev->dev, "DMA End IRQ with no active buffer!\n"); |
3bc43840 GL |
624 | goto out; |
625 | } | |
626 | ||
5ca11fa3 | 627 | camera_status = __raw_readl(pcdev->base + CISR); |
e7c50688 GL |
628 | overrun = CISR_IFO_0; |
629 | if (pcdev->channels == 3) | |
630 | overrun |= CISR_IFO_1 | CISR_IFO_2; | |
631 | if (camera_status & overrun) { | |
632 | dev_dbg(pcdev->dev, "FIFO overrun! CISR: %x\n", camera_status); | |
633 | /* Stop the Capture Interface */ | |
5ca11fa3 EM |
634 | cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB; |
635 | __raw_writel(cicr0, pcdev->base + CICR0); | |
636 | ||
e7c50688 GL |
637 | /* Stop DMA */ |
638 | DCSR(channel) = 0; | |
639 | /* Reset the FIFOs */ | |
5ca11fa3 EM |
640 | cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F; |
641 | __raw_writel(cifr, pcdev->base + CIFR); | |
e7c50688 | 642 | /* Enable End-Of-Frame Interrupt */ |
5ca11fa3 EM |
643 | cicr0 &= ~CICR0_EOFM; |
644 | __raw_writel(cicr0, pcdev->base + CICR0); | |
e7c50688 | 645 | /* Restart the Capture Interface */ |
5ca11fa3 | 646 | __raw_writel(cicr0 | CICR0_ENB, pcdev->base + CICR0); |
e7c50688 GL |
647 | goto out; |
648 | } | |
649 | ||
3bc43840 GL |
650 | vb = &pcdev->active->vb; |
651 | buf = container_of(vb, struct pxa_buffer, vb); | |
652 | WARN_ON(buf->inwork || list_empty(&vb->queue)); | |
7e28adb2 | 653 | dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
654 | vb, vb->baddr, vb->bsize); |
655 | ||
a5462e5b MR |
656 | buf->active_dma &= ~act_dma; |
657 | if (!buf->active_dma) | |
658 | pxa_camera_wakeup(pcdev, vb, buf); | |
3bc43840 GL |
659 | |
660 | out: | |
661 | spin_unlock_irqrestore(&pcdev->lock, flags); | |
662 | } | |
663 | ||
a5462e5b MR |
664 | static void pxa_camera_dma_irq_y(int channel, void *data) |
665 | { | |
666 | struct pxa_camera_dev *pcdev = data; | |
667 | pxa_camera_dma_irq(channel, pcdev, DMA_Y); | |
668 | } | |
669 | ||
670 | static void pxa_camera_dma_irq_u(int channel, void *data) | |
671 | { | |
672 | struct pxa_camera_dev *pcdev = data; | |
673 | pxa_camera_dma_irq(channel, pcdev, DMA_U); | |
674 | } | |
675 | ||
676 | static void pxa_camera_dma_irq_v(int channel, void *data) | |
677 | { | |
678 | struct pxa_camera_dev *pcdev = data; | |
679 | pxa_camera_dma_irq(channel, pcdev, DMA_V); | |
680 | } | |
681 | ||
7102b773 | 682 | static struct videobuf_queue_ops pxa_videobuf_ops = { |
3bc43840 GL |
683 | .buf_setup = pxa_videobuf_setup, |
684 | .buf_prepare = pxa_videobuf_prepare, | |
685 | .buf_queue = pxa_videobuf_queue, | |
686 | .buf_release = pxa_videobuf_release, | |
687 | }; | |
688 | ||
a034d1b7 | 689 | static void pxa_camera_init_videobuf(struct videobuf_queue *q, |
092d3921 PZ |
690 | struct soc_camera_device *icd) |
691 | { | |
a034d1b7 MD |
692 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
693 | struct pxa_camera_dev *pcdev = ici->priv; | |
694 | ||
092d3921 PZ |
695 | /* We must pass NULL as dev pointer, then all pci_* dma operations |
696 | * transform to normal dma_* ones. */ | |
a034d1b7 | 697 | videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock, |
092d3921 PZ |
698 | V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE, |
699 | sizeof(struct pxa_buffer), icd); | |
700 | } | |
701 | ||
cf34cba7 | 702 | static u32 mclk_get_divisor(struct pxa_camera_dev *pcdev) |
3bc43840 | 703 | { |
cf34cba7 GL |
704 | unsigned long mclk = pcdev->mclk; |
705 | u32 div; | |
3bc43840 GL |
706 | unsigned long lcdclk; |
707 | ||
cf34cba7 GL |
708 | lcdclk = clk_get_rate(pcdev->clk); |
709 | pcdev->ciclk = lcdclk; | |
3bc43840 | 710 | |
cf34cba7 GL |
711 | /* mclk <= ciclk / 4 (27.4.2) */ |
712 | if (mclk > lcdclk / 4) { | |
713 | mclk = lcdclk / 4; | |
714 | dev_warn(pcdev->dev, "Limiting master clock to %lu\n", mclk); | |
715 | } | |
716 | ||
717 | /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */ | |
718 | div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1; | |
3bc43840 | 719 | |
cf34cba7 GL |
720 | /* If we're not supplying MCLK, leave it at 0 */ |
721 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
722 | pcdev->mclk = lcdclk / (2 * (div + 1)); | |
3bc43840 | 723 | |
cf34cba7 GL |
724 | dev_dbg(pcdev->dev, "LCD clock %luHz, target freq %luHz, " |
725 | "divisor %u\n", lcdclk, mclk, div); | |
3bc43840 GL |
726 | |
727 | return div; | |
728 | } | |
729 | ||
cf34cba7 GL |
730 | static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev, |
731 | unsigned long pclk) | |
732 | { | |
733 | /* We want a timeout > 1 pixel time, not ">=" */ | |
734 | u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1; | |
735 | ||
736 | __raw_writel(ciclk_per_pixel, pcdev->base + CITOR); | |
737 | } | |
738 | ||
7102b773 | 739 | static void pxa_camera_activate(struct pxa_camera_dev *pcdev) |
3bc43840 GL |
740 | { |
741 | struct pxacamera_platform_data *pdata = pcdev->pdata; | |
742 | u32 cicr4 = 0; | |
743 | ||
744 | dev_dbg(pcdev->dev, "Registered platform device at %p data %p\n", | |
745 | pcdev, pdata); | |
746 | ||
747 | if (pdata && pdata->init) { | |
7e28adb2 | 748 | dev_dbg(pcdev->dev, "%s: Init gpios\n", __func__); |
3bc43840 GL |
749 | pdata->init(pcdev->dev); |
750 | } | |
751 | ||
5ca11fa3 EM |
752 | /* disable all interrupts */ |
753 | __raw_writel(0x3ff, pcdev->base + CICR0); | |
3bc43840 GL |
754 | |
755 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
756 | cicr4 |= CICR4_PCLK_EN; | |
757 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
758 | cicr4 |= CICR4_MCLK_EN; | |
759 | if (pcdev->platform_flags & PXA_CAMERA_PCP) | |
760 | cicr4 |= CICR4_PCP; | |
761 | if (pcdev->platform_flags & PXA_CAMERA_HSP) | |
762 | cicr4 |= CICR4_HSP; | |
763 | if (pcdev->platform_flags & PXA_CAMERA_VSP) | |
764 | cicr4 |= CICR4_VSP; | |
765 | ||
cf34cba7 GL |
766 | __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4); |
767 | ||
768 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
769 | /* Initialise the timeout under the assumption pclk = mclk */ | |
770 | recalculate_fifo_timeout(pcdev, pcdev->mclk); | |
771 | else | |
772 | /* "Safe default" - 13MHz */ | |
773 | recalculate_fifo_timeout(pcdev, 13000000); | |
3bc43840 GL |
774 | |
775 | clk_enable(pcdev->clk); | |
776 | } | |
777 | ||
7102b773 | 778 | static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev) |
3bc43840 | 779 | { |
3bc43840 | 780 | clk_disable(pcdev->clk); |
3bc43840 GL |
781 | } |
782 | ||
783 | static irqreturn_t pxa_camera_irq(int irq, void *data) | |
784 | { | |
785 | struct pxa_camera_dev *pcdev = data; | |
5ca11fa3 | 786 | unsigned long status, cicr0; |
3bc43840 | 787 | |
5ca11fa3 EM |
788 | status = __raw_readl(pcdev->base + CISR); |
789 | dev_dbg(pcdev->dev, "Camera interrupt status 0x%lx\n", status); | |
3bc43840 | 790 | |
e7c50688 GL |
791 | if (!status) |
792 | return IRQ_NONE; | |
793 | ||
5ca11fa3 | 794 | __raw_writel(status, pcdev->base + CISR); |
e7c50688 GL |
795 | |
796 | if (status & CISR_EOF) { | |
797 | int i; | |
798 | for (i = 0; i < pcdev->channels; i++) { | |
799 | DDADR(pcdev->dma_chans[i]) = | |
800 | pcdev->active->dmas[i].sg_dma; | |
801 | DCSR(pcdev->dma_chans[i]) = DCSR_RUN; | |
802 | } | |
5ca11fa3 EM |
803 | cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM; |
804 | __raw_writel(cicr0, pcdev->base + CICR0); | |
e7c50688 GL |
805 | } |
806 | ||
3bc43840 GL |
807 | return IRQ_HANDLED; |
808 | } | |
809 | ||
1c3bb743 GL |
810 | /* |
811 | * The following two functions absolutely depend on the fact, that | |
812 | * there can be only one camera on PXA quick capture interface | |
813 | * Called with .video_lock held | |
814 | */ | |
7102b773 | 815 | static int pxa_camera_add_device(struct soc_camera_device *icd) |
3bc43840 GL |
816 | { |
817 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
818 | struct pxa_camera_dev *pcdev = ici->priv; | |
819 | int ret; | |
820 | ||
3bc43840 GL |
821 | if (pcdev->icd) { |
822 | ret = -EBUSY; | |
823 | goto ebusy; | |
824 | } | |
825 | ||
826 | dev_info(&icd->dev, "PXA Camera driver attached to camera %d\n", | |
827 | icd->devnum); | |
828 | ||
7102b773 | 829 | pxa_camera_activate(pcdev); |
3bc43840 GL |
830 | ret = icd->ops->init(icd); |
831 | ||
832 | if (!ret) | |
833 | pcdev->icd = icd; | |
834 | ||
835 | ebusy: | |
3bc43840 GL |
836 | return ret; |
837 | } | |
838 | ||
1c3bb743 | 839 | /* Called with .video_lock held */ |
7102b773 | 840 | static void pxa_camera_remove_device(struct soc_camera_device *icd) |
3bc43840 GL |
841 | { |
842 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
843 | struct pxa_camera_dev *pcdev = ici->priv; | |
844 | ||
845 | BUG_ON(icd != pcdev->icd); | |
846 | ||
847 | dev_info(&icd->dev, "PXA Camera driver detached from camera %d\n", | |
848 | icd->devnum); | |
849 | ||
850 | /* disable capture, disable interrupts */ | |
5ca11fa3 | 851 | __raw_writel(0x3ff, pcdev->base + CICR0); |
a5462e5b | 852 | |
3bc43840 | 853 | /* Stop DMA engine */ |
a5462e5b MR |
854 | DCSR(pcdev->dma_chans[0]) = 0; |
855 | DCSR(pcdev->dma_chans[1]) = 0; | |
856 | DCSR(pcdev->dma_chans[2]) = 0; | |
3bc43840 GL |
857 | |
858 | icd->ops->release(icd); | |
859 | ||
7102b773 | 860 | pxa_camera_deactivate(pcdev); |
3bc43840 GL |
861 | |
862 | pcdev->icd = NULL; | |
863 | } | |
864 | ||
ad5f2e85 GL |
865 | static int test_platform_param(struct pxa_camera_dev *pcdev, |
866 | unsigned char buswidth, unsigned long *flags) | |
3bc43840 | 867 | { |
ad5f2e85 GL |
868 | /* |
869 | * Platform specified synchronization and pixel clock polarities are | |
870 | * only a recommendation and are only used during probing. The PXA270 | |
871 | * quick capture interface supports both. | |
872 | */ | |
873 | *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ? | |
874 | SOCAM_MASTER : SOCAM_SLAVE) | | |
875 | SOCAM_HSYNC_ACTIVE_HIGH | | |
876 | SOCAM_HSYNC_ACTIVE_LOW | | |
877 | SOCAM_VSYNC_ACTIVE_HIGH | | |
878 | SOCAM_VSYNC_ACTIVE_LOW | | |
2d9329f3 | 879 | SOCAM_DATA_ACTIVE_HIGH | |
ad5f2e85 GL |
880 | SOCAM_PCLK_SAMPLE_RISING | |
881 | SOCAM_PCLK_SAMPLE_FALLING; | |
3bc43840 GL |
882 | |
883 | /* If requested data width is supported by the platform, use it */ | |
ad5f2e85 | 884 | switch (buswidth) { |
3bc43840 | 885 | case 10: |
ad5f2e85 GL |
886 | if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10)) |
887 | return -EINVAL; | |
888 | *flags |= SOCAM_DATAWIDTH_10; | |
3bc43840 GL |
889 | break; |
890 | case 9: | |
ad5f2e85 GL |
891 | if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9)) |
892 | return -EINVAL; | |
893 | *flags |= SOCAM_DATAWIDTH_9; | |
3bc43840 GL |
894 | break; |
895 | case 8: | |
ad5f2e85 GL |
896 | if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8)) |
897 | return -EINVAL; | |
898 | *flags |= SOCAM_DATAWIDTH_8; | |
2a48fc73 RJ |
899 | break; |
900 | default: | |
901 | return -EINVAL; | |
3bc43840 | 902 | } |
ad5f2e85 GL |
903 | |
904 | return 0; | |
905 | } | |
906 | ||
907 | static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt) | |
908 | { | |
64f5905e | 909 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
ad5f2e85 GL |
910 | struct pxa_camera_dev *pcdev = ici->priv; |
911 | unsigned long dw, bpp, bus_flags, camera_flags, common_flags; | |
5ca11fa3 | 912 | u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0; |
ad5f2e85 GL |
913 | int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags); |
914 | ||
915 | if (ret < 0) | |
916 | return ret; | |
917 | ||
918 | camera_flags = icd->ops->query_bus_param(icd); | |
919 | ||
920 | common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags); | |
921 | if (!common_flags) | |
3bc43840 GL |
922 | return -EINVAL; |
923 | ||
e7c50688 GL |
924 | pcdev->channels = 1; |
925 | ||
ad5f2e85 GL |
926 | /* Make choises, based on platform preferences */ |
927 | if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) && | |
928 | (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) { | |
929 | if (pcdev->platform_flags & PXA_CAMERA_HSP) | |
930 | common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH; | |
931 | else | |
932 | common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW; | |
933 | } | |
934 | ||
935 | if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) && | |
936 | (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) { | |
937 | if (pcdev->platform_flags & PXA_CAMERA_VSP) | |
938 | common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH; | |
939 | else | |
940 | common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW; | |
941 | } | |
942 | ||
943 | if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) && | |
944 | (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) { | |
945 | if (pcdev->platform_flags & PXA_CAMERA_PCP) | |
946 | common_flags &= ~SOCAM_PCLK_SAMPLE_RISING; | |
947 | else | |
948 | common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING; | |
949 | } | |
950 | ||
951 | ret = icd->ops->set_bus_param(icd, common_flags); | |
3bc43840 GL |
952 | if (ret < 0) |
953 | return ret; | |
954 | ||
955 | /* Datawidth is now guaranteed to be equal to one of the three values. | |
956 | * We fix bit-per-pixel equal to data-width... */ | |
ad5f2e85 GL |
957 | switch (common_flags & SOCAM_DATAWIDTH_MASK) { |
958 | case SOCAM_DATAWIDTH_10: | |
3bc43840 GL |
959 | dw = 4; |
960 | bpp = 0x40; | |
961 | break; | |
ad5f2e85 | 962 | case SOCAM_DATAWIDTH_9: |
3bc43840 GL |
963 | dw = 3; |
964 | bpp = 0x20; | |
965 | break; | |
966 | default: | |
967 | /* Actually it can only be 8 now, | |
968 | * default is just to silence compiler warnings */ | |
ad5f2e85 | 969 | case SOCAM_DATAWIDTH_8: |
3bc43840 GL |
970 | dw = 2; |
971 | bpp = 0; | |
972 | } | |
973 | ||
974 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
975 | cicr4 |= CICR4_PCLK_EN; | |
976 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
977 | cicr4 |= CICR4_MCLK_EN; | |
ad5f2e85 | 978 | if (common_flags & SOCAM_PCLK_SAMPLE_FALLING) |
3bc43840 | 979 | cicr4 |= CICR4_PCP; |
ad5f2e85 | 980 | if (common_flags & SOCAM_HSYNC_ACTIVE_LOW) |
3bc43840 | 981 | cicr4 |= CICR4_HSP; |
ad5f2e85 | 982 | if (common_flags & SOCAM_VSYNC_ACTIVE_LOW) |
3bc43840 GL |
983 | cicr4 |= CICR4_VSP; |
984 | ||
5ca11fa3 | 985 | cicr0 = __raw_readl(pcdev->base + CICR0); |
3bc43840 | 986 | if (cicr0 & CICR0_ENB) |
5ca11fa3 | 987 | __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0); |
a5462e5b MR |
988 | |
989 | cicr1 = CICR1_PPL_VAL(icd->width - 1) | bpp | dw; | |
990 | ||
991 | switch (pixfmt) { | |
992 | case V4L2_PIX_FMT_YUV422P: | |
e7c50688 | 993 | pcdev->channels = 3; |
a5462e5b | 994 | cicr1 |= CICR1_YCBCR_F; |
2a48fc73 RJ |
995 | /* |
996 | * Normally, pxa bus wants as input UYVY format. We allow all | |
997 | * reorderings of the YUV422 format, as no processing is done, | |
998 | * and the YUV stream is just passed through without any | |
999 | * transformation. Note that UYVY is the only format that | |
1000 | * should be used if pxa framebuffer Overlay2 is used. | |
1001 | */ | |
1002 | case V4L2_PIX_FMT_UYVY: | |
1003 | case V4L2_PIX_FMT_VYUY: | |
a5462e5b | 1004 | case V4L2_PIX_FMT_YUYV: |
2a48fc73 | 1005 | case V4L2_PIX_FMT_YVYU: |
a5462e5b MR |
1006 | cicr1 |= CICR1_COLOR_SP_VAL(2); |
1007 | break; | |
1008 | case V4L2_PIX_FMT_RGB555: | |
1009 | cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) | | |
1010 | CICR1_TBIT | CICR1_COLOR_SP_VAL(1); | |
1011 | break; | |
1012 | case V4L2_PIX_FMT_RGB565: | |
1013 | cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2); | |
1014 | break; | |
1015 | } | |
1016 | ||
5ca11fa3 EM |
1017 | cicr2 = 0; |
1018 | cicr3 = CICR3_LPF_VAL(icd->height - 1) | | |
3bc43840 | 1019 | CICR3_BFW_VAL(min((unsigned short)255, icd->y_skip_top)); |
cf34cba7 | 1020 | cicr4 |= pcdev->mclk_divisor; |
5ca11fa3 EM |
1021 | |
1022 | __raw_writel(cicr1, pcdev->base + CICR1); | |
1023 | __raw_writel(cicr2, pcdev->base + CICR2); | |
1024 | __raw_writel(cicr3, pcdev->base + CICR3); | |
1025 | __raw_writel(cicr4, pcdev->base + CICR4); | |
3bc43840 GL |
1026 | |
1027 | /* CIF interrupts are not used, only DMA */ | |
5ca11fa3 EM |
1028 | cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ? |
1029 | CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP)); | |
1030 | cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK; | |
1031 | __raw_writel(cicr0, pcdev->base + CICR0); | |
3bc43840 GL |
1032 | |
1033 | return 0; | |
1034 | } | |
1035 | ||
2a48fc73 RJ |
1036 | static int pxa_camera_try_bus_param(struct soc_camera_device *icd, |
1037 | unsigned char buswidth) | |
ad5f2e85 | 1038 | { |
cf34cba7 | 1039 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
ad5f2e85 GL |
1040 | struct pxa_camera_dev *pcdev = ici->priv; |
1041 | unsigned long bus_flags, camera_flags; | |
2a48fc73 | 1042 | int ret = test_platform_param(pcdev, buswidth, &bus_flags); |
ad5f2e85 GL |
1043 | |
1044 | if (ret < 0) | |
1045 | return ret; | |
1046 | ||
1047 | camera_flags = icd->ops->query_bus_param(icd); | |
1048 | ||
1049 | return soc_camera_bus_param_compatible(camera_flags, bus_flags) ? 0 : -EINVAL; | |
1050 | } | |
1051 | ||
2a48fc73 RJ |
1052 | static const struct soc_camera_data_format pxa_camera_formats[] = { |
1053 | { | |
1054 | .name = "Planar YUV422 16 bit", | |
1055 | .depth = 16, | |
1056 | .fourcc = V4L2_PIX_FMT_YUV422P, | |
1057 | .colorspace = V4L2_COLORSPACE_JPEG, | |
1058 | }, | |
1059 | }; | |
1060 | ||
1061 | static bool buswidth_supported(struct soc_camera_device *icd, int depth) | |
ad5f2e85 | 1062 | { |
2a48fc73 RJ |
1063 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
1064 | struct pxa_camera_dev *pcdev = ici->priv; | |
1065 | ||
1066 | switch (depth) { | |
1067 | case 8: | |
1068 | return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8); | |
1069 | case 9: | |
1070 | return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9); | |
1071 | case 10: | |
1072 | return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10); | |
1073 | } | |
1074 | return false; | |
ad5f2e85 GL |
1075 | } |
1076 | ||
2a48fc73 | 1077 | static int required_buswidth(const struct soc_camera_data_format *fmt) |
3bc43840 | 1078 | { |
2a48fc73 RJ |
1079 | switch (fmt->fourcc) { |
1080 | case V4L2_PIX_FMT_UYVY: | |
1081 | case V4L2_PIX_FMT_VYUY: | |
1082 | case V4L2_PIX_FMT_YUYV: | |
1083 | case V4L2_PIX_FMT_YVYU: | |
1084 | case V4L2_PIX_FMT_RGB565: | |
1085 | case V4L2_PIX_FMT_RGB555: | |
1086 | return 8; | |
1087 | default: | |
1088 | return fmt->depth; | |
1089 | } | |
1090 | } | |
1091 | ||
1092 | static int pxa_camera_get_formats(struct soc_camera_device *icd, int idx, | |
1093 | struct soc_camera_format_xlate *xlate) | |
1094 | { | |
1095 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
1096 | int formats = 0, buswidth, ret; | |
1097 | ||
1098 | buswidth = required_buswidth(icd->formats + idx); | |
1099 | ||
1100 | if (!buswidth_supported(icd, buswidth)) | |
1101 | return 0; | |
3bc43840 | 1102 | |
2a48fc73 RJ |
1103 | ret = pxa_camera_try_bus_param(icd, buswidth); |
1104 | if (ret < 0) | |
1105 | return 0; | |
1106 | ||
1107 | switch (icd->formats[idx].fourcc) { | |
1108 | case V4L2_PIX_FMT_UYVY: | |
1109 | formats++; | |
1110 | if (xlate) { | |
1111 | xlate->host_fmt = &pxa_camera_formats[0]; | |
1112 | xlate->cam_fmt = icd->formats + idx; | |
1113 | xlate->buswidth = buswidth; | |
1114 | xlate++; | |
1115 | dev_dbg(&ici->dev, "Providing format %s using %s\n", | |
1116 | pxa_camera_formats[0].name, | |
1117 | icd->formats[idx].name); | |
1118 | } | |
1119 | case V4L2_PIX_FMT_VYUY: | |
1120 | case V4L2_PIX_FMT_YUYV: | |
1121 | case V4L2_PIX_FMT_YVYU: | |
1122 | case V4L2_PIX_FMT_RGB565: | |
1123 | case V4L2_PIX_FMT_RGB555: | |
1124 | formats++; | |
1125 | if (xlate) { | |
1126 | xlate->host_fmt = icd->formats + idx; | |
1127 | xlate->cam_fmt = icd->formats + idx; | |
1128 | xlate->buswidth = buswidth; | |
1129 | xlate++; | |
1130 | dev_dbg(&ici->dev, "Providing format %s packed\n", | |
1131 | icd->formats[idx].name); | |
1132 | } | |
1133 | break; | |
1134 | default: | |
1135 | /* Generic pass-through */ | |
1136 | formats++; | |
1137 | if (xlate) { | |
1138 | xlate->host_fmt = icd->formats + idx; | |
1139 | xlate->cam_fmt = icd->formats + idx; | |
1140 | xlate->buswidth = icd->formats[idx].depth; | |
1141 | xlate++; | |
1142 | dev_dbg(&ici->dev, | |
1143 | "Providing format %s in pass-through mode\n", | |
1144 | icd->formats[idx].name); | |
1145 | } | |
1146 | } | |
1147 | ||
1148 | return formats; | |
1149 | } | |
1150 | ||
09e231b3 GL |
1151 | static int pxa_camera_set_crop(struct soc_camera_device *icd, |
1152 | struct v4l2_rect *rect) | |
1153 | { | |
1154 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
1155 | struct pxa_camera_dev *pcdev = ici->priv; | |
1156 | struct soc_camera_sense sense = { | |
1157 | .master_clock = pcdev->mclk, | |
1158 | .pixel_clock_max = pcdev->ciclk / 4, | |
1159 | }; | |
1160 | int ret; | |
1161 | ||
1162 | /* If PCLK is used to latch data from the sensor, check sense */ | |
1163 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
1164 | icd->sense = &sense; | |
1165 | ||
1166 | ret = icd->ops->set_crop(icd, rect); | |
1167 | ||
1168 | icd->sense = NULL; | |
1169 | ||
1170 | if (ret < 0) { | |
1171 | dev_warn(&ici->dev, "Failed to crop to %ux%u@%u:%u\n", | |
1172 | rect->width, rect->height, rect->left, rect->top); | |
1173 | } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) { | |
1174 | if (sense.pixel_clock > sense.pixel_clock_max) { | |
1175 | dev_err(&ici->dev, | |
1176 | "pixel clock %lu set by the camera too high!", | |
1177 | sense.pixel_clock); | |
1178 | return -EIO; | |
1179 | } | |
1180 | recalculate_fifo_timeout(pcdev, sense.pixel_clock); | |
1181 | } | |
1182 | ||
1183 | return ret; | |
1184 | } | |
1185 | ||
d8fac217 | 1186 | static int pxa_camera_set_fmt(struct soc_camera_device *icd, |
09e231b3 | 1187 | struct v4l2_format *f) |
ad5f2e85 | 1188 | { |
2a48fc73 | 1189 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
cf34cba7 | 1190 | struct pxa_camera_dev *pcdev = ici->priv; |
0ad675eb GL |
1191 | const struct soc_camera_data_format *cam_fmt = NULL; |
1192 | const struct soc_camera_format_xlate *xlate = NULL; | |
cf34cba7 GL |
1193 | struct soc_camera_sense sense = { |
1194 | .master_clock = pcdev->mclk, | |
1195 | .pixel_clock_max = pcdev->ciclk / 4, | |
1196 | }; | |
09e231b3 GL |
1197 | struct v4l2_pix_format *pix = &f->fmt.pix; |
1198 | struct v4l2_format cam_f = *f; | |
0ad675eb | 1199 | int ret; |
25c4d74e | 1200 | |
09e231b3 GL |
1201 | xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); |
1202 | if (!xlate) { | |
1203 | dev_warn(&ici->dev, "Format %x not found\n", pix->pixelformat); | |
1204 | return -EINVAL; | |
0ad675eb | 1205 | } |
2a48fc73 | 1206 | |
09e231b3 GL |
1207 | cam_fmt = xlate->cam_fmt; |
1208 | ||
cf34cba7 GL |
1209 | /* If PCLK is used to latch data from the sensor, check sense */ |
1210 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
1211 | icd->sense = &sense; | |
1212 | ||
09e231b3 GL |
1213 | cam_f.fmt.pix.pixelformat = cam_fmt->fourcc; |
1214 | ret = icd->ops->set_fmt(icd, &cam_f); | |
2a48fc73 | 1215 | |
cf34cba7 GL |
1216 | icd->sense = NULL; |
1217 | ||
1218 | if (ret < 0) { | |
2a48fc73 | 1219 | dev_warn(&ici->dev, "Failed to configure for format %x\n", |
09e231b3 | 1220 | pix->pixelformat); |
cf34cba7 GL |
1221 | } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) { |
1222 | if (sense.pixel_clock > sense.pixel_clock_max) { | |
1223 | dev_err(&ici->dev, | |
1224 | "pixel clock %lu set by the camera too high!", | |
1225 | sense.pixel_clock); | |
1226 | return -EIO; | |
1227 | } | |
1228 | recalculate_fifo_timeout(pcdev, sense.pixel_clock); | |
1229 | } | |
2a48fc73 | 1230 | |
09e231b3 | 1231 | if (!ret) { |
0ad675eb GL |
1232 | icd->buswidth = xlate->buswidth; |
1233 | icd->current_fmt = xlate->host_fmt; | |
2a48fc73 | 1234 | } |
25c4d74e GL |
1235 | |
1236 | return ret; | |
ad5f2e85 GL |
1237 | } |
1238 | ||
d8fac217 GL |
1239 | static int pxa_camera_try_fmt(struct soc_camera_device *icd, |
1240 | struct v4l2_format *f) | |
3bc43840 | 1241 | { |
2a48fc73 RJ |
1242 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
1243 | const struct soc_camera_format_xlate *xlate; | |
1244 | struct v4l2_pix_format *pix = &f->fmt.pix; | |
1245 | __u32 pixfmt = pix->pixelformat; | |
06daa1af | 1246 | enum v4l2_field field; |
bf507158 | 1247 | int ret; |
a2c8c68c | 1248 | |
2a48fc73 RJ |
1249 | xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); |
1250 | if (!xlate) { | |
1251 | dev_warn(&ici->dev, "Format %x not found\n", pixfmt); | |
25c4d74e | 1252 | return -EINVAL; |
2a48fc73 | 1253 | } |
25c4d74e | 1254 | |
3bc43840 | 1255 | /* limit to pxa hardware capabilities */ |
2a48fc73 RJ |
1256 | if (pix->height < 32) |
1257 | pix->height = 32; | |
1258 | if (pix->height > 2048) | |
1259 | pix->height = 2048; | |
1260 | if (pix->width < 48) | |
1261 | pix->width = 48; | |
1262 | if (pix->width > 2048) | |
1263 | pix->width = 2048; | |
1264 | pix->width &= ~0x01; | |
1265 | ||
92a8337b RJ |
1266 | /* |
1267 | * YUV422P planar format requires images size to be a 16 bytes | |
1268 | * multiple. If not, zeros will be inserted between Y and U planes, and | |
1269 | * U and V planes, and YUV422P standard would be violated. | |
1270 | */ | |
1271 | if (xlate->host_fmt->fourcc == V4L2_PIX_FMT_YUV422P) { | |
1272 | if (!IS_ALIGNED(pix->width * pix->height, YUV422P_SIZE_ALIGN)) | |
1273 | pix->height = ALIGN(pix->height, YUV422P_X_Y_ALIGN); | |
1274 | if (!IS_ALIGNED(pix->width * pix->height, YUV422P_SIZE_ALIGN)) | |
1275 | pix->width = ALIGN(pix->width, YUV422P_X_Y_ALIGN); | |
1276 | } | |
1277 | ||
2a48fc73 RJ |
1278 | pix->bytesperline = pix->width * |
1279 | DIV_ROUND_UP(xlate->host_fmt->depth, 8); | |
1280 | pix->sizeimage = pix->height * pix->bytesperline; | |
25c4d74e | 1281 | |
bf507158 GL |
1282 | /* camera has to see its format, but the user the original one */ |
1283 | pix->pixelformat = xlate->cam_fmt->fourcc; | |
ad5f2e85 | 1284 | /* limit to sensor capabilities */ |
bf507158 GL |
1285 | ret = icd->ops->try_fmt(icd, f); |
1286 | pix->pixelformat = xlate->host_fmt->fourcc; | |
1287 | ||
06daa1af GL |
1288 | field = pix->field; |
1289 | ||
1290 | if (field == V4L2_FIELD_ANY) { | |
1291 | pix->field = V4L2_FIELD_NONE; | |
1292 | } else if (field != V4L2_FIELD_NONE) { | |
1293 | dev_err(&icd->dev, "Field type %d unsupported.\n", field); | |
1294 | return -EINVAL; | |
1295 | } | |
1296 | ||
bf507158 | 1297 | return ret; |
3bc43840 GL |
1298 | } |
1299 | ||
7102b773 GL |
1300 | static int pxa_camera_reqbufs(struct soc_camera_file *icf, |
1301 | struct v4l2_requestbuffers *p) | |
3bc43840 GL |
1302 | { |
1303 | int i; | |
1304 | ||
1305 | /* This is for locking debugging only. I removed spinlocks and now I | |
1306 | * check whether .prepare is ever called on a linked buffer, or whether | |
1307 | * a dma IRQ can occur for an in-work or unlinked buffer. Until now | |
1308 | * it hadn't triggered */ | |
1309 | for (i = 0; i < p->count; i++) { | |
1310 | struct pxa_buffer *buf = container_of(icf->vb_vidq.bufs[i], | |
1311 | struct pxa_buffer, vb); | |
1312 | buf->inwork = 0; | |
1313 | INIT_LIST_HEAD(&buf->vb.queue); | |
1314 | } | |
1315 | ||
1316 | return 0; | |
1317 | } | |
1318 | ||
7102b773 | 1319 | static unsigned int pxa_camera_poll(struct file *file, poll_table *pt) |
3bc43840 GL |
1320 | { |
1321 | struct soc_camera_file *icf = file->private_data; | |
1322 | struct pxa_buffer *buf; | |
1323 | ||
1324 | buf = list_entry(icf->vb_vidq.stream.next, struct pxa_buffer, | |
1325 | vb.stream); | |
1326 | ||
1327 | poll_wait(file, &buf->vb.done, pt); | |
1328 | ||
1329 | if (buf->vb.state == VIDEOBUF_DONE || | |
1330 | buf->vb.state == VIDEOBUF_ERROR) | |
1331 | return POLLIN|POLLRDNORM; | |
1332 | ||
1333 | return 0; | |
1334 | } | |
1335 | ||
7102b773 GL |
1336 | static int pxa_camera_querycap(struct soc_camera_host *ici, |
1337 | struct v4l2_capability *cap) | |
3bc43840 GL |
1338 | { |
1339 | /* cap->name is set by the firendly caller:-> */ | |
1340 | strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card)); | |
1341 | cap->version = PXA_CAM_VERSION_CODE; | |
1342 | cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; | |
1343 | ||
1344 | return 0; | |
1345 | } | |
1346 | ||
3f6ac497 RJ |
1347 | static int pxa_camera_suspend(struct soc_camera_device *icd, pm_message_t state) |
1348 | { | |
64f5905e | 1349 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
3f6ac497 RJ |
1350 | struct pxa_camera_dev *pcdev = ici->priv; |
1351 | int i = 0, ret = 0; | |
1352 | ||
5ca11fa3 EM |
1353 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0); |
1354 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1); | |
1355 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2); | |
1356 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3); | |
1357 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4); | |
3f6ac497 RJ |
1358 | |
1359 | if ((pcdev->icd) && (pcdev->icd->ops->suspend)) | |
1360 | ret = pcdev->icd->ops->suspend(pcdev->icd, state); | |
1361 | ||
1362 | return ret; | |
1363 | } | |
1364 | ||
1365 | static int pxa_camera_resume(struct soc_camera_device *icd) | |
1366 | { | |
64f5905e | 1367 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
3f6ac497 RJ |
1368 | struct pxa_camera_dev *pcdev = ici->priv; |
1369 | int i = 0, ret = 0; | |
1370 | ||
87f3dd77 EM |
1371 | DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD; |
1372 | DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD; | |
1373 | DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD; | |
3f6ac497 | 1374 | |
5ca11fa3 EM |
1375 | __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0); |
1376 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1); | |
1377 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2); | |
1378 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3); | |
1379 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4); | |
3f6ac497 RJ |
1380 | |
1381 | if ((pcdev->icd) && (pcdev->icd->ops->resume)) | |
1382 | ret = pcdev->icd->ops->resume(pcdev->icd); | |
1383 | ||
1384 | /* Restart frame capture if active buffer exists */ | |
1385 | if (!ret && pcdev->active) { | |
5ca11fa3 EM |
1386 | unsigned long cifr, cicr0; |
1387 | ||
3f6ac497 | 1388 | /* Reset the FIFOs */ |
5ca11fa3 EM |
1389 | cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F; |
1390 | __raw_writel(cifr, pcdev->base + CIFR); | |
1391 | ||
1392 | cicr0 = __raw_readl(pcdev->base + CICR0); | |
1393 | cicr0 &= ~CICR0_EOFM; /* Enable End-Of-Frame Interrupt */ | |
1394 | cicr0 |= CICR0_ENB; /* Restart the Capture Interface */ | |
1395 | __raw_writel(cicr0, pcdev->base + CICR0); | |
3f6ac497 RJ |
1396 | } |
1397 | ||
1398 | return ret; | |
1399 | } | |
1400 | ||
b8d9904c GL |
1401 | static struct soc_camera_host_ops pxa_soc_camera_host_ops = { |
1402 | .owner = THIS_MODULE, | |
1403 | .add = pxa_camera_add_device, | |
1404 | .remove = pxa_camera_remove_device, | |
3f6ac497 RJ |
1405 | .suspend = pxa_camera_suspend, |
1406 | .resume = pxa_camera_resume, | |
09e231b3 | 1407 | .set_crop = pxa_camera_set_crop, |
2a48fc73 | 1408 | .get_formats = pxa_camera_get_formats, |
d8fac217 GL |
1409 | .set_fmt = pxa_camera_set_fmt, |
1410 | .try_fmt = pxa_camera_try_fmt, | |
092d3921 | 1411 | .init_videobuf = pxa_camera_init_videobuf, |
b8d9904c GL |
1412 | .reqbufs = pxa_camera_reqbufs, |
1413 | .poll = pxa_camera_poll, | |
1414 | .querycap = pxa_camera_querycap, | |
b8d9904c GL |
1415 | .set_bus_param = pxa_camera_set_bus_param, |
1416 | }; | |
1417 | ||
1418 | /* Should be allocated dynamically too, but we have only one. */ | |
3bc43840 GL |
1419 | static struct soc_camera_host pxa_soc_camera_host = { |
1420 | .drv_name = PXA_CAM_DRV_NAME, | |
b8d9904c | 1421 | .ops = &pxa_soc_camera_host_ops, |
3bc43840 GL |
1422 | }; |
1423 | ||
1424 | static int pxa_camera_probe(struct platform_device *pdev) | |
1425 | { | |
1426 | struct pxa_camera_dev *pcdev; | |
1427 | struct resource *res; | |
1428 | void __iomem *base; | |
02da4659 | 1429 | int irq; |
3bc43840 GL |
1430 | int err = 0; |
1431 | ||
1432 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1433 | irq = platform_get_irq(pdev, 0); | |
02da4659 | 1434 | if (!res || irq < 0) { |
3bc43840 GL |
1435 | err = -ENODEV; |
1436 | goto exit; | |
1437 | } | |
1438 | ||
1439 | pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL); | |
1440 | if (!pcdev) { | |
7102b773 | 1441 | dev_err(&pdev->dev, "Could not allocate pcdev\n"); |
3bc43840 GL |
1442 | err = -ENOMEM; |
1443 | goto exit; | |
1444 | } | |
1445 | ||
e0d8b13a | 1446 | pcdev->clk = clk_get(&pdev->dev, NULL); |
3bc43840 GL |
1447 | if (IS_ERR(pcdev->clk)) { |
1448 | err = PTR_ERR(pcdev->clk); | |
1449 | goto exit_kfree; | |
1450 | } | |
1451 | ||
1452 | dev_set_drvdata(&pdev->dev, pcdev); | |
1453 | pcdev->res = res; | |
1454 | ||
1455 | pcdev->pdata = pdev->dev.platform_data; | |
1456 | pcdev->platform_flags = pcdev->pdata->flags; | |
ad5f2e85 GL |
1457 | if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 | |
1458 | PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) { | |
3bc43840 GL |
1459 | /* Platform hasn't set available data widths. This is bad. |
1460 | * Warn and use a default. */ | |
1461 | dev_warn(&pdev->dev, "WARNING! Platform hasn't set available " | |
1462 | "data widths, using default 10 bit\n"); | |
1463 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10; | |
1464 | } | |
cf34cba7 GL |
1465 | pcdev->mclk = pcdev->pdata->mclk_10khz * 10000; |
1466 | if (!pcdev->mclk) { | |
3bc43840 | 1467 | dev_warn(&pdev->dev, |
cf34cba7 | 1468 | "mclk == 0! Please, fix your platform data. " |
3bc43840 | 1469 | "Using default 20MHz\n"); |
cf34cba7 | 1470 | pcdev->mclk = 20000000; |
3bc43840 GL |
1471 | } |
1472 | ||
cf34cba7 GL |
1473 | pcdev->dev = &pdev->dev; |
1474 | pcdev->mclk_divisor = mclk_get_divisor(pcdev); | |
1475 | ||
3bc43840 GL |
1476 | INIT_LIST_HEAD(&pcdev->capture); |
1477 | spin_lock_init(&pcdev->lock); | |
1478 | ||
1479 | /* | |
1480 | * Request the regions. | |
1481 | */ | |
1482 | if (!request_mem_region(res->start, res->end - res->start + 1, | |
1483 | PXA_CAM_DRV_NAME)) { | |
1484 | err = -EBUSY; | |
1485 | goto exit_clk; | |
1486 | } | |
1487 | ||
1488 | base = ioremap(res->start, res->end - res->start + 1); | |
1489 | if (!base) { | |
1490 | err = -ENOMEM; | |
1491 | goto exit_release; | |
1492 | } | |
1493 | pcdev->irq = irq; | |
1494 | pcdev->base = base; | |
3bc43840 GL |
1495 | |
1496 | /* request dma */ | |
de3e3b82 | 1497 | err = pxa_request_dma("CI_Y", DMA_PRIO_HIGH, |
1498 | pxa_camera_dma_irq_y, pcdev); | |
1499 | if (err < 0) { | |
3bc43840 | 1500 | dev_err(pcdev->dev, "Can't request DMA for Y\n"); |
3bc43840 GL |
1501 | goto exit_iounmap; |
1502 | } | |
de3e3b82 | 1503 | pcdev->dma_chans[0] = err; |
a5462e5b MR |
1504 | dev_dbg(pcdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]); |
1505 | ||
de3e3b82 | 1506 | err = pxa_request_dma("CI_U", DMA_PRIO_HIGH, |
1507 | pxa_camera_dma_irq_u, pcdev); | |
1508 | if (err < 0) { | |
a5462e5b | 1509 | dev_err(pcdev->dev, "Can't request DMA for U\n"); |
a5462e5b MR |
1510 | goto exit_free_dma_y; |
1511 | } | |
de3e3b82 | 1512 | pcdev->dma_chans[1] = err; |
a5462e5b MR |
1513 | dev_dbg(pcdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]); |
1514 | ||
de3e3b82 | 1515 | err = pxa_request_dma("CI_V", DMA_PRIO_HIGH, |
1516 | pxa_camera_dma_irq_v, pcdev); | |
1517 | if (err < 0) { | |
a5462e5b | 1518 | dev_err(pcdev->dev, "Can't request DMA for V\n"); |
a5462e5b MR |
1519 | goto exit_free_dma_u; |
1520 | } | |
de3e3b82 | 1521 | pcdev->dma_chans[2] = err; |
a5462e5b | 1522 | dev_dbg(pcdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]); |
3bc43840 | 1523 | |
87f3dd77 EM |
1524 | DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD; |
1525 | DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD; | |
1526 | DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD; | |
3bc43840 GL |
1527 | |
1528 | /* request irq */ | |
1529 | err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME, | |
1530 | pcdev); | |
1531 | if (err) { | |
1532 | dev_err(pcdev->dev, "Camera interrupt register failed \n"); | |
1533 | goto exit_free_dma; | |
1534 | } | |
1535 | ||
1536 | pxa_soc_camera_host.priv = pcdev; | |
1537 | pxa_soc_camera_host.dev.parent = &pdev->dev; | |
1538 | pxa_soc_camera_host.nr = pdev->id; | |
b8d9904c | 1539 | err = soc_camera_host_register(&pxa_soc_camera_host); |
3bc43840 GL |
1540 | if (err) |
1541 | goto exit_free_irq; | |
1542 | ||
1543 | return 0; | |
1544 | ||
1545 | exit_free_irq: | |
1546 | free_irq(pcdev->irq, pcdev); | |
1547 | exit_free_dma: | |
a5462e5b MR |
1548 | pxa_free_dma(pcdev->dma_chans[2]); |
1549 | exit_free_dma_u: | |
1550 | pxa_free_dma(pcdev->dma_chans[1]); | |
1551 | exit_free_dma_y: | |
1552 | pxa_free_dma(pcdev->dma_chans[0]); | |
3bc43840 GL |
1553 | exit_iounmap: |
1554 | iounmap(base); | |
1555 | exit_release: | |
1556 | release_mem_region(res->start, res->end - res->start + 1); | |
1557 | exit_clk: | |
1558 | clk_put(pcdev->clk); | |
1559 | exit_kfree: | |
1560 | kfree(pcdev); | |
1561 | exit: | |
1562 | return err; | |
1563 | } | |
1564 | ||
1565 | static int __devexit pxa_camera_remove(struct platform_device *pdev) | |
1566 | { | |
1567 | struct pxa_camera_dev *pcdev = platform_get_drvdata(pdev); | |
1568 | struct resource *res; | |
1569 | ||
1570 | clk_put(pcdev->clk); | |
1571 | ||
a5462e5b MR |
1572 | pxa_free_dma(pcdev->dma_chans[0]); |
1573 | pxa_free_dma(pcdev->dma_chans[1]); | |
1574 | pxa_free_dma(pcdev->dma_chans[2]); | |
3bc43840 GL |
1575 | free_irq(pcdev->irq, pcdev); |
1576 | ||
1577 | soc_camera_host_unregister(&pxa_soc_camera_host); | |
1578 | ||
1579 | iounmap(pcdev->base); | |
1580 | ||
1581 | res = pcdev->res; | |
1582 | release_mem_region(res->start, res->end - res->start + 1); | |
1583 | ||
1584 | kfree(pcdev); | |
1585 | ||
7102b773 | 1586 | dev_info(&pdev->dev, "PXA Camera driver unloaded\n"); |
3bc43840 | 1587 | |
3bc43840 GL |
1588 | return 0; |
1589 | } | |
1590 | ||
3bc43840 GL |
1591 | static struct platform_driver pxa_camera_driver = { |
1592 | .driver = { | |
1593 | .name = PXA_CAM_DRV_NAME, | |
1594 | }, | |
1595 | .probe = pxa_camera_probe, | |
1596 | .remove = __exit_p(pxa_camera_remove), | |
3bc43840 GL |
1597 | }; |
1598 | ||
1599 | ||
1600 | static int __devinit pxa_camera_init(void) | |
1601 | { | |
1602 | return platform_driver_register(&pxa_camera_driver); | |
1603 | } | |
1604 | ||
1605 | static void __exit pxa_camera_exit(void) | |
1606 | { | |
01c1e4ca | 1607 | platform_driver_unregister(&pxa_camera_driver); |
3bc43840 GL |
1608 | } |
1609 | ||
1610 | module_init(pxa_camera_init); | |
1611 | module_exit(pxa_camera_exit); | |
1612 | ||
1613 | MODULE_DESCRIPTION("PXA27x SoC Camera Host driver"); | |
1614 | MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>"); | |
1615 | MODULE_LICENSE("GPL"); |