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3bc43840 GL |
1 | /* |
2 | * V4L2 Driver for PXA camera host | |
3 | * | |
4 | * Copyright (C) 2006, Sascha Hauer, Pengutronix | |
5 | * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
3bc43840 GL |
13 | #include <linux/init.h> |
14 | #include <linux/module.h> | |
7102b773 | 15 | #include <linux/io.h> |
3bc43840 GL |
16 | #include <linux/delay.h> |
17 | #include <linux/dma-mapping.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/fs.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/mm.h> | |
23 | #include <linux/moduleparam.h> | |
24 | #include <linux/time.h> | |
25 | #include <linux/version.h> | |
26 | #include <linux/device.h> | |
27 | #include <linux/platform_device.h> | |
3bc43840 GL |
28 | #include <linux/clk.h> |
29 | ||
30 | #include <media/v4l2-common.h> | |
31 | #include <media/v4l2-dev.h> | |
092d3921 | 32 | #include <media/videobuf-dma-sg.h> |
3bc43840 GL |
33 | #include <media/soc_camera.h> |
34 | ||
35 | #include <linux/videodev2.h> | |
36 | ||
cfbaf4df | 37 | #include <mach/dma.h> |
a09e64fb | 38 | #include <mach/camera.h> |
3bc43840 GL |
39 | |
40 | #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5) | |
41 | #define PXA_CAM_DRV_NAME "pxa27x-camera" | |
42 | ||
5ca11fa3 EM |
43 | /* Camera Interface */ |
44 | #define CICR0 0x0000 | |
45 | #define CICR1 0x0004 | |
46 | #define CICR2 0x0008 | |
47 | #define CICR3 0x000C | |
48 | #define CICR4 0x0010 | |
49 | #define CISR 0x0014 | |
50 | #define CIFR 0x0018 | |
51 | #define CITOR 0x001C | |
52 | #define CIBR0 0x0028 | |
53 | #define CIBR1 0x0030 | |
54 | #define CIBR2 0x0038 | |
55 | ||
56 | #define CICR0_DMAEN (1 << 31) /* DMA request enable */ | |
57 | #define CICR0_PAR_EN (1 << 30) /* Parity enable */ | |
58 | #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */ | |
59 | #define CICR0_ENB (1 << 28) /* Camera interface enable */ | |
60 | #define CICR0_DIS (1 << 27) /* Camera interface disable */ | |
61 | #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */ | |
62 | #define CICR0_TOM (1 << 9) /* Time-out mask */ | |
63 | #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */ | |
64 | #define CICR0_FEM (1 << 7) /* FIFO-empty mask */ | |
65 | #define CICR0_EOLM (1 << 6) /* End-of-line mask */ | |
66 | #define CICR0_PERRM (1 << 5) /* Parity-error mask */ | |
67 | #define CICR0_QDM (1 << 4) /* Quick-disable mask */ | |
68 | #define CICR0_CDM (1 << 3) /* Disable-done mask */ | |
69 | #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */ | |
70 | #define CICR0_EOFM (1 << 1) /* End-of-frame mask */ | |
71 | #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */ | |
72 | ||
73 | #define CICR1_TBIT (1 << 31) /* Transparency bit */ | |
74 | #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */ | |
75 | #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */ | |
76 | #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */ | |
77 | #define CICR1_RGB_F (1 << 11) /* RGB format */ | |
78 | #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */ | |
79 | #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */ | |
80 | #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */ | |
81 | #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */ | |
82 | #define CICR1_DW (0x7 << 0) /* Data width mask */ | |
83 | ||
84 | #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock | |
85 | wait count mask */ | |
86 | #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock | |
87 | wait count mask */ | |
88 | #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */ | |
89 | #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock | |
90 | wait count mask */ | |
91 | #define CICR2_FSW (0x7 << 0) /* Frame stabilization | |
92 | wait count mask */ | |
93 | ||
94 | #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock | |
95 | wait count mask */ | |
96 | #define CICR3_EFW (0xff << 16) /* End-of-frame line clock | |
97 | wait count mask */ | |
98 | #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */ | |
99 | #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock | |
100 | wait count mask */ | |
101 | #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */ | |
102 | ||
103 | #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */ | |
104 | #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */ | |
105 | #define CICR4_PCP (1 << 22) /* Pixel clock polarity */ | |
106 | #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */ | |
107 | #define CICR4_VSP (1 << 20) /* Vertical sync polarity */ | |
108 | #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */ | |
109 | #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */ | |
110 | #define CICR4_DIV (0xff << 0) /* Clock divisor mask */ | |
111 | ||
112 | #define CISR_FTO (1 << 15) /* FIFO time-out */ | |
113 | #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */ | |
114 | #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */ | |
115 | #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */ | |
116 | #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */ | |
117 | #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */ | |
118 | #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */ | |
119 | #define CISR_EOL (1 << 8) /* End of line */ | |
120 | #define CISR_PAR_ERR (1 << 7) /* Parity error */ | |
121 | #define CISR_CQD (1 << 6) /* Camera interface quick disable */ | |
122 | #define CISR_CDD (1 << 5) /* Camera interface disable done */ | |
123 | #define CISR_SOF (1 << 4) /* Start of frame */ | |
124 | #define CISR_EOF (1 << 3) /* End of frame */ | |
125 | #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */ | |
126 | #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */ | |
127 | #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */ | |
128 | ||
129 | #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */ | |
130 | #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */ | |
131 | #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */ | |
132 | #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */ | |
133 | #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */ | |
134 | #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */ | |
135 | #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */ | |
136 | #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */ | |
137 | ||
7102b773 GL |
138 | #define CICR0_SIM_MP (0 << 24) |
139 | #define CICR0_SIM_SP (1 << 24) | |
140 | #define CICR0_SIM_MS (2 << 24) | |
141 | #define CICR0_SIM_EP (3 << 24) | |
142 | #define CICR0_SIM_ES (4 << 24) | |
143 | ||
144 | #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */ | |
145 | #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */ | |
a5462e5b MR |
146 | #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */ |
147 | #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */ | |
148 | #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */ | |
7102b773 GL |
149 | |
150 | #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */ | |
151 | #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */ | |
152 | #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */ | |
153 | #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */ | |
154 | #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */ | |
155 | ||
156 | #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */ | |
157 | #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */ | |
158 | #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */ | |
159 | #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */ | |
160 | ||
3bc43840 GL |
161 | #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \ |
162 | CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \ | |
163 | CICR0_EOFM | CICR0_FOM) | |
164 | ||
92a8337b RJ |
165 | /* |
166 | * YUV422P picture size should be a multiple of 16, so the heuristic aligns | |
167 | * height, width on 4 byte boundaries to reach the 16 multiple for the size. | |
168 | */ | |
169 | #define YUV422P_X_Y_ALIGN 4 | |
170 | #define YUV422P_SIZE_ALIGN YUV422P_X_Y_ALIGN * YUV422P_X_Y_ALIGN | |
171 | ||
3bc43840 GL |
172 | /* |
173 | * Structures | |
174 | */ | |
a5462e5b MR |
175 | enum pxa_camera_active_dma { |
176 | DMA_Y = 0x1, | |
177 | DMA_U = 0x2, | |
178 | DMA_V = 0x4, | |
179 | }; | |
180 | ||
181 | /* descriptor needed for the PXA DMA engine */ | |
182 | struct pxa_cam_dma { | |
183 | dma_addr_t sg_dma; | |
184 | struct pxa_dma_desc *sg_cpu; | |
185 | size_t sg_size; | |
186 | int sglen; | |
187 | }; | |
3bc43840 GL |
188 | |
189 | /* buffer for one video frame */ | |
190 | struct pxa_buffer { | |
191 | /* common v4l buffer stuff -- must be first */ | |
192 | struct videobuf_buffer vb; | |
193 | ||
194 | const struct soc_camera_data_format *fmt; | |
195 | ||
a5462e5b MR |
196 | /* our descriptor lists for Y, U and V channels */ |
197 | struct pxa_cam_dma dmas[3]; | |
198 | ||
3bc43840 | 199 | int inwork; |
a5462e5b MR |
200 | |
201 | enum pxa_camera_active_dma active_dma; | |
3bc43840 GL |
202 | }; |
203 | ||
3bc43840 | 204 | struct pxa_camera_dev { |
eb6c8558 | 205 | struct soc_camera_host soc_host; |
3bc43840 GL |
206 | struct device *dev; |
207 | /* PXA27x is only supposed to handle one camera on its Quick Capture | |
208 | * interface. If anyone ever builds hardware to enable more than | |
209 | * one camera, they will have to modify this driver too */ | |
210 | struct soc_camera_device *icd; | |
211 | struct clk *clk; | |
212 | ||
213 | unsigned int irq; | |
214 | void __iomem *base; | |
a5462e5b | 215 | |
e7c50688 | 216 | int channels; |
a5462e5b | 217 | unsigned int dma_chans[3]; |
3bc43840 | 218 | |
3bc43840 GL |
219 | struct pxacamera_platform_data *pdata; |
220 | struct resource *res; | |
221 | unsigned long platform_flags; | |
cf34cba7 GL |
222 | unsigned long ciclk; |
223 | unsigned long mclk; | |
224 | u32 mclk_divisor; | |
3bc43840 GL |
225 | |
226 | struct list_head capture; | |
227 | ||
228 | spinlock_t lock; | |
229 | ||
3bc43840 | 230 | struct pxa_buffer *active; |
5aa2110f | 231 | struct pxa_dma_desc *sg_tail[3]; |
3f6ac497 RJ |
232 | |
233 | u32 save_cicr[5]; | |
3bc43840 GL |
234 | }; |
235 | ||
236 | static const char *pxa_cam_driver_description = "PXA_Camera"; | |
237 | ||
238 | static unsigned int vid_limit = 16; /* Video memory limit, in Mb */ | |
239 | ||
240 | /* | |
241 | * Videobuf operations | |
242 | */ | |
7102b773 GL |
243 | static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count, |
244 | unsigned int *size) | |
3bc43840 GL |
245 | { |
246 | struct soc_camera_device *icd = vq->priv_data; | |
247 | ||
248 | dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size); | |
249 | ||
92a8337b RJ |
250 | *size = roundup(icd->width * icd->height * |
251 | ((icd->current_fmt->depth + 7) >> 3), 8); | |
3bc43840 GL |
252 | |
253 | if (0 == *count) | |
254 | *count = 32; | |
255 | while (*size * *count > vid_limit * 1024 * 1024) | |
256 | (*count)--; | |
257 | ||
258 | return 0; | |
259 | } | |
260 | ||
261 | static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf) | |
262 | { | |
263 | struct soc_camera_device *icd = vq->priv_data; | |
64f5905e | 264 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
3bc43840 GL |
265 | struct pxa_camera_dev *pcdev = ici->priv; |
266 | struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb); | |
a5462e5b | 267 | int i; |
3bc43840 GL |
268 | |
269 | BUG_ON(in_interrupt()); | |
270 | ||
7e28adb2 | 271 | dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
272 | &buf->vb, buf->vb.baddr, buf->vb.bsize); |
273 | ||
274 | /* This waits until this buffer is out of danger, i.e., until it is no | |
275 | * longer in STATE_QUEUED or STATE_ACTIVE */ | |
276 | videobuf_waiton(&buf->vb, 0, 0); | |
277 | videobuf_dma_unmap(vq, dma); | |
278 | videobuf_dma_free(dma); | |
279 | ||
a5462e5b MR |
280 | for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) { |
281 | if (buf->dmas[i].sg_cpu) | |
282 | dma_free_coherent(pcdev->dev, buf->dmas[i].sg_size, | |
283 | buf->dmas[i].sg_cpu, | |
284 | buf->dmas[i].sg_dma); | |
285 | buf->dmas[i].sg_cpu = NULL; | |
286 | } | |
3bc43840 GL |
287 | |
288 | buf->vb.state = VIDEOBUF_NEEDS_INIT; | |
289 | } | |
290 | ||
37f5aefd RJ |
291 | static int calculate_dma_sglen(struct scatterlist *sglist, int sglen, |
292 | int sg_first_ofs, int size) | |
293 | { | |
294 | int i, offset, dma_len, xfer_len; | |
295 | struct scatterlist *sg; | |
296 | ||
297 | offset = sg_first_ofs; | |
298 | for_each_sg(sglist, sg, sglen, i) { | |
299 | dma_len = sg_dma_len(sg); | |
300 | ||
301 | /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */ | |
302 | xfer_len = roundup(min(dma_len - offset, size), 8); | |
303 | ||
304 | size = max(0, size - xfer_len); | |
305 | offset = 0; | |
306 | if (size == 0) | |
307 | break; | |
308 | } | |
309 | ||
310 | BUG_ON(size != 0); | |
311 | return i + 1; | |
312 | } | |
313 | ||
314 | /** | |
315 | * pxa_init_dma_channel - init dma descriptors | |
316 | * @pcdev: pxa camera device | |
317 | * @buf: pxa buffer to find pxa dma channel | |
318 | * @dma: dma video buffer | |
319 | * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V') | |
320 | * @cibr: camera Receive Buffer Register | |
321 | * @size: bytes to transfer | |
322 | * @sg_first: first element of sg_list | |
323 | * @sg_first_ofs: offset in first element of sg_list | |
324 | * | |
325 | * Prepares the pxa dma descriptors to transfer one camera channel. | |
326 | * Beware sg_first and sg_first_ofs are both input and output parameters. | |
327 | * | |
328 | * Returns 0 or -ENOMEM if no coherent memory is available | |
329 | */ | |
a5462e5b MR |
330 | static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev, |
331 | struct pxa_buffer *buf, | |
332 | struct videobuf_dmabuf *dma, int channel, | |
37f5aefd RJ |
333 | int cibr, int size, |
334 | struct scatterlist **sg_first, int *sg_first_ofs) | |
a5462e5b MR |
335 | { |
336 | struct pxa_cam_dma *pxa_dma = &buf->dmas[channel]; | |
37f5aefd RJ |
337 | struct scatterlist *sg; |
338 | int i, offset, sglen; | |
339 | int dma_len = 0, xfer_len = 0; | |
a5462e5b MR |
340 | |
341 | if (pxa_dma->sg_cpu) | |
342 | dma_free_coherent(pcdev->dev, pxa_dma->sg_size, | |
343 | pxa_dma->sg_cpu, pxa_dma->sg_dma); | |
344 | ||
37f5aefd RJ |
345 | sglen = calculate_dma_sglen(*sg_first, dma->sglen, |
346 | *sg_first_ofs, size); | |
347 | ||
a5462e5b MR |
348 | pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc); |
349 | pxa_dma->sg_cpu = dma_alloc_coherent(pcdev->dev, pxa_dma->sg_size, | |
350 | &pxa_dma->sg_dma, GFP_KERNEL); | |
351 | if (!pxa_dma->sg_cpu) | |
352 | return -ENOMEM; | |
353 | ||
354 | pxa_dma->sglen = sglen; | |
37f5aefd | 355 | offset = *sg_first_ofs; |
a5462e5b | 356 | |
37f5aefd RJ |
357 | dev_dbg(pcdev->dev, "DMA: sg_first=%p, sglen=%d, ofs=%d, dma.desc=%x\n", |
358 | *sg_first, sglen, *sg_first_ofs, pxa_dma->sg_dma); | |
a5462e5b | 359 | |
37f5aefd RJ |
360 | |
361 | for_each_sg(*sg_first, sg, sglen, i) { | |
362 | dma_len = sg_dma_len(sg); | |
a5462e5b MR |
363 | |
364 | /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */ | |
37f5aefd | 365 | xfer_len = roundup(min(dma_len - offset, size), 8); |
a5462e5b | 366 | |
37f5aefd RJ |
367 | size = max(0, size - xfer_len); |
368 | ||
369 | pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr; | |
370 | pxa_dma->sg_cpu[i].dtadr = sg_dma_address(sg) + offset; | |
a5462e5b MR |
371 | pxa_dma->sg_cpu[i].dcmd = |
372 | DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len; | |
256b0233 RJ |
373 | #ifdef DEBUG |
374 | if (!i) | |
375 | pxa_dma->sg_cpu[i].dcmd |= DCMD_STARTIRQEN; | |
376 | #endif | |
a5462e5b MR |
377 | pxa_dma->sg_cpu[i].ddadr = |
378 | pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc); | |
37f5aefd RJ |
379 | |
380 | dev_vdbg(pcdev->dev, "DMA: desc.%08x->@phys=0x%08x, len=%d\n", | |
381 | pxa_dma->sg_dma + i * sizeof(struct pxa_dma_desc), | |
382 | sg_dma_address(sg) + offset, xfer_len); | |
383 | offset = 0; | |
384 | ||
385 | if (size == 0) | |
386 | break; | |
a5462e5b MR |
387 | } |
388 | ||
256b0233 RJ |
389 | pxa_dma->sg_cpu[sglen].ddadr = DDADR_STOP; |
390 | pxa_dma->sg_cpu[sglen].dcmd = DCMD_FLOWSRC | DCMD_BURST8 | DCMD_ENDIRQEN; | |
a5462e5b | 391 | |
37f5aefd RJ |
392 | /* |
393 | * Handle 1 special case : | |
394 | * - in 3 planes (YUV422P format), we might finish with xfer_len equal | |
395 | * to dma_len (end on PAGE boundary). In this case, the sg element | |
396 | * for next plane should be the next after the last used to store the | |
397 | * last scatter gather RAM page | |
398 | */ | |
399 | if (xfer_len >= dma_len) { | |
400 | *sg_first_ofs = xfer_len - dma_len; | |
401 | *sg_first = sg_next(sg); | |
402 | } else { | |
403 | *sg_first_ofs = xfer_len; | |
404 | *sg_first = sg; | |
405 | } | |
406 | ||
a5462e5b MR |
407 | return 0; |
408 | } | |
409 | ||
256b0233 RJ |
410 | static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev, |
411 | struct pxa_buffer *buf) | |
412 | { | |
413 | buf->active_dma = DMA_Y; | |
414 | if (pcdev->channels == 3) | |
415 | buf->active_dma |= DMA_U | DMA_V; | |
416 | } | |
417 | ||
418 | /* | |
419 | * Please check the DMA prepared buffer structure in : | |
420 | * Documentation/video4linux/pxa_camera.txt | |
421 | * Please check also in pxa_camera_check_link_miss() to understand why DMA chain | |
422 | * modification while DMA chain is running will work anyway. | |
423 | */ | |
7102b773 GL |
424 | static int pxa_videobuf_prepare(struct videobuf_queue *vq, |
425 | struct videobuf_buffer *vb, enum v4l2_field field) | |
3bc43840 GL |
426 | { |
427 | struct soc_camera_device *icd = vq->priv_data; | |
64f5905e | 428 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
3bc43840 GL |
429 | struct pxa_camera_dev *pcdev = ici->priv; |
430 | struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); | |
a5462e5b | 431 | int ret; |
a5462e5b | 432 | int size_y, size_u = 0, size_v = 0; |
3bc43840 | 433 | |
7e28adb2 | 434 | dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
435 | vb, vb->baddr, vb->bsize); |
436 | ||
437 | /* Added list head initialization on alloc */ | |
438 | WARN_ON(!list_empty(&vb->queue)); | |
439 | ||
440 | #ifdef DEBUG | |
441 | /* This can be useful if you want to see if we actually fill | |
442 | * the buffer with something */ | |
443 | memset((void *)vb->baddr, 0xaa, vb->bsize); | |
444 | #endif | |
445 | ||
446 | BUG_ON(NULL == icd->current_fmt); | |
447 | ||
448 | /* I think, in buf_prepare you only have to protect global data, | |
449 | * the actual buffer is yours */ | |
450 | buf->inwork = 1; | |
451 | ||
452 | if (buf->fmt != icd->current_fmt || | |
453 | vb->width != icd->width || | |
454 | vb->height != icd->height || | |
455 | vb->field != field) { | |
456 | buf->fmt = icd->current_fmt; | |
457 | vb->width = icd->width; | |
458 | vb->height = icd->height; | |
459 | vb->field = field; | |
460 | vb->state = VIDEOBUF_NEEDS_INIT; | |
461 | } | |
462 | ||
463 | vb->size = vb->width * vb->height * ((buf->fmt->depth + 7) >> 3); | |
464 | if (0 != vb->baddr && vb->bsize < vb->size) { | |
465 | ret = -EINVAL; | |
466 | goto out; | |
467 | } | |
468 | ||
469 | if (vb->state == VIDEOBUF_NEEDS_INIT) { | |
37f5aefd RJ |
470 | int size = vb->size; |
471 | int next_ofs = 0; | |
3bc43840 | 472 | struct videobuf_dmabuf *dma = videobuf_to_dma(vb); |
37f5aefd | 473 | struct scatterlist *sg; |
3bc43840 GL |
474 | |
475 | ret = videobuf_iolock(vq, vb, NULL); | |
476 | if (ret) | |
477 | goto fail; | |
478 | ||
5aa2110f | 479 | if (pcdev->channels == 3) { |
a5462e5b MR |
480 | size_y = size / 2; |
481 | size_u = size_v = size / 4; | |
482 | } else { | |
a5462e5b MR |
483 | size_y = size; |
484 | } | |
485 | ||
37f5aefd | 486 | sg = dma->sglist; |
3bc43840 | 487 | |
37f5aefd RJ |
488 | /* init DMA for Y channel */ |
489 | ret = pxa_init_dma_channel(pcdev, buf, dma, 0, CIBR0, size_y, | |
490 | &sg, &next_ofs); | |
a5462e5b MR |
491 | if (ret) { |
492 | dev_err(pcdev->dev, | |
493 | "DMA initialization for Y/RGB failed\n"); | |
3bc43840 GL |
494 | goto fail; |
495 | } | |
496 | ||
37f5aefd RJ |
497 | /* init DMA for U channel */ |
498 | if (size_u) | |
499 | ret = pxa_init_dma_channel(pcdev, buf, dma, 1, CIBR1, | |
500 | size_u, &sg, &next_ofs); | |
501 | if (ret) { | |
502 | dev_err(pcdev->dev, | |
503 | "DMA initialization for U failed\n"); | |
504 | goto fail_u; | |
505 | } | |
506 | ||
507 | /* init DMA for V channel */ | |
508 | if (size_v) | |
509 | ret = pxa_init_dma_channel(pcdev, buf, dma, 2, CIBR2, | |
510 | size_v, &sg, &next_ofs); | |
511 | if (ret) { | |
512 | dev_err(pcdev->dev, | |
513 | "DMA initialization for V failed\n"); | |
514 | goto fail_v; | |
3bc43840 | 515 | } |
3bc43840 GL |
516 | |
517 | vb->state = VIDEOBUF_PREPARED; | |
518 | } | |
519 | ||
520 | buf->inwork = 0; | |
256b0233 | 521 | pxa_videobuf_set_actdma(pcdev, buf); |
3bc43840 GL |
522 | |
523 | return 0; | |
524 | ||
a5462e5b MR |
525 | fail_v: |
526 | dma_free_coherent(pcdev->dev, buf->dmas[1].sg_size, | |
527 | buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma); | |
528 | fail_u: | |
529 | dma_free_coherent(pcdev->dev, buf->dmas[0].sg_size, | |
530 | buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma); | |
3bc43840 GL |
531 | fail: |
532 | free_buffer(vq, buf); | |
533 | out: | |
534 | buf->inwork = 0; | |
535 | return ret; | |
536 | } | |
537 | ||
256b0233 RJ |
538 | /** |
539 | * pxa_dma_start_channels - start DMA channel for active buffer | |
540 | * @pcdev: pxa camera device | |
541 | * | |
542 | * Initialize DMA channels to the beginning of the active video buffer, and | |
543 | * start these channels. | |
544 | */ | |
545 | static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev) | |
546 | { | |
547 | int i; | |
548 | struct pxa_buffer *active; | |
549 | ||
550 | active = pcdev->active; | |
551 | ||
552 | for (i = 0; i < pcdev->channels; i++) { | |
553 | dev_dbg(pcdev->dev, "%s (channel=%d) ddadr=%08x\n", __func__, | |
554 | i, active->dmas[i].sg_dma); | |
555 | DDADR(pcdev->dma_chans[i]) = active->dmas[i].sg_dma; | |
556 | DCSR(pcdev->dma_chans[i]) = DCSR_RUN; | |
557 | } | |
558 | } | |
559 | ||
560 | static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev) | |
561 | { | |
562 | int i; | |
563 | ||
564 | for (i = 0; i < pcdev->channels; i++) { | |
565 | dev_dbg(pcdev->dev, "%s (channel=%d)\n", __func__, i); | |
566 | DCSR(pcdev->dma_chans[i]) = 0; | |
567 | } | |
568 | } | |
569 | ||
256b0233 RJ |
570 | static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev, |
571 | struct pxa_buffer *buf) | |
572 | { | |
573 | int i; | |
574 | struct pxa_dma_desc *buf_last_desc; | |
575 | ||
576 | for (i = 0; i < pcdev->channels; i++) { | |
577 | buf_last_desc = buf->dmas[i].sg_cpu + buf->dmas[i].sglen; | |
578 | buf_last_desc->ddadr = DDADR_STOP; | |
579 | ||
ae7410e7 GL |
580 | if (pcdev->sg_tail[i]) |
581 | /* Link the new buffer to the old tail */ | |
582 | pcdev->sg_tail[i]->ddadr = buf->dmas[i].sg_dma; | |
256b0233 | 583 | |
ae7410e7 GL |
584 | /* Update the channel tail */ |
585 | pcdev->sg_tail[i] = buf_last_desc; | |
586 | } | |
256b0233 RJ |
587 | } |
588 | ||
589 | /** | |
590 | * pxa_camera_start_capture - start video capturing | |
591 | * @pcdev: camera device | |
592 | * | |
593 | * Launch capturing. DMA channels should not be active yet. They should get | |
594 | * activated at the end of frame interrupt, to capture only whole frames, and | |
595 | * never begin the capture of a partial frame. | |
596 | */ | |
597 | static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev) | |
598 | { | |
599 | unsigned long cicr0, cifr; | |
600 | ||
601 | dev_dbg(pcdev->dev, "%s\n", __func__); | |
602 | /* Reset the FIFOs */ | |
603 | cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F; | |
604 | __raw_writel(cifr, pcdev->base + CIFR); | |
605 | /* Enable End-Of-Frame Interrupt */ | |
606 | cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB; | |
607 | cicr0 &= ~CICR0_EOFM; | |
608 | __raw_writel(cicr0, pcdev->base + CICR0); | |
609 | } | |
610 | ||
611 | static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev) | |
612 | { | |
613 | unsigned long cicr0; | |
614 | ||
615 | pxa_dma_stop_channels(pcdev); | |
616 | ||
617 | cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB; | |
618 | __raw_writel(cicr0, pcdev->base + CICR0); | |
619 | ||
8c62e221 | 620 | pcdev->active = NULL; |
256b0233 RJ |
621 | dev_dbg(pcdev->dev, "%s\n", __func__); |
622 | } | |
623 | ||
7102b773 GL |
624 | static void pxa_videobuf_queue(struct videobuf_queue *vq, |
625 | struct videobuf_buffer *vb) | |
3bc43840 GL |
626 | { |
627 | struct soc_camera_device *icd = vq->priv_data; | |
64f5905e | 628 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
3bc43840 GL |
629 | struct pxa_camera_dev *pcdev = ici->priv; |
630 | struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); | |
3bc43840 GL |
631 | unsigned long flags; |
632 | ||
256b0233 RJ |
633 | dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d active=%p\n", __func__, |
634 | vb, vb->baddr, vb->bsize, pcdev->active); | |
635 | ||
3bc43840 GL |
636 | spin_lock_irqsave(&pcdev->lock, flags); |
637 | ||
638 | list_add_tail(&vb->queue, &pcdev->capture); | |
639 | ||
640 | vb->state = VIDEOBUF_ACTIVE; | |
256b0233 | 641 | pxa_dma_add_tail_buf(pcdev, buf); |
3bc43840 | 642 | |
256b0233 RJ |
643 | if (!pcdev->active) |
644 | pxa_camera_start_capture(pcdev); | |
3bc43840 GL |
645 | |
646 | spin_unlock_irqrestore(&pcdev->lock, flags); | |
3bc43840 GL |
647 | } |
648 | ||
649 | static void pxa_videobuf_release(struct videobuf_queue *vq, | |
650 | struct videobuf_buffer *vb) | |
651 | { | |
652 | struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); | |
653 | #ifdef DEBUG | |
654 | struct soc_camera_device *icd = vq->priv_data; | |
655 | ||
7e28adb2 | 656 | dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, |
3bc43840 GL |
657 | vb, vb->baddr, vb->bsize); |
658 | ||
659 | switch (vb->state) { | |
660 | case VIDEOBUF_ACTIVE: | |
7e28adb2 | 661 | dev_dbg(&icd->dev, "%s (active)\n", __func__); |
3bc43840 GL |
662 | break; |
663 | case VIDEOBUF_QUEUED: | |
7e28adb2 | 664 | dev_dbg(&icd->dev, "%s (queued)\n", __func__); |
3bc43840 GL |
665 | break; |
666 | case VIDEOBUF_PREPARED: | |
7e28adb2 | 667 | dev_dbg(&icd->dev, "%s (prepared)\n", __func__); |
3bc43840 GL |
668 | break; |
669 | default: | |
7e28adb2 | 670 | dev_dbg(&icd->dev, "%s (unknown)\n", __func__); |
3bc43840 GL |
671 | break; |
672 | } | |
673 | #endif | |
674 | ||
675 | free_buffer(vq, buf); | |
676 | } | |
677 | ||
a5462e5b MR |
678 | static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev, |
679 | struct videobuf_buffer *vb, | |
680 | struct pxa_buffer *buf) | |
681 | { | |
256b0233 | 682 | int i; |
5ca11fa3 | 683 | |
a5462e5b MR |
684 | /* _init is used to debug races, see comment in pxa_camera_reqbufs() */ |
685 | list_del_init(&vb->queue); | |
686 | vb->state = VIDEOBUF_DONE; | |
687 | do_gettimeofday(&vb->ts); | |
688 | vb->field_count++; | |
689 | wake_up(&vb->done); | |
256b0233 | 690 | dev_dbg(pcdev->dev, "%s dequeud buffer (vb=0x%p)\n", __func__, vb); |
a5462e5b MR |
691 | |
692 | if (list_empty(&pcdev->capture)) { | |
256b0233 | 693 | pxa_camera_stop_capture(pcdev); |
256b0233 RJ |
694 | for (i = 0; i < pcdev->channels; i++) |
695 | pcdev->sg_tail[i] = NULL; | |
a5462e5b MR |
696 | return; |
697 | } | |
698 | ||
699 | pcdev->active = list_entry(pcdev->capture.next, | |
700 | struct pxa_buffer, vb.queue); | |
701 | } | |
702 | ||
256b0233 RJ |
703 | /** |
704 | * pxa_camera_check_link_miss - check missed DMA linking | |
705 | * @pcdev: camera device | |
706 | * | |
707 | * The DMA chaining is done with DMA running. This means a tiny temporal window | |
708 | * remains, where a buffer is queued on the chain, while the chain is already | |
709 | * stopped. This means the tailed buffer would never be transfered by DMA. | |
710 | * This function restarts the capture for this corner case, where : | |
711 | * - DADR() == DADDR_STOP | |
712 | * - a videobuffer is queued on the pcdev->capture list | |
713 | * | |
714 | * Please check the "DMA hot chaining timeslice issue" in | |
715 | * Documentation/video4linux/pxa_camera.txt | |
716 | * | |
717 | * Context: should only be called within the dma irq handler | |
718 | */ | |
719 | static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev) | |
720 | { | |
721 | int i, is_dma_stopped = 1; | |
722 | ||
723 | for (i = 0; i < pcdev->channels; i++) | |
724 | if (DDADR(pcdev->dma_chans[i]) != DDADR_STOP) | |
725 | is_dma_stopped = 0; | |
726 | dev_dbg(pcdev->dev, "%s : top queued buffer=%p, dma_stopped=%d\n", | |
727 | __func__, pcdev->active, is_dma_stopped); | |
728 | if (pcdev->active && is_dma_stopped) | |
729 | pxa_camera_start_capture(pcdev); | |
730 | } | |
731 | ||
a5462e5b MR |
732 | static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev, |
733 | enum pxa_camera_active_dma act_dma) | |
3bc43840 | 734 | { |
3bc43840 GL |
735 | struct pxa_buffer *buf; |
736 | unsigned long flags; | |
e7c50688 | 737 | u32 status, camera_status, overrun; |
3bc43840 GL |
738 | struct videobuf_buffer *vb; |
739 | ||
740 | spin_lock_irqsave(&pcdev->lock, flags); | |
741 | ||
a5462e5b | 742 | status = DCSR(channel); |
256b0233 RJ |
743 | DCSR(channel) = status; |
744 | ||
745 | camera_status = __raw_readl(pcdev->base + CISR); | |
746 | overrun = CISR_IFO_0; | |
747 | if (pcdev->channels == 3) | |
748 | overrun |= CISR_IFO_1 | CISR_IFO_2; | |
7102b773 | 749 | |
3bc43840 | 750 | if (status & DCSR_BUSERR) { |
7102b773 | 751 | dev_err(pcdev->dev, "DMA Bus Error IRQ!\n"); |
3bc43840 GL |
752 | goto out; |
753 | } | |
754 | ||
256b0233 | 755 | if (!(status & (DCSR_ENDINTR | DCSR_STARTINTR))) { |
7102b773 GL |
756 | dev_err(pcdev->dev, "Unknown DMA IRQ source, " |
757 | "status: 0x%08x\n", status); | |
3bc43840 GL |
758 | goto out; |
759 | } | |
760 | ||
8c62e221 RJ |
761 | /* |
762 | * pcdev->active should not be NULL in DMA irq handler. | |
763 | * | |
764 | * But there is one corner case : if capture was stopped due to an | |
765 | * overrun of channel 1, and at that same channel 2 was completed. | |
766 | * | |
767 | * When handling the overrun in DMA irq for channel 1, we'll stop the | |
768 | * capture and restart it (and thus set pcdev->active to NULL). But the | |
769 | * DMA irq handler will already be pending for channel 2. So on entering | |
770 | * the DMA irq handler for channel 2 there will be no active buffer, yet | |
771 | * that is normal. | |
772 | */ | |
773 | if (!pcdev->active) | |
3bc43840 | 774 | goto out; |
3bc43840 GL |
775 | |
776 | vb = &pcdev->active->vb; | |
777 | buf = container_of(vb, struct pxa_buffer, vb); | |
778 | WARN_ON(buf->inwork || list_empty(&vb->queue)); | |
3bc43840 | 779 | |
256b0233 RJ |
780 | dev_dbg(pcdev->dev, "%s channel=%d %s%s(vb=0x%p) dma.desc=%x\n", |
781 | __func__, channel, status & DCSR_STARTINTR ? "SOF " : "", | |
782 | status & DCSR_ENDINTR ? "EOF " : "", vb, DDADR(channel)); | |
783 | ||
784 | if (status & DCSR_ENDINTR) { | |
8c62e221 RJ |
785 | /* |
786 | * It's normal if the last frame creates an overrun, as there | |
787 | * are no more DMA descriptors to fetch from QCI fifos | |
788 | */ | |
789 | if (camera_status & overrun && | |
790 | !list_is_last(pcdev->capture.next, &pcdev->capture)) { | |
256b0233 RJ |
791 | dev_dbg(pcdev->dev, "FIFO overrun! CISR: %x\n", |
792 | camera_status); | |
793 | pxa_camera_stop_capture(pcdev); | |
794 | pxa_camera_start_capture(pcdev); | |
795 | goto out; | |
796 | } | |
797 | buf->active_dma &= ~act_dma; | |
798 | if (!buf->active_dma) { | |
799 | pxa_camera_wakeup(pcdev, vb, buf); | |
800 | pxa_camera_check_link_miss(pcdev); | |
801 | } | |
802 | } | |
3bc43840 GL |
803 | |
804 | out: | |
805 | spin_unlock_irqrestore(&pcdev->lock, flags); | |
806 | } | |
807 | ||
a5462e5b MR |
808 | static void pxa_camera_dma_irq_y(int channel, void *data) |
809 | { | |
810 | struct pxa_camera_dev *pcdev = data; | |
811 | pxa_camera_dma_irq(channel, pcdev, DMA_Y); | |
812 | } | |
813 | ||
814 | static void pxa_camera_dma_irq_u(int channel, void *data) | |
815 | { | |
816 | struct pxa_camera_dev *pcdev = data; | |
817 | pxa_camera_dma_irq(channel, pcdev, DMA_U); | |
818 | } | |
819 | ||
820 | static void pxa_camera_dma_irq_v(int channel, void *data) | |
821 | { | |
822 | struct pxa_camera_dev *pcdev = data; | |
823 | pxa_camera_dma_irq(channel, pcdev, DMA_V); | |
824 | } | |
825 | ||
7102b773 | 826 | static struct videobuf_queue_ops pxa_videobuf_ops = { |
3bc43840 GL |
827 | .buf_setup = pxa_videobuf_setup, |
828 | .buf_prepare = pxa_videobuf_prepare, | |
829 | .buf_queue = pxa_videobuf_queue, | |
830 | .buf_release = pxa_videobuf_release, | |
831 | }; | |
832 | ||
a034d1b7 | 833 | static void pxa_camera_init_videobuf(struct videobuf_queue *q, |
092d3921 PZ |
834 | struct soc_camera_device *icd) |
835 | { | |
a034d1b7 MD |
836 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
837 | struct pxa_camera_dev *pcdev = ici->priv; | |
838 | ||
092d3921 PZ |
839 | /* We must pass NULL as dev pointer, then all pci_* dma operations |
840 | * transform to normal dma_* ones. */ | |
a034d1b7 | 841 | videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock, |
092d3921 PZ |
842 | V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE, |
843 | sizeof(struct pxa_buffer), icd); | |
844 | } | |
845 | ||
cf34cba7 | 846 | static u32 mclk_get_divisor(struct pxa_camera_dev *pcdev) |
3bc43840 | 847 | { |
cf34cba7 GL |
848 | unsigned long mclk = pcdev->mclk; |
849 | u32 div; | |
3bc43840 GL |
850 | unsigned long lcdclk; |
851 | ||
cf34cba7 GL |
852 | lcdclk = clk_get_rate(pcdev->clk); |
853 | pcdev->ciclk = lcdclk; | |
3bc43840 | 854 | |
cf34cba7 GL |
855 | /* mclk <= ciclk / 4 (27.4.2) */ |
856 | if (mclk > lcdclk / 4) { | |
857 | mclk = lcdclk / 4; | |
858 | dev_warn(pcdev->dev, "Limiting master clock to %lu\n", mclk); | |
859 | } | |
860 | ||
861 | /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */ | |
862 | div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1; | |
3bc43840 | 863 | |
cf34cba7 GL |
864 | /* If we're not supplying MCLK, leave it at 0 */ |
865 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
866 | pcdev->mclk = lcdclk / (2 * (div + 1)); | |
3bc43840 | 867 | |
cf34cba7 GL |
868 | dev_dbg(pcdev->dev, "LCD clock %luHz, target freq %luHz, " |
869 | "divisor %u\n", lcdclk, mclk, div); | |
3bc43840 GL |
870 | |
871 | return div; | |
872 | } | |
873 | ||
cf34cba7 GL |
874 | static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev, |
875 | unsigned long pclk) | |
876 | { | |
877 | /* We want a timeout > 1 pixel time, not ">=" */ | |
878 | u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1; | |
879 | ||
880 | __raw_writel(ciclk_per_pixel, pcdev->base + CITOR); | |
881 | } | |
882 | ||
7102b773 | 883 | static void pxa_camera_activate(struct pxa_camera_dev *pcdev) |
3bc43840 GL |
884 | { |
885 | struct pxacamera_platform_data *pdata = pcdev->pdata; | |
886 | u32 cicr4 = 0; | |
887 | ||
888 | dev_dbg(pcdev->dev, "Registered platform device at %p data %p\n", | |
889 | pcdev, pdata); | |
890 | ||
891 | if (pdata && pdata->init) { | |
7e28adb2 | 892 | dev_dbg(pcdev->dev, "%s: Init gpios\n", __func__); |
3bc43840 GL |
893 | pdata->init(pcdev->dev); |
894 | } | |
895 | ||
5ca11fa3 EM |
896 | /* disable all interrupts */ |
897 | __raw_writel(0x3ff, pcdev->base + CICR0); | |
3bc43840 GL |
898 | |
899 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
900 | cicr4 |= CICR4_PCLK_EN; | |
901 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
902 | cicr4 |= CICR4_MCLK_EN; | |
903 | if (pcdev->platform_flags & PXA_CAMERA_PCP) | |
904 | cicr4 |= CICR4_PCP; | |
905 | if (pcdev->platform_flags & PXA_CAMERA_HSP) | |
906 | cicr4 |= CICR4_HSP; | |
907 | if (pcdev->platform_flags & PXA_CAMERA_VSP) | |
908 | cicr4 |= CICR4_VSP; | |
909 | ||
cf34cba7 GL |
910 | __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4); |
911 | ||
912 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
913 | /* Initialise the timeout under the assumption pclk = mclk */ | |
914 | recalculate_fifo_timeout(pcdev, pcdev->mclk); | |
915 | else | |
916 | /* "Safe default" - 13MHz */ | |
917 | recalculate_fifo_timeout(pcdev, 13000000); | |
3bc43840 GL |
918 | |
919 | clk_enable(pcdev->clk); | |
920 | } | |
921 | ||
7102b773 | 922 | static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev) |
3bc43840 | 923 | { |
3bc43840 | 924 | clk_disable(pcdev->clk); |
3bc43840 GL |
925 | } |
926 | ||
927 | static irqreturn_t pxa_camera_irq(int irq, void *data) | |
928 | { | |
929 | struct pxa_camera_dev *pcdev = data; | |
5ca11fa3 | 930 | unsigned long status, cicr0; |
256b0233 RJ |
931 | struct pxa_buffer *buf; |
932 | struct videobuf_buffer *vb; | |
3bc43840 | 933 | |
5ca11fa3 EM |
934 | status = __raw_readl(pcdev->base + CISR); |
935 | dev_dbg(pcdev->dev, "Camera interrupt status 0x%lx\n", status); | |
3bc43840 | 936 | |
e7c50688 GL |
937 | if (!status) |
938 | return IRQ_NONE; | |
939 | ||
5ca11fa3 | 940 | __raw_writel(status, pcdev->base + CISR); |
e7c50688 GL |
941 | |
942 | if (status & CISR_EOF) { | |
256b0233 RJ |
943 | pcdev->active = list_first_entry(&pcdev->capture, |
944 | struct pxa_buffer, vb.queue); | |
945 | vb = &pcdev->active->vb; | |
946 | buf = container_of(vb, struct pxa_buffer, vb); | |
947 | pxa_videobuf_set_actdma(pcdev, buf); | |
948 | ||
949 | pxa_dma_start_channels(pcdev); | |
950 | ||
5ca11fa3 EM |
951 | cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM; |
952 | __raw_writel(cicr0, pcdev->base + CICR0); | |
e7c50688 GL |
953 | } |
954 | ||
3bc43840 GL |
955 | return IRQ_HANDLED; |
956 | } | |
957 | ||
1c3bb743 GL |
958 | /* |
959 | * The following two functions absolutely depend on the fact, that | |
960 | * there can be only one camera on PXA quick capture interface | |
961 | * Called with .video_lock held | |
962 | */ | |
7102b773 | 963 | static int pxa_camera_add_device(struct soc_camera_device *icd) |
3bc43840 GL |
964 | { |
965 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
966 | struct pxa_camera_dev *pcdev = ici->priv; | |
967 | int ret; | |
968 | ||
3bc43840 GL |
969 | if (pcdev->icd) { |
970 | ret = -EBUSY; | |
971 | goto ebusy; | |
972 | } | |
973 | ||
974 | dev_info(&icd->dev, "PXA Camera driver attached to camera %d\n", | |
975 | icd->devnum); | |
976 | ||
7102b773 | 977 | pxa_camera_activate(pcdev); |
3bc43840 GL |
978 | ret = icd->ops->init(icd); |
979 | ||
980 | if (!ret) | |
981 | pcdev->icd = icd; | |
982 | ||
983 | ebusy: | |
3bc43840 GL |
984 | return ret; |
985 | } | |
986 | ||
1c3bb743 | 987 | /* Called with .video_lock held */ |
7102b773 | 988 | static void pxa_camera_remove_device(struct soc_camera_device *icd) |
3bc43840 GL |
989 | { |
990 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
991 | struct pxa_camera_dev *pcdev = ici->priv; | |
992 | ||
993 | BUG_ON(icd != pcdev->icd); | |
994 | ||
995 | dev_info(&icd->dev, "PXA Camera driver detached from camera %d\n", | |
996 | icd->devnum); | |
997 | ||
998 | /* disable capture, disable interrupts */ | |
5ca11fa3 | 999 | __raw_writel(0x3ff, pcdev->base + CICR0); |
a5462e5b | 1000 | |
3bc43840 | 1001 | /* Stop DMA engine */ |
a5462e5b MR |
1002 | DCSR(pcdev->dma_chans[0]) = 0; |
1003 | DCSR(pcdev->dma_chans[1]) = 0; | |
1004 | DCSR(pcdev->dma_chans[2]) = 0; | |
3bc43840 GL |
1005 | |
1006 | icd->ops->release(icd); | |
1007 | ||
7102b773 | 1008 | pxa_camera_deactivate(pcdev); |
3bc43840 GL |
1009 | |
1010 | pcdev->icd = NULL; | |
1011 | } | |
1012 | ||
ad5f2e85 GL |
1013 | static int test_platform_param(struct pxa_camera_dev *pcdev, |
1014 | unsigned char buswidth, unsigned long *flags) | |
3bc43840 | 1015 | { |
ad5f2e85 GL |
1016 | /* |
1017 | * Platform specified synchronization and pixel clock polarities are | |
1018 | * only a recommendation and are only used during probing. The PXA270 | |
1019 | * quick capture interface supports both. | |
1020 | */ | |
1021 | *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ? | |
1022 | SOCAM_MASTER : SOCAM_SLAVE) | | |
1023 | SOCAM_HSYNC_ACTIVE_HIGH | | |
1024 | SOCAM_HSYNC_ACTIVE_LOW | | |
1025 | SOCAM_VSYNC_ACTIVE_HIGH | | |
1026 | SOCAM_VSYNC_ACTIVE_LOW | | |
2d9329f3 | 1027 | SOCAM_DATA_ACTIVE_HIGH | |
ad5f2e85 GL |
1028 | SOCAM_PCLK_SAMPLE_RISING | |
1029 | SOCAM_PCLK_SAMPLE_FALLING; | |
3bc43840 GL |
1030 | |
1031 | /* If requested data width is supported by the platform, use it */ | |
ad5f2e85 | 1032 | switch (buswidth) { |
3bc43840 | 1033 | case 10: |
ad5f2e85 GL |
1034 | if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10)) |
1035 | return -EINVAL; | |
1036 | *flags |= SOCAM_DATAWIDTH_10; | |
3bc43840 GL |
1037 | break; |
1038 | case 9: | |
ad5f2e85 GL |
1039 | if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9)) |
1040 | return -EINVAL; | |
1041 | *flags |= SOCAM_DATAWIDTH_9; | |
3bc43840 GL |
1042 | break; |
1043 | case 8: | |
ad5f2e85 GL |
1044 | if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8)) |
1045 | return -EINVAL; | |
1046 | *flags |= SOCAM_DATAWIDTH_8; | |
2a48fc73 RJ |
1047 | break; |
1048 | default: | |
1049 | return -EINVAL; | |
3bc43840 | 1050 | } |
ad5f2e85 GL |
1051 | |
1052 | return 0; | |
1053 | } | |
1054 | ||
1055 | static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt) | |
1056 | { | |
64f5905e | 1057 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
ad5f2e85 GL |
1058 | struct pxa_camera_dev *pcdev = ici->priv; |
1059 | unsigned long dw, bpp, bus_flags, camera_flags, common_flags; | |
5ca11fa3 | 1060 | u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0; |
ad5f2e85 GL |
1061 | int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags); |
1062 | ||
1063 | if (ret < 0) | |
1064 | return ret; | |
1065 | ||
1066 | camera_flags = icd->ops->query_bus_param(icd); | |
1067 | ||
1068 | common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags); | |
1069 | if (!common_flags) | |
3bc43840 GL |
1070 | return -EINVAL; |
1071 | ||
e7c50688 GL |
1072 | pcdev->channels = 1; |
1073 | ||
ad5f2e85 GL |
1074 | /* Make choises, based on platform preferences */ |
1075 | if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) && | |
1076 | (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) { | |
1077 | if (pcdev->platform_flags & PXA_CAMERA_HSP) | |
1078 | common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH; | |
1079 | else | |
1080 | common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW; | |
1081 | } | |
1082 | ||
1083 | if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) && | |
1084 | (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) { | |
1085 | if (pcdev->platform_flags & PXA_CAMERA_VSP) | |
1086 | common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH; | |
1087 | else | |
1088 | common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW; | |
1089 | } | |
1090 | ||
1091 | if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) && | |
1092 | (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) { | |
1093 | if (pcdev->platform_flags & PXA_CAMERA_PCP) | |
1094 | common_flags &= ~SOCAM_PCLK_SAMPLE_RISING; | |
1095 | else | |
1096 | common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING; | |
1097 | } | |
1098 | ||
1099 | ret = icd->ops->set_bus_param(icd, common_flags); | |
3bc43840 GL |
1100 | if (ret < 0) |
1101 | return ret; | |
1102 | ||
1103 | /* Datawidth is now guaranteed to be equal to one of the three values. | |
1104 | * We fix bit-per-pixel equal to data-width... */ | |
ad5f2e85 GL |
1105 | switch (common_flags & SOCAM_DATAWIDTH_MASK) { |
1106 | case SOCAM_DATAWIDTH_10: | |
3bc43840 GL |
1107 | dw = 4; |
1108 | bpp = 0x40; | |
1109 | break; | |
ad5f2e85 | 1110 | case SOCAM_DATAWIDTH_9: |
3bc43840 GL |
1111 | dw = 3; |
1112 | bpp = 0x20; | |
1113 | break; | |
1114 | default: | |
1115 | /* Actually it can only be 8 now, | |
1116 | * default is just to silence compiler warnings */ | |
ad5f2e85 | 1117 | case SOCAM_DATAWIDTH_8: |
3bc43840 GL |
1118 | dw = 2; |
1119 | bpp = 0; | |
1120 | } | |
1121 | ||
1122 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
1123 | cicr4 |= CICR4_PCLK_EN; | |
1124 | if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN) | |
1125 | cicr4 |= CICR4_MCLK_EN; | |
ad5f2e85 | 1126 | if (common_flags & SOCAM_PCLK_SAMPLE_FALLING) |
3bc43840 | 1127 | cicr4 |= CICR4_PCP; |
ad5f2e85 | 1128 | if (common_flags & SOCAM_HSYNC_ACTIVE_LOW) |
3bc43840 | 1129 | cicr4 |= CICR4_HSP; |
ad5f2e85 | 1130 | if (common_flags & SOCAM_VSYNC_ACTIVE_LOW) |
3bc43840 GL |
1131 | cicr4 |= CICR4_VSP; |
1132 | ||
5ca11fa3 | 1133 | cicr0 = __raw_readl(pcdev->base + CICR0); |
3bc43840 | 1134 | if (cicr0 & CICR0_ENB) |
5ca11fa3 | 1135 | __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0); |
a5462e5b MR |
1136 | |
1137 | cicr1 = CICR1_PPL_VAL(icd->width - 1) | bpp | dw; | |
1138 | ||
1139 | switch (pixfmt) { | |
1140 | case V4L2_PIX_FMT_YUV422P: | |
e7c50688 | 1141 | pcdev->channels = 3; |
a5462e5b | 1142 | cicr1 |= CICR1_YCBCR_F; |
2a48fc73 RJ |
1143 | /* |
1144 | * Normally, pxa bus wants as input UYVY format. We allow all | |
1145 | * reorderings of the YUV422 format, as no processing is done, | |
1146 | * and the YUV stream is just passed through without any | |
1147 | * transformation. Note that UYVY is the only format that | |
1148 | * should be used if pxa framebuffer Overlay2 is used. | |
1149 | */ | |
1150 | case V4L2_PIX_FMT_UYVY: | |
1151 | case V4L2_PIX_FMT_VYUY: | |
a5462e5b | 1152 | case V4L2_PIX_FMT_YUYV: |
2a48fc73 | 1153 | case V4L2_PIX_FMT_YVYU: |
a5462e5b MR |
1154 | cicr1 |= CICR1_COLOR_SP_VAL(2); |
1155 | break; | |
1156 | case V4L2_PIX_FMT_RGB555: | |
1157 | cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) | | |
1158 | CICR1_TBIT | CICR1_COLOR_SP_VAL(1); | |
1159 | break; | |
1160 | case V4L2_PIX_FMT_RGB565: | |
1161 | cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2); | |
1162 | break; | |
1163 | } | |
1164 | ||
5ca11fa3 EM |
1165 | cicr2 = 0; |
1166 | cicr3 = CICR3_LPF_VAL(icd->height - 1) | | |
3bc43840 | 1167 | CICR3_BFW_VAL(min((unsigned short)255, icd->y_skip_top)); |
cf34cba7 | 1168 | cicr4 |= pcdev->mclk_divisor; |
5ca11fa3 EM |
1169 | |
1170 | __raw_writel(cicr1, pcdev->base + CICR1); | |
1171 | __raw_writel(cicr2, pcdev->base + CICR2); | |
1172 | __raw_writel(cicr3, pcdev->base + CICR3); | |
1173 | __raw_writel(cicr4, pcdev->base + CICR4); | |
3bc43840 GL |
1174 | |
1175 | /* CIF interrupts are not used, only DMA */ | |
5ca11fa3 EM |
1176 | cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ? |
1177 | CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP)); | |
1178 | cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK; | |
1179 | __raw_writel(cicr0, pcdev->base + CICR0); | |
3bc43840 GL |
1180 | |
1181 | return 0; | |
1182 | } | |
1183 | ||
2a48fc73 RJ |
1184 | static int pxa_camera_try_bus_param(struct soc_camera_device *icd, |
1185 | unsigned char buswidth) | |
ad5f2e85 | 1186 | { |
cf34cba7 | 1187 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
ad5f2e85 GL |
1188 | struct pxa_camera_dev *pcdev = ici->priv; |
1189 | unsigned long bus_flags, camera_flags; | |
2a48fc73 | 1190 | int ret = test_platform_param(pcdev, buswidth, &bus_flags); |
ad5f2e85 GL |
1191 | |
1192 | if (ret < 0) | |
1193 | return ret; | |
1194 | ||
1195 | camera_flags = icd->ops->query_bus_param(icd); | |
1196 | ||
1197 | return soc_camera_bus_param_compatible(camera_flags, bus_flags) ? 0 : -EINVAL; | |
1198 | } | |
1199 | ||
2a48fc73 RJ |
1200 | static const struct soc_camera_data_format pxa_camera_formats[] = { |
1201 | { | |
1202 | .name = "Planar YUV422 16 bit", | |
1203 | .depth = 16, | |
1204 | .fourcc = V4L2_PIX_FMT_YUV422P, | |
1205 | .colorspace = V4L2_COLORSPACE_JPEG, | |
1206 | }, | |
1207 | }; | |
1208 | ||
1209 | static bool buswidth_supported(struct soc_camera_device *icd, int depth) | |
ad5f2e85 | 1210 | { |
2a48fc73 RJ |
1211 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
1212 | struct pxa_camera_dev *pcdev = ici->priv; | |
1213 | ||
1214 | switch (depth) { | |
1215 | case 8: | |
1216 | return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8); | |
1217 | case 9: | |
1218 | return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9); | |
1219 | case 10: | |
1220 | return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10); | |
1221 | } | |
1222 | return false; | |
ad5f2e85 GL |
1223 | } |
1224 | ||
2a48fc73 | 1225 | static int required_buswidth(const struct soc_camera_data_format *fmt) |
3bc43840 | 1226 | { |
2a48fc73 RJ |
1227 | switch (fmt->fourcc) { |
1228 | case V4L2_PIX_FMT_UYVY: | |
1229 | case V4L2_PIX_FMT_VYUY: | |
1230 | case V4L2_PIX_FMT_YUYV: | |
1231 | case V4L2_PIX_FMT_YVYU: | |
1232 | case V4L2_PIX_FMT_RGB565: | |
1233 | case V4L2_PIX_FMT_RGB555: | |
1234 | return 8; | |
1235 | default: | |
1236 | return fmt->depth; | |
1237 | } | |
1238 | } | |
1239 | ||
1240 | static int pxa_camera_get_formats(struct soc_camera_device *icd, int idx, | |
1241 | struct soc_camera_format_xlate *xlate) | |
1242 | { | |
1243 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
1244 | int formats = 0, buswidth, ret; | |
1245 | ||
1246 | buswidth = required_buswidth(icd->formats + idx); | |
1247 | ||
1248 | if (!buswidth_supported(icd, buswidth)) | |
1249 | return 0; | |
3bc43840 | 1250 | |
2a48fc73 RJ |
1251 | ret = pxa_camera_try_bus_param(icd, buswidth); |
1252 | if (ret < 0) | |
1253 | return 0; | |
1254 | ||
1255 | switch (icd->formats[idx].fourcc) { | |
1256 | case V4L2_PIX_FMT_UYVY: | |
1257 | formats++; | |
1258 | if (xlate) { | |
1259 | xlate->host_fmt = &pxa_camera_formats[0]; | |
1260 | xlate->cam_fmt = icd->formats + idx; | |
1261 | xlate->buswidth = buswidth; | |
1262 | xlate++; | |
1263 | dev_dbg(&ici->dev, "Providing format %s using %s\n", | |
1264 | pxa_camera_formats[0].name, | |
1265 | icd->formats[idx].name); | |
1266 | } | |
1267 | case V4L2_PIX_FMT_VYUY: | |
1268 | case V4L2_PIX_FMT_YUYV: | |
1269 | case V4L2_PIX_FMT_YVYU: | |
1270 | case V4L2_PIX_FMT_RGB565: | |
1271 | case V4L2_PIX_FMT_RGB555: | |
1272 | formats++; | |
1273 | if (xlate) { | |
1274 | xlate->host_fmt = icd->formats + idx; | |
1275 | xlate->cam_fmt = icd->formats + idx; | |
1276 | xlate->buswidth = buswidth; | |
1277 | xlate++; | |
1278 | dev_dbg(&ici->dev, "Providing format %s packed\n", | |
1279 | icd->formats[idx].name); | |
1280 | } | |
1281 | break; | |
1282 | default: | |
1283 | /* Generic pass-through */ | |
1284 | formats++; | |
1285 | if (xlate) { | |
1286 | xlate->host_fmt = icd->formats + idx; | |
1287 | xlate->cam_fmt = icd->formats + idx; | |
1288 | xlate->buswidth = icd->formats[idx].depth; | |
1289 | xlate++; | |
1290 | dev_dbg(&ici->dev, | |
1291 | "Providing format %s in pass-through mode\n", | |
1292 | icd->formats[idx].name); | |
1293 | } | |
1294 | } | |
1295 | ||
1296 | return formats; | |
1297 | } | |
1298 | ||
09e231b3 GL |
1299 | static int pxa_camera_set_crop(struct soc_camera_device *icd, |
1300 | struct v4l2_rect *rect) | |
1301 | { | |
1302 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); | |
1303 | struct pxa_camera_dev *pcdev = ici->priv; | |
1304 | struct soc_camera_sense sense = { | |
1305 | .master_clock = pcdev->mclk, | |
1306 | .pixel_clock_max = pcdev->ciclk / 4, | |
1307 | }; | |
1308 | int ret; | |
1309 | ||
1310 | /* If PCLK is used to latch data from the sensor, check sense */ | |
1311 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
1312 | icd->sense = &sense; | |
1313 | ||
1314 | ret = icd->ops->set_crop(icd, rect); | |
1315 | ||
1316 | icd->sense = NULL; | |
1317 | ||
1318 | if (ret < 0) { | |
1319 | dev_warn(&ici->dev, "Failed to crop to %ux%u@%u:%u\n", | |
1320 | rect->width, rect->height, rect->left, rect->top); | |
1321 | } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) { | |
1322 | if (sense.pixel_clock > sense.pixel_clock_max) { | |
1323 | dev_err(&ici->dev, | |
1324 | "pixel clock %lu set by the camera too high!", | |
1325 | sense.pixel_clock); | |
1326 | return -EIO; | |
1327 | } | |
1328 | recalculate_fifo_timeout(pcdev, sense.pixel_clock); | |
1329 | } | |
1330 | ||
1331 | return ret; | |
1332 | } | |
1333 | ||
d8fac217 | 1334 | static int pxa_camera_set_fmt(struct soc_camera_device *icd, |
09e231b3 | 1335 | struct v4l2_format *f) |
ad5f2e85 | 1336 | { |
2a48fc73 | 1337 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
cf34cba7 | 1338 | struct pxa_camera_dev *pcdev = ici->priv; |
0ad675eb GL |
1339 | const struct soc_camera_data_format *cam_fmt = NULL; |
1340 | const struct soc_camera_format_xlate *xlate = NULL; | |
cf34cba7 GL |
1341 | struct soc_camera_sense sense = { |
1342 | .master_clock = pcdev->mclk, | |
1343 | .pixel_clock_max = pcdev->ciclk / 4, | |
1344 | }; | |
09e231b3 GL |
1345 | struct v4l2_pix_format *pix = &f->fmt.pix; |
1346 | struct v4l2_format cam_f = *f; | |
0ad675eb | 1347 | int ret; |
25c4d74e | 1348 | |
09e231b3 GL |
1349 | xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); |
1350 | if (!xlate) { | |
1351 | dev_warn(&ici->dev, "Format %x not found\n", pix->pixelformat); | |
1352 | return -EINVAL; | |
0ad675eb | 1353 | } |
2a48fc73 | 1354 | |
09e231b3 GL |
1355 | cam_fmt = xlate->cam_fmt; |
1356 | ||
cf34cba7 GL |
1357 | /* If PCLK is used to latch data from the sensor, check sense */ |
1358 | if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) | |
1359 | icd->sense = &sense; | |
1360 | ||
09e231b3 GL |
1361 | cam_f.fmt.pix.pixelformat = cam_fmt->fourcc; |
1362 | ret = icd->ops->set_fmt(icd, &cam_f); | |
2a48fc73 | 1363 | |
cf34cba7 GL |
1364 | icd->sense = NULL; |
1365 | ||
1366 | if (ret < 0) { | |
2a48fc73 | 1367 | dev_warn(&ici->dev, "Failed to configure for format %x\n", |
09e231b3 | 1368 | pix->pixelformat); |
cf34cba7 GL |
1369 | } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) { |
1370 | if (sense.pixel_clock > sense.pixel_clock_max) { | |
1371 | dev_err(&ici->dev, | |
1372 | "pixel clock %lu set by the camera too high!", | |
1373 | sense.pixel_clock); | |
1374 | return -EIO; | |
1375 | } | |
1376 | recalculate_fifo_timeout(pcdev, sense.pixel_clock); | |
1377 | } | |
2a48fc73 | 1378 | |
09e231b3 | 1379 | if (!ret) { |
0ad675eb GL |
1380 | icd->buswidth = xlate->buswidth; |
1381 | icd->current_fmt = xlate->host_fmt; | |
2a48fc73 | 1382 | } |
25c4d74e GL |
1383 | |
1384 | return ret; | |
ad5f2e85 GL |
1385 | } |
1386 | ||
d8fac217 GL |
1387 | static int pxa_camera_try_fmt(struct soc_camera_device *icd, |
1388 | struct v4l2_format *f) | |
3bc43840 | 1389 | { |
2a48fc73 RJ |
1390 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
1391 | const struct soc_camera_format_xlate *xlate; | |
1392 | struct v4l2_pix_format *pix = &f->fmt.pix; | |
1393 | __u32 pixfmt = pix->pixelformat; | |
06daa1af | 1394 | enum v4l2_field field; |
bf507158 | 1395 | int ret; |
a2c8c68c | 1396 | |
2a48fc73 RJ |
1397 | xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); |
1398 | if (!xlate) { | |
1399 | dev_warn(&ici->dev, "Format %x not found\n", pixfmt); | |
25c4d74e | 1400 | return -EINVAL; |
2a48fc73 | 1401 | } |
25c4d74e | 1402 | |
3bc43840 | 1403 | /* limit to pxa hardware capabilities */ |
2a48fc73 RJ |
1404 | if (pix->height < 32) |
1405 | pix->height = 32; | |
1406 | if (pix->height > 2048) | |
1407 | pix->height = 2048; | |
1408 | if (pix->width < 48) | |
1409 | pix->width = 48; | |
1410 | if (pix->width > 2048) | |
1411 | pix->width = 2048; | |
1412 | pix->width &= ~0x01; | |
1413 | ||
92a8337b RJ |
1414 | /* |
1415 | * YUV422P planar format requires images size to be a 16 bytes | |
1416 | * multiple. If not, zeros will be inserted between Y and U planes, and | |
1417 | * U and V planes, and YUV422P standard would be violated. | |
1418 | */ | |
1419 | if (xlate->host_fmt->fourcc == V4L2_PIX_FMT_YUV422P) { | |
1420 | if (!IS_ALIGNED(pix->width * pix->height, YUV422P_SIZE_ALIGN)) | |
1421 | pix->height = ALIGN(pix->height, YUV422P_X_Y_ALIGN); | |
1422 | if (!IS_ALIGNED(pix->width * pix->height, YUV422P_SIZE_ALIGN)) | |
1423 | pix->width = ALIGN(pix->width, YUV422P_X_Y_ALIGN); | |
1424 | } | |
1425 | ||
2a48fc73 RJ |
1426 | pix->bytesperline = pix->width * |
1427 | DIV_ROUND_UP(xlate->host_fmt->depth, 8); | |
1428 | pix->sizeimage = pix->height * pix->bytesperline; | |
25c4d74e | 1429 | |
bf507158 GL |
1430 | /* camera has to see its format, but the user the original one */ |
1431 | pix->pixelformat = xlate->cam_fmt->fourcc; | |
ad5f2e85 | 1432 | /* limit to sensor capabilities */ |
bf507158 GL |
1433 | ret = icd->ops->try_fmt(icd, f); |
1434 | pix->pixelformat = xlate->host_fmt->fourcc; | |
1435 | ||
06daa1af GL |
1436 | field = pix->field; |
1437 | ||
1438 | if (field == V4L2_FIELD_ANY) { | |
1439 | pix->field = V4L2_FIELD_NONE; | |
1440 | } else if (field != V4L2_FIELD_NONE) { | |
1441 | dev_err(&icd->dev, "Field type %d unsupported.\n", field); | |
1442 | return -EINVAL; | |
1443 | } | |
1444 | ||
bf507158 | 1445 | return ret; |
3bc43840 GL |
1446 | } |
1447 | ||
7102b773 GL |
1448 | static int pxa_camera_reqbufs(struct soc_camera_file *icf, |
1449 | struct v4l2_requestbuffers *p) | |
3bc43840 GL |
1450 | { |
1451 | int i; | |
1452 | ||
1453 | /* This is for locking debugging only. I removed spinlocks and now I | |
1454 | * check whether .prepare is ever called on a linked buffer, or whether | |
1455 | * a dma IRQ can occur for an in-work or unlinked buffer. Until now | |
1456 | * it hadn't triggered */ | |
1457 | for (i = 0; i < p->count; i++) { | |
1458 | struct pxa_buffer *buf = container_of(icf->vb_vidq.bufs[i], | |
1459 | struct pxa_buffer, vb); | |
1460 | buf->inwork = 0; | |
1461 | INIT_LIST_HEAD(&buf->vb.queue); | |
1462 | } | |
1463 | ||
1464 | return 0; | |
1465 | } | |
1466 | ||
7102b773 | 1467 | static unsigned int pxa_camera_poll(struct file *file, poll_table *pt) |
3bc43840 GL |
1468 | { |
1469 | struct soc_camera_file *icf = file->private_data; | |
1470 | struct pxa_buffer *buf; | |
1471 | ||
1472 | buf = list_entry(icf->vb_vidq.stream.next, struct pxa_buffer, | |
1473 | vb.stream); | |
1474 | ||
1475 | poll_wait(file, &buf->vb.done, pt); | |
1476 | ||
1477 | if (buf->vb.state == VIDEOBUF_DONE || | |
1478 | buf->vb.state == VIDEOBUF_ERROR) | |
1479 | return POLLIN|POLLRDNORM; | |
1480 | ||
1481 | return 0; | |
1482 | } | |
1483 | ||
7102b773 GL |
1484 | static int pxa_camera_querycap(struct soc_camera_host *ici, |
1485 | struct v4l2_capability *cap) | |
3bc43840 GL |
1486 | { |
1487 | /* cap->name is set by the firendly caller:-> */ | |
1488 | strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card)); | |
1489 | cap->version = PXA_CAM_VERSION_CODE; | |
1490 | cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; | |
1491 | ||
1492 | return 0; | |
1493 | } | |
1494 | ||
3f6ac497 RJ |
1495 | static int pxa_camera_suspend(struct soc_camera_device *icd, pm_message_t state) |
1496 | { | |
64f5905e | 1497 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
3f6ac497 RJ |
1498 | struct pxa_camera_dev *pcdev = ici->priv; |
1499 | int i = 0, ret = 0; | |
1500 | ||
5ca11fa3 EM |
1501 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0); |
1502 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1); | |
1503 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2); | |
1504 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3); | |
1505 | pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4); | |
3f6ac497 RJ |
1506 | |
1507 | if ((pcdev->icd) && (pcdev->icd->ops->suspend)) | |
1508 | ret = pcdev->icd->ops->suspend(pcdev->icd, state); | |
1509 | ||
1510 | return ret; | |
1511 | } | |
1512 | ||
1513 | static int pxa_camera_resume(struct soc_camera_device *icd) | |
1514 | { | |
64f5905e | 1515 | struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); |
3f6ac497 RJ |
1516 | struct pxa_camera_dev *pcdev = ici->priv; |
1517 | int i = 0, ret = 0; | |
1518 | ||
87f3dd77 EM |
1519 | DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD; |
1520 | DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD; | |
1521 | DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD; | |
3f6ac497 | 1522 | |
5ca11fa3 EM |
1523 | __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0); |
1524 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1); | |
1525 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2); | |
1526 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3); | |
1527 | __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4); | |
3f6ac497 RJ |
1528 | |
1529 | if ((pcdev->icd) && (pcdev->icd->ops->resume)) | |
1530 | ret = pcdev->icd->ops->resume(pcdev->icd); | |
1531 | ||
1532 | /* Restart frame capture if active buffer exists */ | |
256b0233 RJ |
1533 | if (!ret && pcdev->active) |
1534 | pxa_camera_start_capture(pcdev); | |
3f6ac497 RJ |
1535 | |
1536 | return ret; | |
1537 | } | |
1538 | ||
b8d9904c GL |
1539 | static struct soc_camera_host_ops pxa_soc_camera_host_ops = { |
1540 | .owner = THIS_MODULE, | |
1541 | .add = pxa_camera_add_device, | |
1542 | .remove = pxa_camera_remove_device, | |
3f6ac497 RJ |
1543 | .suspend = pxa_camera_suspend, |
1544 | .resume = pxa_camera_resume, | |
09e231b3 | 1545 | .set_crop = pxa_camera_set_crop, |
2a48fc73 | 1546 | .get_formats = pxa_camera_get_formats, |
d8fac217 GL |
1547 | .set_fmt = pxa_camera_set_fmt, |
1548 | .try_fmt = pxa_camera_try_fmt, | |
092d3921 | 1549 | .init_videobuf = pxa_camera_init_videobuf, |
b8d9904c GL |
1550 | .reqbufs = pxa_camera_reqbufs, |
1551 | .poll = pxa_camera_poll, | |
1552 | .querycap = pxa_camera_querycap, | |
b8d9904c GL |
1553 | .set_bus_param = pxa_camera_set_bus_param, |
1554 | }; | |
1555 | ||
3bc43840 GL |
1556 | static int pxa_camera_probe(struct platform_device *pdev) |
1557 | { | |
1558 | struct pxa_camera_dev *pcdev; | |
1559 | struct resource *res; | |
1560 | void __iomem *base; | |
02da4659 | 1561 | int irq; |
3bc43840 GL |
1562 | int err = 0; |
1563 | ||
1564 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1565 | irq = platform_get_irq(pdev, 0); | |
02da4659 | 1566 | if (!res || irq < 0) { |
3bc43840 GL |
1567 | err = -ENODEV; |
1568 | goto exit; | |
1569 | } | |
1570 | ||
1571 | pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL); | |
1572 | if (!pcdev) { | |
7102b773 | 1573 | dev_err(&pdev->dev, "Could not allocate pcdev\n"); |
3bc43840 GL |
1574 | err = -ENOMEM; |
1575 | goto exit; | |
1576 | } | |
1577 | ||
e0d8b13a | 1578 | pcdev->clk = clk_get(&pdev->dev, NULL); |
3bc43840 GL |
1579 | if (IS_ERR(pcdev->clk)) { |
1580 | err = PTR_ERR(pcdev->clk); | |
1581 | goto exit_kfree; | |
1582 | } | |
1583 | ||
eb6c8558 | 1584 | platform_set_drvdata(pdev, pcdev); |
3bc43840 GL |
1585 | pcdev->res = res; |
1586 | ||
1587 | pcdev->pdata = pdev->dev.platform_data; | |
1588 | pcdev->platform_flags = pcdev->pdata->flags; | |
ad5f2e85 GL |
1589 | if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 | |
1590 | PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) { | |
3bc43840 GL |
1591 | /* Platform hasn't set available data widths. This is bad. |
1592 | * Warn and use a default. */ | |
1593 | dev_warn(&pdev->dev, "WARNING! Platform hasn't set available " | |
1594 | "data widths, using default 10 bit\n"); | |
1595 | pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10; | |
1596 | } | |
cf34cba7 GL |
1597 | pcdev->mclk = pcdev->pdata->mclk_10khz * 10000; |
1598 | if (!pcdev->mclk) { | |
3bc43840 | 1599 | dev_warn(&pdev->dev, |
cf34cba7 | 1600 | "mclk == 0! Please, fix your platform data. " |
3bc43840 | 1601 | "Using default 20MHz\n"); |
cf34cba7 | 1602 | pcdev->mclk = 20000000; |
3bc43840 GL |
1603 | } |
1604 | ||
cf34cba7 GL |
1605 | pcdev->dev = &pdev->dev; |
1606 | pcdev->mclk_divisor = mclk_get_divisor(pcdev); | |
1607 | ||
3bc43840 GL |
1608 | INIT_LIST_HEAD(&pcdev->capture); |
1609 | spin_lock_init(&pcdev->lock); | |
1610 | ||
1611 | /* | |
1612 | * Request the regions. | |
1613 | */ | |
eb6c8558 | 1614 | if (!request_mem_region(res->start, resource_size(res), |
3bc43840 GL |
1615 | PXA_CAM_DRV_NAME)) { |
1616 | err = -EBUSY; | |
1617 | goto exit_clk; | |
1618 | } | |
1619 | ||
eb6c8558 | 1620 | base = ioremap(res->start, resource_size(res)); |
3bc43840 GL |
1621 | if (!base) { |
1622 | err = -ENOMEM; | |
1623 | goto exit_release; | |
1624 | } | |
1625 | pcdev->irq = irq; | |
1626 | pcdev->base = base; | |
3bc43840 GL |
1627 | |
1628 | /* request dma */ | |
de3e3b82 | 1629 | err = pxa_request_dma("CI_Y", DMA_PRIO_HIGH, |
1630 | pxa_camera_dma_irq_y, pcdev); | |
1631 | if (err < 0) { | |
3bc43840 | 1632 | dev_err(pcdev->dev, "Can't request DMA for Y\n"); |
3bc43840 GL |
1633 | goto exit_iounmap; |
1634 | } | |
de3e3b82 | 1635 | pcdev->dma_chans[0] = err; |
a5462e5b MR |
1636 | dev_dbg(pcdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]); |
1637 | ||
de3e3b82 | 1638 | err = pxa_request_dma("CI_U", DMA_PRIO_HIGH, |
1639 | pxa_camera_dma_irq_u, pcdev); | |
1640 | if (err < 0) { | |
a5462e5b | 1641 | dev_err(pcdev->dev, "Can't request DMA for U\n"); |
a5462e5b MR |
1642 | goto exit_free_dma_y; |
1643 | } | |
de3e3b82 | 1644 | pcdev->dma_chans[1] = err; |
a5462e5b MR |
1645 | dev_dbg(pcdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]); |
1646 | ||
de3e3b82 | 1647 | err = pxa_request_dma("CI_V", DMA_PRIO_HIGH, |
1648 | pxa_camera_dma_irq_v, pcdev); | |
1649 | if (err < 0) { | |
a5462e5b | 1650 | dev_err(pcdev->dev, "Can't request DMA for V\n"); |
a5462e5b MR |
1651 | goto exit_free_dma_u; |
1652 | } | |
de3e3b82 | 1653 | pcdev->dma_chans[2] = err; |
a5462e5b | 1654 | dev_dbg(pcdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]); |
3bc43840 | 1655 | |
87f3dd77 EM |
1656 | DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD; |
1657 | DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD; | |
1658 | DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD; | |
3bc43840 GL |
1659 | |
1660 | /* request irq */ | |
1661 | err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME, | |
1662 | pcdev); | |
1663 | if (err) { | |
1664 | dev_err(pcdev->dev, "Camera interrupt register failed \n"); | |
1665 | goto exit_free_dma; | |
1666 | } | |
1667 | ||
eb6c8558 GL |
1668 | pcdev->soc_host.drv_name = PXA_CAM_DRV_NAME; |
1669 | pcdev->soc_host.ops = &pxa_soc_camera_host_ops; | |
1670 | pcdev->soc_host.priv = pcdev; | |
1671 | pcdev->soc_host.dev.parent = &pdev->dev; | |
1672 | pcdev->soc_host.nr = pdev->id; | |
1673 | err = soc_camera_host_register(&pcdev->soc_host); | |
3bc43840 GL |
1674 | if (err) |
1675 | goto exit_free_irq; | |
1676 | ||
1677 | return 0; | |
1678 | ||
1679 | exit_free_irq: | |
1680 | free_irq(pcdev->irq, pcdev); | |
1681 | exit_free_dma: | |
a5462e5b MR |
1682 | pxa_free_dma(pcdev->dma_chans[2]); |
1683 | exit_free_dma_u: | |
1684 | pxa_free_dma(pcdev->dma_chans[1]); | |
1685 | exit_free_dma_y: | |
1686 | pxa_free_dma(pcdev->dma_chans[0]); | |
3bc43840 GL |
1687 | exit_iounmap: |
1688 | iounmap(base); | |
1689 | exit_release: | |
eb6c8558 | 1690 | release_mem_region(res->start, resource_size(res)); |
3bc43840 GL |
1691 | exit_clk: |
1692 | clk_put(pcdev->clk); | |
1693 | exit_kfree: | |
1694 | kfree(pcdev); | |
1695 | exit: | |
1696 | return err; | |
1697 | } | |
1698 | ||
1699 | static int __devexit pxa_camera_remove(struct platform_device *pdev) | |
1700 | { | |
1701 | struct pxa_camera_dev *pcdev = platform_get_drvdata(pdev); | |
1702 | struct resource *res; | |
1703 | ||
1704 | clk_put(pcdev->clk); | |
1705 | ||
a5462e5b MR |
1706 | pxa_free_dma(pcdev->dma_chans[0]); |
1707 | pxa_free_dma(pcdev->dma_chans[1]); | |
1708 | pxa_free_dma(pcdev->dma_chans[2]); | |
3bc43840 GL |
1709 | free_irq(pcdev->irq, pcdev); |
1710 | ||
eb6c8558 | 1711 | soc_camera_host_unregister(&pcdev->soc_host); |
3bc43840 GL |
1712 | |
1713 | iounmap(pcdev->base); | |
1714 | ||
1715 | res = pcdev->res; | |
eb6c8558 | 1716 | release_mem_region(res->start, resource_size(res)); |
3bc43840 GL |
1717 | |
1718 | kfree(pcdev); | |
1719 | ||
7102b773 | 1720 | dev_info(&pdev->dev, "PXA Camera driver unloaded\n"); |
3bc43840 | 1721 | |
3bc43840 GL |
1722 | return 0; |
1723 | } | |
1724 | ||
3bc43840 GL |
1725 | static struct platform_driver pxa_camera_driver = { |
1726 | .driver = { | |
1727 | .name = PXA_CAM_DRV_NAME, | |
1728 | }, | |
1729 | .probe = pxa_camera_probe, | |
1730 | .remove = __exit_p(pxa_camera_remove), | |
3bc43840 GL |
1731 | }; |
1732 | ||
1733 | ||
1734 | static int __devinit pxa_camera_init(void) | |
1735 | { | |
1736 | return platform_driver_register(&pxa_camera_driver); | |
1737 | } | |
1738 | ||
1739 | static void __exit pxa_camera_exit(void) | |
1740 | { | |
01c1e4ca | 1741 | platform_driver_unregister(&pxa_camera_driver); |
3bc43840 GL |
1742 | } |
1743 | ||
1744 | module_init(pxa_camera_init); | |
1745 | module_exit(pxa_camera_exit); | |
1746 | ||
1747 | MODULE_DESCRIPTION("PXA27x SoC Camera Host driver"); | |
1748 | MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>"); | |
1749 | MODULE_LICENSE("GPL"); |