Commit | Line | Data |
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5fd8f738 | 1 | /* |
97d97422 | 2 | * Samsung S5P/EXYNOS4 SoC series FIMC (CAMIF) driver |
5fd8f738 | 3 | * |
0c9204d3 SN |
4 | * Copyright (C) 2010-2012 Samsung Electronics Co., Ltd. |
5 | * Sylwester Nawrocki <s.nawrocki@samsung.com> | |
5fd8f738 SN |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published | |
9 | * by the Free Software Foundation, either version 2 of the License, | |
10 | * or (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/kernel.h> | |
5fd8f738 SN |
15 | #include <linux/types.h> |
16 | #include <linux/errno.h> | |
17 | #include <linux/bug.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/platform_device.h> | |
e9e21083 | 21 | #include <linux/pm_runtime.h> |
5fd8f738 SN |
22 | #include <linux/list.h> |
23 | #include <linux/io.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/clk.h> | |
26 | #include <media/v4l2-ioctl.h> | |
2dab38e2 SN |
27 | #include <media/videobuf2-core.h> |
28 | #include <media/videobuf2-dma-contig.h> | |
5fd8f738 SN |
29 | |
30 | #include "fimc-core.h" | |
c83a1ff0 | 31 | #include "fimc-reg.h" |
d3953223 | 32 | #include "fimc-mdevice.h" |
5fd8f738 | 33 | |
a25be18d | 34 | static char *fimc_clocks[MAX_FIMC_CLOCKS] = { |
ebdfea81 | 35 | "sclk_fimc", "fimc" |
a25be18d | 36 | }; |
5fd8f738 SN |
37 | |
38 | static struct fimc_fmt fimc_formats[] = { | |
39 | { | |
ef7af59b | 40 | .name = "RGB565", |
f83f71fd | 41 | .fourcc = V4L2_PIX_FMT_RGB565, |
ef7af59b | 42 | .depth = { 16 }, |
3d112d9a | 43 | .color = FIMC_FMT_RGB565, |
ef7af59b SN |
44 | .memplanes = 1, |
45 | .colplanes = 1, | |
ef7af59b | 46 | .flags = FMT_FLAGS_M2M, |
5fd8f738 | 47 | }, { |
ef7af59b SN |
48 | .name = "BGR666", |
49 | .fourcc = V4L2_PIX_FMT_BGR666, | |
50 | .depth = { 32 }, | |
3d112d9a | 51 | .color = FIMC_FMT_RGB666, |
ef7af59b SN |
52 | .memplanes = 1, |
53 | .colplanes = 1, | |
54 | .flags = FMT_FLAGS_M2M, | |
5fd8f738 | 55 | }, { |
dafb9c70 | 56 | .name = "ARGB8888, 32 bpp", |
ef7af59b SN |
57 | .fourcc = V4L2_PIX_FMT_RGB32, |
58 | .depth = { 32 }, | |
3d112d9a | 59 | .color = FIMC_FMT_RGB888, |
ef7af59b SN |
60 | .memplanes = 1, |
61 | .colplanes = 1, | |
dafb9c70 SN |
62 | .flags = FMT_FLAGS_M2M | FMT_HAS_ALPHA, |
63 | }, { | |
64 | .name = "ARGB1555", | |
65 | .fourcc = V4L2_PIX_FMT_RGB555, | |
66 | .depth = { 16 }, | |
3d112d9a | 67 | .color = FIMC_FMT_RGB555, |
dafb9c70 SN |
68 | .memplanes = 1, |
69 | .colplanes = 1, | |
70 | .flags = FMT_FLAGS_M2M_OUT | FMT_HAS_ALPHA, | |
71 | }, { | |
72 | .name = "ARGB4444", | |
73 | .fourcc = V4L2_PIX_FMT_RGB444, | |
74 | .depth = { 16 }, | |
3d112d9a | 75 | .color = FIMC_FMT_RGB444, |
dafb9c70 SN |
76 | .memplanes = 1, |
77 | .colplanes = 1, | |
78 | .flags = FMT_FLAGS_M2M_OUT | FMT_HAS_ALPHA, | |
5fd8f738 | 79 | }, { |
ef7af59b SN |
80 | .name = "YUV 4:2:2 packed, YCbYCr", |
81 | .fourcc = V4L2_PIX_FMT_YUYV, | |
82 | .depth = { 16 }, | |
3d112d9a | 83 | .color = FIMC_FMT_YCBYCR422, |
ef7af59b SN |
84 | .memplanes = 1, |
85 | .colplanes = 1, | |
86 | .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8, | |
87 | .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM, | |
5f3cc447 | 88 | }, { |
ef7af59b SN |
89 | .name = "YUV 4:2:2 packed, CbYCrY", |
90 | .fourcc = V4L2_PIX_FMT_UYVY, | |
91 | .depth = { 16 }, | |
3d112d9a | 92 | .color = FIMC_FMT_CBYCRY422, |
ef7af59b SN |
93 | .memplanes = 1, |
94 | .colplanes = 1, | |
95 | .mbus_code = V4L2_MBUS_FMT_UYVY8_2X8, | |
96 | .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM, | |
5fd8f738 | 97 | }, { |
ef7af59b SN |
98 | .name = "YUV 4:2:2 packed, CrYCbY", |
99 | .fourcc = V4L2_PIX_FMT_VYUY, | |
100 | .depth = { 16 }, | |
3d112d9a | 101 | .color = FIMC_FMT_CRYCBY422, |
ef7af59b SN |
102 | .memplanes = 1, |
103 | .colplanes = 1, | |
104 | .mbus_code = V4L2_MBUS_FMT_VYUY8_2X8, | |
105 | .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM, | |
5fd8f738 | 106 | }, { |
ef7af59b SN |
107 | .name = "YUV 4:2:2 packed, YCrYCb", |
108 | .fourcc = V4L2_PIX_FMT_YVYU, | |
109 | .depth = { 16 }, | |
3d112d9a | 110 | .color = FIMC_FMT_YCRYCB422, |
ef7af59b SN |
111 | .memplanes = 1, |
112 | .colplanes = 1, | |
113 | .mbus_code = V4L2_MBUS_FMT_YVYU8_2X8, | |
114 | .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM, | |
5fd8f738 | 115 | }, { |
ef7af59b SN |
116 | .name = "YUV 4:2:2 planar, Y/Cb/Cr", |
117 | .fourcc = V4L2_PIX_FMT_YUV422P, | |
118 | .depth = { 12 }, | |
3d112d9a | 119 | .color = FIMC_FMT_YCBYCR422, |
ef7af59b SN |
120 | .memplanes = 1, |
121 | .colplanes = 3, | |
122 | .flags = FMT_FLAGS_M2M, | |
5fd8f738 | 123 | }, { |
ef7af59b SN |
124 | .name = "YUV 4:2:2 planar, Y/CbCr", |
125 | .fourcc = V4L2_PIX_FMT_NV16, | |
126 | .depth = { 16 }, | |
3d112d9a | 127 | .color = FIMC_FMT_YCBYCR422, |
ef7af59b SN |
128 | .memplanes = 1, |
129 | .colplanes = 2, | |
130 | .flags = FMT_FLAGS_M2M, | |
5fd8f738 | 131 | }, { |
ef7af59b SN |
132 | .name = "YUV 4:2:2 planar, Y/CrCb", |
133 | .fourcc = V4L2_PIX_FMT_NV61, | |
134 | .depth = { 16 }, | |
3d112d9a | 135 | .color = FIMC_FMT_YCRYCB422, |
ef7af59b SN |
136 | .memplanes = 1, |
137 | .colplanes = 2, | |
138 | .flags = FMT_FLAGS_M2M, | |
5fd8f738 | 139 | }, { |
ef7af59b SN |
140 | .name = "YUV 4:2:0 planar, YCbCr", |
141 | .fourcc = V4L2_PIX_FMT_YUV420, | |
142 | .depth = { 12 }, | |
3d112d9a | 143 | .color = FIMC_FMT_YCBCR420, |
ef7af59b SN |
144 | .memplanes = 1, |
145 | .colplanes = 3, | |
146 | .flags = FMT_FLAGS_M2M, | |
5fd8f738 | 147 | }, { |
ef7af59b SN |
148 | .name = "YUV 4:2:0 planar, Y/CbCr", |
149 | .fourcc = V4L2_PIX_FMT_NV12, | |
150 | .depth = { 12 }, | |
3d112d9a | 151 | .color = FIMC_FMT_YCBCR420, |
ef7af59b SN |
152 | .memplanes = 1, |
153 | .colplanes = 2, | |
154 | .flags = FMT_FLAGS_M2M, | |
155 | }, { | |
156 | .name = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr", | |
157 | .fourcc = V4L2_PIX_FMT_NV12M, | |
3d112d9a | 158 | .color = FIMC_FMT_YCBCR420, |
ef7af59b SN |
159 | .depth = { 8, 4 }, |
160 | .memplanes = 2, | |
161 | .colplanes = 2, | |
162 | .flags = FMT_FLAGS_M2M, | |
163 | }, { | |
164 | .name = "YUV 4:2:0 non-contiguous 3-planar, Y/Cb/Cr", | |
165 | .fourcc = V4L2_PIX_FMT_YUV420M, | |
3d112d9a | 166 | .color = FIMC_FMT_YCBCR420, |
ef7af59b SN |
167 | .depth = { 8, 2, 2 }, |
168 | .memplanes = 3, | |
169 | .colplanes = 3, | |
170 | .flags = FMT_FLAGS_M2M, | |
171 | }, { | |
172 | .name = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr, tiled", | |
173 | .fourcc = V4L2_PIX_FMT_NV12MT, | |
3d112d9a | 174 | .color = FIMC_FMT_YCBCR420, |
ef7af59b SN |
175 | .depth = { 8, 4 }, |
176 | .memplanes = 2, | |
177 | .colplanes = 2, | |
178 | .flags = FMT_FLAGS_M2M, | |
ee7160e5 SN |
179 | }, { |
180 | .name = "JPEG encoded data", | |
181 | .fourcc = V4L2_PIX_FMT_JPEG, | |
3d112d9a | 182 | .color = FIMC_FMT_JPEG, |
ee7160e5 SN |
183 | .depth = { 8 }, |
184 | .memplanes = 1, | |
185 | .colplanes = 1, | |
186 | .mbus_code = V4L2_MBUS_FMT_JPEG_1X8, | |
187 | .flags = FMT_FLAGS_CAM, | |
5f3cc447 | 188 | }, |
548aafcd | 189 | }; |
5fd8f738 | 190 | |
bb7c276e | 191 | struct fimc_fmt *fimc_get_format(unsigned int index) |
dafb9c70 | 192 | { |
97d97422 SN |
193 | if (index >= ARRAY_SIZE(fimc_formats)) |
194 | return NULL; | |
195 | ||
196 | return &fimc_formats[index]; | |
dafb9c70 SN |
197 | } |
198 | ||
ee7160e5 SN |
199 | int fimc_check_scaler_ratio(struct fimc_ctx *ctx, int sw, int sh, |
200 | int dw, int dh, int rotation) | |
5fd8f738 | 201 | { |
ee7160e5 SN |
202 | if (rotation == 90 || rotation == 270) |
203 | swap(dw, dh); | |
5fd8f738 | 204 | |
ee7160e5 SN |
205 | if (!ctx->scaler.enabled) |
206 | return (sw == dw && sh == dh) ? 0 : -EINVAL; | |
5fd8f738 | 207 | |
ee7160e5 | 208 | if ((sw >= SCALER_MAX_HRATIO * dw) || (sh >= SCALER_MAX_VRATIO * dh)) |
1b09f292 HK |
209 | return -EINVAL; |
210 | ||
5fd8f738 SN |
211 | return 0; |
212 | } | |
213 | ||
214 | static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift) | |
215 | { | |
548aafcd SN |
216 | u32 sh = 6; |
217 | ||
218 | if (src >= 64 * tar) | |
5fd8f738 | 219 | return -EINVAL; |
548aafcd SN |
220 | |
221 | while (sh--) { | |
222 | u32 tmp = 1 << sh; | |
223 | if (src >= tar * tmp) { | |
224 | *shift = sh, *ratio = tmp; | |
225 | return 0; | |
226 | } | |
5fd8f738 | 227 | } |
548aafcd | 228 | *shift = 0, *ratio = 1; |
5fd8f738 SN |
229 | return 0; |
230 | } | |
231 | ||
5f3cc447 | 232 | int fimc_set_scaler_info(struct fimc_ctx *ctx) |
5fd8f738 | 233 | { |
bb7c276e | 234 | struct fimc_variant *variant = ctx->fimc_dev->variant; |
30c9939d | 235 | struct device *dev = &ctx->fimc_dev->pdev->dev; |
5fd8f738 SN |
236 | struct fimc_scaler *sc = &ctx->scaler; |
237 | struct fimc_frame *s_frame = &ctx->s_frame; | |
238 | struct fimc_frame *d_frame = &ctx->d_frame; | |
239 | int tx, ty, sx, sy; | |
240 | int ret; | |
241 | ||
47654df8 SN |
242 | if (ctx->rotation == 90 || ctx->rotation == 270) { |
243 | ty = d_frame->width; | |
244 | tx = d_frame->height; | |
245 | } else { | |
246 | tx = d_frame->width; | |
247 | ty = d_frame->height; | |
248 | } | |
5fd8f738 | 249 | if (tx <= 0 || ty <= 0) { |
30c9939d | 250 | dev_err(dev, "Invalid target size: %dx%d", tx, ty); |
5fd8f738 SN |
251 | return -EINVAL; |
252 | } | |
253 | ||
254 | sx = s_frame->width; | |
255 | sy = s_frame->height; | |
256 | if (sx <= 0 || sy <= 0) { | |
30c9939d | 257 | dev_err(dev, "Invalid source size: %dx%d", sx, sy); |
5fd8f738 SN |
258 | return -EINVAL; |
259 | } | |
5fd8f738 SN |
260 | sc->real_width = sx; |
261 | sc->real_height = sy; | |
5fd8f738 SN |
262 | |
263 | ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor); | |
264 | if (ret) | |
265 | return ret; | |
266 | ||
267 | ret = fimc_get_scaler_factor(sy, ty, &sc->pre_vratio, &sc->vfactor); | |
268 | if (ret) | |
269 | return ret; | |
270 | ||
271 | sc->pre_dst_width = sx / sc->pre_hratio; | |
272 | sc->pre_dst_height = sy / sc->pre_vratio; | |
273 | ||
b241c6d6 HK |
274 | if (variant->has_mainscaler_ext) { |
275 | sc->main_hratio = (sx << 14) / (tx << sc->hfactor); | |
276 | sc->main_vratio = (sy << 14) / (ty << sc->vfactor); | |
277 | } else { | |
278 | sc->main_hratio = (sx << 8) / (tx << sc->hfactor); | |
279 | sc->main_vratio = (sy << 8) / (ty << sc->vfactor); | |
280 | ||
281 | } | |
5fd8f738 SN |
282 | |
283 | sc->scaleup_h = (tx >= sx) ? 1 : 0; | |
284 | sc->scaleup_v = (ty >= sy) ? 1 : 0; | |
285 | ||
286 | /* check to see if input and output size/format differ */ | |
287 | if (s_frame->fmt->color == d_frame->fmt->color | |
288 | && s_frame->width == d_frame->width | |
289 | && s_frame->height == d_frame->height) | |
290 | sc->copy_mode = 1; | |
291 | else | |
292 | sc->copy_mode = 0; | |
293 | ||
294 | return 0; | |
295 | } | |
296 | ||
e9e21083 | 297 | static irqreturn_t fimc_irq_handler(int irq, void *priv) |
5fd8f738 | 298 | { |
548aafcd | 299 | struct fimc_dev *fimc = priv; |
4ecbf5d1 | 300 | struct fimc_ctx *ctx; |
5fd8f738 | 301 | |
5fd8f738 SN |
302 | fimc_hw_clear_irq(fimc); |
303 | ||
e9e21083 SN |
304 | spin_lock(&fimc->slock); |
305 | ||
4ecbf5d1 | 306 | if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) { |
e9e21083 SN |
307 | if (test_and_clear_bit(ST_M2M_SUSPENDING, &fimc->state)) { |
308 | set_bit(ST_M2M_SUSPENDED, &fimc->state); | |
309 | wake_up(&fimc->irq_queue); | |
310 | goto out; | |
311 | } | |
4ecbf5d1 SN |
312 | ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev); |
313 | if (ctx != NULL) { | |
e9e21083 | 314 | spin_unlock(&fimc->slock); |
4ecbf5d1 | 315 | fimc_m2m_job_finish(ctx, VB2_BUF_STATE_DONE); |
5fd8f738 | 316 | |
4ecbf5d1 SN |
317 | if (ctx->state & FIMC_CTX_SHUT) { |
318 | ctx->state &= ~FIMC_CTX_SHUT; | |
319 | wake_up(&fimc->irq_queue); | |
320 | } | |
efb13c3d | 321 | return IRQ_HANDLED; |
5fd8f738 | 322 | } |
ee7160e5 | 323 | } else if (test_bit(ST_CAPT_PEND, &fimc->state)) { |
97d97422 SN |
324 | int last_buf = test_bit(ST_CAPT_JPEG, &fimc->state) && |
325 | fimc->vid_cap.reqbufs_count == 1; | |
326 | fimc_capture_irq_handler(fimc, !last_buf); | |
5fd8f738 | 327 | } |
e9e21083 | 328 | out: |
5fd8f738 SN |
329 | spin_unlock(&fimc->slock); |
330 | return IRQ_HANDLED; | |
331 | } | |
332 | ||
ef7af59b | 333 | /* The color format (colplanes, memplanes) must be already configured. */ |
2dab38e2 | 334 | int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb, |
548aafcd | 335 | struct fimc_frame *frame, struct fimc_addr *paddr) |
5fd8f738 | 336 | { |
5fd8f738 | 337 | int ret = 0; |
548aafcd | 338 | u32 pix_size; |
5fd8f738 | 339 | |
2dab38e2 | 340 | if (vb == NULL || frame == NULL) |
5fd8f738 SN |
341 | return -EINVAL; |
342 | ||
343 | pix_size = frame->width * frame->height; | |
344 | ||
ef7af59b SN |
345 | dbg("memplanes= %d, colplanes= %d, pix_size= %d", |
346 | frame->fmt->memplanes, frame->fmt->colplanes, pix_size); | |
347 | ||
ba7fcb0c | 348 | paddr->y = vb2_dma_contig_plane_dma_addr(vb, 0); |
5fd8f738 | 349 | |
ef7af59b SN |
350 | if (frame->fmt->memplanes == 1) { |
351 | switch (frame->fmt->colplanes) { | |
5fd8f738 SN |
352 | case 1: |
353 | paddr->cb = 0; | |
354 | paddr->cr = 0; | |
355 | break; | |
356 | case 2: | |
357 | /* decompose Y into Y/Cb */ | |
358 | paddr->cb = (u32)(paddr->y + pix_size); | |
359 | paddr->cr = 0; | |
360 | break; | |
361 | case 3: | |
362 | paddr->cb = (u32)(paddr->y + pix_size); | |
363 | /* decompose Y into Y/Cb/Cr */ | |
3d112d9a | 364 | if (FIMC_FMT_YCBCR420 == frame->fmt->color) |
5fd8f738 SN |
365 | paddr->cr = (u32)(paddr->cb |
366 | + (pix_size >> 2)); | |
367 | else /* 422 */ | |
368 | paddr->cr = (u32)(paddr->cb | |
369 | + (pix_size >> 1)); | |
370 | break; | |
371 | default: | |
372 | return -EINVAL; | |
373 | } | |
ef7af59b SN |
374 | } else { |
375 | if (frame->fmt->memplanes >= 2) | |
ba7fcb0c | 376 | paddr->cb = vb2_dma_contig_plane_dma_addr(vb, 1); |
ef7af59b SN |
377 | |
378 | if (frame->fmt->memplanes == 3) | |
ba7fcb0c | 379 | paddr->cr = vb2_dma_contig_plane_dma_addr(vb, 2); |
5fd8f738 SN |
380 | } |
381 | ||
548aafcd SN |
382 | dbg("PHYS_ADDR: y= 0x%X cb= 0x%X cr= 0x%X ret= %d", |
383 | paddr->y, paddr->cb, paddr->cr, ret); | |
5fd8f738 SN |
384 | |
385 | return ret; | |
386 | } | |
387 | ||
388 | /* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */ | |
9e803a04 | 389 | void fimc_set_yuv_order(struct fimc_ctx *ctx) |
5fd8f738 SN |
390 | { |
391 | /* The one only mode supported in SoC. */ | |
c83a1ff0 SN |
392 | ctx->in_order_2p = FIMC_REG_CIOCTRL_ORDER422_2P_LSB_CRCB; |
393 | ctx->out_order_2p = FIMC_REG_CIOCTRL_ORDER422_2P_LSB_CRCB; | |
5fd8f738 SN |
394 | |
395 | /* Set order for 1 plane input formats. */ | |
396 | switch (ctx->s_frame.fmt->color) { | |
3d112d9a | 397 | case FIMC_FMT_YCRYCB422: |
c83a1ff0 | 398 | ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_CBYCRY; |
5fd8f738 | 399 | break; |
3d112d9a | 400 | case FIMC_FMT_CBYCRY422: |
c83a1ff0 | 401 | ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_YCRYCB; |
5fd8f738 | 402 | break; |
3d112d9a | 403 | case FIMC_FMT_CRYCBY422: |
c83a1ff0 | 404 | ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_YCBYCR; |
5fd8f738 | 405 | break; |
3d112d9a | 406 | case FIMC_FMT_YCBYCR422: |
5fd8f738 | 407 | default: |
c83a1ff0 | 408 | ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_CRYCBY; |
5fd8f738 SN |
409 | break; |
410 | } | |
411 | dbg("ctx->in_order_1p= %d", ctx->in_order_1p); | |
412 | ||
413 | switch (ctx->d_frame.fmt->color) { | |
3d112d9a | 414 | case FIMC_FMT_YCRYCB422: |
c83a1ff0 | 415 | ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_CBYCRY; |
5fd8f738 | 416 | break; |
3d112d9a | 417 | case FIMC_FMT_CBYCRY422: |
c83a1ff0 | 418 | ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_YCRYCB; |
5fd8f738 | 419 | break; |
3d112d9a | 420 | case FIMC_FMT_CRYCBY422: |
c83a1ff0 | 421 | ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_YCBYCR; |
5fd8f738 | 422 | break; |
3d112d9a | 423 | case FIMC_FMT_YCBYCR422: |
5fd8f738 | 424 | default: |
c83a1ff0 | 425 | ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_CRYCBY; |
5fd8f738 SN |
426 | break; |
427 | } | |
428 | dbg("ctx->out_order_1p= %d", ctx->out_order_1p); | |
429 | } | |
430 | ||
9e803a04 | 431 | void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f) |
ddc79e0f | 432 | { |
bb7c276e | 433 | struct fimc_variant *variant = ctx->fimc_dev->variant; |
ef7af59b SN |
434 | u32 i, depth = 0; |
435 | ||
436 | for (i = 0; i < f->fmt->colplanes; i++) | |
437 | depth += f->fmt->depth[i]; | |
ddc79e0f SN |
438 | |
439 | f->dma_offset.y_h = f->offs_h; | |
440 | if (!variant->pix_hoff) | |
ef7af59b | 441 | f->dma_offset.y_h *= (depth >> 3); |
ddc79e0f SN |
442 | |
443 | f->dma_offset.y_v = f->offs_v; | |
444 | ||
445 | f->dma_offset.cb_h = f->offs_h; | |
446 | f->dma_offset.cb_v = f->offs_v; | |
447 | ||
448 | f->dma_offset.cr_h = f->offs_h; | |
449 | f->dma_offset.cr_v = f->offs_v; | |
450 | ||
451 | if (!variant->pix_hoff) { | |
ef7af59b | 452 | if (f->fmt->colplanes == 3) { |
ddc79e0f SN |
453 | f->dma_offset.cb_h >>= 1; |
454 | f->dma_offset.cr_h >>= 1; | |
455 | } | |
3d112d9a | 456 | if (f->fmt->color == FIMC_FMT_YCBCR420) { |
ddc79e0f SN |
457 | f->dma_offset.cb_v >>= 1; |
458 | f->dma_offset.cr_v >>= 1; | |
459 | } | |
460 | } | |
461 | ||
462 | dbg("in_offset: color= %d, y_h= %d, y_v= %d", | |
463 | f->fmt->color, f->dma_offset.y_h, f->dma_offset.y_v); | |
464 | } | |
465 | ||
9448ab7d SN |
466 | int fimc_set_color_effect(struct fimc_ctx *ctx, enum v4l2_colorfx colorfx) |
467 | { | |
468 | struct fimc_effect *effect = &ctx->effect; | |
469 | ||
470 | switch (colorfx) { | |
471 | case V4L2_COLORFX_NONE: | |
472 | effect->type = FIMC_REG_CIIMGEFF_FIN_BYPASS; | |
473 | break; | |
474 | case V4L2_COLORFX_BW: | |
475 | effect->type = FIMC_REG_CIIMGEFF_FIN_ARBITRARY; | |
476 | effect->pat_cb = 128; | |
477 | effect->pat_cr = 128; | |
478 | break; | |
479 | case V4L2_COLORFX_SEPIA: | |
480 | effect->type = FIMC_REG_CIIMGEFF_FIN_ARBITRARY; | |
481 | effect->pat_cb = 115; | |
482 | effect->pat_cr = 145; | |
483 | break; | |
484 | case V4L2_COLORFX_NEGATIVE: | |
485 | effect->type = FIMC_REG_CIIMGEFF_FIN_NEGATIVE; | |
486 | break; | |
487 | case V4L2_COLORFX_EMBOSS: | |
488 | effect->type = FIMC_REG_CIIMGEFF_FIN_EMBOSSING; | |
489 | break; | |
490 | case V4L2_COLORFX_ART_FREEZE: | |
491 | effect->type = FIMC_REG_CIIMGEFF_FIN_ARTFREEZE; | |
492 | break; | |
493 | case V4L2_COLORFX_SILHOUETTE: | |
494 | effect->type = FIMC_REG_CIIMGEFF_FIN_SILHOUETTE; | |
495 | break; | |
496 | case V4L2_COLORFX_SET_CBCR: | |
497 | effect->type = FIMC_REG_CIIMGEFF_FIN_ARBITRARY; | |
498 | effect->pat_cb = ctx->ctrls.colorfx_cbcr->val >> 8; | |
499 | effect->pat_cr = ctx->ctrls.colorfx_cbcr->val & 0xff; | |
500 | break; | |
501 | default: | |
502 | return -EINVAL; | |
503 | } | |
504 | ||
505 | return 0; | |
506 | } | |
507 | ||
131b6c61 SN |
508 | /* |
509 | * V4L2 controls handling | |
510 | */ | |
511 | #define ctrl_to_ctx(__ctrl) \ | |
9448ab7d | 512 | container_of((__ctrl)->handler, struct fimc_ctx, ctrls.handler) |
131b6c61 | 513 | |
dafb9c70 | 514 | static int __fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_ctrl *ctrl) |
131b6c61 | 515 | { |
131b6c61 | 516 | struct fimc_dev *fimc = ctx->fimc_dev; |
bb7c276e | 517 | struct fimc_variant *variant = fimc->variant; |
dafb9c70 | 518 | unsigned int flags = FIMC_DST_FMT | FIMC_SRC_FMT; |
131b6c61 SN |
519 | int ret = 0; |
520 | ||
521 | if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE) | |
522 | return 0; | |
523 | ||
524 | switch (ctrl->id) { | |
525 | case V4L2_CID_HFLIP: | |
131b6c61 SN |
526 | ctx->hflip = ctrl->val; |
527 | break; | |
528 | ||
529 | case V4L2_CID_VFLIP: | |
131b6c61 SN |
530 | ctx->vflip = ctrl->val; |
531 | break; | |
532 | ||
533 | case V4L2_CID_ROTATE: | |
534 | if (fimc_capture_pending(fimc) || | |
dafb9c70 | 535 | (ctx->state & flags) == flags) { |
ee7160e5 | 536 | ret = fimc_check_scaler_ratio(ctx, ctx->s_frame.width, |
131b6c61 SN |
537 | ctx->s_frame.height, ctx->d_frame.width, |
538 | ctx->d_frame.height, ctrl->val); | |
dafb9c70 SN |
539 | if (ret) |
540 | return -EINVAL; | |
131b6c61 SN |
541 | } |
542 | if ((ctrl->val == 90 || ctrl->val == 270) && | |
543 | !variant->has_out_rot) | |
544 | return -EINVAL; | |
dafb9c70 | 545 | |
131b6c61 SN |
546 | ctx->rotation = ctrl->val; |
547 | break; | |
548 | ||
dafb9c70 SN |
549 | case V4L2_CID_ALPHA_COMPONENT: |
550 | ctx->d_frame.alpha = ctrl->val; | |
551 | break; | |
9448ab7d SN |
552 | |
553 | case V4L2_CID_COLORFX: | |
554 | ret = fimc_set_color_effect(ctx, ctrl->val); | |
555 | if (ret) | |
556 | return ret; | |
557 | break; | |
131b6c61 | 558 | } |
9448ab7d | 559 | |
131b6c61 SN |
560 | ctx->state |= FIMC_PARAMS; |
561 | set_bit(ST_CAPT_APPLY_CFG, &fimc->state); | |
131b6c61 SN |
562 | return 0; |
563 | } | |
564 | ||
dafb9c70 SN |
565 | static int fimc_s_ctrl(struct v4l2_ctrl *ctrl) |
566 | { | |
567 | struct fimc_ctx *ctx = ctrl_to_ctx(ctrl); | |
568 | unsigned long flags; | |
569 | int ret; | |
570 | ||
efb13c3d | 571 | spin_lock_irqsave(&ctx->fimc_dev->slock, flags); |
dafb9c70 | 572 | ret = __fimc_s_ctrl(ctx, ctrl); |
efb13c3d | 573 | spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags); |
dafb9c70 SN |
574 | |
575 | return ret; | |
576 | } | |
577 | ||
131b6c61 SN |
578 | static const struct v4l2_ctrl_ops fimc_ctrl_ops = { |
579 | .s_ctrl = fimc_s_ctrl, | |
580 | }; | |
581 | ||
582 | int fimc_ctrls_create(struct fimc_ctx *ctx) | |
583 | { | |
bb7c276e | 584 | struct fimc_variant *variant = ctx->fimc_dev->variant; |
dafb9c70 | 585 | unsigned int max_alpha = fimc_get_alpha_mask(ctx->d_frame.fmt); |
9448ab7d SN |
586 | struct fimc_ctrls *ctrls = &ctx->ctrls; |
587 | struct v4l2_ctrl_handler *handler = &ctrls->handler; | |
dafb9c70 | 588 | |
9448ab7d | 589 | if (ctx->ctrls.ready) |
131b6c61 | 590 | return 0; |
131b6c61 | 591 | |
9448ab7d SN |
592 | v4l2_ctrl_handler_init(handler, 6); |
593 | ||
594 | ctrls->rotate = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops, | |
53e5ab94 | 595 | V4L2_CID_ROTATE, 0, 270, 90, 0); |
9448ab7d | 596 | ctrls->hflip = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops, |
53e5ab94 | 597 | V4L2_CID_HFLIP, 0, 1, 1, 0); |
9448ab7d | 598 | ctrls->vflip = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops, |
53e5ab94 | 599 | V4L2_CID_VFLIP, 0, 1, 1, 0); |
9448ab7d | 600 | |
dafb9c70 | 601 | if (variant->has_alpha) |
9448ab7d SN |
602 | ctrls->alpha = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops, |
603 | V4L2_CID_ALPHA_COMPONENT, | |
604 | 0, max_alpha, 1, 0); | |
dafb9c70 | 605 | else |
9448ab7d SN |
606 | ctrls->alpha = NULL; |
607 | ||
608 | ctrls->colorfx = v4l2_ctrl_new_std_menu(handler, &fimc_ctrl_ops, | |
609 | V4L2_CID_COLORFX, V4L2_COLORFX_SET_CBCR, | |
610 | ~0x983f, V4L2_COLORFX_NONE); | |
611 | ||
612 | ctrls->colorfx_cbcr = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops, | |
613 | V4L2_CID_COLORFX_CBCR, 0, 0xffff, 1, 0); | |
dafb9c70 | 614 | |
9448ab7d | 615 | ctx->effect.type = FIMC_REG_CIIMGEFF_FIN_BYPASS; |
131b6c61 | 616 | |
9448ab7d SN |
617 | if (!handler->error) { |
618 | v4l2_ctrl_cluster(3, &ctrls->colorfx); | |
619 | ctrls->ready = true; | |
620 | } | |
621 | ||
622 | return handler->error; | |
131b6c61 SN |
623 | } |
624 | ||
625 | void fimc_ctrls_delete(struct fimc_ctx *ctx) | |
626 | { | |
9448ab7d SN |
627 | struct fimc_ctrls *ctrls = &ctx->ctrls; |
628 | ||
629 | if (ctrls->ready) { | |
630 | v4l2_ctrl_handler_free(&ctrls->handler); | |
631 | ctrls->ready = false; | |
632 | ctrls->alpha = NULL; | |
131b6c61 SN |
633 | } |
634 | } | |
635 | ||
636 | void fimc_ctrls_activate(struct fimc_ctx *ctx, bool active) | |
637 | { | |
dafb9c70 | 638 | unsigned int has_alpha = ctx->d_frame.fmt->flags & FMT_HAS_ALPHA; |
9448ab7d | 639 | struct fimc_ctrls *ctrls = &ctx->ctrls; |
dafb9c70 | 640 | |
9448ab7d | 641 | if (!ctrls->ready) |
131b6c61 SN |
642 | return; |
643 | ||
9448ab7d SN |
644 | mutex_lock(&ctrls->handler.lock); |
645 | v4l2_ctrl_activate(ctrls->rotate, active); | |
646 | v4l2_ctrl_activate(ctrls->hflip, active); | |
647 | v4l2_ctrl_activate(ctrls->vflip, active); | |
648 | v4l2_ctrl_activate(ctrls->colorfx, active); | |
649 | if (ctrls->alpha) | |
650 | v4l2_ctrl_activate(ctrls->alpha, active && has_alpha); | |
131b6c61 SN |
651 | |
652 | if (active) { | |
9448ab7d SN |
653 | fimc_set_color_effect(ctx, ctrls->colorfx->cur.val); |
654 | ctx->rotation = ctrls->rotate->val; | |
655 | ctx->hflip = ctrls->hflip->val; | |
656 | ctx->vflip = ctrls->vflip->val; | |
131b6c61 | 657 | } else { |
9448ab7d | 658 | ctx->effect.type = FIMC_REG_CIIMGEFF_FIN_BYPASS; |
131b6c61 SN |
659 | ctx->rotation = 0; |
660 | ctx->hflip = 0; | |
661 | ctx->vflip = 0; | |
662 | } | |
9448ab7d | 663 | mutex_unlock(&ctrls->handler.lock); |
131b6c61 SN |
664 | } |
665 | ||
dafb9c70 SN |
666 | /* Update maximum value of the alpha color control */ |
667 | void fimc_alpha_ctrl_update(struct fimc_ctx *ctx) | |
668 | { | |
669 | struct fimc_dev *fimc = ctx->fimc_dev; | |
9448ab7d | 670 | struct v4l2_ctrl *ctrl = ctx->ctrls.alpha; |
dafb9c70 SN |
671 | |
672 | if (ctrl == NULL || !fimc->variant->has_alpha) | |
673 | return; | |
674 | ||
675 | v4l2_ctrl_lock(ctrl); | |
676 | ctrl->maximum = fimc_get_alpha_mask(ctx->d_frame.fmt); | |
677 | ||
678 | if (ctrl->cur.val > ctrl->maximum) | |
679 | ctrl->cur.val = ctrl->maximum; | |
680 | ||
681 | v4l2_ctrl_unlock(ctrl); | |
682 | } | |
683 | ||
e578588e | 684 | int fimc_fill_format(struct fimc_frame *frame, struct v4l2_format *f) |
5fd8f738 | 685 | { |
e578588e | 686 | struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp; |
91707b8b | 687 | int i; |
5fd8f738 | 688 | |
e578588e SN |
689 | pixm->width = frame->o_width; |
690 | pixm->height = frame->o_height; | |
691 | pixm->field = V4L2_FIELD_NONE; | |
692 | pixm->pixelformat = frame->fmt->fourcc; | |
693 | pixm->colorspace = V4L2_COLORSPACE_JPEG; | |
694 | pixm->num_planes = frame->fmt->memplanes; | |
91707b8b SN |
695 | |
696 | for (i = 0; i < pixm->num_planes; ++i) { | |
e578588e | 697 | int bpl = frame->f_width; |
91707b8b SN |
698 | if (frame->fmt->colplanes == 1) /* packed formats */ |
699 | bpl = (bpl * frame->fmt->depth[0]) / 8; | |
91707b8b | 700 | pixm->plane_fmt[i].bytesperline = bpl; |
91707b8b SN |
701 | pixm->plane_fmt[i].sizeimage = (frame->o_width * |
702 | frame->o_height * frame->fmt->depth[i]) / 8; | |
703 | } | |
5fd8f738 SN |
704 | return 0; |
705 | } | |
706 | ||
4db5e27e SN |
707 | void fimc_fill_frame(struct fimc_frame *frame, struct v4l2_format *f) |
708 | { | |
709 | struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp; | |
710 | ||
711 | frame->f_width = pixm->plane_fmt[0].bytesperline; | |
712 | if (frame->fmt->colplanes == 1) | |
713 | frame->f_width = (frame->f_width * 8) / frame->fmt->depth[0]; | |
714 | frame->f_height = pixm->height; | |
715 | frame->width = pixm->width; | |
716 | frame->height = pixm->height; | |
717 | frame->o_width = pixm->width; | |
718 | frame->o_height = pixm->height; | |
719 | frame->offs_h = 0; | |
720 | frame->offs_v = 0; | |
721 | } | |
722 | ||
723 | /** | |
724 | * fimc_adjust_mplane_format - adjust bytesperline/sizeimage for each plane | |
725 | * @fmt: fimc pixel format description (input) | |
726 | * @width: requested pixel width | |
727 | * @height: requested pixel height | |
728 | * @pix: multi-plane format to adjust | |
729 | */ | |
730 | void fimc_adjust_mplane_format(struct fimc_fmt *fmt, u32 width, u32 height, | |
731 | struct v4l2_pix_format_mplane *pix) | |
732 | { | |
733 | u32 bytesperline = 0; | |
734 | int i; | |
735 | ||
736 | pix->colorspace = V4L2_COLORSPACE_JPEG; | |
737 | pix->field = V4L2_FIELD_NONE; | |
738 | pix->num_planes = fmt->memplanes; | |
dafb9c70 | 739 | pix->pixelformat = fmt->fourcc; |
4db5e27e SN |
740 | pix->height = height; |
741 | pix->width = width; | |
742 | ||
743 | for (i = 0; i < pix->num_planes; ++i) { | |
744 | u32 bpl = pix->plane_fmt[i].bytesperline; | |
745 | u32 *sizeimage = &pix->plane_fmt[i].sizeimage; | |
746 | ||
747 | if (fmt->colplanes > 1 && (bpl == 0 || bpl < pix->width)) | |
748 | bpl = pix->width; /* Planar */ | |
749 | ||
750 | if (fmt->colplanes == 1 && /* Packed */ | |
751 | (bpl == 0 || ((bpl * 8) / fmt->depth[i]) < pix->width)) | |
752 | bpl = (pix->width * fmt->depth[0]) / 8; | |
753 | ||
754 | if (i == 0) /* Same bytesperline for each plane. */ | |
755 | bytesperline = bpl; | |
756 | ||
757 | pix->plane_fmt[i].bytesperline = bytesperline; | |
758 | *sizeimage = (pix->width * pix->height * fmt->depth[i]) / 8; | |
759 | } | |
760 | } | |
761 | ||
cf52df8a SN |
762 | /** |
763 | * fimc_find_format - lookup fimc color format by fourcc or media bus format | |
764 | * @pixelformat: fourcc to match, ignored if null | |
765 | * @mbus_code: media bus code to match, ignored if null | |
766 | * @mask: the color flags to match | |
767 | * @index: offset in the fimc_formats array, ignored if negative | |
768 | */ | |
63746be5 | 769 | struct fimc_fmt *fimc_find_format(const u32 *pixelformat, const u32 *mbus_code, |
cf52df8a | 770 | unsigned int mask, int index) |
5fd8f738 | 771 | { |
cf52df8a | 772 | struct fimc_fmt *fmt, *def_fmt = NULL; |
5fd8f738 | 773 | unsigned int i; |
cf52df8a | 774 | int id = 0; |
5fd8f738 | 775 | |
63746be5 | 776 | if (index >= (int)ARRAY_SIZE(fimc_formats)) |
cf52df8a | 777 | return NULL; |
5f3cc447 SN |
778 | |
779 | for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) { | |
780 | fmt = &fimc_formats[i]; | |
cf52df8a SN |
781 | if (!(fmt->flags & mask)) |
782 | continue; | |
783 | if (pixelformat && fmt->fourcc == *pixelformat) | |
784 | return fmt; | |
785 | if (mbus_code && fmt->mbus_code == *mbus_code) | |
786 | return fmt; | |
787 | if (index == id) | |
788 | def_fmt = fmt; | |
789 | id++; | |
5f3cc447 | 790 | } |
cf52df8a | 791 | return def_fmt; |
5f3cc447 SN |
792 | } |
793 | ||
e9e21083 | 794 | static void fimc_clk_put(struct fimc_dev *fimc) |
5fd8f738 SN |
795 | { |
796 | int i; | |
6ec0163b | 797 | for (i = 0; i < MAX_FIMC_CLOCKS; i++) { |
bd7d8888 SN |
798 | if (IS_ERR_OR_NULL(fimc->clock[i])) |
799 | continue; | |
800 | clk_unprepare(fimc->clock[i]); | |
801 | clk_put(fimc->clock[i]); | |
802 | fimc->clock[i] = NULL; | |
5fd8f738 SN |
803 | } |
804 | } | |
805 | ||
806 | static int fimc_clk_get(struct fimc_dev *fimc) | |
807 | { | |
bd7d8888 SN |
808 | int i, ret; |
809 | ||
6ec0163b | 810 | for (i = 0; i < MAX_FIMC_CLOCKS; i++) { |
a25be18d | 811 | fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clocks[i]); |
bd7d8888 SN |
812 | if (IS_ERR(fimc->clock[i])) |
813 | goto err; | |
814 | ret = clk_prepare(fimc->clock[i]); | |
815 | if (ret < 0) { | |
816 | clk_put(fimc->clock[i]); | |
817 | fimc->clock[i] = NULL; | |
818 | goto err; | |
819 | } | |
5fd8f738 | 820 | } |
e9e21083 | 821 | return 0; |
bd7d8888 SN |
822 | err: |
823 | fimc_clk_put(fimc); | |
824 | dev_err(&fimc->pdev->dev, "failed to get clock: %s\n", | |
825 | fimc_clocks[i]); | |
826 | return -ENXIO; | |
e9e21083 SN |
827 | } |
828 | ||
829 | static int fimc_m2m_suspend(struct fimc_dev *fimc) | |
830 | { | |
831 | unsigned long flags; | |
832 | int timeout; | |
833 | ||
834 | spin_lock_irqsave(&fimc->slock, flags); | |
835 | if (!fimc_m2m_pending(fimc)) { | |
836 | spin_unlock_irqrestore(&fimc->slock, flags); | |
837 | return 0; | |
838 | } | |
839 | clear_bit(ST_M2M_SUSPENDED, &fimc->state); | |
840 | set_bit(ST_M2M_SUSPENDING, &fimc->state); | |
841 | spin_unlock_irqrestore(&fimc->slock, flags); | |
842 | ||
843 | timeout = wait_event_timeout(fimc->irq_queue, | |
844 | test_bit(ST_M2M_SUSPENDED, &fimc->state), | |
845 | FIMC_SHUTDOWN_TIMEOUT); | |
846 | ||
847 | clear_bit(ST_M2M_SUSPENDING, &fimc->state); | |
848 | return timeout == 0 ? -EAGAIN : 0; | |
849 | } | |
850 | ||
851 | static int fimc_m2m_resume(struct fimc_dev *fimc) | |
852 | { | |
853 | unsigned long flags; | |
854 | ||
855 | spin_lock_irqsave(&fimc->slock, flags); | |
856 | /* Clear for full H/W setup in first run after resume */ | |
857 | fimc->m2m.ctx = NULL; | |
858 | spin_unlock_irqrestore(&fimc->slock, flags); | |
859 | ||
860 | if (test_and_clear_bit(ST_M2M_SUSPENDED, &fimc->state)) | |
861 | fimc_m2m_job_finish(fimc->m2m.ctx, | |
862 | VB2_BUF_STATE_ERROR); | |
5fd8f738 SN |
863 | return 0; |
864 | } | |
865 | ||
866 | static int fimc_probe(struct platform_device *pdev) | |
867 | { | |
bb7c276e SN |
868 | struct fimc_drvdata *drv_data = fimc_get_drvdata(pdev); |
869 | struct s5p_platform_fimc *pdata; | |
5fd8f738 SN |
870 | struct fimc_dev *fimc; |
871 | struct resource *res; | |
5fd8f738 SN |
872 | int ret = 0; |
873 | ||
a7d5bbcf | 874 | if (pdev->id >= drv_data->num_entities) { |
5fd8f738 SN |
875 | dev_err(&pdev->dev, "Invalid platform device id: %d\n", |
876 | pdev->id); | |
877 | return -EINVAL; | |
878 | } | |
879 | ||
6d91a51a | 880 | fimc = devm_kzalloc(&pdev->dev, sizeof(*fimc), GFP_KERNEL); |
5fd8f738 SN |
881 | if (!fimc) |
882 | return -ENOMEM; | |
883 | ||
884 | fimc->id = pdev->id; | |
e9e21083 | 885 | |
5fd8f738 SN |
886 | fimc->variant = drv_data->variant[fimc->id]; |
887 | fimc->pdev = pdev; | |
117182d1 SN |
888 | pdata = pdev->dev.platform_data; |
889 | fimc->pdata = pdata; | |
e9e21083 | 890 | |
5f3cc447 | 891 | init_waitqueue_head(&fimc->irq_queue); |
5fd8f738 | 892 | spin_lock_init(&fimc->slock); |
5fd8f738 SN |
893 | mutex_init(&fimc->lock); |
894 | ||
895 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
6d91a51a SN |
896 | fimc->regs = devm_request_and_ioremap(&pdev->dev, res); |
897 | if (fimc->regs == NULL) { | |
898 | dev_err(&pdev->dev, "Failed to obtain io memory\n"); | |
899 | return -ENOENT; | |
5fd8f738 SN |
900 | } |
901 | ||
5fd8f738 | 902 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
6d91a51a SN |
903 | if (res == NULL) { |
904 | dev_err(&pdev->dev, "Failed to get IRQ resource\n"); | |
905 | return -ENXIO; | |
5fd8f738 | 906 | } |
5fd8f738 | 907 | |
e9e21083 SN |
908 | ret = fimc_clk_get(fimc); |
909 | if (ret) | |
6d91a51a | 910 | return ret; |
e9e21083 SN |
911 | clk_set_rate(fimc->clock[CLK_BUS], drv_data->lclk_frequency); |
912 | clk_enable(fimc->clock[CLK_BUS]); | |
913 | ||
6ec0163b | 914 | ret = devm_request_irq(&pdev->dev, res->start, fimc_irq_handler, |
5af86c26 | 915 | 0, dev_name(&pdev->dev), fimc); |
5fd8f738 SN |
916 | if (ret) { |
917 | dev_err(&pdev->dev, "failed to install irq (%d)\n", ret); | |
918 | goto err_clk; | |
919 | } | |
920 | ||
693f5c40 SN |
921 | ret = fimc_initialize_capture_subdev(fimc); |
922 | if (ret) | |
923 | goto err_clk; | |
924 | ||
925 | platform_set_drvdata(pdev, fimc); | |
e9e21083 SN |
926 | pm_runtime_enable(&pdev->dev); |
927 | ret = pm_runtime_get_sync(&pdev->dev); | |
928 | if (ret < 0) | |
693f5c40 | 929 | goto err_sd; |
2dab38e2 | 930 | /* Initialize contiguous memory allocator */ |
e9e21083 | 931 | fimc->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev); |
2dab38e2 SN |
932 | if (IS_ERR(fimc->alloc_ctx)) { |
933 | ret = PTR_ERR(fimc->alloc_ctx); | |
e9e21083 | 934 | goto err_pm; |
2dab38e2 SN |
935 | } |
936 | ||
96a85742 | 937 | dev_dbg(&pdev->dev, "FIMC.%d registered successfully\n", fimc->id); |
5fd8f738 | 938 | |
e9e21083 | 939 | pm_runtime_put(&pdev->dev); |
5fd8f738 | 940 | return 0; |
e9e21083 SN |
941 | err_pm: |
942 | pm_runtime_put(&pdev->dev); | |
693f5c40 SN |
943 | err_sd: |
944 | fimc_unregister_capture_subdev(fimc); | |
5fd8f738 | 945 | err_clk: |
e9e21083 | 946 | fimc_clk_put(fimc); |
5fd8f738 SN |
947 | return ret; |
948 | } | |
949 | ||
e9e21083 | 950 | static int fimc_runtime_resume(struct device *dev) |
5fd8f738 | 951 | { |
e9e21083 | 952 | struct fimc_dev *fimc = dev_get_drvdata(dev); |
5fd8f738 | 953 | |
e9e21083 SN |
954 | dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state); |
955 | ||
956 | /* Enable clocks and perform basic initalization */ | |
957 | clk_enable(fimc->clock[CLK_GATE]); | |
5fd8f738 | 958 | fimc_hw_reset(fimc); |
e9e21083 SN |
959 | |
960 | /* Resume the capture or mem-to-mem device */ | |
961 | if (fimc_capture_busy(fimc)) | |
962 | return fimc_capture_resume(fimc); | |
f664684a SN |
963 | |
964 | return fimc_m2m_resume(fimc); | |
e9e21083 SN |
965 | } |
966 | ||
967 | static int fimc_runtime_suspend(struct device *dev) | |
968 | { | |
969 | struct fimc_dev *fimc = dev_get_drvdata(dev); | |
970 | int ret = 0; | |
971 | ||
972 | if (fimc_capture_busy(fimc)) | |
973 | ret = fimc_capture_suspend(fimc); | |
974 | else | |
975 | ret = fimc_m2m_suspend(fimc); | |
976 | if (!ret) | |
977 | clk_disable(fimc->clock[CLK_GATE]); | |
978 | ||
979 | dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state); | |
980 | return ret; | |
981 | } | |
982 | ||
983 | #ifdef CONFIG_PM_SLEEP | |
984 | static int fimc_resume(struct device *dev) | |
985 | { | |
986 | struct fimc_dev *fimc = dev_get_drvdata(dev); | |
987 | unsigned long flags; | |
988 | ||
989 | dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state); | |
990 | ||
991 | /* Do not resume if the device was idle before system suspend */ | |
992 | spin_lock_irqsave(&fimc->slock, flags); | |
993 | if (!test_and_clear_bit(ST_LPM, &fimc->state) || | |
994 | (!fimc_m2m_active(fimc) && !fimc_capture_busy(fimc))) { | |
995 | spin_unlock_irqrestore(&fimc->slock, flags); | |
996 | return 0; | |
997 | } | |
998 | fimc_hw_reset(fimc); | |
e9e21083 SN |
999 | spin_unlock_irqrestore(&fimc->slock, flags); |
1000 | ||
1001 | if (fimc_capture_busy(fimc)) | |
1002 | return fimc_capture_resume(fimc); | |
1003 | ||
1004 | return fimc_m2m_resume(fimc); | |
1005 | } | |
1006 | ||
1007 | static int fimc_suspend(struct device *dev) | |
1008 | { | |
1009 | struct fimc_dev *fimc = dev_get_drvdata(dev); | |
1010 | ||
1011 | dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state); | |
1012 | ||
1013 | if (test_and_set_bit(ST_LPM, &fimc->state)) | |
1014 | return 0; | |
1015 | if (fimc_capture_busy(fimc)) | |
1016 | return fimc_capture_suspend(fimc); | |
1017 | ||
1018 | return fimc_m2m_suspend(fimc); | |
1019 | } | |
1020 | #endif /* CONFIG_PM_SLEEP */ | |
1021 | ||
1022 | static int __devexit fimc_remove(struct platform_device *pdev) | |
1023 | { | |
1024 | struct fimc_dev *fimc = platform_get_drvdata(pdev); | |
1025 | ||
1026 | pm_runtime_disable(&pdev->dev); | |
e9e21083 | 1027 | pm_runtime_set_suspended(&pdev->dev); |
5fd8f738 | 1028 | |
693f5c40 | 1029 | fimc_unregister_capture_subdev(fimc); |
2dab38e2 SN |
1030 | vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx); |
1031 | ||
e9e21083 SN |
1032 | clk_disable(fimc->clock[CLK_BUS]); |
1033 | fimc_clk_put(fimc); | |
548aafcd | 1034 | |
e9e21083 | 1035 | dev_info(&pdev->dev, "driver unloaded\n"); |
5fd8f738 SN |
1036 | return 0; |
1037 | } | |
1038 | ||
a7d5bbcf | 1039 | /* Image pixel limits, similar across several FIMC HW revisions. */ |
25b9875f | 1040 | static struct fimc_pix_limit s5p_pix_limit[4] = { |
a7d5bbcf SN |
1041 | [0] = { |
1042 | .scaler_en_w = 3264, | |
1043 | .scaler_dis_w = 8192, | |
1044 | .in_rot_en_h = 1920, | |
1045 | .in_rot_dis_w = 8192, | |
1046 | .out_rot_en_w = 1920, | |
1047 | .out_rot_dis_w = 4224, | |
1048 | }, | |
1049 | [1] = { | |
1050 | .scaler_en_w = 4224, | |
1051 | .scaler_dis_w = 8192, | |
1052 | .in_rot_en_h = 1920, | |
1053 | .in_rot_dis_w = 8192, | |
1054 | .out_rot_en_w = 1920, | |
1055 | .out_rot_dis_w = 4224, | |
1056 | }, | |
1057 | [2] = { | |
1058 | .scaler_en_w = 1920, | |
1059 | .scaler_dis_w = 8192, | |
1060 | .in_rot_en_h = 1280, | |
1061 | .in_rot_dis_w = 8192, | |
1062 | .out_rot_en_w = 1280, | |
1063 | .out_rot_dis_w = 1920, | |
1064 | }, | |
25b9875f SN |
1065 | [3] = { |
1066 | .scaler_en_w = 1920, | |
1067 | .scaler_dis_w = 8192, | |
1068 | .in_rot_en_h = 1366, | |
1069 | .in_rot_dis_w = 8192, | |
1070 | .out_rot_en_w = 1366, | |
1071 | .out_rot_dis_w = 1920, | |
1072 | }, | |
a7d5bbcf SN |
1073 | }; |
1074 | ||
bb7c276e | 1075 | static struct fimc_variant fimc0_variant_s5p = { |
a7d5bbcf SN |
1076 | .has_inp_rot = 1, |
1077 | .has_out_rot = 1, | |
d3953223 | 1078 | .has_cam_if = 1, |
5fd8f738 SN |
1079 | .min_inp_pixsize = 16, |
1080 | .min_out_pixsize = 16, | |
a7d5bbcf | 1081 | .hor_offs_align = 8, |
9c63afcb | 1082 | .min_vsize_align = 16, |
a7d5bbcf SN |
1083 | .out_buf_count = 4, |
1084 | .pix_limit = &s5p_pix_limit[0], | |
5fd8f738 SN |
1085 | }; |
1086 | ||
bb7c276e | 1087 | static struct fimc_variant fimc2_variant_s5p = { |
d3953223 | 1088 | .has_cam_if = 1, |
5fd8f738 SN |
1089 | .min_inp_pixsize = 16, |
1090 | .min_out_pixsize = 16, | |
a7d5bbcf | 1091 | .hor_offs_align = 8, |
9c63afcb | 1092 | .min_vsize_align = 16, |
a7d5bbcf | 1093 | .out_buf_count = 4, |
bb7c276e | 1094 | .pix_limit = &s5p_pix_limit[1], |
5fd8f738 SN |
1095 | }; |
1096 | ||
bb7c276e | 1097 | static struct fimc_variant fimc0_variant_s5pv210 = { |
a7d5bbcf SN |
1098 | .pix_hoff = 1, |
1099 | .has_inp_rot = 1, | |
1100 | .has_out_rot = 1, | |
d3953223 | 1101 | .has_cam_if = 1, |
5fd8f738 | 1102 | .min_inp_pixsize = 16, |
548aafcd | 1103 | .min_out_pixsize = 16, |
a7d5bbcf | 1104 | .hor_offs_align = 8, |
9c63afcb | 1105 | .min_vsize_align = 16, |
a7d5bbcf SN |
1106 | .out_buf_count = 4, |
1107 | .pix_limit = &s5p_pix_limit[1], | |
1108 | }; | |
5fd8f738 | 1109 | |
bb7c276e | 1110 | static struct fimc_variant fimc1_variant_s5pv210 = { |
a7d5bbcf SN |
1111 | .pix_hoff = 1, |
1112 | .has_inp_rot = 1, | |
1113 | .has_out_rot = 1, | |
d3953223 | 1114 | .has_cam_if = 1, |
b241c6d6 | 1115 | .has_mainscaler_ext = 1, |
a7d5bbcf SN |
1116 | .min_inp_pixsize = 16, |
1117 | .min_out_pixsize = 16, | |
1118 | .hor_offs_align = 1, | |
9c63afcb | 1119 | .min_vsize_align = 1, |
a7d5bbcf SN |
1120 | .out_buf_count = 4, |
1121 | .pix_limit = &s5p_pix_limit[2], | |
5fd8f738 SN |
1122 | }; |
1123 | ||
bb7c276e | 1124 | static struct fimc_variant fimc2_variant_s5pv210 = { |
d3953223 | 1125 | .has_cam_if = 1, |
ddc79e0f | 1126 | .pix_hoff = 1, |
5fd8f738 | 1127 | .min_inp_pixsize = 16, |
548aafcd | 1128 | .min_out_pixsize = 16, |
a7d5bbcf | 1129 | .hor_offs_align = 8, |
9c63afcb | 1130 | .min_vsize_align = 16, |
a7d5bbcf SN |
1131 | .out_buf_count = 4, |
1132 | .pix_limit = &s5p_pix_limit[2], | |
1133 | }; | |
5fd8f738 | 1134 | |
bb7c276e | 1135 | static struct fimc_variant fimc0_variant_exynos4 = { |
a7d5bbcf SN |
1136 | .pix_hoff = 1, |
1137 | .has_inp_rot = 1, | |
1138 | .has_out_rot = 1, | |
d3953223 | 1139 | .has_cam_if = 1, |
798174ab | 1140 | .has_cistatus2 = 1, |
b241c6d6 | 1141 | .has_mainscaler_ext = 1, |
dafb9c70 | 1142 | .has_alpha = 1, |
a7d5bbcf SN |
1143 | .min_inp_pixsize = 16, |
1144 | .min_out_pixsize = 16, | |
566afaac | 1145 | .hor_offs_align = 2, |
9c63afcb | 1146 | .min_vsize_align = 1, |
a7d5bbcf SN |
1147 | .out_buf_count = 32, |
1148 | .pix_limit = &s5p_pix_limit[1], | |
1149 | }; | |
1150 | ||
bb7c276e | 1151 | static struct fimc_variant fimc3_variant_exynos4 = { |
a7d5bbcf | 1152 | .pix_hoff = 1, |
d3953223 | 1153 | .has_cam_if = 1, |
798174ab | 1154 | .has_cistatus2 = 1, |
b241c6d6 | 1155 | .has_mainscaler_ext = 1, |
dafb9c70 | 1156 | .has_alpha = 1, |
a7d5bbcf SN |
1157 | .min_inp_pixsize = 16, |
1158 | .min_out_pixsize = 16, | |
566afaac | 1159 | .hor_offs_align = 2, |
9c63afcb | 1160 | .min_vsize_align = 1, |
a7d5bbcf | 1161 | .out_buf_count = 32, |
25b9875f | 1162 | .pix_limit = &s5p_pix_limit[3], |
5fd8f738 SN |
1163 | }; |
1164 | ||
a7d5bbcf | 1165 | /* S5PC100 */ |
bb7c276e | 1166 | static struct fimc_drvdata fimc_drvdata_s5p = { |
5fd8f738 | 1167 | .variant = { |
a7d5bbcf SN |
1168 | [0] = &fimc0_variant_s5p, |
1169 | [1] = &fimc0_variant_s5p, | |
5fd8f738 SN |
1170 | [2] = &fimc2_variant_s5p, |
1171 | }, | |
a7d5bbcf SN |
1172 | .num_entities = 3, |
1173 | .lclk_frequency = 133000000UL, | |
5fd8f738 SN |
1174 | }; |
1175 | ||
a7d5bbcf | 1176 | /* S5PV210, S5PC110 */ |
bb7c276e | 1177 | static struct fimc_drvdata fimc_drvdata_s5pv210 = { |
5fd8f738 | 1178 | .variant = { |
a7d5bbcf SN |
1179 | [0] = &fimc0_variant_s5pv210, |
1180 | [1] = &fimc1_variant_s5pv210, | |
5fd8f738 SN |
1181 | [2] = &fimc2_variant_s5pv210, |
1182 | }, | |
a7d5bbcf SN |
1183 | .num_entities = 3, |
1184 | .lclk_frequency = 166000000UL, | |
1185 | }; | |
1186 | ||
bb7c276e SN |
1187 | /* EXYNOS4210, S5PV310, S5PC210 */ |
1188 | static struct fimc_drvdata fimc_drvdata_exynos4 = { | |
a7d5bbcf | 1189 | .variant = { |
25b9875f SN |
1190 | [0] = &fimc0_variant_exynos4, |
1191 | [1] = &fimc0_variant_exynos4, | |
1192 | [2] = &fimc0_variant_exynos4, | |
d3953223 | 1193 | [3] = &fimc3_variant_exynos4, |
a7d5bbcf SN |
1194 | }, |
1195 | .num_entities = 4, | |
1196 | .lclk_frequency = 166000000UL, | |
5fd8f738 SN |
1197 | }; |
1198 | ||
1199 | static struct platform_device_id fimc_driver_ids[] = { | |
1200 | { | |
1201 | .name = "s5p-fimc", | |
1202 | .driver_data = (unsigned long)&fimc_drvdata_s5p, | |
1203 | }, { | |
1204 | .name = "s5pv210-fimc", | |
1205 | .driver_data = (unsigned long)&fimc_drvdata_s5pv210, | |
a7d5bbcf | 1206 | }, { |
25b9875f SN |
1207 | .name = "exynos4-fimc", |
1208 | .driver_data = (unsigned long)&fimc_drvdata_exynos4, | |
5fd8f738 SN |
1209 | }, |
1210 | {}, | |
1211 | }; | |
1212 | MODULE_DEVICE_TABLE(platform, fimc_driver_ids); | |
1213 | ||
e9e21083 SN |
1214 | static const struct dev_pm_ops fimc_pm_ops = { |
1215 | SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend, fimc_resume) | |
1216 | SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL) | |
1217 | }; | |
1218 | ||
5fd8f738 SN |
1219 | static struct platform_driver fimc_driver = { |
1220 | .probe = fimc_probe, | |
d3953223 | 1221 | .remove = __devexit_p(fimc_remove), |
5fd8f738 SN |
1222 | .id_table = fimc_driver_ids, |
1223 | .driver = { | |
d3953223 | 1224 | .name = FIMC_MODULE_NAME, |
5fd8f738 | 1225 | .owner = THIS_MODULE, |
e9e21083 | 1226 | .pm = &fimc_pm_ops, |
5fd8f738 SN |
1227 | } |
1228 | }; | |
1229 | ||
d3953223 | 1230 | int __init fimc_register_driver(void) |
5fd8f738 | 1231 | { |
ecd9acbf | 1232 | return platform_driver_register(&fimc_driver); |
5fd8f738 SN |
1233 | } |
1234 | ||
d3953223 | 1235 | void __exit fimc_unregister_driver(void) |
5fd8f738 SN |
1236 | { |
1237 | platform_driver_unregister(&fimc_driver); | |
1238 | } |