projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[media] s5p-fimc: Use correct fourcc code for 32-bit RGB format
[deliverable/linux.git] / drivers / media / video / s5p-fimc / fimc-core.c
CommitLineData
5fd8f738
SN		 1/*
2 * S5P camera interface (video postprocessor) driver
3 *
5f3cc447 4 * Copyright (c) 2010 Samsung Electronics Co., Ltd
5fd8f738
SN		 5 *
6 * Sylwester Nawrocki, <s.nawrocki@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published
10 * by the Free Software Foundation, either version 2 of the License,
11 * or (at your option) any later version.
12 */
13
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/version.h>
17#include <linux/types.h>
18#include <linux/errno.h>
19#include <linux/bug.h>
20#include <linux/interrupt.h>
21#include <linux/device.h>
22#include <linux/platform_device.h>
23#include <linux/list.h>
24#include <linux/io.h>
25#include <linux/slab.h>
26#include <linux/clk.h>
27#include <media/v4l2-ioctl.h>
28#include <media/videobuf-dma-contig.h>
29
30#include "fimc-core.h"
31
32static char *fimc_clock_name[NUM_FIMC_CLOCKS] = { "sclk_fimc", "fimc" };
33
34static struct fimc_fmt fimc_formats[] = {
35 {
36 .name = "RGB565",
37 .fourcc = V4L2_PIX_FMT_RGB565X,
38 .depth = 16,
39 .color = S5P_FIMC_RGB565,
40 .buff_cnt = 1,
5f3cc447
SN		 41 .planes_cnt = 1,
42 .mbus_code = V4L2_MBUS_FMT_RGB565_2X8_BE,
43 .flags = FMT_FLAGS_M2M,
5fd8f738
SN		 44 }, {
45 .name = "BGR666",
46 .fourcc = V4L2_PIX_FMT_BGR666,
47 .depth = 32,
48 .color = S5P_FIMC_RGB666,
49 .buff_cnt = 1,
5f3cc447
SN		 50 .planes_cnt = 1,
51 .flags = FMT_FLAGS_M2M,
5fd8f738 52 }, {
a8365fc2
SN		 53 .name = "XRGB-8-8-8-8, 32 bpp",
54 .fourcc = V4L2_PIX_FMT_RGB32,
5fd8f738
SN		 55 .depth = 32,
56 .color = S5P_FIMC_RGB888,
57 .buff_cnt = 1,
5f3cc447
SN		 58 .planes_cnt = 1,
59 .flags = FMT_FLAGS_M2M,
5fd8f738
SN		 60 }, {
61 .name = "YUV 4:2:2 packed, YCbYCr",
62 .fourcc = V4L2_PIX_FMT_YUYV,
63 .depth = 16,
64 .color = S5P_FIMC_YCBYCR422,
65 .buff_cnt = 1,
5f3cc447
SN		 66 .planes_cnt = 1,
67 .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8,
68 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
69 }, {
5fd8f738
SN		 70 .name = "YUV 4:2:2 packed, CbYCrY",
71 .fourcc = V4L2_PIX_FMT_UYVY,
72 .depth = 16,
73 .color = S5P_FIMC_CBYCRY422,
74 .buff_cnt = 1,
5f3cc447
SN		 75 .planes_cnt = 1,
76 .mbus_code = V4L2_MBUS_FMT_UYVY8_2X8,
77 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
5fd8f738
SN		 78 }, {
79 .name = "YUV 4:2:2 packed, CrYCbY",
80 .fourcc = V4L2_PIX_FMT_VYUY,
81 .depth = 16,
82 .color = S5P_FIMC_CRYCBY422,
83 .buff_cnt = 1,
5f3cc447
SN		 84 .planes_cnt = 1,
85 .mbus_code = V4L2_MBUS_FMT_VYUY8_2X8,
86 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
5fd8f738
SN		 87 }, {
88 .name = "YUV 4:2:2 packed, YCrYCb",
89 .fourcc = V4L2_PIX_FMT_YVYU,
90 .depth = 16,
91 .color = S5P_FIMC_YCRYCB422,
92 .buff_cnt = 1,
5f3cc447
SN		 93 .planes_cnt = 1,
94 .mbus_code = V4L2_MBUS_FMT_YVYU8_2X8,
95 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
5fd8f738
SN		 96 }, {
97 .name = "YUV 4:2:2 planar, Y/Cb/Cr",
98 .fourcc = V4L2_PIX_FMT_YUV422P,
99 .depth = 12,
100 .color = S5P_FIMC_YCBCR422,
101 .buff_cnt = 1,
5f3cc447
SN		 102 .planes_cnt = 3,
103 .flags = FMT_FLAGS_M2M,
5fd8f738
SN		 104 }, {
105 .name = "YUV 4:2:2 planar, Y/CbCr",
106 .fourcc = V4L2_PIX_FMT_NV16,
107 .depth = 16,
108 .color = S5P_FIMC_YCBCR422,
109 .buff_cnt = 1,
5f3cc447
SN		 110 .planes_cnt = 2,
111 .flags = FMT_FLAGS_M2M,
5fd8f738
SN		 112 }, {
113 .name = "YUV 4:2:2 planar, Y/CrCb",
114 .fourcc = V4L2_PIX_FMT_NV61,
115 .depth = 16,
116 .color = S5P_FIMC_RGB565,
117 .buff_cnt = 1,
5f3cc447
SN		 118 .planes_cnt = 2,
119 .flags = FMT_FLAGS_M2M,
5fd8f738
SN		 120 }, {
121 .name = "YUV 4:2:0 planar, YCbCr",
122 .fourcc = V4L2_PIX_FMT_YUV420,
123 .depth = 12,
124 .color = S5P_FIMC_YCBCR420,
125 .buff_cnt = 1,
5f3cc447
SN		 126 .planes_cnt = 3,
127 .flags = FMT_FLAGS_M2M,
5fd8f738
SN		 128 }, {
129 .name = "YUV 4:2:0 planar, Y/CbCr",
130 .fourcc = V4L2_PIX_FMT_NV12,
131 .depth = 12,
132 .color = S5P_FIMC_YCBCR420,
133 .buff_cnt = 1,
5f3cc447
SN		 134 .planes_cnt = 2,
135 .flags = FMT_FLAGS_M2M,
136 },
548aafcd 137};
5fd8f738
SN		 138
139static struct v4l2_queryctrl fimc_ctrls[] = {
140 {
141 .id = V4L2_CID_HFLIP,
142 .type = V4L2_CTRL_TYPE_BOOLEAN,
143 .name = "Horizontal flip",
144 .minimum = 0,
145 .maximum = 1,
146 .default_value = 0,
548aafcd 147 }, {
5fd8f738
SN		 148 .id = V4L2_CID_VFLIP,
149 .type = V4L2_CTRL_TYPE_BOOLEAN,
150 .name = "Vertical flip",
151 .minimum = 0,
152 .maximum = 1,
153 .default_value = 0,
548aafcd 154 }, {
5fd8f738
SN		 155 .id = V4L2_CID_ROTATE,
156 .type = V4L2_CTRL_TYPE_INTEGER,
157 .name = "Rotation (CCW)",
158 .minimum = 0,
159 .maximum = 270,
160 .step = 90,
161 .default_value = 0,
162 },
163};
164
165
166static struct v4l2_queryctrl *get_ctrl(int id)
167{
168 int i;
169
170 for (i = 0; i < ARRAY_SIZE(fimc_ctrls); ++i)
171 if (id == fimc_ctrls[i].id)
172 return &fimc_ctrls[i];
173 return NULL;
174}
175
5f3cc447 176int fimc_check_scaler_ratio(struct v4l2_rect *r, struct fimc_frame *f)
5fd8f738
SN		 177{
178 if (r->width > f->width) {
179 if (f->width > (r->width * SCALER_MAX_HRATIO))
180 return -EINVAL;
181 } else {
182 if ((f->width * SCALER_MAX_HRATIO) < r->width)
183 return -EINVAL;
184 }
185
186 if (r->height > f->height) {
187 if (f->height > (r->height * SCALER_MAX_VRATIO))
188 return -EINVAL;
189 } else {
190 if ((f->height * SCALER_MAX_VRATIO) < r->height)
191 return -EINVAL;
192 }
193
194 return 0;
195}
196
197static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
198{
548aafcd
SN		 199 u32 sh = 6;
200
201 if (src >= 64 * tar)
5fd8f738 202 return -EINVAL;
548aafcd
SN		 203
204 while (sh--) {
205 u32 tmp = 1 << sh;
206 if (src >= tar * tmp) {
207 *shift = sh, *ratio = tmp;
208 return 0;
209 }
5fd8f738
SN		 210 }
211
548aafcd
SN		 212 *shift = 0, *ratio = 1;
213
214 dbg("s: %d, t: %d, shift: %d, ratio: %d",
215 src, tar, *shift, *ratio);
5fd8f738
SN		 216 return 0;
217}
218
5f3cc447 219int fimc_set_scaler_info(struct fimc_ctx *ctx)
5fd8f738
SN		 220{
221 struct fimc_scaler *sc = &ctx->scaler;
222 struct fimc_frame *s_frame = &ctx->s_frame;
223 struct fimc_frame *d_frame = &ctx->d_frame;
224 int tx, ty, sx, sy;
225 int ret;
226
47654df8
SN		 227 if (ctx->rotation == 90 || ctx->rotation == 270) {
228 ty = d_frame->width;
229 tx = d_frame->height;
230 } else {
231 tx = d_frame->width;
232 ty = d_frame->height;
233 }
5fd8f738
SN		 234 if (tx <= 0 || ty <= 0) {
235 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
236 "invalid target size: %d x %d", tx, ty);
237 return -EINVAL;
238 }
239
240 sx = s_frame->width;
241 sy = s_frame->height;
242 if (sx <= 0 || sy <= 0) {
243 err("invalid source size: %d x %d", sx, sy);
244 return -EINVAL;
245 }
246
247 sc->real_width = sx;
248 sc->real_height = sy;
249 dbg("sx= %d, sy= %d, tx= %d, ty= %d", sx, sy, tx, ty);
250
251 ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
252 if (ret)
253 return ret;
254
255 ret = fimc_get_scaler_factor(sy, ty, &sc->pre_vratio, &sc->vfactor);
256 if (ret)
257 return ret;
258
259 sc->pre_dst_width = sx / sc->pre_hratio;
260 sc->pre_dst_height = sy / sc->pre_vratio;
261
262 sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
263 sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
264
265 sc->scaleup_h = (tx >= sx) ? 1 : 0;
266 sc->scaleup_v = (ty >= sy) ? 1 : 0;
267
268 /* check to see if input and output size/format differ */
269 if (s_frame->fmt->color == d_frame->fmt->color
270 && s_frame->width == d_frame->width
271 && s_frame->height == d_frame->height)
272 sc->copy_mode = 1;
273 else
274 sc->copy_mode = 0;
275
276 return 0;
277}
278
5f3cc447
SN		 279static void fimc_capture_handler(struct fimc_dev *fimc)
280{
281 struct fimc_vid_cap *cap = &fimc->vid_cap;
282 struct fimc_vid_buffer *v_buf = NULL;
283
284 if (!list_empty(&cap->active_buf_q)) {
285 v_buf = active_queue_pop(cap);
286 fimc_buf_finish(fimc, v_buf);
287 }
288
289 if (test_and_clear_bit(ST_CAPT_SHUT, &fimc->state)) {
290 wake_up(&fimc->irq_queue);
291 return;
292 }
293
294 if (!list_empty(&cap->pending_buf_q)) {
295
296 v_buf = pending_queue_pop(cap);
297 fimc_hw_set_output_addr(fimc, &v_buf->paddr, cap->buf_index);
298 v_buf->index = cap->buf_index;
299
300 dbg("hw ptr: %d, sw ptr: %d",
301 fimc_hw_get_frame_index(fimc), cap->buf_index);
302
303 spin_lock(&fimc->irqlock);
304 v_buf->vb.state = VIDEOBUF_ACTIVE;
305 spin_unlock(&fimc->irqlock);
306
307 /* Move the buffer to the capture active queue */
308 active_queue_add(cap, v_buf);
309
310 dbg("next frame: %d, done frame: %d",
311 fimc_hw_get_frame_index(fimc), v_buf->index);
312
313 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
314 cap->buf_index = 0;
315
316 } else if (test_and_clear_bit(ST_CAPT_STREAM, &fimc->state) &&
317 cap->active_buf_cnt <= 1) {
318 fimc_deactivate_capture(fimc);
319 }
320
321 dbg("frame: %d, active_buf_cnt= %d",
322 fimc_hw_get_frame_index(fimc), cap->active_buf_cnt);
323}
5fd8f738
SN		 324
325static irqreturn_t fimc_isr(int irq, void *priv)
326{
327 struct fimc_vid_buffer *src_buf, *dst_buf;
5fd8f738 328 struct fimc_ctx *ctx;
548aafcd 329 struct fimc_dev *fimc = priv;
5fd8f738
SN		 330
331 BUG_ON(!fimc);
332 fimc_hw_clear_irq(fimc);
333
334 spin_lock(&fimc->slock);
335
336 if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) {
337 ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev);
338 if (!ctx || !ctx->m2m_ctx)
339 goto isr_unlock;
340 src_buf = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
341 dst_buf = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
342 if (src_buf && dst_buf) {
343 spin_lock(&fimc->irqlock);
548aafcd 344 src_buf->vb.state = dst_buf->vb.state = VIDEOBUF_DONE;
5fd8f738
SN		 345 wake_up(&src_buf->vb.done);
346 wake_up(&dst_buf->vb.done);
347 spin_unlock(&fimc->irqlock);
348 v4l2_m2m_job_finish(fimc->m2m.m2m_dev, ctx->m2m_ctx);
349 }
5f3cc447
SN		 350 goto isr_unlock;
351
352 }
353
354 if (test_bit(ST_CAPT_RUN, &fimc->state))
355 fimc_capture_handler(fimc);
356
357 if (test_and_clear_bit(ST_CAPT_PEND, &fimc->state)) {
358 set_bit(ST_CAPT_RUN, &fimc->state);
359 wake_up(&fimc->irq_queue);
5fd8f738
SN		 360 }
361
362isr_unlock:
363 spin_unlock(&fimc->slock);
364 return IRQ_HANDLED;
365}
366
367/* The color format (planes_cnt, buff_cnt) must be already configured. */
548aafcd
SN		 368int fimc_prepare_addr(struct fimc_ctx *ctx, struct fimc_vid_buffer *buf,
369 struct fimc_frame *frame, struct fimc_addr *paddr)
5fd8f738 370{
5fd8f738 371 int ret = 0;
548aafcd 372 u32 pix_size;
5fd8f738 373
548aafcd 374 if (buf == NULL || frame == NULL)
5fd8f738
SN		 375 return -EINVAL;
376
377 pix_size = frame->width * frame->height;
378
379 dbg("buff_cnt= %d, planes_cnt= %d, frame->size= %d, pix_size= %d",
380 frame->fmt->buff_cnt, frame->fmt->planes_cnt,
381 frame->size, pix_size);
382
383 if (frame->fmt->buff_cnt == 1) {
384 paddr->y = videobuf_to_dma_contig(&buf->vb);
385 switch (frame->fmt->planes_cnt) {
386 case 1:
387 paddr->cb = 0;
388 paddr->cr = 0;
389 break;
390 case 2:
391 /* decompose Y into Y/Cb */
392 paddr->cb = (u32)(paddr->y + pix_size);
393 paddr->cr = 0;
394 break;
395 case 3:
396 paddr->cb = (u32)(paddr->y + pix_size);
397 /* decompose Y into Y/Cb/Cr */
398 if (S5P_FIMC_YCBCR420 == frame->fmt->color)
399 paddr->cr = (u32)(paddr->cb
400 + (pix_size >> 2));
401 else /* 422 */
402 paddr->cr = (u32)(paddr->cb
403 + (pix_size >> 1));
404 break;
405 default:
406 return -EINVAL;
407 }
408 }
409
548aafcd
SN		 410 dbg("PHYS_ADDR: y= 0x%X cb= 0x%X cr= 0x%X ret= %d",
411 paddr->y, paddr->cb, paddr->cr, ret);
5fd8f738
SN		 412
413 return ret;
414}
415
416/* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */
417static void fimc_set_yuv_order(struct fimc_ctx *ctx)
418{
419 /* The one only mode supported in SoC. */
420 ctx->in_order_2p = S5P_FIMC_LSB_CRCB;
421 ctx->out_order_2p = S5P_FIMC_LSB_CRCB;
422
423 /* Set order for 1 plane input formats. */
424 switch (ctx->s_frame.fmt->color) {
425 case S5P_FIMC_YCRYCB422:
426 ctx->in_order_1p = S5P_FIMC_IN_YCRYCB;
427 break;
428 case S5P_FIMC_CBYCRY422:
429 ctx->in_order_1p = S5P_FIMC_IN_CBYCRY;
430 break;
431 case S5P_FIMC_CRYCBY422:
432 ctx->in_order_1p = S5P_FIMC_IN_CRYCBY;
433 break;
434 case S5P_FIMC_YCBYCR422:
435 default:
436 ctx->in_order_1p = S5P_FIMC_IN_YCBYCR;
437 break;
438 }
439 dbg("ctx->in_order_1p= %d", ctx->in_order_1p);
440
441 switch (ctx->d_frame.fmt->color) {
442 case S5P_FIMC_YCRYCB422:
443 ctx->out_order_1p = S5P_FIMC_OUT_YCRYCB;
444 break;
445 case S5P_FIMC_CBYCRY422:
446 ctx->out_order_1p = S5P_FIMC_OUT_CBYCRY;
447 break;
448 case S5P_FIMC_CRYCBY422:
449 ctx->out_order_1p = S5P_FIMC_OUT_CRYCBY;
450 break;
451 case S5P_FIMC_YCBYCR422:
452 default:
453 ctx->out_order_1p = S5P_FIMC_OUT_YCBYCR;
454 break;
455 }
456 dbg("ctx->out_order_1p= %d", ctx->out_order_1p);
457}
458
ddc79e0f
SN		 459static void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f)
460{
461 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
462
463 f->dma_offset.y_h = f->offs_h;
464 if (!variant->pix_hoff)
465 f->dma_offset.y_h *= (f->fmt->depth >> 3);
466
467 f->dma_offset.y_v = f->offs_v;
468
469 f->dma_offset.cb_h = f->offs_h;
470 f->dma_offset.cb_v = f->offs_v;
471
472 f->dma_offset.cr_h = f->offs_h;
473 f->dma_offset.cr_v = f->offs_v;
474
475 if (!variant->pix_hoff) {
476 if (f->fmt->planes_cnt == 3) {
477 f->dma_offset.cb_h >>= 1;
478 f->dma_offset.cr_h >>= 1;
479 }
480 if (f->fmt->color == S5P_FIMC_YCBCR420) {
481 f->dma_offset.cb_v >>= 1;
482 f->dma_offset.cr_v >>= 1;
483 }
484 }
485
486 dbg("in_offset: color= %d, y_h= %d, y_v= %d",
487 f->fmt->color, f->dma_offset.y_h, f->dma_offset.y_v);
488}
489
5fd8f738
SN		 490/**
491 * fimc_prepare_config - check dimensions, operation and color mode
492 * and pre-calculate offset and the scaling coefficients.
493 *
494 * @ctx: hardware context information
495 * @flags: flags indicating which parameters to check/update
496 *
497 * Return: 0 if dimensions are valid or non zero otherwise.
498 */
5f3cc447 499int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags)
5fd8f738
SN		 500{
501 struct fimc_frame *s_frame, *d_frame;
502 struct fimc_vid_buffer *buf = NULL;
5fd8f738
SN		 503 int ret = 0;
504
505 s_frame = &ctx->s_frame;
506 d_frame = &ctx->d_frame;
507
508 if (flags & FIMC_PARAMS) {
ddc79e0f
SN		 509 /* Prepare the DMA offset ratios for scaler. */
510 fimc_prepare_dma_offset(ctx, &ctx->s_frame);
511 fimc_prepare_dma_offset(ctx, &ctx->d_frame);
5fd8f738 512
5fd8f738
SN		 513 if (s_frame->height > (SCALER_MAX_VRATIO * d_frame->height) ||
514 s_frame->width > (SCALER_MAX_HRATIO * d_frame->width)) {
515 err("out of scaler range");
516 return -EINVAL;
517 }
ddc79e0f 518 fimc_set_yuv_order(ctx);
5fd8f738
SN		 519 }
520
521 /* Input DMA mode is not allowed when the scaler is disabled. */
522 ctx->scaler.enabled = 1;
523
524 if (flags & FIMC_SRC_ADDR) {
525 buf = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
548aafcd 526 ret = fimc_prepare_addr(ctx, buf, s_frame, &s_frame->paddr);
5fd8f738
SN		 527 if (ret)
528 return ret;
529 }
530
531 if (flags & FIMC_DST_ADDR) {
532 buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
548aafcd 533 ret = fimc_prepare_addr(ctx, buf, d_frame, &d_frame->paddr);
5fd8f738
SN		 534 }
535
536 return ret;
537}
538
539static void fimc_dma_run(void *priv)
540{
541 struct fimc_ctx *ctx = priv;
542 struct fimc_dev *fimc;
543 unsigned long flags;
544 u32 ret;
545
546 if (WARN(!ctx, "null hardware context"))
547 return;
548
549 fimc = ctx->fimc_dev;
550
551 spin_lock_irqsave(&ctx->slock, flags);
552 set_bit(ST_M2M_PEND, &fimc->state);
553
554 ctx->state |= (FIMC_SRC_ADDR | FIMC_DST_ADDR);
555 ret = fimc_prepare_config(ctx, ctx->state);
556 if (ret) {
548aafcd 557 err("Wrong parameters");
5fd8f738
SN		 558 goto dma_unlock;
559 }
548aafcd
SN		 560 /* Reconfigure hardware if the context has changed. */
561 if (fimc->m2m.ctx != ctx) {
5fd8f738 562 ctx->state |= FIMC_PARAMS;
548aafcd
SN		 563 fimc->m2m.ctx = ctx;
564 }
5fd8f738
SN		 565
566 fimc_hw_set_input_addr(fimc, &ctx->s_frame.paddr);
567
568 if (ctx->state & FIMC_PARAMS) {
569 fimc_hw_set_input_path(ctx);
570 fimc_hw_set_in_dma(ctx);
571 if (fimc_set_scaler_info(ctx)) {
548aafcd 572 err("Scaler setup error");
5fd8f738
SN		 573 goto dma_unlock;
574 }
5fd8f738
SN		 575 fimc_hw_set_scaler(ctx);
576 fimc_hw_set_target_format(ctx);
577 fimc_hw_set_rotation(ctx);
578 fimc_hw_set_effect(ctx);
579 }
580
581 fimc_hw_set_output_path(ctx);
582 if (ctx->state & (FIMC_DST_ADDR | FIMC_PARAMS))
548aafcd 583 fimc_hw_set_output_addr(fimc, &ctx->d_frame.paddr, -1);
5fd8f738
SN		 584
585 if (ctx->state & FIMC_PARAMS)
586 fimc_hw_set_out_dma(ctx);
587
548aafcd 588 fimc_activate_capture(ctx);
5fd8f738 589
5f3cc447 590 ctx->state &= (FIMC_CTX_M2M | FIMC_CTX_CAP);
548aafcd 591 fimc_hw_activate_input_dma(fimc, true);
5fd8f738
SN		 592
593dma_unlock:
594 spin_unlock_irqrestore(&ctx->slock, flags);
595}
596
03e30ca5
PO		 597static void fimc_job_abort(void *priv)
598{
599 /* Nothing done in job_abort. */
600}
5fd8f738
SN		 601
602static void fimc_buf_release(struct videobuf_queue *vq,
603 struct videobuf_buffer *vb)
604{
605 videobuf_dma_contig_free(vq, vb);
606 vb->state = VIDEOBUF_NEEDS_INIT;
607}
608
609static int fimc_buf_setup(struct videobuf_queue *vq, unsigned int *count,
610 unsigned int *size)
611{
612 struct fimc_ctx *ctx = vq->priv_data;
613 struct fimc_frame *frame;
614
548aafcd 615 frame = ctx_get_frame(ctx, vq->type);
03e30ca5
PO		 616 if (IS_ERR(frame))
617 return PTR_ERR(frame);
5fd8f738
SN		 618
619 *size = (frame->width * frame->height * frame->fmt->depth) >> 3;
620 if (0 == *count)
621 *count = 1;
622 return 0;
623}
624
625static int fimc_buf_prepare(struct videobuf_queue *vq,
626 struct videobuf_buffer *vb, enum v4l2_field field)
627{
628 struct fimc_ctx *ctx = vq->priv_data;
629 struct v4l2_device *v4l2_dev = &ctx->fimc_dev->m2m.v4l2_dev;
630 struct fimc_frame *frame;
631 int ret;
632
548aafcd 633 frame = ctx_get_frame(ctx, vq->type);
03e30ca5
PO		 634 if (IS_ERR(frame))
635 return PTR_ERR(frame);
5fd8f738
SN		 636
637 if (vb->baddr) {
638 if (vb->bsize < frame->size) {
639 v4l2_err(v4l2_dev,
640 "User-provided buffer too small (%d < %d)\n",
641 vb->bsize, frame->size);
642 WARN_ON(1);
643 return -EINVAL;
644 }
645 } else if (vb->state != VIDEOBUF_NEEDS_INIT
646 && vb->bsize < frame->size) {
647 return -EINVAL;
648 }
649
650 vb->width = frame->width;
651 vb->height = frame->height;
652 vb->bytesperline = (frame->width * frame->fmt->depth) >> 3;
653 vb->size = frame->size;
654 vb->field = field;
655
656 if (VIDEOBUF_NEEDS_INIT == vb->state) {
657 ret = videobuf_iolock(vq, vb, NULL);
658 if (ret) {
659 v4l2_err(v4l2_dev, "Iolock failed\n");
660 fimc_buf_release(vq, vb);
661 return ret;
662 }
663 }
664 vb->state = VIDEOBUF_PREPARED;
665
666 return 0;
667}
668
669static void fimc_buf_queue(struct videobuf_queue *vq,
670 struct videobuf_buffer *vb)
671{
672 struct fimc_ctx *ctx = vq->priv_data;
5f3cc447
SN		 673 struct fimc_dev *fimc = ctx->fimc_dev;
674 struct fimc_vid_cap *cap = &fimc->vid_cap;
675 unsigned long flags;
676
677 dbg("ctx: %p, ctx->state: 0x%x", ctx, ctx->state);
678
679 if ((ctx->state & FIMC_CTX_M2M) && ctx->m2m_ctx) {
680 v4l2_m2m_buf_queue(ctx->m2m_ctx, vq, vb);
681 } else if (ctx->state & FIMC_CTX_CAP) {
682 spin_lock_irqsave(&fimc->slock, flags);
683 fimc_vid_cap_buf_queue(fimc, (struct fimc_vid_buffer *)vb);
684
685 dbg("fimc->cap.active_buf_cnt: %d",
686 fimc->vid_cap.active_buf_cnt);
687
688 if (cap->active_buf_cnt >= cap->reqbufs_count ||
689 cap->active_buf_cnt >= FIMC_MAX_OUT_BUFS) {
690 if (!test_and_set_bit(ST_CAPT_STREAM, &fimc->state))
691 fimc_activate_capture(ctx);
692 }
693 spin_unlock_irqrestore(&fimc->slock, flags);
694 }
5fd8f738
SN		 695}
696
5f3cc447 697struct videobuf_queue_ops fimc_qops = {
5fd8f738
SN		 698 .buf_setup = fimc_buf_setup,
699 .buf_prepare = fimc_buf_prepare,
700 .buf_queue = fimc_buf_queue,
701 .buf_release = fimc_buf_release,
702};
703
704static int fimc_m2m_querycap(struct file *file, void *priv,
705 struct v4l2_capability *cap)
706{
707 struct fimc_ctx *ctx = file->private_data;
708 struct fimc_dev *fimc = ctx->fimc_dev;
709
710 strncpy(cap->driver, fimc->pdev->name, sizeof(cap->driver) - 1);
711 strncpy(cap->card, fimc->pdev->name, sizeof(cap->card) - 1);
712 cap->bus_info[0] = 0;
713 cap->version = KERNEL_VERSION(1, 0, 0);
714 cap->capabilities = V4L2_CAP_STREAMING |
715 V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT;
716
717 return 0;
718}
719
5f3cc447 720int fimc_vidioc_enum_fmt(struct file *file, void *priv,
5fd8f738
SN		 721 struct v4l2_fmtdesc *f)
722{
723 struct fimc_fmt *fmt;
724
725 if (f->index >= ARRAY_SIZE(fimc_formats))
726 return -EINVAL;
727
728 fmt = &fimc_formats[f->index];
729 strncpy(f->description, fmt->name, sizeof(f->description) - 1);
730 f->pixelformat = fmt->fourcc;
5f3cc447 731
5fd8f738
SN		 732 return 0;
733}
734
5f3cc447 735int fimc_vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
5fd8f738
SN		 736{
737 struct fimc_ctx *ctx = priv;
5f3cc447 738 struct fimc_dev *fimc = ctx->fimc_dev;
5fd8f738
SN		 739 struct fimc_frame *frame;
740
548aafcd 741 frame = ctx_get_frame(ctx, f->type);
03e30ca5
PO		 742 if (IS_ERR(frame))
743 return PTR_ERR(frame);
5fd8f738 744
5f3cc447
SN		 745 if (mutex_lock_interruptible(&fimc->lock))
746 return -ERESTARTSYS;
747
5fd8f738
SN		 748 f->fmt.pix.width = frame->width;
749 f->fmt.pix.height = frame->height;
750 f->fmt.pix.field = V4L2_FIELD_NONE;
751 f->fmt.pix.pixelformat = frame->fmt->fourcc;
752
5f3cc447 753 mutex_unlock(&fimc->lock);
5fd8f738
SN		 754 return 0;
755}
756
5f3cc447 757struct fimc_fmt *find_format(struct v4l2_format *f, unsigned int mask)
5fd8f738
SN		 758{
759 struct fimc_fmt *fmt;
760 unsigned int i;
761
762 for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
763 fmt = &fimc_formats[i];
5f3cc447
SN		 764 if (fmt->fourcc == f->fmt.pix.pixelformat &&
765 (fmt->flags & mask))
5fd8f738
SN		 766 break;
767 }
5fd8f738 768
5f3cc447 769 return (i == ARRAY_SIZE(fimc_formats)) ? NULL : fmt;
5fd8f738
SN		 770}
771
5f3cc447
SN		 772struct fimc_fmt *find_mbus_format(struct v4l2_mbus_framefmt *f,
773 unsigned int mask)
5fd8f738
SN		 774{
775 struct fimc_fmt *fmt;
5f3cc447
SN		 776 unsigned int i;
777
778 for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
779 fmt = &fimc_formats[i];
780 if (fmt->mbus_code == f->code && (fmt->flags & mask))
781 break;
782 }
783
784 return (i == ARRAY_SIZE(fimc_formats)) ? NULL : fmt;
785}
786
787
788int fimc_vidioc_try_fmt(struct file *file, void *priv, struct v4l2_format *f)
789{
5fd8f738
SN		 790 struct fimc_ctx *ctx = priv;
791 struct fimc_dev *fimc = ctx->fimc_dev;
5fd8f738 792 struct samsung_fimc_variant *variant = fimc->variant;
5f3cc447
SN		 793 struct v4l2_pix_format *pix = &f->fmt.pix;
794 struct fimc_fmt *fmt;
795 u32 max_width, mod_x, mod_y, mask;
796 int ret = -EINVAL, is_output = 0;
5fd8f738 797
5f3cc447
SN		 798 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
799 if (ctx->state & FIMC_CTX_CAP)
800 return -EINVAL;
801 is_output = 1;
802 } else if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
5fd8f738
SN		 803 return -EINVAL;
804 }
805
5f3cc447
SN		 806 dbg("w: %d, h: %d, bpl: %d",
807 pix->width, pix->height, pix->bytesperline);
808
809 if (mutex_lock_interruptible(&fimc->lock))
810 return -ERESTARTSYS;
811
812 mask = is_output ? FMT_FLAGS_M2M : FMT_FLAGS_M2M | FMT_FLAGS_CAM;
813 fmt = find_format(f, mask);
814 if (!fmt) {
815 v4l2_err(&fimc->m2m.v4l2_dev, "Fourcc format (0x%X) invalid.\n",
816 pix->pixelformat);
817 goto tf_out;
818 }
819
5fd8f738
SN		 820 if (pix->field == V4L2_FIELD_ANY)
821 pix->field = V4L2_FIELD_NONE;
822 else if (V4L2_FIELD_NONE != pix->field)
5f3cc447 823 goto tf_out;
5fd8f738 824
5f3cc447 825 if (is_output) {
a7d5bbcf 826 max_width = variant->pix_limit->scaler_dis_w;
5f3cc447 827 mod_x = ffs(variant->min_inp_pixsize) - 1;
5fd8f738 828 } else {
a7d5bbcf 829 max_width = variant->pix_limit->out_rot_dis_w;
5f3cc447 830 mod_x = ffs(variant->min_out_pixsize) - 1;
5fd8f738
SN		 831 }
832
5fd8f738 833 if (tiled_fmt(fmt)) {
5f3cc447
SN		 834 mod_x = 6; /* 64 x 32 pixels tile */
835 mod_y = 5;
836 } else {
837 if (fimc->id == 1 && fimc->variant->pix_hoff)
838 mod_y = fimc_fmt_is_rgb(fmt->color) ? 0 : 1;
839 else
840 mod_y = mod_x;
5fd8f738
SN		 841 }
842
5f3cc447 843 dbg("mod_x: %d, mod_y: %d, max_w: %d", mod_x, mod_y, max_width);
5fd8f738 844
5f3cc447 845 v4l_bound_align_image(&pix->width, 16, max_width, mod_x,
a7d5bbcf 846 &pix->height, 8, variant->pix_limit->scaler_dis_w, mod_y, 0);
5fd8f738
SN		 847
848 if (pix->bytesperline == 0 ||
5f3cc447 849 (pix->bytesperline * 8 / fmt->depth) > pix->width)
5fd8f738
SN		 850 pix->bytesperline = (pix->width * fmt->depth) >> 3;
851
852 if (pix->sizeimage == 0)
853 pix->sizeimage = pix->height * pix->bytesperline;
854
5f3cc447
SN		 855 dbg("w: %d, h: %d, bpl: %d, depth: %d",
856 pix->width, pix->height, pix->bytesperline, fmt->depth);
5fd8f738 857
5f3cc447 858 ret = 0;
5fd8f738 859
5f3cc447
SN		 860tf_out:
861 mutex_unlock(&fimc->lock);
862 return ret;
863}
5fd8f738
SN		 864
865static int fimc_m2m_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
866{
867 struct fimc_ctx *ctx = priv;
28f06ff4
SN		 868 struct fimc_dev *fimc = ctx->fimc_dev;
869 struct v4l2_device *v4l2_dev = &fimc->m2m.v4l2_dev;
870 struct videobuf_queue *vq;
5fd8f738
SN		 871 struct fimc_frame *frame;
872 struct v4l2_pix_format *pix;
873 unsigned long flags;
874 int ret = 0;
875
5f3cc447 876 ret = fimc_vidioc_try_fmt(file, priv, f);
5fd8f738
SN		 877 if (ret)
878 return ret;
879
28f06ff4
SN		 880 if (mutex_lock_interruptible(&fimc->lock))
881 return -ERESTARTSYS;
5fd8f738 882
28f06ff4
SN		 883 vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
884 mutex_lock(&vq->vb_lock);
5fd8f738 885
28f06ff4
SN		 886 if (videobuf_queue_is_busy(vq)) {
887 v4l2_err(v4l2_dev, "%s: queue (%d) busy\n", __func__, f->type);
888 ret = -EBUSY;
889 goto sf_out;
890 }
5fd8f738 891
28f06ff4 892 spin_lock_irqsave(&ctx->slock, flags);
5fd8f738 893 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
5fd8f738 894 frame = &ctx->s_frame;
5fd8f738 895 ctx->state |= FIMC_SRC_FMT;
5fd8f738 896 } else if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
5fd8f738 897 frame = &ctx->d_frame;
5fd8f738 898 ctx->state |= FIMC_DST_FMT;
5fd8f738 899 } else {
28f06ff4 900 spin_unlock_irqrestore(&ctx->slock, flags);
5fd8f738
SN		 901 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
902 "Wrong buffer/video queue type (%d)\n", f->type);
590a58d1 903 ret = -EINVAL;
28f06ff4 904 goto sf_out;
5fd8f738 905 }
28f06ff4 906 spin_unlock_irqrestore(&ctx->slock, flags);
5fd8f738
SN		 907
908 pix = &f->fmt.pix;
5f3cc447 909 frame->fmt = find_format(f, FMT_FLAGS_M2M);
5fd8f738
SN		 910 if (!frame->fmt) {
911 ret = -EINVAL;
28f06ff4 912 goto sf_out;
5fd8f738
SN		 913 }
914
28f06ff4
SN		 915 frame->f_width = pix->bytesperline * 8 / frame->fmt->depth;
916 frame->f_height = pix->height;
917 frame->width = pix->width;
918 frame->height = pix->height;
919 frame->o_width = pix->width;
5fd8f738 920 frame->o_height = pix->height;
28f06ff4
SN		 921 frame->offs_h = 0;
922 frame->offs_v = 0;
923 frame->size = (pix->width * pix->height * frame->fmt->depth) >> 3;
924 vq->field = pix->field;
925
5fd8f738
SN		 926 spin_lock_irqsave(&ctx->slock, flags);
927 ctx->state |= FIMC_PARAMS;
928 spin_unlock_irqrestore(&ctx->slock, flags);
929
28f06ff4 930 dbg("f_w: %d, f_h: %d", frame->f_width, frame->f_height);
5fd8f738 931
28f06ff4
SN		 932sf_out:
933 mutex_unlock(&vq->vb_lock);
934 mutex_unlock(&fimc->lock);
5fd8f738
SN		 935 return ret;
936}
937
938static int fimc_m2m_reqbufs(struct file *file, void *priv,
939 struct v4l2_requestbuffers *reqbufs)
940{
941 struct fimc_ctx *ctx = priv;
942 return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
943}
944
945static int fimc_m2m_querybuf(struct file *file, void *priv,
946 struct v4l2_buffer *buf)
947{
948 struct fimc_ctx *ctx = priv;
949 return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
950}
951
952static int fimc_m2m_qbuf(struct file *file, void *priv,
953 struct v4l2_buffer *buf)
954{
955 struct fimc_ctx *ctx = priv;
956
957 return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
958}
959
960static int fimc_m2m_dqbuf(struct file *file, void *priv,
961 struct v4l2_buffer *buf)
962{
963 struct fimc_ctx *ctx = priv;
964 return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
965}
966
967static int fimc_m2m_streamon(struct file *file, void *priv,
968 enum v4l2_buf_type type)
969{
970 struct fimc_ctx *ctx = priv;
971 return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
972}
973
974static int fimc_m2m_streamoff(struct file *file, void *priv,
975 enum v4l2_buf_type type)
976{
977 struct fimc_ctx *ctx = priv;
978 return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
979}
980
5f3cc447 981int fimc_vidioc_queryctrl(struct file *file, void *priv,
5fd8f738
SN		 982 struct v4l2_queryctrl *qc)
983{
5f3cc447 984 struct fimc_ctx *ctx = priv;
5fd8f738 985 struct v4l2_queryctrl *c;
69e05e83 986 int ret = -EINVAL;
5f3cc447 987
5fd8f738 988 c = get_ctrl(qc->id);
5f3cc447
SN		 989 if (c) {
990 *qc = *c;
991 return 0;
992 }
993
69e05e83
SN		 994 if (ctx->state & FIMC_CTX_CAP) {
995 if (mutex_lock_interruptible(&ctx->fimc_dev->lock))
996 return -ERESTARTSYS;
997 ret = v4l2_subdev_call(ctx->fimc_dev->vid_cap.sd,
5f3cc447 998 core, queryctrl, qc);
69e05e83
SN		 999 mutex_unlock(&ctx->fimc_dev->lock);
1000 }
1001 return ret;
5fd8f738
SN		 1002}
1003
5f3cc447 1004int fimc_vidioc_g_ctrl(struct file *file, void *priv,
5fd8f738
SN		 1005 struct v4l2_control *ctrl)
1006{
1007 struct fimc_ctx *ctx = priv;
5f3cc447
SN		 1008 struct fimc_dev *fimc = ctx->fimc_dev;
1009 int ret = 0;
1010
1011 if (mutex_lock_interruptible(&fimc->lock))
1012 return -ERESTARTSYS;
5fd8f738
SN		 1013
1014 switch (ctrl->id) {
1015 case V4L2_CID_HFLIP:
1016 ctrl->value = (FLIP_X_AXIS & ctx->flip) ? 1 : 0;
1017 break;
1018 case V4L2_CID_VFLIP:
1019 ctrl->value = (FLIP_Y_AXIS & ctx->flip) ? 1 : 0;
1020 break;
1021 case V4L2_CID_ROTATE:
1022 ctrl->value = ctx->rotation;
1023 break;
1024 default:
5f3cc447
SN		 1025 if (ctx->state & FIMC_CTX_CAP) {
1026 ret = v4l2_subdev_call(fimc->vid_cap.sd, core,
1027 g_ctrl, ctrl);
1028 } else {
1029 v4l2_err(&fimc->m2m.v4l2_dev,
1030 "Invalid control\n");
1031 ret = -EINVAL;
1032 }
5fd8f738
SN		 1033 }
1034 dbg("ctrl->value= %d", ctrl->value);
5f3cc447
SN		 1035
1036 mutex_unlock(&fimc->lock);
1037 return ret;
5fd8f738
SN		 1038}
1039
5f3cc447 1040int check_ctrl_val(struct fimc_ctx *ctx, struct v4l2_control *ctrl)
5fd8f738
SN		 1041{
1042 struct v4l2_queryctrl *c;
1043 c = get_ctrl(ctrl->id);
1044 if (!c)
1045 return -EINVAL;
1046
1047 if (ctrl->value < c->minimum || ctrl->value > c->maximum
1048 || (c->step != 0 && ctrl->value % c->step != 0)) {
1049 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
1050 "Invalid control value\n");
1051 return -ERANGE;
1052 }
1053
1054 return 0;
1055}
1056
5f3cc447 1057int fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_control *ctrl)
5fd8f738 1058{
5fd8f738 1059 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
5f3cc447 1060 struct fimc_dev *fimc = ctx->fimc_dev;
5fd8f738 1061 unsigned long flags;
5fd8f738 1062
5f3cc447
SN		 1063 if (ctx->rotation != 0 &&
1064 (ctrl->id == V4L2_CID_HFLIP || ctrl->id == V4L2_CID_VFLIP)) {
1065 v4l2_err(&fimc->m2m.v4l2_dev,
1066 "Simultaneous flip and rotation is not supported\n");
1067 return -EINVAL;
1068 }
1069
1070 spin_lock_irqsave(&ctx->slock, flags);
5fd8f738
SN		 1071
1072 switch (ctrl->id) {
1073 case V4L2_CID_HFLIP:
5fd8f738
SN		 1074 if (ctrl->value)
1075 ctx->flip |= FLIP_X_AXIS;
1076 else
1077 ctx->flip &= ~FLIP_X_AXIS;
1078 break;
1079
1080 case V4L2_CID_VFLIP:
5fd8f738
SN		 1081 if (ctrl->value)
1082 ctx->flip |= FLIP_Y_AXIS;
1083 else
1084 ctx->flip &= ~FLIP_Y_AXIS;
1085 break;
1086
1087 case V4L2_CID_ROTATE:
5f3cc447
SN		 1088 /* Check for the output rotator availability */
1089 if ((ctrl->value == 90 || ctrl->value == 270) &&
1090 (ctx->in_path == FIMC_DMA && !variant->has_out_rot)) {
1091 spin_unlock_irqrestore(&ctx->slock, flags);
1092 return -EINVAL;
1093 } else {
1094 ctx->rotation = ctrl->value;
5fd8f738 1095 }
5fd8f738
SN		 1096 break;
1097
1098 default:
5f3cc447
SN		 1099 spin_unlock_irqrestore(&ctx->slock, flags);
1100 v4l2_err(&fimc->m2m.v4l2_dev, "Invalid control\n");
5fd8f738
SN		 1101 return -EINVAL;
1102 }
5fd8f738
SN		 1103 ctx->state |= FIMC_PARAMS;
1104 spin_unlock_irqrestore(&ctx->slock, flags);
5f3cc447 1105
5fd8f738
SN		 1106 return 0;
1107}
1108
5f3cc447
SN		 1109static int fimc_m2m_s_ctrl(struct file *file, void *priv,
1110 struct v4l2_control *ctrl)
1111{
1112 struct fimc_ctx *ctx = priv;
1113 int ret = 0;
1114
1115 ret = check_ctrl_val(ctx, ctrl);
1116 if (ret)
1117 return ret;
1118
1119 ret = fimc_s_ctrl(ctx, ctrl);
1120 return 0;
1121}
5fd8f738 1122
e004e02f 1123static int fimc_m2m_cropcap(struct file *file, void *fh,
5f3cc447 1124 struct v4l2_cropcap *cr)
5fd8f738
SN		 1125{
1126 struct fimc_frame *frame;
1127 struct fimc_ctx *ctx = fh;
5f3cc447 1128 struct fimc_dev *fimc = ctx->fimc_dev;
5fd8f738 1129
548aafcd 1130 frame = ctx_get_frame(ctx, cr->type);
03e30ca5
PO		 1131 if (IS_ERR(frame))
1132 return PTR_ERR(frame);
5fd8f738 1133
5f3cc447
SN		 1134 if (mutex_lock_interruptible(&fimc->lock))
1135 return -ERESTARTSYS;
1136
1137 cr->bounds.left = 0;
1138 cr->bounds.top = 0;
1139 cr->bounds.width = frame->f_width;
1140 cr->bounds.height = frame->f_height;
1141 cr->defrect = cr->bounds;
1142
1143 mutex_unlock(&fimc->lock);
5fd8f738
SN		 1144 return 0;
1145}
1146
e004e02f 1147static int fimc_m2m_g_crop(struct file *file, void *fh, struct v4l2_crop *cr)
5fd8f738
SN		 1148{
1149 struct fimc_frame *frame;
1150 struct fimc_ctx *ctx = file->private_data;
5f3cc447 1151 struct fimc_dev *fimc = ctx->fimc_dev;
5fd8f738 1152
548aafcd 1153 frame = ctx_get_frame(ctx, cr->type);
03e30ca5
PO		 1154 if (IS_ERR(frame))
1155 return PTR_ERR(frame);
5fd8f738 1156
5f3cc447
SN		 1157 if (mutex_lock_interruptible(&fimc->lock))
1158 return -ERESTARTSYS;
1159
5fd8f738
SN		 1160 cr->c.left = frame->offs_h;
1161 cr->c.top = frame->offs_v;
1162 cr->c.width = frame->width;
1163 cr->c.height = frame->height;
1164
5f3cc447 1165 mutex_unlock(&fimc->lock);
5fd8f738
SN		 1166 return 0;
1167}
1168
5f3cc447 1169int fimc_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr)
5fd8f738 1170{
5fd8f738 1171 struct fimc_dev *fimc = ctx->fimc_dev;
5fd8f738 1172 struct fimc_frame *f;
5f3cc447
SN		 1173 u32 min_size, halign;
1174
5fd8f738
SN		 1175 if (cr->c.top < 0 || cr->c.left < 0) {
1176 v4l2_err(&fimc->m2m.v4l2_dev,
1177 "doesn't support negative values for top & left\n");
1178 return -EINVAL;
1179 }
1180
e004e02f
SN		 1181 if (cr->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
1182 f = (ctx->state & FIMC_CTX_CAP) ? &ctx->s_frame : &ctx->d_frame;
1183 else if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT &&
1184 ctx->state & FIMC_CTX_M2M)
1185 f = &ctx->s_frame;
1186 else
1187 return -EINVAL;
5fd8f738 1188
e004e02f
SN		 1189 min_size = (f == &ctx->s_frame) ?
1190 fimc->variant->min_inp_pixsize : fimc->variant->min_out_pixsize;
5fd8f738 1191
5f3cc447
SN		 1192 if (ctx->state & FIMC_CTX_M2M) {
1193 if (fimc->id == 1 && fimc->variant->pix_hoff)
1194 halign = fimc_fmt_is_rgb(f->fmt->color) ? 0 : 1;
1195 else
1196 halign = ffs(min_size) - 1;
1197 /* there are more strict aligment requirements at camera interface */
1198 } else {
1199 min_size = 16;
1200 halign = 4;
5fd8f738
SN		 1201 }
1202
5f3cc447
SN		 1203 v4l_bound_align_image(&cr->c.width, min_size, f->o_width,
1204 ffs(min_size) - 1,
1205 &cr->c.height, min_size, f->o_height,
1206 halign, 64/(ALIGN(f->fmt->depth, 8)));
1207
1208 /* adjust left/top if cropping rectangle is out of bounds */
1209 if (cr->c.left + cr->c.width > f->o_width)
1210 cr->c.left = f->o_width - cr->c.width;
1211 if (cr->c.top + cr->c.height > f->o_height)
1212 cr->c.top = f->o_height - cr->c.height;
1213
1214 cr->c.left = round_down(cr->c.left, min_size);
1215 cr->c.top = round_down(cr->c.top,
1216 ctx->state & FIMC_CTX_M2M ? 8 : 16);
1217
1218 dbg("l:%d, t:%d, w:%d, h:%d, f_w: %d, f_h: %d",
1219 cr->c.left, cr->c.top, cr->c.width, cr->c.height,
1220 f->f_width, f->f_height);
1221
1222 return 0;
1223}
1224
1225
1226static int fimc_m2m_s_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1227{
1228 struct fimc_ctx *ctx = file->private_data;
1229 struct fimc_dev *fimc = ctx->fimc_dev;
1230 unsigned long flags;
1231 struct fimc_frame *f;
1232 int ret;
1233
1234 ret = fimc_try_crop(ctx, cr);
1235 if (ret)
1236 return ret;
1237
1238 f = (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) ?
1239 &ctx->s_frame : &ctx->d_frame;
1240
69e05e83
SN		 1241 if (mutex_lock_interruptible(&fimc->lock))
1242 return -ERESTARTSYS;
1243
5fd8f738 1244 spin_lock_irqsave(&ctx->slock, flags);
5f3cc447
SN		 1245 if (~ctx->state & (FIMC_SRC_FMT | FIMC_DST_FMT)) {
1246 /* Check to see if scaling ratio is within supported range */
5fd8f738
SN		 1247 if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
1248 ret = fimc_check_scaler_ratio(&cr->c, &ctx->d_frame);
5f3cc447 1249 else
5fd8f738 1250 ret = fimc_check_scaler_ratio(&cr->c, &ctx->s_frame);
5fd8f738 1251 if (ret) {
5f3cc447 1252 v4l2_err(&fimc->m2m.v4l2_dev, "Out of scaler range");
69e05e83
SN		 1253 ret = -EINVAL;
1254 goto scr_unlock;
5fd8f738
SN		 1255 }
1256 }
1257 ctx->state |= FIMC_PARAMS;
5fd8f738
SN		 1258
1259 f->offs_h = cr->c.left;
1260 f->offs_v = cr->c.top;
5f3cc447 1261 f->width = cr->c.width;
5fd8f738 1262 f->height = cr->c.height;
5f3cc447 1263
69e05e83 1264scr_unlock:
5f3cc447 1265 spin_unlock_irqrestore(&ctx->slock, flags);
69e05e83 1266 mutex_unlock(&fimc->lock);
5fd8f738
SN		 1267 return 0;
1268}
1269
1270static const struct v4l2_ioctl_ops fimc_m2m_ioctl_ops = {
1271 .vidioc_querycap = fimc_m2m_querycap,
1272
5f3cc447
SN		 1273 .vidioc_enum_fmt_vid_cap = fimc_vidioc_enum_fmt,
1274 .vidioc_enum_fmt_vid_out = fimc_vidioc_enum_fmt,
5fd8f738 1275
5f3cc447
SN		 1276 .vidioc_g_fmt_vid_cap = fimc_vidioc_g_fmt,
1277 .vidioc_g_fmt_vid_out = fimc_vidioc_g_fmt,
5fd8f738 1278
5f3cc447
SN		 1279 .vidioc_try_fmt_vid_cap = fimc_vidioc_try_fmt,
1280 .vidioc_try_fmt_vid_out = fimc_vidioc_try_fmt,
5fd8f738
SN		 1281
1282 .vidioc_s_fmt_vid_cap = fimc_m2m_s_fmt,
1283 .vidioc_s_fmt_vid_out = fimc_m2m_s_fmt,
1284
1285 .vidioc_reqbufs = fimc_m2m_reqbufs,
1286 .vidioc_querybuf = fimc_m2m_querybuf,
1287
1288 .vidioc_qbuf = fimc_m2m_qbuf,
1289 .vidioc_dqbuf = fimc_m2m_dqbuf,
1290
1291 .vidioc_streamon = fimc_m2m_streamon,
1292 .vidioc_streamoff = fimc_m2m_streamoff,
1293
5f3cc447
SN		 1294 .vidioc_queryctrl = fimc_vidioc_queryctrl,
1295 .vidioc_g_ctrl = fimc_vidioc_g_ctrl,
5fd8f738
SN		 1296 .vidioc_s_ctrl = fimc_m2m_s_ctrl,
1297
e004e02f 1298 .vidioc_g_crop = fimc_m2m_g_crop,
5fd8f738 1299 .vidioc_s_crop = fimc_m2m_s_crop,
e004e02f 1300 .vidioc_cropcap = fimc_m2m_cropcap
5fd8f738
SN		 1301
1302};
1303
1304static void queue_init(void *priv, struct videobuf_queue *vq,
1305 enum v4l2_buf_type type)
1306{
1307 struct fimc_ctx *ctx = priv;
1308 struct fimc_dev *fimc = ctx->fimc_dev;
1309
1310 videobuf_queue_dma_contig_init(vq, &fimc_qops,
548aafcd 1311 &fimc->pdev->dev,
5fd8f738 1312 &fimc->irqlock, type, V4L2_FIELD_NONE,
e3cfd447 1313 sizeof(struct fimc_vid_buffer), priv, NULL);
5fd8f738
SN		 1314}
1315
1316static int fimc_m2m_open(struct file *file)
1317{
1318 struct fimc_dev *fimc = video_drvdata(file);
1319 struct fimc_ctx *ctx = NULL;
1320 int err = 0;
1321
5f3cc447
SN		 1322 if (mutex_lock_interruptible(&fimc->lock))
1323 return -ERESTARTSYS;
1324
1325 dbg("pid: %d, state: 0x%lx, refcnt: %d",
1326 task_pid_nr(current), fimc->state, fimc->vid_cap.refcnt);
1327
1328 /*
1329 * Return if the corresponding video capture node
1330 * is already opened.
1331 */
1332 if (fimc->vid_cap.refcnt > 0) {
29adc2c0
DC		 1333 err = -EBUSY;
1334 goto err_unlock;
5f3cc447
SN		 1335 }
1336
5fd8f738
SN		 1337 fimc->m2m.refcnt++;
1338 set_bit(ST_OUTDMA_RUN, &fimc->state);
5fd8f738
SN		 1339
1340 ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
29adc2c0
DC		 1341 if (!ctx) {
1342 err = -ENOMEM;
1343 goto err_unlock;
1344 }
5fd8f738
SN		 1345
1346 file->private_data = ctx;
1347 ctx->fimc_dev = fimc;
548aafcd 1348 /* Default color format */
5fd8f738
SN		 1349 ctx->s_frame.fmt = &fimc_formats[0];
1350 ctx->d_frame.fmt = &fimc_formats[0];
5f3cc447
SN		 1351 /* Setup the device context for mem2mem mode. */
1352 ctx->state = FIMC_CTX_M2M;
5fd8f738 1353 ctx->flags = 0;
5fd8f738
SN		 1354 ctx->in_path = FIMC_DMA;
1355 ctx->out_path = FIMC_DMA;
1356 spin_lock_init(&ctx->slock);
1357
1358 ctx->m2m_ctx = v4l2_m2m_ctx_init(ctx, fimc->m2m.m2m_dev, queue_init);
1359 if (IS_ERR(ctx->m2m_ctx)) {
1360 err = PTR_ERR(ctx->m2m_ctx);
1361 kfree(ctx);
1362 }
5f3cc447 1363
29adc2c0 1364err_unlock:
5f3cc447 1365 mutex_unlock(&fimc->lock);
5fd8f738
SN		 1366 return err;
1367}
1368
1369static int fimc_m2m_release(struct file *file)
1370{
1371 struct fimc_ctx *ctx = file->private_data;
1372 struct fimc_dev *fimc = ctx->fimc_dev;
1373
5f3cc447
SN		 1374 mutex_lock(&fimc->lock);
1375
1376 dbg("pid: %d, state: 0x%lx, refcnt= %d",
1377 task_pid_nr(current), fimc->state, fimc->m2m.refcnt);
1378
5fd8f738
SN		 1379 v4l2_m2m_ctx_release(ctx->m2m_ctx);
1380 kfree(ctx);
5fd8f738
SN		 1381 if (--fimc->m2m.refcnt <= 0)
1382 clear_bit(ST_OUTDMA_RUN, &fimc->state);
5f3cc447 1383
5fd8f738
SN		 1384 mutex_unlock(&fimc->lock);
1385 return 0;
1386}
1387
1388static unsigned int fimc_m2m_poll(struct file *file,
1389 struct poll_table_struct *wait)
1390{
1391 struct fimc_ctx *ctx = file->private_data;
5f3cc447 1392
5fd8f738
SN		 1393 return v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
1394}
1395
1396
1397static int fimc_m2m_mmap(struct file *file, struct vm_area_struct *vma)
1398{
1399 struct fimc_ctx *ctx = file->private_data;
5f3cc447 1400
5fd8f738
SN		 1401 return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
1402}
1403
1404static const struct v4l2_file_operations fimc_m2m_fops = {
1405 .owner = THIS_MODULE,
1406 .open = fimc_m2m_open,
1407 .release = fimc_m2m_release,
1408 .poll = fimc_m2m_poll,
69e05e83 1409 .unlocked_ioctl = video_ioctl2,
5fd8f738
SN		 1410 .mmap = fimc_m2m_mmap,
1411};
1412
1413static struct v4l2_m2m_ops m2m_ops = {
1414 .device_run = fimc_dma_run,
1415 .job_abort = fimc_job_abort,
1416};
1417
1418
1419static int fimc_register_m2m_device(struct fimc_dev *fimc)
1420{
1421 struct video_device *vfd;
1422 struct platform_device *pdev;
1423 struct v4l2_device *v4l2_dev;
1424 int ret = 0;
1425
1426 if (!fimc)
1427 return -ENODEV;
1428
1429 pdev = fimc->pdev;
1430 v4l2_dev = &fimc->m2m.v4l2_dev;
1431
1432 /* set name if it is empty */
1433 if (!v4l2_dev->name[0])
1434 snprintf(v4l2_dev->name, sizeof(v4l2_dev->name),
1435 "%s.m2m", dev_name(&pdev->dev));
1436
1437 ret = v4l2_device_register(&pdev->dev, v4l2_dev);
1438 if (ret)
548aafcd 1439 goto err_m2m_r1;
5fd8f738
SN		 1440
1441 vfd = video_device_alloc();
1442 if (!vfd) {
1443 v4l2_err(v4l2_dev, "Failed to allocate video device\n");
1444 goto err_m2m_r1;
1445 }
1446
1447 vfd->fops = &fimc_m2m_fops;
1448 vfd->ioctl_ops = &fimc_m2m_ioctl_ops;
1449 vfd->minor = -1;
1450 vfd->release = video_device_release;
1451
1452 snprintf(vfd->name, sizeof(vfd->name), "%s:m2m", dev_name(&pdev->dev));
1453
1454 video_set_drvdata(vfd, fimc);
1455 platform_set_drvdata(pdev, fimc);
1456
1457 fimc->m2m.vfd = vfd;
1458 fimc->m2m.m2m_dev = v4l2_m2m_init(&m2m_ops);
1459 if (IS_ERR(fimc->m2m.m2m_dev)) {
1460 v4l2_err(v4l2_dev, "failed to initialize v4l2-m2m device\n");
1461 ret = PTR_ERR(fimc->m2m.m2m_dev);
1462 goto err_m2m_r2;
1463 }
1464
1465 ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
1466 if (ret) {
1467 v4l2_err(v4l2_dev,
1468 "%s(): failed to register video device\n", __func__);
1469 goto err_m2m_r3;
1470 }
1471 v4l2_info(v4l2_dev,
1472 "FIMC m2m driver registered as /dev/video%d\n", vfd->num);
1473
1474 return 0;
1475
1476err_m2m_r3:
1477 v4l2_m2m_release(fimc->m2m.m2m_dev);
1478err_m2m_r2:
1479 video_device_release(fimc->m2m.vfd);
1480err_m2m_r1:
1481 v4l2_device_unregister(v4l2_dev);
1482
1483 return ret;
1484}
1485
1486static void fimc_unregister_m2m_device(struct fimc_dev *fimc)
1487{
1488 if (fimc) {
1489 v4l2_m2m_release(fimc->m2m.m2m_dev);
1490 video_unregister_device(fimc->m2m.vfd);
548aafcd 1491
5fd8f738
SN		 1492 v4l2_device_unregister(&fimc->m2m.v4l2_dev);
1493 }
1494}
1495
1496static void fimc_clk_release(struct fimc_dev *fimc)
1497{
1498 int i;
1499 for (i = 0; i < NUM_FIMC_CLOCKS; i++) {
1500 if (fimc->clock[i]) {
1501 clk_disable(fimc->clock[i]);
1502 clk_put(fimc->clock[i]);
1503 }
1504 }
1505}
1506
1507static int fimc_clk_get(struct fimc_dev *fimc)
1508{
1509 int i;
1510 for (i = 0; i < NUM_FIMC_CLOCKS; i++) {
1511 fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clock_name[i]);
1512 if (IS_ERR(fimc->clock[i])) {
1513 dev_err(&fimc->pdev->dev,
1514 "failed to get fimc clock: %s\n",
1515 fimc_clock_name[i]);
1516 return -ENXIO;
1517 }
1518 clk_enable(fimc->clock[i]);
1519 }
1520 return 0;
1521}
1522
1523static int fimc_probe(struct platform_device *pdev)
1524{
1525 struct fimc_dev *fimc;
1526 struct resource *res;
1527 struct samsung_fimc_driverdata *drv_data;
1528 int ret = 0;
1529
1530 dev_dbg(&pdev->dev, "%s():\n", __func__);
1531
1532 drv_data = (struct samsung_fimc_driverdata *)
1533 platform_get_device_id(pdev)->driver_data;
1534
a7d5bbcf 1535 if (pdev->id >= drv_data->num_entities) {
5fd8f738
SN		 1536 dev_err(&pdev->dev, "Invalid platform device id: %d\n",
1537 pdev->id);
1538 return -EINVAL;
1539 }
1540
1541 fimc = kzalloc(sizeof(struct fimc_dev), GFP_KERNEL);
1542 if (!fimc)
1543 return -ENOMEM;
1544
1545 fimc->id = pdev->id;
1546 fimc->variant = drv_data->variant[fimc->id];
1547 fimc->pdev = pdev;
5f3cc447 1548 fimc->pdata = pdev->dev.platform_data;
5fd8f738
SN		 1549 fimc->state = ST_IDLE;
1550
1551 spin_lock_init(&fimc->irqlock);
5f3cc447 1552 init_waitqueue_head(&fimc->irq_queue);
5fd8f738
SN		 1553 spin_lock_init(&fimc->slock);
1554
1555 mutex_init(&fimc->lock);
1556
1557 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1558 if (!res) {
1559 dev_err(&pdev->dev, "failed to find the registers\n");
1560 ret = -ENOENT;
1561 goto err_info;
1562 }
1563
1564 fimc->regs_res = request_mem_region(res->start, resource_size(res),
1565 dev_name(&pdev->dev));
1566 if (!fimc->regs_res) {
1567 dev_err(&pdev->dev, "failed to obtain register region\n");
1568 ret = -ENOENT;
1569 goto err_info;
1570 }
1571
1572 fimc->regs = ioremap(res->start, resource_size(res));
1573 if (!fimc->regs) {
1574 dev_err(&pdev->dev, "failed to map registers\n");
1575 ret = -ENXIO;
1576 goto err_req_region;
1577 }
1578
1579 ret = fimc_clk_get(fimc);
1580 if (ret)
1581 goto err_regs_unmap;
5f3cc447 1582 clk_set_rate(fimc->clock[0], drv_data->lclk_frequency);
5fd8f738
SN		 1583
1584 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1585 if (!res) {
1586 dev_err(&pdev->dev, "failed to get IRQ resource\n");
1587 ret = -ENXIO;
1588 goto err_clk;
1589 }
1590 fimc->irq = res->start;
1591
1592 fimc_hw_reset(fimc);
1593
1594 ret = request_irq(fimc->irq, fimc_isr, 0, pdev->name, fimc);
1595 if (ret) {
1596 dev_err(&pdev->dev, "failed to install irq (%d)\n", ret);
1597 goto err_clk;
1598 }
1599
5fd8f738
SN		 1600 ret = fimc_register_m2m_device(fimc);
1601 if (ret)
548aafcd 1602 goto err_irq;
5fd8f738 1603
5f3cc447
SN		 1604 /* At least one camera sensor is required to register capture node */
1605 if (fimc->pdata) {
1606 int i;
1607 for (i = 0; i < FIMC_MAX_CAMIF_CLIENTS; ++i)
1608 if (fimc->pdata->isp_info[i])
1609 break;
1610
1611 if (i < FIMC_MAX_CAMIF_CLIENTS) {
1612 ret = fimc_register_capture_device(fimc);
1613 if (ret)
1614 goto err_m2m;
1615 }
1616 }
1617
a7d5bbcf
SN		 1618 /*
1619 * Exclude the additional output DMA address registers by masking
1620 * them out on HW revisions that provide extended capabilites.
1621 */
1622 if (fimc->variant->out_buf_count > 4)
1623 fimc_hw_set_dma_seq(fimc, 0xF);
1624
5fd8f738
SN		 1625 dev_dbg(&pdev->dev, "%s(): fimc-%d registered successfully\n",
1626 __func__, fimc->id);
1627
1628 return 0;
1629
5f3cc447
SN		 1630err_m2m:
1631 fimc_unregister_m2m_device(fimc);
5fd8f738
SN		 1632err_irq:
1633 free_irq(fimc->irq, fimc);
1634err_clk:
1635 fimc_clk_release(fimc);
1636err_regs_unmap:
1637 iounmap(fimc->regs);
1638err_req_region:
1639 release_resource(fimc->regs_res);
1640 kfree(fimc->regs_res);
1641err_info:
1642 kfree(fimc);
548aafcd 1643
5fd8f738
SN		 1644 return ret;
1645}
1646
1647static int __devexit fimc_remove(struct platform_device *pdev)
1648{
1649 struct fimc_dev *fimc =
1650 (struct fimc_dev *)platform_get_drvdata(pdev);
1651
5fd8f738 1652 free_irq(fimc->irq, fimc);
5fd8f738
SN		 1653 fimc_hw_reset(fimc);
1654
1655 fimc_unregister_m2m_device(fimc);
5f3cc447
SN		 1656 fimc_unregister_capture_device(fimc);
1657
5fd8f738
SN		 1658 fimc_clk_release(fimc);
1659 iounmap(fimc->regs);
1660 release_resource(fimc->regs_res);
1661 kfree(fimc->regs_res);
1662 kfree(fimc);
548aafcd
SN		 1663
1664 dev_info(&pdev->dev, "%s driver unloaded\n", pdev->name);
5fd8f738
SN		 1665 return 0;
1666}
1667
a7d5bbcf
SN		 1668/* Image pixel limits, similar across several FIMC HW revisions. */
1669static struct fimc_pix_limit s5p_pix_limit[3] = {
1670 [0] = {
1671 .scaler_en_w = 3264,
1672 .scaler_dis_w = 8192,
1673 .in_rot_en_h = 1920,
1674 .in_rot_dis_w = 8192,
1675 .out_rot_en_w = 1920,
1676 .out_rot_dis_w = 4224,
1677 },
1678 [1] = {
1679 .scaler_en_w = 4224,
1680 .scaler_dis_w = 8192,
1681 .in_rot_en_h = 1920,
1682 .in_rot_dis_w = 8192,
1683 .out_rot_en_w = 1920,
1684 .out_rot_dis_w = 4224,
1685 },
1686 [2] = {
1687 .scaler_en_w = 1920,
1688 .scaler_dis_w = 8192,
1689 .in_rot_en_h = 1280,
1690 .in_rot_dis_w = 8192,
1691 .out_rot_en_w = 1280,
1692 .out_rot_dis_w = 1920,
1693 },
1694};
1695
1696static struct samsung_fimc_variant fimc0_variant_s5p = {
1697 .has_inp_rot = 1,
1698 .has_out_rot = 1,
5fd8f738
SN		 1699 .min_inp_pixsize = 16,
1700 .min_out_pixsize = 16,
a7d5bbcf
SN		 1701 .hor_offs_align = 8,
1702 .out_buf_count = 4,
1703 .pix_limit = &s5p_pix_limit[0],
5fd8f738
SN		 1704};
1705
1706static struct samsung_fimc_variant fimc2_variant_s5p = {
1707 .min_inp_pixsize = 16,
1708 .min_out_pixsize = 16,
a7d5bbcf
SN		 1709 .hor_offs_align = 8,
1710 .out_buf_count = 4,
1711 .pix_limit = &s5p_pix_limit[1],
5fd8f738
SN		 1712};
1713
a7d5bbcf
SN		 1714static struct samsung_fimc_variant fimc0_variant_s5pv210 = {
1715 .pix_hoff = 1,
1716 .has_inp_rot = 1,
1717 .has_out_rot = 1,
5fd8f738 1718 .min_inp_pixsize = 16,
548aafcd 1719 .min_out_pixsize = 16,
a7d5bbcf
SN		 1720 .hor_offs_align = 8,
1721 .out_buf_count = 4,
1722 .pix_limit = &s5p_pix_limit[1],
1723};
5fd8f738 1724
a7d5bbcf
SN		 1725static struct samsung_fimc_variant fimc1_variant_s5pv210 = {
1726 .pix_hoff = 1,
1727 .has_inp_rot = 1,
1728 .has_out_rot = 1,
1729 .min_inp_pixsize = 16,
1730 .min_out_pixsize = 16,
1731 .hor_offs_align = 1,
1732 .out_buf_count = 4,
1733 .pix_limit = &s5p_pix_limit[2],
5fd8f738
SN		 1734};
1735
1736static struct samsung_fimc_variant fimc2_variant_s5pv210 = {
ddc79e0f 1737 .pix_hoff = 1,
5fd8f738 1738 .min_inp_pixsize = 16,
548aafcd 1739 .min_out_pixsize = 16,
a7d5bbcf
SN		 1740 .hor_offs_align = 8,
1741 .out_buf_count = 4,
1742 .pix_limit = &s5p_pix_limit[2],
1743};
5fd8f738 1744
a7d5bbcf
SN		 1745static struct samsung_fimc_variant fimc0_variant_s5pv310 = {
1746 .pix_hoff = 1,
1747 .has_inp_rot = 1,
1748 .has_out_rot = 1,
1749 .min_inp_pixsize = 16,
1750 .min_out_pixsize = 16,
1751 .hor_offs_align = 1,
1752 .out_buf_count = 32,
1753 .pix_limit = &s5p_pix_limit[1],
1754};
1755
1756static struct samsung_fimc_variant fimc2_variant_s5pv310 = {
1757 .pix_hoff = 1,
1758 .min_inp_pixsize = 16,
1759 .min_out_pixsize = 16,
1760 .hor_offs_align = 1,
1761 .out_buf_count = 32,
1762 .pix_limit = &s5p_pix_limit[2],
5fd8f738
SN		 1763};
1764
a7d5bbcf 1765/* S5PC100 */
5fd8f738
SN		 1766static struct samsung_fimc_driverdata fimc_drvdata_s5p = {
1767 .variant = {
a7d5bbcf
SN		 1768 [0] = &fimc0_variant_s5p,
1769 [1] = &fimc0_variant_s5p,
5fd8f738
SN		 1770 [2] = &fimc2_variant_s5p,
1771 },
a7d5bbcf
SN		 1772 .num_entities = 3,
1773 .lclk_frequency = 133000000UL,
5fd8f738
SN		 1774};
1775
a7d5bbcf 1776/* S5PV210, S5PC110 */
5fd8f738
SN		 1777static struct samsung_fimc_driverdata fimc_drvdata_s5pv210 = {
1778 .variant = {
a7d5bbcf
SN		 1779 [0] = &fimc0_variant_s5pv210,
1780 [1] = &fimc1_variant_s5pv210,
5fd8f738
SN		 1781 [2] = &fimc2_variant_s5pv210,
1782 },
a7d5bbcf
SN		 1783 .num_entities = 3,
1784 .lclk_frequency = 166000000UL,
1785};
1786
1787/* S5PV310, S5PC210 */
1788static struct samsung_fimc_driverdata fimc_drvdata_s5pv310 = {
1789 .variant = {
1790 [0] = &fimc0_variant_s5pv310,
1791 [1] = &fimc0_variant_s5pv310,
1792 [2] = &fimc0_variant_s5pv310,
1793 [3] = &fimc2_variant_s5pv310,
1794 },
1795 .num_entities = 4,
1796 .lclk_frequency = 166000000UL,
5fd8f738
SN		 1797};
1798
1799static struct platform_device_id fimc_driver_ids[] = {
1800 {
1801 .name = "s5p-fimc",
1802 .driver_data = (unsigned long)&fimc_drvdata_s5p,
1803 }, {
1804 .name = "s5pv210-fimc",
1805 .driver_data = (unsigned long)&fimc_drvdata_s5pv210,
a7d5bbcf
SN		 1806 }, {
1807 .name = "s5pv310-fimc",
1808 .driver_data = (unsigned long)&fimc_drvdata_s5pv310,
5fd8f738
SN		 1809 },
1810 {},
1811};
1812MODULE_DEVICE_TABLE(platform, fimc_driver_ids);
1813
1814static struct platform_driver fimc_driver = {
1815 .probe = fimc_probe,
1816 .remove = __devexit_p(fimc_remove),
1817 .id_table = fimc_driver_ids,
1818 .driver = {
1819 .name = MODULE_NAME,
1820 .owner = THIS_MODULE,
1821 }
1822};
1823
5fd8f738
SN		 1824static int __init fimc_init(void)
1825{
548aafcd
SN		 1826 int ret = platform_driver_register(&fimc_driver);
1827 if (ret)
1828 err("platform_driver_register failed: %d\n", ret);
1829 return ret;
5fd8f738
SN		 1830}
1831
1832static void __exit fimc_exit(void)
1833{
1834 platform_driver_unregister(&fimc_driver);
1835}
1836
1837module_init(fimc_init);
1838module_exit(fimc_exit);
1839
5f3cc447
SN		 1840MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
1841MODULE_DESCRIPTION("S5P FIMC camera host interface/video postprocessor driver");
5fd8f738 1842MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.132777 seconds and 5 git commands to generate.