Commit | Line | Data |
---|---|---|
5fd8f738 | 1 | /* |
3a3f9449 | 2 | * Copyright (C) 2010 - 2011 Samsung Electronics Co., Ltd. |
5fd8f738 SN |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #ifndef FIMC_CORE_H_ | |
10 | #define FIMC_CORE_H_ | |
11 | ||
5f3cc447 SN |
12 | /*#define DEBUG*/ |
13 | ||
2319c539 | 14 | #include <linux/platform_device.h> |
aee7126c | 15 | #include <linux/sched.h> |
4ecbf5d1 | 16 | #include <linux/spinlock.h> |
5fd8f738 | 17 | #include <linux/types.h> |
aee7126c | 18 | #include <linux/videodev2.h> |
2dab38e2 | 19 | #include <linux/io.h> |
574e1717 SN |
20 | |
21 | #include <media/media-entity.h> | |
2dab38e2 | 22 | #include <media/videobuf2-core.h> |
5fd8f738 SN |
23 | #include <media/v4l2-device.h> |
24 | #include <media/v4l2-mem2mem.h> | |
5f3cc447 | 25 | #include <media/v4l2-mediabus.h> |
df7e09a3 | 26 | #include <media/s5p_fimc.h> |
aee7126c | 27 | |
5fd8f738 SN |
28 | #include "regs-fimc.h" |
29 | ||
30 | #define err(fmt, args...) \ | |
31 | printk(KERN_ERR "%s:%d: " fmt "\n", __func__, __LINE__, ##args) | |
32 | ||
5fd8f738 | 33 | #define dbg(fmt, args...) \ |
1e004695 | 34 | pr_debug("%s:%d: " fmt "\n", __func__, __LINE__, ##args) |
5fd8f738 | 35 | |
5f3cc447 SN |
36 | /* Time to wait for next frame VSYNC interrupt while stopping operation. */ |
37 | #define FIMC_SHUTDOWN_TIMEOUT ((100*HZ)/1000) | |
ebdfea81 | 38 | #define MAX_FIMC_CLOCKS 2 |
5fd8f738 | 39 | #define MODULE_NAME "s5p-fimc" |
a7d5bbcf | 40 | #define FIMC_MAX_DEVS 4 |
5fd8f738 SN |
41 | #define FIMC_MAX_OUT_BUFS 4 |
42 | #define SCALER_MAX_HRATIO 64 | |
43 | #define SCALER_MAX_VRATIO 64 | |
548aafcd | 44 | #define DMA_MIN_SIZE 8 |
5fd8f738 | 45 | |
a25be18d SN |
46 | /* indices to the clocks array */ |
47 | enum { | |
48 | CLK_BUS, | |
49 | CLK_GATE, | |
a25be18d SN |
50 | }; |
51 | ||
5f3cc447 | 52 | enum fimc_dev_flags { |
e9e21083 SN |
53 | ST_LPM, |
54 | /* m2m node */ | |
55 | ST_M2M_RUN, | |
5fd8f738 | 56 | ST_M2M_PEND, |
e9e21083 SN |
57 | ST_M2M_SUSPENDING, |
58 | ST_M2M_SUSPENDED, | |
59 | /* capture node */ | |
5f3cc447 SN |
60 | ST_CAPT_PEND, |
61 | ST_CAPT_RUN, | |
62 | ST_CAPT_STREAM, | |
63 | ST_CAPT_SHUT, | |
e9e21083 | 64 | ST_CAPT_BUSY, |
5fd8f738 SN |
65 | }; |
66 | ||
e9e21083 | 67 | #define fimc_m2m_active(dev) test_bit(ST_M2M_RUN, &(dev)->state) |
5fd8f738 SN |
68 | #define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state) |
69 | ||
5f3cc447 SN |
70 | #define fimc_capture_running(dev) test_bit(ST_CAPT_RUN, &(dev)->state) |
71 | #define fimc_capture_pending(dev) test_bit(ST_CAPT_PEND, &(dev)->state) | |
e9e21083 | 72 | #define fimc_capture_busy(dev) test_bit(ST_CAPT_BUSY, &(dev)->state) |
5f3cc447 | 73 | |
5fd8f738 | 74 | enum fimc_datapath { |
5f3cc447 | 75 | FIMC_CAMERA, |
5fd8f738 SN |
76 | FIMC_DMA, |
77 | FIMC_LCDFIFO, | |
78 | FIMC_WRITEBACK | |
79 | }; | |
80 | ||
81 | enum fimc_color_fmt { | |
548aafcd | 82 | S5P_FIMC_RGB565 = 0x10, |
5fd8f738 SN |
83 | S5P_FIMC_RGB666, |
84 | S5P_FIMC_RGB888, | |
548aafcd SN |
85 | S5P_FIMC_RGB30_LOCAL, |
86 | S5P_FIMC_YCBCR420 = 0x20, | |
5fd8f738 SN |
87 | S5P_FIMC_YCBYCR422, |
88 | S5P_FIMC_YCRYCB422, | |
89 | S5P_FIMC_CBYCRY422, | |
90 | S5P_FIMC_CRYCBY422, | |
5fd8f738 | 91 | S5P_FIMC_YCBCR444_LOCAL, |
5fd8f738 SN |
92 | }; |
93 | ||
548aafcd SN |
94 | #define fimc_fmt_is_rgb(x) ((x) & 0x10) |
95 | ||
5fd8f738 SN |
96 | /* Cb/Cr chrominance components order for 2 plane Y/CbCr 4:2:2 formats. */ |
97 | #define S5P_FIMC_LSB_CRCB S5P_CIOCTRL_ORDER422_2P_LSB_CRCB | |
98 | ||
99 | /* The embedded image effect selection */ | |
100 | #define S5P_FIMC_EFFECT_ORIGINAL S5P_CIIMGEFF_FIN_BYPASS | |
101 | #define S5P_FIMC_EFFECT_ARBITRARY S5P_CIIMGEFF_FIN_ARBITRARY | |
102 | #define S5P_FIMC_EFFECT_NEGATIVE S5P_CIIMGEFF_FIN_NEGATIVE | |
103 | #define S5P_FIMC_EFFECT_ARTFREEZE S5P_CIIMGEFF_FIN_ARTFREEZE | |
104 | #define S5P_FIMC_EFFECT_EMBOSSING S5P_CIIMGEFF_FIN_EMBOSSING | |
105 | #define S5P_FIMC_EFFECT_SIKHOUETTE S5P_CIIMGEFF_FIN_SILHOUETTE | |
106 | ||
107 | /* The hardware context state. */ | |
548aafcd SN |
108 | #define FIMC_PARAMS (1 << 0) |
109 | #define FIMC_SRC_ADDR (1 << 1) | |
110 | #define FIMC_DST_ADDR (1 << 2) | |
111 | #define FIMC_SRC_FMT (1 << 3) | |
112 | #define FIMC_DST_FMT (1 << 4) | |
113 | #define FIMC_CTX_M2M (1 << 5) | |
114 | #define FIMC_CTX_CAP (1 << 6) | |
4ecbf5d1 | 115 | #define FIMC_CTX_SHUT (1 << 7) |
5fd8f738 SN |
116 | |
117 | /* Image conversion flags */ | |
118 | #define FIMC_IN_DMA_ACCESS_TILED (1 << 0) | |
119 | #define FIMC_IN_DMA_ACCESS_LINEAR (0 << 0) | |
120 | #define FIMC_OUT_DMA_ACCESS_TILED (1 << 1) | |
121 | #define FIMC_OUT_DMA_ACCESS_LINEAR (0 << 1) | |
122 | #define FIMC_SCAN_MODE_PROGRESSIVE (0 << 2) | |
123 | #define FIMC_SCAN_MODE_INTERLACED (1 << 2) | |
548aafcd SN |
124 | /* |
125 | * YCbCr data dynamic range for RGB-YUV color conversion. | |
126 | * Y/Cb/Cr: (0 ~ 255) */ | |
5fd8f738 SN |
127 | #define FIMC_COLOR_RANGE_WIDE (0 << 3) |
128 | /* Y (16 ~ 235), Cb/Cr (16 ~ 240) */ | |
129 | #define FIMC_COLOR_RANGE_NARROW (1 << 3) | |
130 | ||
131 | #define FLIP_NONE 0 | |
132 | #define FLIP_X_AXIS 1 | |
133 | #define FLIP_Y_AXIS 2 | |
134 | #define FLIP_XY_AXIS (FLIP_X_AXIS | FLIP_Y_AXIS) | |
135 | ||
136 | /** | |
137 | * struct fimc_fmt - the driver's internal color format data | |
5f3cc447 | 138 | * @mbus_code: Media Bus pixel code, -1 if not applicable |
5fd8f738 | 139 | * @name: format description |
5f3cc447 | 140 | * @fourcc: the fourcc code for this format, 0 if not applicable |
5fd8f738 | 141 | * @color: the corresponding fimc_color_fmt |
ef7af59b SN |
142 | * @memplanes: number of physically non-contiguous data planes |
143 | * @colplanes: number of physically contiguous data planes | |
3495dcef SN |
144 | * @depth: per plane driver's private 'number of bits per pixel' |
145 | * @flags: flags indicating which operation mode format applies to | |
5fd8f738 SN |
146 | */ |
147 | struct fimc_fmt { | |
5f3cc447 | 148 | enum v4l2_mbus_pixelcode mbus_code; |
5fd8f738 SN |
149 | char *name; |
150 | u32 fourcc; | |
151 | u32 color; | |
ef7af59b SN |
152 | u16 memplanes; |
153 | u16 colplanes; | |
154 | u8 depth[VIDEO_MAX_PLANES]; | |
5f3cc447 SN |
155 | u16 flags; |
156 | #define FMT_FLAGS_CAM (1 << 0) | |
157 | #define FMT_FLAGS_M2M (1 << 1) | |
5fd8f738 SN |
158 | }; |
159 | ||
160 | /** | |
161 | * struct fimc_dma_offset - pixel offset information for DMA | |
162 | * @y_h: y value horizontal offset | |
163 | * @y_v: y value vertical offset | |
164 | * @cb_h: cb value horizontal offset | |
165 | * @cb_v: cb value vertical offset | |
166 | * @cr_h: cr value horizontal offset | |
167 | * @cr_v: cr value vertical offset | |
168 | */ | |
169 | struct fimc_dma_offset { | |
170 | int y_h; | |
171 | int y_v; | |
172 | int cb_h; | |
173 | int cb_v; | |
174 | int cr_h; | |
175 | int cr_v; | |
176 | }; | |
177 | ||
178 | /** | |
3495dcef | 179 | * struct fimc_effect - color effect information |
5fd8f738 SN |
180 | * @type: effect type |
181 | * @pat_cb: cr value when type is "arbitrary" | |
182 | * @pat_cr: cr value when type is "arbitrary" | |
183 | */ | |
184 | struct fimc_effect { | |
185 | u32 type; | |
186 | u8 pat_cb; | |
187 | u8 pat_cr; | |
188 | }; | |
189 | ||
190 | /** | |
191 | * struct fimc_scaler - the configuration data for FIMC inetrnal scaler | |
548aafcd SN |
192 | * @scaleup_h: flag indicating scaling up horizontally |
193 | * @scaleup_v: flag indicating scaling up vertically | |
194 | * @copy_mode: flag indicating transparent DMA transfer (no scaling | |
195 | * and color format conversion) | |
196 | * @enabled: flag indicating if the scaler is used | |
5fd8f738 SN |
197 | * @hfactor: horizontal shift factor |
198 | * @vfactor: vertical shift factor | |
199 | * @pre_hratio: horizontal ratio of the prescaler | |
200 | * @pre_vratio: vertical ratio of the prescaler | |
201 | * @pre_dst_width: the prescaler's destination width | |
202 | * @pre_dst_height: the prescaler's destination height | |
5fd8f738 SN |
203 | * @main_hratio: the main scaler's horizontal ratio |
204 | * @main_vratio: the main scaler's vertical ratio | |
548aafcd SN |
205 | * @real_width: source pixel (width - offset) |
206 | * @real_height: source pixel (height - offset) | |
5fd8f738 SN |
207 | */ |
208 | struct fimc_scaler { | |
dda7ae78 SN |
209 | unsigned int scaleup_h:1; |
210 | unsigned int scaleup_v:1; | |
211 | unsigned int copy_mode:1; | |
212 | unsigned int enabled:1; | |
5fd8f738 SN |
213 | u32 hfactor; |
214 | u32 vfactor; | |
215 | u32 pre_hratio; | |
216 | u32 pre_vratio; | |
217 | u32 pre_dst_width; | |
218 | u32 pre_dst_height; | |
5fd8f738 SN |
219 | u32 main_hratio; |
220 | u32 main_vratio; | |
221 | u32 real_width; | |
222 | u32 real_height; | |
5fd8f738 SN |
223 | }; |
224 | ||
225 | /** | |
226 | * struct fimc_addr - the FIMC physical address set for DMA | |
5fd8f738 SN |
227 | * @y: luminance plane physical address |
228 | * @cb: Cb plane physical address | |
229 | * @cr: Cr plane physical address | |
230 | */ | |
231 | struct fimc_addr { | |
232 | u32 y; | |
233 | u32 cb; | |
234 | u32 cr; | |
235 | }; | |
236 | ||
237 | /** | |
238 | * struct fimc_vid_buffer - the driver's video buffer | |
5f3cc447 | 239 | * @vb: v4l videobuf buffer |
3495dcef | 240 | * @list: linked list structure for buffer queue |
5f3cc447 SN |
241 | * @paddr: precalculated physical address set |
242 | * @index: buffer index for the output DMA engine | |
5fd8f738 SN |
243 | */ |
244 | struct fimc_vid_buffer { | |
2dab38e2 SN |
245 | struct vb2_buffer vb; |
246 | struct list_head list; | |
5f3cc447 SN |
247 | struct fimc_addr paddr; |
248 | int index; | |
5fd8f738 SN |
249 | }; |
250 | ||
251 | /** | |
548aafcd | 252 | * struct fimc_frame - source/target frame properties |
5fd8f738 SN |
253 | * @f_width: image full width (virtual screen size) |
254 | * @f_height: image full height (virtual screen size) | |
255 | * @o_width: original image width as set by S_FMT | |
256 | * @o_height: original image height as set by S_FMT | |
257 | * @offs_h: image horizontal pixel offset | |
258 | * @offs_v: image vertical pixel offset | |
259 | * @width: image pixel width | |
260 | * @height: image pixel weight | |
ef7af59b | 261 | * @payload: image size in bytes (w x h x bpp) |
3495dcef | 262 | * @paddr: image frame buffer physical addresses |
5fd8f738 | 263 | * @dma_offset: DMA offset in bytes |
3495dcef | 264 | * @fmt: fimc color format pointer |
5fd8f738 SN |
265 | */ |
266 | struct fimc_frame { | |
267 | u32 f_width; | |
268 | u32 f_height; | |
269 | u32 o_width; | |
270 | u32 o_height; | |
271 | u32 offs_h; | |
272 | u32 offs_v; | |
273 | u32 width; | |
274 | u32 height; | |
ef7af59b | 275 | unsigned long payload[VIDEO_MAX_PLANES]; |
5fd8f738 SN |
276 | struct fimc_addr paddr; |
277 | struct fimc_dma_offset dma_offset; | |
278 | struct fimc_fmt *fmt; | |
279 | }; | |
280 | ||
281 | /** | |
282 | * struct fimc_m2m_device - v4l2 memory-to-memory device data | |
283 | * @vfd: the video device node for v4l2 m2m mode | |
5fd8f738 SN |
284 | * @m2m_dev: v4l2 memory-to-memory device data |
285 | * @ctx: hardware context data | |
286 | * @refcnt: the reference counter | |
287 | */ | |
288 | struct fimc_m2m_device { | |
289 | struct video_device *vfd; | |
5fd8f738 SN |
290 | struct v4l2_m2m_dev *m2m_dev; |
291 | struct fimc_ctx *ctx; | |
292 | int refcnt; | |
293 | }; | |
294 | ||
5f3cc447 SN |
295 | /** |
296 | * struct fimc_vid_cap - camera capture device information | |
297 | * @ctx: hardware context data | |
298 | * @vfd: video device node for camera capture mode | |
5f3cc447 | 299 | * @sd: pointer to camera sensor subdevice currently in use |
574e1717 | 300 | * @vd_pad: fimc video capture node pad |
5f3cc447 SN |
301 | * @fmt: Media Bus format configured at selected image sensor |
302 | * @pending_buf_q: the pending buffer queue head | |
303 | * @active_buf_q: the queue head of buffers scheduled in hardware | |
304 | * @vbq: the capture am video buffer queue | |
305 | * @active_buf_cnt: number of video buffers scheduled in hardware | |
306 | * @buf_index: index for managing the output DMA buffers | |
307 | * @frame_count: the frame counter for statistics | |
308 | * @reqbufs_count: the number of buffers requested in REQBUFS ioctl | |
309 | * @input_index: input (camera sensor) index | |
310 | * @refcnt: driver's private reference counter | |
311 | */ | |
312 | struct fimc_vid_cap { | |
313 | struct fimc_ctx *ctx; | |
2dab38e2 | 314 | struct vb2_alloc_ctx *alloc_ctx; |
5f3cc447 | 315 | struct video_device *vfd; |
2dab38e2 | 316 | struct v4l2_subdev *sd;; |
574e1717 | 317 | struct media_pad vd_pad; |
5f3cc447 SN |
318 | struct v4l2_mbus_framefmt fmt; |
319 | struct list_head pending_buf_q; | |
320 | struct list_head active_buf_q; | |
2dab38e2 | 321 | struct vb2_queue vbq; |
5f3cc447 SN |
322 | int active_buf_cnt; |
323 | int buf_index; | |
324 | unsigned int frame_count; | |
325 | unsigned int reqbufs_count; | |
326 | int input_index; | |
327 | int refcnt; | |
328 | }; | |
329 | ||
a7d5bbcf SN |
330 | /** |
331 | * struct fimc_pix_limit - image pixel size limits in various IP configurations | |
332 | * | |
333 | * @scaler_en_w: max input pixel width when the scaler is enabled | |
334 | * @scaler_dis_w: max input pixel width when the scaler is disabled | |
335 | * @in_rot_en_h: max input width with the input rotator is on | |
336 | * @in_rot_dis_w: max input width with the input rotator is off | |
337 | * @out_rot_en_w: max output width with the output rotator on | |
338 | * @out_rot_dis_w: max output width with the output rotator off | |
339 | */ | |
340 | struct fimc_pix_limit { | |
341 | u16 scaler_en_w; | |
342 | u16 scaler_dis_w; | |
343 | u16 in_rot_en_h; | |
344 | u16 in_rot_dis_w; | |
345 | u16 out_rot_en_w; | |
346 | u16 out_rot_dis_w; | |
347 | }; | |
348 | ||
5fd8f738 SN |
349 | /** |
350 | * struct samsung_fimc_variant - camera interface variant information | |
351 | * | |
352 | * @pix_hoff: indicate whether horizontal offset is in pixels or in bytes | |
353 | * @has_inp_rot: set if has input rotator | |
354 | * @has_out_rot: set if has output rotator | |
798174ab | 355 | * @has_cistatus2: 1 if CISTATUS2 register is present in this IP revision |
b241c6d6 HK |
356 | * @has_mainscaler_ext: 1 if extended mainscaler ratios in CIEXTEN register |
357 | * are present in this IP revision | |
a7d5bbcf | 358 | * @pix_limit: pixel size constraints for the scaler |
5fd8f738 SN |
359 | * @min_inp_pixsize: minimum input pixel size |
360 | * @min_out_pixsize: minimum output pixel size | |
a7d5bbcf SN |
361 | * @hor_offs_align: horizontal pixel offset aligment |
362 | * @out_buf_count: the number of buffers in output DMA sequence | |
5fd8f738 SN |
363 | */ |
364 | struct samsung_fimc_variant { | |
365 | unsigned int pix_hoff:1; | |
366 | unsigned int has_inp_rot:1; | |
367 | unsigned int has_out_rot:1; | |
798174ab | 368 | unsigned int has_cistatus2:1; |
b241c6d6 | 369 | unsigned int has_mainscaler_ext:1; |
a7d5bbcf | 370 | struct fimc_pix_limit *pix_limit; |
5fd8f738 SN |
371 | u16 min_inp_pixsize; |
372 | u16 min_out_pixsize; | |
a7d5bbcf SN |
373 | u16 hor_offs_align; |
374 | u16 out_buf_count; | |
5fd8f738 SN |
375 | }; |
376 | ||
377 | /** | |
548aafcd | 378 | * struct samsung_fimc_driverdata - per device type driver data for init time. |
5fd8f738 SN |
379 | * |
380 | * @variant: the variant information for this driver. | |
381 | * @dev_cnt: number of fimc sub-devices available in SoC | |
5f3cc447 | 382 | * @lclk_frequency: fimc bus clock frequency |
5fd8f738 SN |
383 | */ |
384 | struct samsung_fimc_driverdata { | |
385 | struct samsung_fimc_variant *variant[FIMC_MAX_DEVS]; | |
5f3cc447 | 386 | unsigned long lclk_frequency; |
a7d5bbcf | 387 | int num_entities; |
5fd8f738 SN |
388 | }; |
389 | ||
390 | struct fimc_ctx; | |
391 | ||
392 | /** | |
548aafcd | 393 | * struct fimc_dev - abstraction for FIMC entity |
5fd8f738 SN |
394 | * @slock: the spinlock protecting this data structure |
395 | * @lock: the mutex protecting this data structure | |
396 | * @pdev: pointer to the FIMC platform device | |
5f3cc447 | 397 | * @pdata: pointer to the device platform data |
3495dcef | 398 | * @variant: the IP variant information |
a25be18d SN |
399 | * @id: FIMC device index (0..FIMC_MAX_DEVS) |
400 | * @num_clocks: the number of clocks managed by this device instance | |
3495dcef | 401 | * @clock: clocks required for FIMC operation |
5fd8f738 SN |
402 | * @regs: the mapped hardware registers |
403 | * @regs_res: the resource claimed for IO registers | |
3495dcef SN |
404 | * @irq: FIMC interrupt number |
405 | * @irq_queue: interrupt handler waitqueue | |
30c9939d | 406 | * @v4l2_dev: root v4l2_device |
5fd8f738 | 407 | * @m2m: memory-to-memory V4L2 device information |
5f3cc447 SN |
408 | * @vid_cap: camera capture device information |
409 | * @state: flags used to synchronize m2m and capture mode operation | |
3495dcef | 410 | * @alloc_ctx: videobuf2 memory allocator context |
5fd8f738 SN |
411 | */ |
412 | struct fimc_dev { | |
413 | spinlock_t slock; | |
414 | struct mutex lock; | |
415 | struct platform_device *pdev; | |
df7e09a3 | 416 | struct s5p_platform_fimc *pdata; |
5fd8f738 | 417 | struct samsung_fimc_variant *variant; |
a25be18d SN |
418 | u16 id; |
419 | u16 num_clocks; | |
420 | struct clk *clock[MAX_FIMC_CLOCKS]; | |
5fd8f738 SN |
421 | void __iomem *regs; |
422 | struct resource *regs_res; | |
423 | int irq; | |
5f3cc447 | 424 | wait_queue_head_t irq_queue; |
30c9939d | 425 | struct v4l2_device *v4l2_dev; |
5fd8f738 | 426 | struct fimc_m2m_device m2m; |
5f3cc447 | 427 | struct fimc_vid_cap vid_cap; |
5fd8f738 | 428 | unsigned long state; |
2dab38e2 | 429 | struct vb2_alloc_ctx *alloc_ctx; |
5fd8f738 SN |
430 | }; |
431 | ||
432 | /** | |
433 | * fimc_ctx - the device context data | |
3495dcef | 434 | * @slock: spinlock protecting this data structure |
5fd8f738 SN |
435 | * @s_frame: source frame properties |
436 | * @d_frame: destination frame properties | |
437 | * @out_order_1p: output 1-plane YCBCR order | |
438 | * @out_order_2p: output 2-plane YCBCR order | |
439 | * @in_order_1p input 1-plane YCBCR order | |
440 | * @in_order_2p: input 2-plane YCBCR order | |
441 | * @in_path: input mode (DMA or camera) | |
442 | * @out_path: output mode (DMA or FIFO) | |
443 | * @scaler: image scaler properties | |
444 | * @effect: image effect | |
445 | * @rotation: image clockwise rotation in degrees | |
446 | * @flip: image flip mode | |
548aafcd | 447 | * @flags: additional flags for image conversion |
5fd8f738 SN |
448 | * @state: flags to keep track of user configuration |
449 | * @fimc_dev: the FIMC device this context applies to | |
450 | * @m2m_ctx: memory-to-memory device context | |
451 | */ | |
452 | struct fimc_ctx { | |
453 | spinlock_t slock; | |
454 | struct fimc_frame s_frame; | |
455 | struct fimc_frame d_frame; | |
456 | u32 out_order_1p; | |
457 | u32 out_order_2p; | |
458 | u32 in_order_1p; | |
459 | u32 in_order_2p; | |
460 | enum fimc_datapath in_path; | |
461 | enum fimc_datapath out_path; | |
462 | struct fimc_scaler scaler; | |
463 | struct fimc_effect effect; | |
464 | int rotation; | |
465 | u32 flip; | |
466 | u32 flags; | |
467 | u32 state; | |
468 | struct fimc_dev *fimc_dev; | |
469 | struct v4l2_m2m_ctx *m2m_ctx; | |
470 | }; | |
471 | ||
4ecbf5d1 SN |
472 | static inline bool fimc_capture_active(struct fimc_dev *fimc) |
473 | { | |
474 | unsigned long flags; | |
475 | bool ret; | |
476 | ||
477 | spin_lock_irqsave(&fimc->slock, flags); | |
478 | ret = !!(fimc->state & (1 << ST_CAPT_RUN) || | |
479 | fimc->state & (1 << ST_CAPT_PEND)); | |
480 | spin_unlock_irqrestore(&fimc->slock, flags); | |
481 | return ret; | |
482 | } | |
483 | ||
484 | static inline void fimc_ctx_state_lock_set(u32 state, struct fimc_ctx *ctx) | |
485 | { | |
486 | unsigned long flags; | |
487 | ||
488 | spin_lock_irqsave(&ctx->slock, flags); | |
489 | ctx->state |= state; | |
490 | spin_unlock_irqrestore(&ctx->slock, flags); | |
491 | } | |
492 | ||
493 | static inline bool fimc_ctx_state_is_set(u32 mask, struct fimc_ctx *ctx) | |
494 | { | |
495 | unsigned long flags; | |
496 | bool ret; | |
497 | ||
498 | spin_lock_irqsave(&ctx->slock, flags); | |
499 | ret = (ctx->state & mask) == mask; | |
500 | spin_unlock_irqrestore(&ctx->slock, flags); | |
501 | return ret; | |
502 | } | |
503 | ||
5fd8f738 SN |
504 | static inline int tiled_fmt(struct fimc_fmt *fmt) |
505 | { | |
ef7af59b | 506 | return fmt->fourcc == V4L2_PIX_FMT_NV12MT; |
5fd8f738 SN |
507 | } |
508 | ||
509 | static inline void fimc_hw_clear_irq(struct fimc_dev *dev) | |
510 | { | |
511 | u32 cfg = readl(dev->regs + S5P_CIGCTRL); | |
512 | cfg |= S5P_CIGCTRL_IRQ_CLR; | |
513 | writel(cfg, dev->regs + S5P_CIGCTRL); | |
514 | } | |
515 | ||
548aafcd | 516 | static inline void fimc_hw_enable_scaler(struct fimc_dev *dev, bool on) |
5fd8f738 SN |
517 | { |
518 | u32 cfg = readl(dev->regs + S5P_CISCCTRL); | |
548aafcd SN |
519 | if (on) |
520 | cfg |= S5P_CISCCTRL_SCALERSTART; | |
521 | else | |
522 | cfg &= ~S5P_CISCCTRL_SCALERSTART; | |
5fd8f738 SN |
523 | writel(cfg, dev->regs + S5P_CISCCTRL); |
524 | } | |
525 | ||
548aafcd | 526 | static inline void fimc_hw_activate_input_dma(struct fimc_dev *dev, bool on) |
5fd8f738 | 527 | { |
548aafcd SN |
528 | u32 cfg = readl(dev->regs + S5P_MSCTRL); |
529 | if (on) | |
530 | cfg |= S5P_MSCTRL_ENVID; | |
531 | else | |
532 | cfg &= ~S5P_MSCTRL_ENVID; | |
533 | writel(cfg, dev->regs + S5P_MSCTRL); | |
5fd8f738 SN |
534 | } |
535 | ||
536 | static inline void fimc_hw_dis_capture(struct fimc_dev *dev) | |
537 | { | |
538 | u32 cfg = readl(dev->regs + S5P_CIIMGCPT); | |
539 | cfg &= ~(S5P_CIIMGCPT_IMGCPTEN | S5P_CIIMGCPT_IMGCPTEN_SC); | |
540 | writel(cfg, dev->regs + S5P_CIIMGCPT); | |
541 | } | |
542 | ||
a7d5bbcf SN |
543 | /** |
544 | * fimc_hw_set_dma_seq - configure output DMA buffer sequence | |
545 | * @mask: each bit corresponds to one of 32 output buffer registers set | |
546 | * 1 to include buffer in the sequence, 0 to disable | |
547 | * | |
548 | * This function mask output DMA ring buffers, i.e. it allows to configure | |
549 | * which of the output buffer address registers will be used by the DMA | |
550 | * engine. | |
551 | */ | |
552 | static inline void fimc_hw_set_dma_seq(struct fimc_dev *dev, u32 mask) | |
553 | { | |
554 | writel(mask, dev->regs + S5P_CIFCNTSEQ); | |
555 | } | |
556 | ||
548aafcd SN |
557 | static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx, |
558 | enum v4l2_buf_type type) | |
03e30ca5 PO |
559 | { |
560 | struct fimc_frame *frame; | |
561 | ||
ef7af59b | 562 | if (V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE == type) { |
4ecbf5d1 | 563 | if (fimc_ctx_state_is_set(FIMC_CTX_M2M, ctx)) |
5f3cc447 SN |
564 | frame = &ctx->s_frame; |
565 | else | |
566 | return ERR_PTR(-EINVAL); | |
ef7af59b | 567 | } else if (V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE == type) { |
03e30ca5 PO |
568 | frame = &ctx->d_frame; |
569 | } else { | |
30c9939d | 570 | v4l2_err(ctx->fimc_dev->v4l2_dev, |
03e30ca5 PO |
571 | "Wrong buffer/video queue type (%d)\n", type); |
572 | return ERR_PTR(-EINVAL); | |
573 | } | |
574 | ||
575 | return frame; | |
576 | } | |
577 | ||
798174ab | 578 | /* Return an index to the buffer actually being written. */ |
5f3cc447 SN |
579 | static inline u32 fimc_hw_get_frame_index(struct fimc_dev *dev) |
580 | { | |
798174ab SN |
581 | u32 reg; |
582 | ||
583 | if (dev->variant->has_cistatus2) { | |
584 | reg = readl(dev->regs + S5P_CISTATUS2) & 0x3F; | |
585 | return reg > 0 ? --reg : reg; | |
586 | } else { | |
587 | reg = readl(dev->regs + S5P_CISTATUS); | |
588 | return (reg & S5P_CISTATUS_FRAMECNT_MASK) >> | |
589 | S5P_CISTATUS_FRAMECNT_SHIFT; | |
590 | } | |
5f3cc447 SN |
591 | } |
592 | ||
5fd8f738 SN |
593 | /* -----------------------------------------------------*/ |
594 | /* fimc-reg.c */ | |
548aafcd | 595 | void fimc_hw_reset(struct fimc_dev *fimc); |
5fd8f738 SN |
596 | void fimc_hw_set_rotation(struct fimc_ctx *ctx); |
597 | void fimc_hw_set_target_format(struct fimc_ctx *ctx); | |
598 | void fimc_hw_set_out_dma(struct fimc_ctx *ctx); | |
548aafcd SN |
599 | void fimc_hw_en_lastirq(struct fimc_dev *fimc, int enable); |
600 | void fimc_hw_en_irq(struct fimc_dev *fimc, int enable); | |
b241c6d6 HK |
601 | void fimc_hw_set_prescaler(struct fimc_ctx *ctx); |
602 | void fimc_hw_set_mainscaler(struct fimc_ctx *ctx); | |
5fd8f738 SN |
603 | void fimc_hw_en_capture(struct fimc_ctx *ctx); |
604 | void fimc_hw_set_effect(struct fimc_ctx *ctx); | |
605 | void fimc_hw_set_in_dma(struct fimc_ctx *ctx); | |
606 | void fimc_hw_set_input_path(struct fimc_ctx *ctx); | |
607 | void fimc_hw_set_output_path(struct fimc_ctx *ctx); | |
548aafcd SN |
608 | void fimc_hw_set_input_addr(struct fimc_dev *fimc, struct fimc_addr *paddr); |
609 | void fimc_hw_set_output_addr(struct fimc_dev *fimc, struct fimc_addr *paddr, | |
ef7af59b | 610 | int index); |
5f3cc447 | 611 | int fimc_hw_set_camera_source(struct fimc_dev *fimc, |
df7e09a3 | 612 | struct s5p_fimc_isp_info *cam); |
5f3cc447 SN |
613 | int fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f); |
614 | int fimc_hw_set_camera_polarity(struct fimc_dev *fimc, | |
df7e09a3 | 615 | struct s5p_fimc_isp_info *cam); |
5f3cc447 | 616 | int fimc_hw_set_camera_type(struct fimc_dev *fimc, |
df7e09a3 | 617 | struct s5p_fimc_isp_info *cam); |
5f3cc447 SN |
618 | |
619 | /* -----------------------------------------------------*/ | |
620 | /* fimc-core.c */ | |
ef7af59b SN |
621 | int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv, |
622 | struct v4l2_fmtdesc *f); | |
623 | int fimc_vidioc_g_fmt_mplane(struct file *file, void *priv, | |
624 | struct v4l2_format *f); | |
625 | int fimc_vidioc_try_fmt_mplane(struct file *file, void *priv, | |
626 | struct v4l2_format *f); | |
5f3cc447 SN |
627 | int fimc_vidioc_queryctrl(struct file *file, void *priv, |
628 | struct v4l2_queryctrl *qc); | |
629 | int fimc_vidioc_g_ctrl(struct file *file, void *priv, | |
630 | struct v4l2_control *ctrl); | |
631 | ||
632 | int fimc_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr); | |
633 | int check_ctrl_val(struct fimc_ctx *ctx, struct v4l2_control *ctrl); | |
634 | int fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_control *ctrl); | |
635 | ||
636 | struct fimc_fmt *find_format(struct v4l2_format *f, unsigned int mask); | |
637 | struct fimc_fmt *find_mbus_format(struct v4l2_mbus_framefmt *f, | |
638 | unsigned int mask); | |
639 | ||
1b09f292 | 640 | int fimc_check_scaler_ratio(int sw, int sh, int dw, int dh, int rot); |
5f3cc447 SN |
641 | int fimc_set_scaler_info(struct fimc_ctx *ctx); |
642 | int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags); | |
2dab38e2 | 643 | int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb, |
5f3cc447 | 644 | struct fimc_frame *frame, struct fimc_addr *paddr); |
30c9939d SN |
645 | int fimc_register_m2m_device(struct fimc_dev *fimc, |
646 | struct v4l2_device *v4l2_dev); | |
647 | void fimc_unregister_m2m_device(struct fimc_dev *fimc); | |
5f3cc447 SN |
648 | |
649 | /* -----------------------------------------------------*/ | |
650 | /* fimc-capture.c */ | |
30c9939d SN |
651 | int fimc_register_capture_device(struct fimc_dev *fimc, |
652 | struct v4l2_device *v4l2_dev); | |
5f3cc447 | 653 | void fimc_unregister_capture_device(struct fimc_dev *fimc); |
5f3cc447 SN |
654 | int fimc_vid_cap_buf_queue(struct fimc_dev *fimc, |
655 | struct fimc_vid_buffer *fimc_vb); | |
e9e21083 SN |
656 | int fimc_capture_suspend(struct fimc_dev *fimc); |
657 | int fimc_capture_resume(struct fimc_dev *fimc); | |
548aafcd SN |
658 | |
659 | /* Locking: the caller holds fimc->slock */ | |
660 | static inline void fimc_activate_capture(struct fimc_ctx *ctx) | |
661 | { | |
662 | fimc_hw_enable_scaler(ctx->fimc_dev, ctx->scaler.enabled); | |
663 | fimc_hw_en_capture(ctx); | |
664 | } | |
665 | ||
666 | static inline void fimc_deactivate_capture(struct fimc_dev *fimc) | |
667 | { | |
668 | fimc_hw_en_lastirq(fimc, true); | |
669 | fimc_hw_dis_capture(fimc); | |
670 | fimc_hw_enable_scaler(fimc, false); | |
671 | fimc_hw_en_lastirq(fimc, false); | |
672 | } | |
5fd8f738 | 673 | |
5f3cc447 | 674 | /* |
2dab38e2 SN |
675 | * Add buf to the capture active buffers queue. |
676 | * Locking: Need to be called with fimc_dev::slock held. | |
5f3cc447 SN |
677 | */ |
678 | static inline void active_queue_add(struct fimc_vid_cap *vid_cap, | |
2dab38e2 | 679 | struct fimc_vid_buffer *buf) |
5f3cc447 | 680 | { |
2dab38e2 | 681 | list_add_tail(&buf->list, &vid_cap->active_buf_q); |
5f3cc447 SN |
682 | vid_cap->active_buf_cnt++; |
683 | } | |
684 | ||
685 | /* | |
686 | * Pop a video buffer from the capture active buffers queue | |
2dab38e2 | 687 | * Locking: Need to be called with fimc_dev::slock held. |
5f3cc447 SN |
688 | */ |
689 | static inline struct fimc_vid_buffer * | |
690 | active_queue_pop(struct fimc_vid_cap *vid_cap) | |
691 | { | |
692 | struct fimc_vid_buffer *buf; | |
693 | buf = list_entry(vid_cap->active_buf_q.next, | |
2dab38e2 SN |
694 | struct fimc_vid_buffer, list); |
695 | list_del(&buf->list); | |
5f3cc447 SN |
696 | vid_cap->active_buf_cnt--; |
697 | return buf; | |
698 | } | |
699 | ||
700 | /* Add video buffer to the capture pending buffers queue */ | |
701 | static inline void fimc_pending_queue_add(struct fimc_vid_cap *vid_cap, | |
702 | struct fimc_vid_buffer *buf) | |
703 | { | |
2dab38e2 | 704 | list_add_tail(&buf->list, &vid_cap->pending_buf_q); |
5f3cc447 SN |
705 | } |
706 | ||
707 | /* Add video buffer to the capture pending buffers queue */ | |
708 | static inline struct fimc_vid_buffer * | |
709 | pending_queue_pop(struct fimc_vid_cap *vid_cap) | |
710 | { | |
711 | struct fimc_vid_buffer *buf; | |
712 | buf = list_entry(vid_cap->pending_buf_q.next, | |
2dab38e2 SN |
713 | struct fimc_vid_buffer, list); |
714 | list_del(&buf->list); | |
5f3cc447 SN |
715 | return buf; |
716 | } | |
717 | ||
5fd8f738 | 718 | #endif /* FIMC_CORE_H_ */ |