[deliverable/linux.git] / drivers / media / video / s5p-fimc / fimc-core.h

/*
 * Copyright (c) 2010 Samsung Electronics
 *
 * Sylwester Nawrocki, <s.nawrocki@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef FIMC_CORE_H_
#define FIMC_CORE_H_

#include <linux/types.h>
#include <media/videobuf-core.h>
#include <media/v4l2-device.h>
#include <media/v4l2-mem2mem.h>
#include <linux/videodev2.h>
#include "regs-fimc.h"

#define err(fmt, args...) \
	printk(KERN_ERR "%s:%d: " fmt "\n", __func__, __LINE__, ##args)

#ifdef DEBUG
#define dbg(fmt, args...) \
	printk(KERN_DEBUG "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
#else
#define dbg(fmt, args...)
#endif

#define NUM_FIMC_CLOCKS		2
#define MODULE_NAME		"s5p-fimc"
#define FIMC_MAX_DEVS		3
#define FIMC_MAX_OUT_BUFS	4
#define SCALER_MAX_HRATIO	64
#define SCALER_MAX_VRATIO	64

enum {
	ST_IDLE,
	ST_OUTDMA_RUN,
	ST_M2M_PEND,
};

#define fimc_m2m_active(dev) test_bit(ST_OUTDMA_RUN, &(dev)->state)
#define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)

enum fimc_datapath {
	FIMC_ITU_CAM_A,
	FIMC_ITU_CAM_B,
	FIMC_MIPI_CAM,
	FIMC_DMA,
	FIMC_LCDFIFO,
	FIMC_WRITEBACK
};

enum fimc_color_fmt {
	S5P_FIMC_RGB565,
	S5P_FIMC_RGB666,
	S5P_FIMC_RGB888,
	S5P_FIMC_YCBCR420,
	S5P_FIMC_YCBCR422,
	S5P_FIMC_YCBYCR422,
	S5P_FIMC_YCRYCB422,
	S5P_FIMC_CBYCRY422,
	S5P_FIMC_CRYCBY422,
	S5P_FIMC_RGB30_LOCAL,
	S5P_FIMC_YCBCR444_LOCAL,
	S5P_FIMC_MAX_COLOR = S5P_FIMC_YCBCR444_LOCAL,
	S5P_FIMC_COLOR_MASK = 0x0F,
};

/* Y/Cb/Cr components order at DMA output for 1 plane YCbCr 4:2:2 formats. */
#define	S5P_FIMC_OUT_CRYCBY	S5P_CIOCTRL_ORDER422_CRYCBY
#define	S5P_FIMC_OUT_CBYCRY	S5P_CIOCTRL_ORDER422_YCRYCB
#define	S5P_FIMC_OUT_YCRYCB	S5P_CIOCTRL_ORDER422_CBYCRY
#define	S5P_FIMC_OUT_YCBYCR	S5P_CIOCTRL_ORDER422_YCBYCR

/* Input Y/Cb/Cr components order for 1 plane YCbCr 4:2:2 color formats. */
#define	S5P_FIMC_IN_CRYCBY	S5P_MSCTRL_ORDER422_CRYCBY
#define	S5P_FIMC_IN_CBYCRY	S5P_MSCTRL_ORDER422_YCRYCB
#define	S5P_FIMC_IN_YCRYCB	S5P_MSCTRL_ORDER422_CBYCRY
#define	S5P_FIMC_IN_YCBYCR	S5P_MSCTRL_ORDER422_YCBYCR

/* Cb/Cr chrominance components order for 2 plane Y/CbCr 4:2:2 formats. */
#define	S5P_FIMC_LSB_CRCB	S5P_CIOCTRL_ORDER422_2P_LSB_CRCB

/* The embedded image effect selection */
#define	S5P_FIMC_EFFECT_ORIGINAL	S5P_CIIMGEFF_FIN_BYPASS
#define	S5P_FIMC_EFFECT_ARBITRARY	S5P_CIIMGEFF_FIN_ARBITRARY
#define	S5P_FIMC_EFFECT_NEGATIVE	S5P_CIIMGEFF_FIN_NEGATIVE
#define	S5P_FIMC_EFFECT_ARTFREEZE	S5P_CIIMGEFF_FIN_ARTFREEZE
#define	S5P_FIMC_EFFECT_EMBOSSING	S5P_CIIMGEFF_FIN_EMBOSSING
#define	S5P_FIMC_EFFECT_SIKHOUETTE	S5P_CIIMGEFF_FIN_SILHOUETTE

/* The hardware context state. */
#define	FIMC_PARAMS			(1 << 0)
#define	FIMC_SRC_ADDR			(1 << 1)
#define	FIMC_DST_ADDR			(1 << 2)
#define	FIMC_SRC_FMT			(1 << 3)
#define	FIMC_DST_FMT			(1 << 4)

/* Image conversion flags */
#define	FIMC_IN_DMA_ACCESS_TILED	(1 << 0)
#define	FIMC_IN_DMA_ACCESS_LINEAR	(0 << 0)
#define	FIMC_OUT_DMA_ACCESS_TILED	(1 << 1)
#define	FIMC_OUT_DMA_ACCESS_LINEAR	(0 << 1)
#define	FIMC_SCAN_MODE_PROGRESSIVE	(0 << 2)
#define	FIMC_SCAN_MODE_INTERLACED	(1 << 2)
/* YCbCr data dynamic range for RGB-YUV color conversion. Y/Cb/Cr: (0 ~ 255) */
#define	FIMC_COLOR_RANGE_WIDE		(0 << 3)
/* Y (16 ~ 235), Cb/Cr (16 ~ 240) */
#define	FIMC_COLOR_RANGE_NARROW		(1 << 3)

#define	FLIP_NONE			0
#define	FLIP_X_AXIS			1
#define	FLIP_Y_AXIS			2
#define	FLIP_XY_AXIS			(FLIP_X_AXIS | FLIP_Y_AXIS)

/**
 * struct fimc_fmt - the driver's internal color format data
 * @name: format description
 * @fourcc: the fourcc code for this format
 * @color: the corresponding fimc_color_fmt
 * @depth: number of bits per pixel
 * @buff_cnt: number of physically non-contiguous data planes
 * @planes_cnt: number of physically contiguous data planes
 */
struct fimc_fmt {
	char	*name;
	u32	fourcc;
	u32	color;
	u32	depth;
	u16	buff_cnt;
	u16	planes_cnt;
};

/**
 * struct fimc_dma_offset - pixel offset information for DMA
 * @y_h:	y value horizontal offset
 * @y_v:	y value vertical offset
 * @cb_h:	cb value horizontal offset
 * @cb_v:	cb value vertical offset
 * @cr_h:	cr value horizontal offset
 * @cr_v:	cr value vertical offset
 */
struct fimc_dma_offset {
	int	y_h;
	int	y_v;
	int	cb_h;
	int	cb_v;
	int	cr_h;
	int	cr_v;
};

/**
 * struct fimc_effect - the configuration data for the "Arbitrary" image effect
 * @type:	effect type
 * @pat_cb:	cr value when type is "arbitrary"
 * @pat_cr:	cr value when type is "arbitrary"
 */
struct fimc_effect {
	u32	type;
	u8	pat_cb;
	u8	pat_cr;
};

/**
 * struct fimc_scaler - the configuration data for FIMC inetrnal scaler
 *
 * @enabled:		the flag set when the scaler is used
 * @hfactor:		horizontal shift factor
 * @vfactor:		vertical shift factor
 * @pre_hratio:		horizontal ratio of the prescaler
 * @pre_vratio:		vertical ratio of the prescaler
 * @pre_dst_width:	the prescaler's destination width
 * @pre_dst_height:	the prescaler's destination height
 * @scaleup_h:		flag indicating scaling up horizontally
 * @scaleup_v:		flag indicating scaling up vertically
 * @main_hratio:	the main scaler's horizontal ratio
 * @main_vratio:	the main scaler's vertical ratio
 * @real_width:		source width - offset
 * @real_height:	source height - offset
 * @copy_mode:		flag set if one-to-one mode is used, i.e. no scaling
 *			and color format conversion
 */
struct fimc_scaler {
	u32	enabled;
	u32	hfactor;
	u32	vfactor;
	u32	pre_hratio;
	u32	pre_vratio;
	u32	pre_dst_width;
	u32	pre_dst_height;
	u32	scaleup_h;
	u32	scaleup_v;
	u32	main_hratio;
	u32	main_vratio;
	u32	real_width;
	u32	real_height;
	u32	copy_mode;
};

/**
 * struct fimc_addr - the FIMC physical address set for DMA
 *
 * @y:	 luminance plane physical address
 * @cb:	 Cb plane physical address
 * @cr:	 Cr plane physical address
 */
struct fimc_addr {
	u32	y;
	u32	cb;
	u32	cr;
};

/**
 * struct fimc_vid_buffer - the driver's video buffer
 * @vb:	v4l videobuf buffer
 */
struct fimc_vid_buffer {
	struct videobuf_buffer	vb;
};

/**
 * struct fimc_frame - input/output frame format properties
 *
 * @f_width:	image full width (virtual screen size)
 * @f_height:	image full height (virtual screen size)
 * @o_width:	original image width as set by S_FMT
 * @o_height:	original image height as set by S_FMT
 * @offs_h:	image horizontal pixel offset
 * @offs_v:	image vertical pixel offset
 * @width:	image pixel width
 * @height:	image pixel weight
 * @paddr:	image frame buffer physical addresses
 * @buf_cnt:	number of buffers depending on a color format
 * @size:	image size in bytes
 * @color:	color format
 * @dma_offset:	DMA offset in bytes
 */
struct fimc_frame {
	u32	f_width;
	u32	f_height;
	u32	o_width;
	u32	o_height;
	u32	offs_h;
	u32	offs_v;
	u32	width;
	u32	height;
	u32	size;
	struct fimc_addr	paddr;
	struct fimc_dma_offset	dma_offset;
	struct fimc_fmt		*fmt;
};

/**
 * struct fimc_m2m_device - v4l2 memory-to-memory device data
 * @vfd: the video device node for v4l2 m2m mode
 * @v4l2_dev: v4l2 device for m2m mode
 * @m2m_dev: v4l2 memory-to-memory device data
 * @ctx: hardware context data
 * @refcnt: the reference counter
 */
struct fimc_m2m_device {
	struct video_device	*vfd;
	struct v4l2_device	v4l2_dev;
	struct v4l2_m2m_dev	*m2m_dev;
	struct fimc_ctx		*ctx;
	int			refcnt;
};

/**
 * struct samsung_fimc_variant - camera interface variant information
 *
 * @pix_hoff: indicate whether horizontal offset is in pixels or in bytes
 * @has_inp_rot: set if has input rotator
 * @has_out_rot: set if has output rotator
 * @min_inp_pixsize: minimum input pixel size
 * @min_out_pixsize: minimum output pixel size
 * @scaler_en_w: maximum input pixel width when the scaler is enabled
 * @scaler_dis_w: maximum input pixel width when the scaler is disabled
 * @in_rot_en_h: maximum input width when the input rotator is used
 * @in_rot_dis_w: maximum input width when the input rotator is used
 * @out_rot_en_w: maximum output width for the output rotator enabled
 * @out_rot_dis_w: maximum output width for the output rotator enabled
 */
struct samsung_fimc_variant {
	unsigned int	pix_hoff:1;
	unsigned int	has_inp_rot:1;
	unsigned int	has_out_rot:1;

	u16		min_inp_pixsize;
	u16		min_out_pixsize;
	u16		scaler_en_w;
	u16		scaler_dis_w;
	u16		in_rot_en_h;
	u16		in_rot_dis_w;
	u16		out_rot_en_w;
	u16		out_rot_dis_w;
};

/**
 * struct samsung_fimc_driverdata - per-device type driver data for init time.
 *
 * @variant: the variant information for this driver.
 * @dev_cnt: number of fimc sub-devices available in SoC
 */
struct samsung_fimc_driverdata {
	struct samsung_fimc_variant *variant[FIMC_MAX_DEVS];
	int	devs_cnt;
};

struct fimc_ctx;

/**
 * struct fimc_subdev - abstraction for a FIMC entity
 *
 * @slock:	the spinlock protecting this data structure
 * @lock:	the mutex protecting this data structure
 * @pdev:	pointer to the FIMC platform device
 * @id:		FIMC device index (0..2)
 * @clock[]:	the clocks required for FIMC operation
 * @regs:	the mapped hardware registers
 * @regs_res:	the resource claimed for IO registers
 * @irq:	interrupt number of the FIMC subdevice
 * @irqlock:	spinlock protecting videbuffer queue
 * @m2m:	memory-to-memory V4L2 device information
 * @state:	the FIMC device state flags
 */
struct fimc_dev {
	spinlock_t			slock;
	struct mutex			lock;
	struct platform_device		*pdev;
	struct samsung_fimc_variant	*variant;
	int				id;
	struct clk			*clock[NUM_FIMC_CLOCKS];
	void __iomem			*regs;
	struct resource			*regs_res;
	int				irq;
	spinlock_t			irqlock;
	struct workqueue_struct		*work_queue;
	struct fimc_m2m_device		m2m;
	unsigned long			state;
};

/**
 * fimc_ctx - the device context data
 *
 * @lock:		mutex protecting this data structure
 * @s_frame:		source frame properties
 * @d_frame:		destination frame properties
 * @out_order_1p:	output 1-plane YCBCR order
 * @out_order_2p:	output 2-plane YCBCR order
 * @in_order_1p		input 1-plane YCBCR order
 * @in_order_2p:	input 2-plane YCBCR order
 * @in_path:		input mode (DMA or camera)
 * @out_path:		output mode (DMA or FIFO)
 * @scaler:		image scaler properties
 * @effect:		image effect
 * @rotation:		image clockwise rotation in degrees
 * @flip:		image flip mode
 * @flags:		an additional flags for image conversion
 * @state:		flags to keep track of user configuration
 * @fimc_dev:		the FIMC device this context applies to
 * @m2m_ctx:		memory-to-memory device context
 */
struct fimc_ctx {
	spinlock_t		slock;
	struct fimc_frame	s_frame;
	struct fimc_frame	d_frame;
	u32			out_order_1p;
	u32			out_order_2p;
	u32			in_order_1p;
	u32			in_order_2p;
	enum fimc_datapath	in_path;
	enum fimc_datapath	out_path;
	struct fimc_scaler	scaler;
	struct fimc_effect	effect;
	int			rotation;
	u32			flip;
	u32			flags;
	u32			state;
	struct fimc_dev		*fimc_dev;
	struct v4l2_m2m_ctx	*m2m_ctx;
};


static inline int tiled_fmt(struct fimc_fmt *fmt)
{
	return 0;
}

static inline void fimc_hw_clear_irq(struct fimc_dev *dev)
{
	u32 cfg = readl(dev->regs + S5P_CIGCTRL);
	cfg |= S5P_CIGCTRL_IRQ_CLR;
	writel(cfg, dev->regs + S5P_CIGCTRL);
}

static inline void fimc_hw_start_scaler(struct fimc_dev *dev)
{
	u32 cfg = readl(dev->regs + S5P_CISCCTRL);
	cfg |= S5P_CISCCTRL_SCALERSTART;
	writel(cfg, dev->regs + S5P_CISCCTRL);
}

static inline void fimc_hw_stop_scaler(struct fimc_dev *dev)
{
	u32 cfg = readl(dev->regs + S5P_CISCCTRL);
	cfg &= ~S5P_CISCCTRL_SCALERSTART;
	writel(cfg, dev->regs + S5P_CISCCTRL);
}

static inline void fimc_hw_dis_capture(struct fimc_dev *dev)
{
	u32 cfg = readl(dev->regs + S5P_CIIMGCPT);
	cfg &= ~(S5P_CIIMGCPT_IMGCPTEN | S5P_CIIMGCPT_IMGCPTEN_SC);
	writel(cfg, dev->regs + S5P_CIIMGCPT);
}

static inline void fimc_hw_start_in_dma(struct fimc_dev *dev)
{
	u32 cfg = readl(dev->regs + S5P_MSCTRL);
	cfg |= S5P_MSCTRL_ENVID;
	writel(cfg, dev->regs + S5P_MSCTRL);
}

static inline void fimc_hw_stop_in_dma(struct fimc_dev *dev)
{
	u32 cfg = readl(dev->regs + S5P_MSCTRL);
	cfg &= ~S5P_MSCTRL_ENVID;
	writel(cfg, dev->regs + S5P_MSCTRL);
}

static inline struct fimc_frame *ctx_m2m_get_frame(struct fimc_ctx *ctx,
						   enum v4l2_buf_type type)
{
	struct fimc_frame *frame;

	if (V4L2_BUF_TYPE_VIDEO_OUTPUT == type) {
		frame = &ctx->s_frame;
	} else if (V4L2_BUF_TYPE_VIDEO_CAPTURE == type) {
		frame = &ctx->d_frame;
	} else {
		v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
			"Wrong buffer/video queue type (%d)\n", type);
		return ERR_PTR(-EINVAL);
	}

	return frame;
}

/* -----------------------------------------------------*/
/* fimc-reg.c						*/
void fimc_hw_reset(struct fimc_dev *dev);
void fimc_hw_set_rotation(struct fimc_ctx *ctx);
void fimc_hw_set_target_format(struct fimc_ctx *ctx);
void fimc_hw_set_out_dma(struct fimc_ctx *ctx);
void fimc_hw_en_lastirq(struct fimc_dev *dev, int enable);
void fimc_hw_en_irq(struct fimc_dev *dev, int enable);
void fimc_hw_set_prescaler(struct fimc_ctx *ctx);
void fimc_hw_set_scaler(struct fimc_ctx *ctx);
void fimc_hw_en_capture(struct fimc_ctx *ctx);
void fimc_hw_set_effect(struct fimc_ctx *ctx);
void fimc_hw_set_in_dma(struct fimc_ctx *ctx);
void fimc_hw_set_input_path(struct fimc_ctx *ctx);
void fimc_hw_set_output_path(struct fimc_ctx *ctx);
void fimc_hw_set_input_addr(struct fimc_dev *dev, struct fimc_addr *paddr);
void fimc_hw_set_output_addr(struct fimc_dev *dev, struct fimc_addr *paddr);

#endif /* FIMC_CORE_H_ */
Commit	Line	Data
5fd8f738 SN	1	/*
	2	* Copyright (c) 2010 Samsung Electronics
	3	*
	4	* Sylwester Nawrocki, <s.nawrocki@samsung.com>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#ifndef FIMC_CORE_H_
	12	#define FIMC_CORE_H_
	13
	14	#include <linux/types.h>
	15	#include <media/videobuf-core.h>
	16	#include <media/v4l2-device.h>
	17	#include <media/v4l2-mem2mem.h>
	18	#include <linux/videodev2.h>
	19	#include "regs-fimc.h"
	20
	21	#define err(fmt, args...) \
	22	printk(KERN_ERR "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
	23
	24	#ifdef DEBUG
	25	#define dbg(fmt, args...) \
	26	printk(KERN_DEBUG "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
	27	#else
	28	#define dbg(fmt, args...)
	29	#endif
	30
5fd8f738 SN	31	#define NUM_FIMC_CLOCKS 2
	32	#define MODULE_NAME "s5p-fimc"
	33	#define FIMC_MAX_DEVS 3
	34	#define FIMC_MAX_OUT_BUFS 4
	35	#define SCALER_MAX_HRATIO 64
	36	#define SCALER_MAX_VRATIO 64
	37
	38	enum {
	39	ST_IDLE,
	40	ST_OUTDMA_RUN,
	41	ST_M2M_PEND,
	42	};
	43
	44	#define fimc_m2m_active(dev) test_bit(ST_OUTDMA_RUN, &(dev)->state)
	45	#define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)
	46
	47	enum fimc_datapath {
	48	FIMC_ITU_CAM_A,
	49	FIMC_ITU_CAM_B,
	50	FIMC_MIPI_CAM,
	51	FIMC_DMA,
	52	FIMC_LCDFIFO,
	53	FIMC_WRITEBACK
	54	};
	55
	56	enum fimc_color_fmt {
	57	S5P_FIMC_RGB565,
	58	S5P_FIMC_RGB666,
	59	S5P_FIMC_RGB888,
	60	S5P_FIMC_YCBCR420,
	61	S5P_FIMC_YCBCR422,
	62	S5P_FIMC_YCBYCR422,
	63	S5P_FIMC_YCRYCB422,
	64	S5P_FIMC_CBYCRY422,
	65	S5P_FIMC_CRYCBY422,
	66	S5P_FIMC_RGB30_LOCAL,
	67	S5P_FIMC_YCBCR444_LOCAL,
	68	S5P_FIMC_MAX_COLOR = S5P_FIMC_YCBCR444_LOCAL,
	69	S5P_FIMC_COLOR_MASK = 0x0F,
	70	};
	71
	72	/* Y/Cb/Cr components order at DMA output for 1 plane YCbCr 4:2:2 formats. */
	73	#define S5P_FIMC_OUT_CRYCBY S5P_CIOCTRL_ORDER422_CRYCBY
	74	#define S5P_FIMC_OUT_CBYCRY S5P_CIOCTRL_ORDER422_YCRYCB
	75	#define S5P_FIMC_OUT_YCRYCB S5P_CIOCTRL_ORDER422_CBYCRY
	76	#define S5P_FIMC_OUT_YCBYCR S5P_CIOCTRL_ORDER422_YCBYCR
	77
	78	/* Input Y/Cb/Cr components order for 1 plane YCbCr 4:2:2 color formats. */
	79	#define S5P_FIMC_IN_CRYCBY S5P_MSCTRL_ORDER422_CRYCBY
	80	#define S5P_FIMC_IN_CBYCRY S5P_MSCTRL_ORDER422_YCRYCB
	81	#define S5P_FIMC_IN_YCRYCB S5P_MSCTRL_ORDER422_CBYCRY
	82	#define S5P_FIMC_IN_YCBYCR S5P_MSCTRL_ORDER422_YCBYCR
	83
	84	/* Cb/Cr chrominance components order for 2 plane Y/CbCr 4:2:2 formats. */
	85	#define S5P_FIMC_LSB_CRCB S5P_CIOCTRL_ORDER422_2P_LSB_CRCB
	86
	87	/* The embedded image effect selection */
	88	#define S5P_FIMC_EFFECT_ORIGINAL S5P_CIIMGEFF_FIN_BYPASS
	89	#define S5P_FIMC_EFFECT_ARBITRARY S5P_CIIMGEFF_FIN_ARBITRARY
	90	#define S5P_FIMC_EFFECT_NEGATIVE S5P_CIIMGEFF_FIN_NEGATIVE
	91	#define S5P_FIMC_EFFECT_ARTFREEZE S5P_CIIMGEFF_FIN_ARTFREEZE
	92	#define S5P_FIMC_EFFECT_EMBOSSING S5P_CIIMGEFF_FIN_EMBOSSING
	93	#define S5P_FIMC_EFFECT_SIKHOUETTE S5P_CIIMGEFF_FIN_SILHOUETTE
	94
95	/* The hardware context state. */
96	#define FIMC_PARAMS (1 << 0)
97	#define FIMC_SRC_ADDR (1 << 1)
98	#define FIMC_DST_ADDR (1 << 2)
99	#define FIMC_SRC_FMT (1 << 3)
100	#define FIMC_DST_FMT (1 << 4)
101
102	/* Image conversion flags */
103	#define FIMC_IN_DMA_ACCESS_TILED (1 << 0)
104	#define FIMC_IN_DMA_ACCESS_LINEAR (0 << 0)
105	#define FIMC_OUT_DMA_ACCESS_TILED (1 << 1)
106	#define FIMC_OUT_DMA_ACCESS_LINEAR (0 << 1)
107	#define FIMC_SCAN_MODE_PROGRESSIVE (0 << 2)
108	#define FIMC_SCAN_MODE_INTERLACED (1 << 2)
109	/* YCbCr data dynamic range for RGB-YUV color conversion. Y/Cb/Cr: (0 ~ 255) */
110	#define FIMC_COLOR_RANGE_WIDE (0 << 3)
111	/* Y (16 ~ 235), Cb/Cr (16 ~ 240) */
112	#define FIMC_COLOR_RANGE_NARROW (1 << 3)
113
114	#define FLIP_NONE 0
115	#define FLIP_X_AXIS 1
116	#define FLIP_Y_AXIS 2
117	#define FLIP_XY_AXIS (FLIP_X_AXIS \| FLIP_Y_AXIS)
118
119	/**
120	* struct fimc_fmt - the driver's internal color format data
121	* @name: format description
122	* @fourcc: the fourcc code for this format
123	* @color: the corresponding fimc_color_fmt
124	* @depth: number of bits per pixel
125	* @buff_cnt: number of physically non-contiguous data planes
126	* @planes_cnt: number of physically contiguous data planes
127	*/
128	struct fimc_fmt {
129	char *name;
130	u32 fourcc;
131	u32 color;
132	u32 depth;
133	u16 buff_cnt;
134	u16 planes_cnt;
135	};
136
137	/**
138	* struct fimc_dma_offset - pixel offset information for DMA
139	* @y_h: y value horizontal offset
140	* @y_v: y value vertical offset
141	* @cb_h: cb value horizontal offset
142	* @cb_v: cb value vertical offset
143	* @cr_h: cr value horizontal offset
144	* @cr_v: cr value vertical offset
145	*/
146	struct fimc_dma_offset {
147	int y_h;
148	int y_v;
149	int cb_h;
150	int cb_v;
151	int cr_h;
152	int cr_v;
153	};
154
155	/**
156	* struct fimc_effect - the configuration data for the "Arbitrary" image effect
157	* @type: effect type
158	* @pat_cb: cr value when type is "arbitrary"
159	* @pat_cr: cr value when type is "arbitrary"
160	*/
161	struct fimc_effect {
162	u32 type;
163	u8 pat_cb;
164	u8 pat_cr;
165	};
166
167	/**
168	* struct fimc_scaler - the configuration data for FIMC inetrnal scaler
169	*
170	* @enabled: the flag set when the scaler is used
171	* @hfactor: horizontal shift factor
172	* @vfactor: vertical shift factor
173	* @pre_hratio: horizontal ratio of the prescaler
174	* @pre_vratio: vertical ratio of the prescaler
175	* @pre_dst_width: the prescaler's destination width
176	* @pre_dst_height: the prescaler's destination height
177	* @scaleup_h: flag indicating scaling up horizontally
178	* @scaleup_v: flag indicating scaling up vertically
179	* @main_hratio: the main scaler's horizontal ratio
180	* @main_vratio: the main scaler's vertical ratio
181	* @real_width: source width - offset
182	* @real_height: source height - offset
183	* @copy_mode: flag set if one-to-one mode is used, i.e. no scaling
184	* and color format conversion
185	*/
186	struct fimc_scaler {
187	u32 enabled;
188	u32 hfactor;
189	u32 vfactor;
190	u32 pre_hratio;
191	u32 pre_vratio;
192	u32 pre_dst_width;
193	u32 pre_dst_height;
194	u32 scaleup_h;
195	u32 scaleup_v;
196	u32 main_hratio;
197	u32 main_vratio;
198	u32 real_width;
199	u32 real_height;
200	u32 copy_mode;
201	};
202
203	/**
204	* struct fimc_addr - the FIMC physical address set for DMA
205	*
206	* @y: luminance plane physical address
207	* @cb: Cb plane physical address
208	* @cr: Cr plane physical address
209	*/
210	struct fimc_addr {
211	u32 y;
212	u32 cb;
213	u32 cr;
214	};
215
216	/**
217	* struct fimc_vid_buffer - the driver's video buffer
218	* @vb: v4l videobuf buffer
219	*/
220	struct fimc_vid_buffer {
221	struct videobuf_buffer vb;
222	};
223
224	/**
225	* struct fimc_frame - input/output frame format properties
226	*
227	* @f_width: image full width (virtual screen size)
228	* @f_height: image full height (virtual screen size)
229	* @o_width: original image width as set by S_FMT
230	* @o_height: original image height as set by S_FMT
231	* @offs_h: image horizontal pixel offset
232	* @offs_v: image vertical pixel offset
233	* @width: image pixel width
234	* @height: image pixel weight
235	* @paddr: image frame buffer physical addresses
236	* @buf_cnt: number of buffers depending on a color format
237	* @size: image size in bytes
238	* @color: color format
239	* @dma_offset: DMA offset in bytes
240	*/
241	struct fimc_frame {
242	u32 f_width;
243	u32 f_height;
244	u32 o_width;
245	u32 o_height;
246	u32 offs_h;
247	u32 offs_v;
248	u32 width;
249	u32 height;
250	u32 size;
251	struct fimc_addr paddr;
252	struct fimc_dma_offset dma_offset;
253	struct fimc_fmt *fmt;
254	};
255
256	/**
257	* struct fimc_m2m_device - v4l2 memory-to-memory device data
258	* @vfd: the video device node for v4l2 m2m mode
259	* @v4l2_dev: v4l2 device for m2m mode
260	* @m2m_dev: v4l2 memory-to-memory device data
261	* @ctx: hardware context data
262	* @refcnt: the reference counter
263	*/
264	struct fimc_m2m_device {
265	struct video_device *vfd;
266	struct v4l2_device v4l2_dev;
267	struct v4l2_m2m_dev *m2m_dev;
268	struct fimc_ctx *ctx;
269	int refcnt;
270	};
271
272	/**
273	* struct samsung_fimc_variant - camera interface variant information
274	*
275	* @pix_hoff: indicate whether horizontal offset is in pixels or in bytes
276	* @has_inp_rot: set if has input rotator
277	* @has_out_rot: set if has output rotator
278	* @min_inp_pixsize: minimum input pixel size
279	* @min_out_pixsize: minimum output pixel size
280	* @scaler_en_w: maximum input pixel width when the scaler is enabled
281	* @scaler_dis_w: maximum input pixel width when the scaler is disabled
282	* @in_rot_en_h: maximum input width when the input rotator is used
283	* @in_rot_dis_w: maximum input width when the input rotator is used
284	* @out_rot_en_w: maximum output width for the output rotator enabled
285	* @out_rot_dis_w: maximum output width for the output rotator enabled
286	*/
287	struct samsung_fimc_variant {
288	unsigned int pix_hoff:1;
289	unsigned int has_inp_rot:1;
290	unsigned int has_out_rot:1;
291
292	u16 min_inp_pixsize;
293	u16 min_out_pixsize;
294	u16 scaler_en_w;
295	u16 scaler_dis_w;
296	u16 in_rot_en_h;
297	u16 in_rot_dis_w;
298	u16 out_rot_en_w;
299	u16 out_rot_dis_w;
300	};
301
302	/**
303	* struct samsung_fimc_driverdata - per-device type driver data for init time.
304	*
305	* @variant: the variant information for this driver.
306	* @dev_cnt: number of fimc sub-devices available in SoC
307	*/
308	struct samsung_fimc_driverdata {
309	struct samsung_fimc_variant *variant[FIMC_MAX_DEVS];
310	int devs_cnt;
311	};
312
313	struct fimc_ctx;
314
315	/**
316	* struct fimc_subdev - abstraction for a FIMC entity
317	*
318	* @slock: the spinlock protecting this data structure
319	* @lock: the mutex protecting this data structure
320	* @pdev: pointer to the FIMC platform device
321	* @id: FIMC device index (0..2)
322	* @clock[]: the clocks required for FIMC operation
323	* @regs: the mapped hardware registers
324	* @regs_res: the resource claimed for IO registers
325	* @irq: interrupt number of the FIMC subdevice
326	* @irqlock: spinlock protecting videbuffer queue
327	* @m2m: memory-to-memory V4L2 device information
328	* @state: the FIMC device state flags
329	*/
330	struct fimc_dev {
331	spinlock_t slock;
332	struct mutex lock;
333	struct platform_device *pdev;
334	struct samsung_fimc_variant *variant;
335	int id;
336	struct clk *clock[NUM_FIMC_CLOCKS];
337	void __iomem *regs;
338	struct resource *regs_res;
339	int irq;
340	spinlock_t irqlock;
341	struct workqueue_struct *work_queue;
342	struct fimc_m2m_device m2m;
343	unsigned long state;
344	};
345
346	/**
347	* fimc_ctx - the device context data
348	*
349	* @lock: mutex protecting this data structure
350	* @s_frame: source frame properties
351	* @d_frame: destination frame properties
352	* @out_order_1p: output 1-plane YCBCR order
353	* @out_order_2p: output 2-plane YCBCR order
354	* @in_order_1p input 1-plane YCBCR order
355	* @in_order_2p: input 2-plane YCBCR order
356	* @in_path: input mode (DMA or camera)
357	* @out_path: output mode (DMA or FIFO)
358	* @scaler: image scaler properties
359	* @effect: image effect
360	* @rotation: image clockwise rotation in degrees
361	* @flip: image flip mode
362	* @flags: an additional flags for image conversion
363	* @state: flags to keep track of user configuration
364	* @fimc_dev: the FIMC device this context applies to
365	* @m2m_ctx: memory-to-memory device context
366	*/
367	struct fimc_ctx {
368	spinlock_t slock;
369	struct fimc_frame s_frame;
370	struct fimc_frame d_frame;
371	u32 out_order_1p;
372	u32 out_order_2p;
373	u32 in_order_1p;
374	u32 in_order_2p;
375	enum fimc_datapath in_path;
376	enum fimc_datapath out_path;
377	struct fimc_scaler scaler;
378	struct fimc_effect effect;
379	int rotation;
380	u32 flip;
381	u32 flags;
382	u32 state;
383	struct fimc_dev *fimc_dev;
384	struct v4l2_m2m_ctx *m2m_ctx;
385	};
386
387
388	static inline int tiled_fmt(struct fimc_fmt *fmt)
389	{
390	return 0;
391	}
392
393	static inline void fimc_hw_clear_irq(struct fimc_dev *dev)
394	{
395	u32 cfg = readl(dev->regs + S5P_CIGCTRL);
396	cfg \|= S5P_CIGCTRL_IRQ_CLR;
397	writel(cfg, dev->regs + S5P_CIGCTRL);
398	}
399
400	static inline void fimc_hw_start_scaler(struct fimc_dev *dev)
401	{
402	u32 cfg = readl(dev->regs + S5P_CISCCTRL);
403	cfg \|= S5P_CISCCTRL_SCALERSTART;
404	writel(cfg, dev->regs + S5P_CISCCTRL);
405	}
406
407	static inline void fimc_hw_stop_scaler(struct fimc_dev *dev)
408	{
409	u32 cfg = readl(dev->regs + S5P_CISCCTRL);
410	cfg &= ~S5P_CISCCTRL_SCALERSTART;
411	writel(cfg, dev->regs + S5P_CISCCTRL);
412	}
413
414	static inline void fimc_hw_dis_capture(struct fimc_dev *dev)
415	{
416	u32 cfg = readl(dev->regs + S5P_CIIMGCPT);
417	cfg &= ~(S5P_CIIMGCPT_IMGCPTEN \| S5P_CIIMGCPT_IMGCPTEN_SC);
418	writel(cfg, dev->regs + S5P_CIIMGCPT);
419	}
420
421	static inline void fimc_hw_start_in_dma(struct fimc_dev *dev)
422	{
423	u32 cfg = readl(dev->regs + S5P_MSCTRL);
424	cfg \|= S5P_MSCTRL_ENVID;
425	writel(cfg, dev->regs + S5P_MSCTRL);
426	}
427
428	static inline void fimc_hw_stop_in_dma(struct fimc_dev *dev)
429	{
430	u32 cfg = readl(dev->regs + S5P_MSCTRL);
431	cfg &= ~S5P_MSCTRL_ENVID;
432	writel(cfg, dev->regs + S5P_MSCTRL);
433	}
434
03e30ca5 PO	435	static inline struct fimc_frame ctx_m2m_get_frame(struct fimc_ctx ctx,
	436	enum v4l2_buf_type type)
	437	{
	438	struct fimc_frame *frame;
	439
	440	if (V4L2_BUF_TYPE_VIDEO_OUTPUT == type) {
	441	frame = &ctx->s_frame;
	442	} else if (V4L2_BUF_TYPE_VIDEO_CAPTURE == type) {
	443	frame = &ctx->d_frame;
	444	} else {
	445	v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
	446	"Wrong buffer/video queue type (%d)\n", type);
	447	return ERR_PTR(-EINVAL);
	448	}
	449
	450	return frame;
	451	}
	452
5fd8f738 SN	453	/* -----------------------------------------------------*/
	454	/* fimc-reg.c */
	455	void fimc_hw_reset(struct fimc_dev *dev);
	456	void fimc_hw_set_rotation(struct fimc_ctx *ctx);
	457	void fimc_hw_set_target_format(struct fimc_ctx *ctx);
	458	void fimc_hw_set_out_dma(struct fimc_ctx *ctx);
	459	void fimc_hw_en_lastirq(struct fimc_dev *dev, int enable);
	460	void fimc_hw_en_irq(struct fimc_dev *dev, int enable);
	461	void fimc_hw_set_prescaler(struct fimc_ctx *ctx);
	462	void fimc_hw_set_scaler(struct fimc_ctx *ctx);
	463	void fimc_hw_en_capture(struct fimc_ctx *ctx);
	464	void fimc_hw_set_effect(struct fimc_ctx *ctx);
	465	void fimc_hw_set_in_dma(struct fimc_ctx *ctx);
	466	void fimc_hw_set_input_path(struct fimc_ctx *ctx);
	467	void fimc_hw_set_output_path(struct fimc_ctx *ctx);
	468	void fimc_hw_set_input_addr(struct fimc_dev dev, struct fimc_addr paddr);
	469	void fimc_hw_set_output_addr(struct fimc_dev dev, struct fimc_addr paddr);
	470
	471	#endif /* FIMC_CORE_H_ */