Commit | Line | Data |
---|---|---|
5fd8f738 | 1 | /* |
3a3f9449 | 2 | * Copyright (C) 2010 - 2011 Samsung Electronics Co., Ltd. |
5fd8f738 SN |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #ifndef FIMC_CORE_H_ | |
10 | #define FIMC_CORE_H_ | |
11 | ||
5f3cc447 SN |
12 | /*#define DEBUG*/ |
13 | ||
2319c539 | 14 | #include <linux/platform_device.h> |
aee7126c | 15 | #include <linux/sched.h> |
4ecbf5d1 | 16 | #include <linux/spinlock.h> |
5fd8f738 | 17 | #include <linux/types.h> |
aee7126c | 18 | #include <linux/videodev2.h> |
2dab38e2 | 19 | #include <linux/io.h> |
574e1717 SN |
20 | |
21 | #include <media/media-entity.h> | |
2dab38e2 | 22 | #include <media/videobuf2-core.h> |
131b6c61 | 23 | #include <media/v4l2-ctrls.h> |
5fd8f738 SN |
24 | #include <media/v4l2-device.h> |
25 | #include <media/v4l2-mem2mem.h> | |
5f3cc447 | 26 | #include <media/v4l2-mediabus.h> |
df7e09a3 | 27 | #include <media/s5p_fimc.h> |
aee7126c | 28 | |
5fd8f738 SN |
29 | #include "regs-fimc.h" |
30 | ||
31 | #define err(fmt, args...) \ | |
32 | printk(KERN_ERR "%s:%d: " fmt "\n", __func__, __LINE__, ##args) | |
33 | ||
5fd8f738 | 34 | #define dbg(fmt, args...) \ |
1e004695 | 35 | pr_debug("%s:%d: " fmt "\n", __func__, __LINE__, ##args) |
5fd8f738 | 36 | |
5f3cc447 SN |
37 | /* Time to wait for next frame VSYNC interrupt while stopping operation. */ |
38 | #define FIMC_SHUTDOWN_TIMEOUT ((100*HZ)/1000) | |
ebdfea81 | 39 | #define MAX_FIMC_CLOCKS 2 |
d3953223 | 40 | #define FIMC_MODULE_NAME "s5p-fimc" |
a7d5bbcf | 41 | #define FIMC_MAX_DEVS 4 |
5fd8f738 SN |
42 | #define FIMC_MAX_OUT_BUFS 4 |
43 | #define SCALER_MAX_HRATIO 64 | |
44 | #define SCALER_MAX_VRATIO 64 | |
548aafcd | 45 | #define DMA_MIN_SIZE 8 |
5fd8f738 | 46 | |
a25be18d SN |
47 | /* indices to the clocks array */ |
48 | enum { | |
49 | CLK_BUS, | |
50 | CLK_GATE, | |
a25be18d SN |
51 | }; |
52 | ||
5f3cc447 | 53 | enum fimc_dev_flags { |
e9e21083 SN |
54 | ST_LPM, |
55 | /* m2m node */ | |
56 | ST_M2M_RUN, | |
5fd8f738 | 57 | ST_M2M_PEND, |
e9e21083 SN |
58 | ST_M2M_SUSPENDING, |
59 | ST_M2M_SUSPENDED, | |
60 | /* capture node */ | |
5f3cc447 SN |
61 | ST_CAPT_PEND, |
62 | ST_CAPT_RUN, | |
63 | ST_CAPT_STREAM, | |
64 | ST_CAPT_SHUT, | |
e9e21083 | 65 | ST_CAPT_BUSY, |
131b6c61 | 66 | ST_CAPT_APPLY_CFG, |
5fd8f738 SN |
67 | }; |
68 | ||
e9e21083 | 69 | #define fimc_m2m_active(dev) test_bit(ST_M2M_RUN, &(dev)->state) |
5fd8f738 SN |
70 | #define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state) |
71 | ||
5f3cc447 SN |
72 | #define fimc_capture_running(dev) test_bit(ST_CAPT_RUN, &(dev)->state) |
73 | #define fimc_capture_pending(dev) test_bit(ST_CAPT_PEND, &(dev)->state) | |
e9e21083 | 74 | #define fimc_capture_busy(dev) test_bit(ST_CAPT_BUSY, &(dev)->state) |
5f3cc447 | 75 | |
5fd8f738 | 76 | enum fimc_datapath { |
5f3cc447 | 77 | FIMC_CAMERA, |
5fd8f738 SN |
78 | FIMC_DMA, |
79 | FIMC_LCDFIFO, | |
80 | FIMC_WRITEBACK | |
81 | }; | |
82 | ||
83 | enum fimc_color_fmt { | |
548aafcd | 84 | S5P_FIMC_RGB565 = 0x10, |
5fd8f738 SN |
85 | S5P_FIMC_RGB666, |
86 | S5P_FIMC_RGB888, | |
548aafcd SN |
87 | S5P_FIMC_RGB30_LOCAL, |
88 | S5P_FIMC_YCBCR420 = 0x20, | |
5fd8f738 SN |
89 | S5P_FIMC_YCBYCR422, |
90 | S5P_FIMC_YCRYCB422, | |
91 | S5P_FIMC_CBYCRY422, | |
92 | S5P_FIMC_CRYCBY422, | |
5fd8f738 | 93 | S5P_FIMC_YCBCR444_LOCAL, |
5fd8f738 SN |
94 | }; |
95 | ||
548aafcd SN |
96 | #define fimc_fmt_is_rgb(x) ((x) & 0x10) |
97 | ||
5fd8f738 SN |
98 | /* Cb/Cr chrominance components order for 2 plane Y/CbCr 4:2:2 formats. */ |
99 | #define S5P_FIMC_LSB_CRCB S5P_CIOCTRL_ORDER422_2P_LSB_CRCB | |
100 | ||
101 | /* The embedded image effect selection */ | |
102 | #define S5P_FIMC_EFFECT_ORIGINAL S5P_CIIMGEFF_FIN_BYPASS | |
103 | #define S5P_FIMC_EFFECT_ARBITRARY S5P_CIIMGEFF_FIN_ARBITRARY | |
104 | #define S5P_FIMC_EFFECT_NEGATIVE S5P_CIIMGEFF_FIN_NEGATIVE | |
105 | #define S5P_FIMC_EFFECT_ARTFREEZE S5P_CIIMGEFF_FIN_ARTFREEZE | |
106 | #define S5P_FIMC_EFFECT_EMBOSSING S5P_CIIMGEFF_FIN_EMBOSSING | |
107 | #define S5P_FIMC_EFFECT_SIKHOUETTE S5P_CIIMGEFF_FIN_SILHOUETTE | |
108 | ||
109 | /* The hardware context state. */ | |
548aafcd SN |
110 | #define FIMC_PARAMS (1 << 0) |
111 | #define FIMC_SRC_ADDR (1 << 1) | |
112 | #define FIMC_DST_ADDR (1 << 2) | |
113 | #define FIMC_SRC_FMT (1 << 3) | |
114 | #define FIMC_DST_FMT (1 << 4) | |
115 | #define FIMC_CTX_M2M (1 << 5) | |
116 | #define FIMC_CTX_CAP (1 << 6) | |
4ecbf5d1 | 117 | #define FIMC_CTX_SHUT (1 << 7) |
5fd8f738 SN |
118 | |
119 | /* Image conversion flags */ | |
120 | #define FIMC_IN_DMA_ACCESS_TILED (1 << 0) | |
121 | #define FIMC_IN_DMA_ACCESS_LINEAR (0 << 0) | |
122 | #define FIMC_OUT_DMA_ACCESS_TILED (1 << 1) | |
123 | #define FIMC_OUT_DMA_ACCESS_LINEAR (0 << 1) | |
124 | #define FIMC_SCAN_MODE_PROGRESSIVE (0 << 2) | |
125 | #define FIMC_SCAN_MODE_INTERLACED (1 << 2) | |
548aafcd SN |
126 | /* |
127 | * YCbCr data dynamic range for RGB-YUV color conversion. | |
128 | * Y/Cb/Cr: (0 ~ 255) */ | |
5fd8f738 SN |
129 | #define FIMC_COLOR_RANGE_WIDE (0 << 3) |
130 | /* Y (16 ~ 235), Cb/Cr (16 ~ 240) */ | |
131 | #define FIMC_COLOR_RANGE_NARROW (1 << 3) | |
132 | ||
5fd8f738 SN |
133 | /** |
134 | * struct fimc_fmt - the driver's internal color format data | |
5f3cc447 | 135 | * @mbus_code: Media Bus pixel code, -1 if not applicable |
5fd8f738 | 136 | * @name: format description |
5f3cc447 | 137 | * @fourcc: the fourcc code for this format, 0 if not applicable |
5fd8f738 | 138 | * @color: the corresponding fimc_color_fmt |
ef7af59b SN |
139 | * @memplanes: number of physically non-contiguous data planes |
140 | * @colplanes: number of physically contiguous data planes | |
3495dcef SN |
141 | * @depth: per plane driver's private 'number of bits per pixel' |
142 | * @flags: flags indicating which operation mode format applies to | |
5fd8f738 SN |
143 | */ |
144 | struct fimc_fmt { | |
5f3cc447 | 145 | enum v4l2_mbus_pixelcode mbus_code; |
5fd8f738 SN |
146 | char *name; |
147 | u32 fourcc; | |
148 | u32 color; | |
ef7af59b SN |
149 | u16 memplanes; |
150 | u16 colplanes; | |
151 | u8 depth[VIDEO_MAX_PLANES]; | |
5f3cc447 SN |
152 | u16 flags; |
153 | #define FMT_FLAGS_CAM (1 << 0) | |
154 | #define FMT_FLAGS_M2M (1 << 1) | |
5fd8f738 SN |
155 | }; |
156 | ||
157 | /** | |
158 | * struct fimc_dma_offset - pixel offset information for DMA | |
159 | * @y_h: y value horizontal offset | |
160 | * @y_v: y value vertical offset | |
161 | * @cb_h: cb value horizontal offset | |
162 | * @cb_v: cb value vertical offset | |
163 | * @cr_h: cr value horizontal offset | |
164 | * @cr_v: cr value vertical offset | |
165 | */ | |
166 | struct fimc_dma_offset { | |
167 | int y_h; | |
168 | int y_v; | |
169 | int cb_h; | |
170 | int cb_v; | |
171 | int cr_h; | |
172 | int cr_v; | |
173 | }; | |
174 | ||
175 | /** | |
3495dcef | 176 | * struct fimc_effect - color effect information |
5fd8f738 SN |
177 | * @type: effect type |
178 | * @pat_cb: cr value when type is "arbitrary" | |
179 | * @pat_cr: cr value when type is "arbitrary" | |
180 | */ | |
181 | struct fimc_effect { | |
182 | u32 type; | |
183 | u8 pat_cb; | |
184 | u8 pat_cr; | |
185 | }; | |
186 | ||
187 | /** | |
188 | * struct fimc_scaler - the configuration data for FIMC inetrnal scaler | |
548aafcd SN |
189 | * @scaleup_h: flag indicating scaling up horizontally |
190 | * @scaleup_v: flag indicating scaling up vertically | |
191 | * @copy_mode: flag indicating transparent DMA transfer (no scaling | |
192 | * and color format conversion) | |
193 | * @enabled: flag indicating if the scaler is used | |
5fd8f738 SN |
194 | * @hfactor: horizontal shift factor |
195 | * @vfactor: vertical shift factor | |
196 | * @pre_hratio: horizontal ratio of the prescaler | |
197 | * @pre_vratio: vertical ratio of the prescaler | |
198 | * @pre_dst_width: the prescaler's destination width | |
199 | * @pre_dst_height: the prescaler's destination height | |
5fd8f738 SN |
200 | * @main_hratio: the main scaler's horizontal ratio |
201 | * @main_vratio: the main scaler's vertical ratio | |
548aafcd SN |
202 | * @real_width: source pixel (width - offset) |
203 | * @real_height: source pixel (height - offset) | |
5fd8f738 SN |
204 | */ |
205 | struct fimc_scaler { | |
dda7ae78 SN |
206 | unsigned int scaleup_h:1; |
207 | unsigned int scaleup_v:1; | |
208 | unsigned int copy_mode:1; | |
209 | unsigned int enabled:1; | |
5fd8f738 SN |
210 | u32 hfactor; |
211 | u32 vfactor; | |
212 | u32 pre_hratio; | |
213 | u32 pre_vratio; | |
214 | u32 pre_dst_width; | |
215 | u32 pre_dst_height; | |
5fd8f738 SN |
216 | u32 main_hratio; |
217 | u32 main_vratio; | |
218 | u32 real_width; | |
219 | u32 real_height; | |
5fd8f738 SN |
220 | }; |
221 | ||
222 | /** | |
223 | * struct fimc_addr - the FIMC physical address set for DMA | |
5fd8f738 SN |
224 | * @y: luminance plane physical address |
225 | * @cb: Cb plane physical address | |
226 | * @cr: Cr plane physical address | |
227 | */ | |
228 | struct fimc_addr { | |
229 | u32 y; | |
230 | u32 cb; | |
231 | u32 cr; | |
232 | }; | |
233 | ||
234 | /** | |
235 | * struct fimc_vid_buffer - the driver's video buffer | |
5f3cc447 | 236 | * @vb: v4l videobuf buffer |
3495dcef | 237 | * @list: linked list structure for buffer queue |
5f3cc447 SN |
238 | * @paddr: precalculated physical address set |
239 | * @index: buffer index for the output DMA engine | |
5fd8f738 SN |
240 | */ |
241 | struct fimc_vid_buffer { | |
2dab38e2 SN |
242 | struct vb2_buffer vb; |
243 | struct list_head list; | |
5f3cc447 SN |
244 | struct fimc_addr paddr; |
245 | int index; | |
5fd8f738 SN |
246 | }; |
247 | ||
248 | /** | |
548aafcd | 249 | * struct fimc_frame - source/target frame properties |
5fd8f738 SN |
250 | * @f_width: image full width (virtual screen size) |
251 | * @f_height: image full height (virtual screen size) | |
252 | * @o_width: original image width as set by S_FMT | |
253 | * @o_height: original image height as set by S_FMT | |
254 | * @offs_h: image horizontal pixel offset | |
255 | * @offs_v: image vertical pixel offset | |
256 | * @width: image pixel width | |
257 | * @height: image pixel weight | |
ef7af59b | 258 | * @payload: image size in bytes (w x h x bpp) |
3495dcef | 259 | * @paddr: image frame buffer physical addresses |
5fd8f738 | 260 | * @dma_offset: DMA offset in bytes |
3495dcef | 261 | * @fmt: fimc color format pointer |
5fd8f738 SN |
262 | */ |
263 | struct fimc_frame { | |
264 | u32 f_width; | |
265 | u32 f_height; | |
266 | u32 o_width; | |
267 | u32 o_height; | |
268 | u32 offs_h; | |
269 | u32 offs_v; | |
270 | u32 width; | |
271 | u32 height; | |
ef7af59b | 272 | unsigned long payload[VIDEO_MAX_PLANES]; |
5fd8f738 SN |
273 | struct fimc_addr paddr; |
274 | struct fimc_dma_offset dma_offset; | |
275 | struct fimc_fmt *fmt; | |
276 | }; | |
277 | ||
278 | /** | |
279 | * struct fimc_m2m_device - v4l2 memory-to-memory device data | |
280 | * @vfd: the video device node for v4l2 m2m mode | |
5fd8f738 SN |
281 | * @m2m_dev: v4l2 memory-to-memory device data |
282 | * @ctx: hardware context data | |
283 | * @refcnt: the reference counter | |
284 | */ | |
285 | struct fimc_m2m_device { | |
286 | struct video_device *vfd; | |
5fd8f738 SN |
287 | struct v4l2_m2m_dev *m2m_dev; |
288 | struct fimc_ctx *ctx; | |
289 | int refcnt; | |
290 | }; | |
291 | ||
5f3cc447 SN |
292 | /** |
293 | * struct fimc_vid_cap - camera capture device information | |
294 | * @ctx: hardware context data | |
295 | * @vfd: video device node for camera capture mode | |
5f3cc447 | 296 | * @sd: pointer to camera sensor subdevice currently in use |
574e1717 | 297 | * @vd_pad: fimc video capture node pad |
5f3cc447 SN |
298 | * @fmt: Media Bus format configured at selected image sensor |
299 | * @pending_buf_q: the pending buffer queue head | |
300 | * @active_buf_q: the queue head of buffers scheduled in hardware | |
301 | * @vbq: the capture am video buffer queue | |
302 | * @active_buf_cnt: number of video buffers scheduled in hardware | |
303 | * @buf_index: index for managing the output DMA buffers | |
304 | * @frame_count: the frame counter for statistics | |
305 | * @reqbufs_count: the number of buffers requested in REQBUFS ioctl | |
306 | * @input_index: input (camera sensor) index | |
307 | * @refcnt: driver's private reference counter | |
d09a7dc8 | 308 | * @input: capture input type, grp_id of the attached subdev |
d3953223 | 309 | * @user_subdev_api: true if subdevs are not configured by the host driver |
5f3cc447 SN |
310 | */ |
311 | struct fimc_vid_cap { | |
312 | struct fimc_ctx *ctx; | |
2dab38e2 | 313 | struct vb2_alloc_ctx *alloc_ctx; |
5f3cc447 | 314 | struct video_device *vfd; |
2dab38e2 | 315 | struct v4l2_subdev *sd;; |
574e1717 | 316 | struct media_pad vd_pad; |
5f3cc447 SN |
317 | struct v4l2_mbus_framefmt fmt; |
318 | struct list_head pending_buf_q; | |
319 | struct list_head active_buf_q; | |
2dab38e2 | 320 | struct vb2_queue vbq; |
5f3cc447 SN |
321 | int active_buf_cnt; |
322 | int buf_index; | |
323 | unsigned int frame_count; | |
324 | unsigned int reqbufs_count; | |
325 | int input_index; | |
326 | int refcnt; | |
d09a7dc8 | 327 | u32 input; |
d3953223 | 328 | bool user_subdev_api; |
5f3cc447 SN |
329 | }; |
330 | ||
a7d5bbcf SN |
331 | /** |
332 | * struct fimc_pix_limit - image pixel size limits in various IP configurations | |
333 | * | |
334 | * @scaler_en_w: max input pixel width when the scaler is enabled | |
335 | * @scaler_dis_w: max input pixel width when the scaler is disabled | |
336 | * @in_rot_en_h: max input width with the input rotator is on | |
337 | * @in_rot_dis_w: max input width with the input rotator is off | |
338 | * @out_rot_en_w: max output width with the output rotator on | |
339 | * @out_rot_dis_w: max output width with the output rotator off | |
340 | */ | |
341 | struct fimc_pix_limit { | |
342 | u16 scaler_en_w; | |
343 | u16 scaler_dis_w; | |
344 | u16 in_rot_en_h; | |
345 | u16 in_rot_dis_w; | |
346 | u16 out_rot_en_w; | |
347 | u16 out_rot_dis_w; | |
348 | }; | |
349 | ||
5fd8f738 SN |
350 | /** |
351 | * struct samsung_fimc_variant - camera interface variant information | |
352 | * | |
353 | * @pix_hoff: indicate whether horizontal offset is in pixels or in bytes | |
354 | * @has_inp_rot: set if has input rotator | |
355 | * @has_out_rot: set if has output rotator | |
798174ab | 356 | * @has_cistatus2: 1 if CISTATUS2 register is present in this IP revision |
b241c6d6 HK |
357 | * @has_mainscaler_ext: 1 if extended mainscaler ratios in CIEXTEN register |
358 | * are present in this IP revision | |
d3953223 | 359 | * @has_cam_if: set if this instance has a camera input interface |
a7d5bbcf | 360 | * @pix_limit: pixel size constraints for the scaler |
5fd8f738 SN |
361 | * @min_inp_pixsize: minimum input pixel size |
362 | * @min_out_pixsize: minimum output pixel size | |
a7d5bbcf SN |
363 | * @hor_offs_align: horizontal pixel offset aligment |
364 | * @out_buf_count: the number of buffers in output DMA sequence | |
5fd8f738 SN |
365 | */ |
366 | struct samsung_fimc_variant { | |
367 | unsigned int pix_hoff:1; | |
368 | unsigned int has_inp_rot:1; | |
369 | unsigned int has_out_rot:1; | |
798174ab | 370 | unsigned int has_cistatus2:1; |
b241c6d6 | 371 | unsigned int has_mainscaler_ext:1; |
d3953223 | 372 | unsigned int has_cam_if:1; |
a7d5bbcf | 373 | struct fimc_pix_limit *pix_limit; |
5fd8f738 SN |
374 | u16 min_inp_pixsize; |
375 | u16 min_out_pixsize; | |
a7d5bbcf SN |
376 | u16 hor_offs_align; |
377 | u16 out_buf_count; | |
5fd8f738 SN |
378 | }; |
379 | ||
380 | /** | |
548aafcd | 381 | * struct samsung_fimc_driverdata - per device type driver data for init time. |
5fd8f738 SN |
382 | * |
383 | * @variant: the variant information for this driver. | |
384 | * @dev_cnt: number of fimc sub-devices available in SoC | |
5f3cc447 | 385 | * @lclk_frequency: fimc bus clock frequency |
5fd8f738 SN |
386 | */ |
387 | struct samsung_fimc_driverdata { | |
388 | struct samsung_fimc_variant *variant[FIMC_MAX_DEVS]; | |
5f3cc447 | 389 | unsigned long lclk_frequency; |
a7d5bbcf | 390 | int num_entities; |
5fd8f738 SN |
391 | }; |
392 | ||
d3953223 SN |
393 | struct fimc_pipeline { |
394 | struct media_pipeline *pipe; | |
395 | struct v4l2_subdev *sensor; | |
396 | struct v4l2_subdev *csis; | |
397 | }; | |
398 | ||
5fd8f738 SN |
399 | struct fimc_ctx; |
400 | ||
401 | /** | |
548aafcd | 402 | * struct fimc_dev - abstraction for FIMC entity |
5fd8f738 SN |
403 | * @slock: the spinlock protecting this data structure |
404 | * @lock: the mutex protecting this data structure | |
405 | * @pdev: pointer to the FIMC platform device | |
5f3cc447 | 406 | * @pdata: pointer to the device platform data |
3495dcef | 407 | * @variant: the IP variant information |
a25be18d SN |
408 | * @id: FIMC device index (0..FIMC_MAX_DEVS) |
409 | * @num_clocks: the number of clocks managed by this device instance | |
3495dcef | 410 | * @clock: clocks required for FIMC operation |
5fd8f738 SN |
411 | * @regs: the mapped hardware registers |
412 | * @regs_res: the resource claimed for IO registers | |
3495dcef SN |
413 | * @irq: FIMC interrupt number |
414 | * @irq_queue: interrupt handler waitqueue | |
30c9939d | 415 | * @v4l2_dev: root v4l2_device |
5fd8f738 | 416 | * @m2m: memory-to-memory V4L2 device information |
5f3cc447 SN |
417 | * @vid_cap: camera capture device information |
418 | * @state: flags used to synchronize m2m and capture mode operation | |
3495dcef | 419 | * @alloc_ctx: videobuf2 memory allocator context |
d3953223 | 420 | * @pipeline: fimc video capture pipeline data structure |
5fd8f738 SN |
421 | */ |
422 | struct fimc_dev { | |
423 | spinlock_t slock; | |
424 | struct mutex lock; | |
425 | struct platform_device *pdev; | |
df7e09a3 | 426 | struct s5p_platform_fimc *pdata; |
5fd8f738 | 427 | struct samsung_fimc_variant *variant; |
a25be18d SN |
428 | u16 id; |
429 | u16 num_clocks; | |
430 | struct clk *clock[MAX_FIMC_CLOCKS]; | |
5fd8f738 SN |
431 | void __iomem *regs; |
432 | struct resource *regs_res; | |
433 | int irq; | |
5f3cc447 | 434 | wait_queue_head_t irq_queue; |
30c9939d | 435 | struct v4l2_device *v4l2_dev; |
5fd8f738 | 436 | struct fimc_m2m_device m2m; |
5f3cc447 | 437 | struct fimc_vid_cap vid_cap; |
5fd8f738 | 438 | unsigned long state; |
2dab38e2 | 439 | struct vb2_alloc_ctx *alloc_ctx; |
d3953223 | 440 | struct fimc_pipeline pipeline; |
5fd8f738 SN |
441 | }; |
442 | ||
443 | /** | |
444 | * fimc_ctx - the device context data | |
3495dcef | 445 | * @slock: spinlock protecting this data structure |
5fd8f738 SN |
446 | * @s_frame: source frame properties |
447 | * @d_frame: destination frame properties | |
448 | * @out_order_1p: output 1-plane YCBCR order | |
449 | * @out_order_2p: output 2-plane YCBCR order | |
450 | * @in_order_1p input 1-plane YCBCR order | |
451 | * @in_order_2p: input 2-plane YCBCR order | |
452 | * @in_path: input mode (DMA or camera) | |
453 | * @out_path: output mode (DMA or FIFO) | |
454 | * @scaler: image scaler properties | |
455 | * @effect: image effect | |
456 | * @rotation: image clockwise rotation in degrees | |
131b6c61 SN |
457 | * @hflip: indicates image horizontal flip if set |
458 | * @vflip: indicates image vertical flip if set | |
548aafcd | 459 | * @flags: additional flags for image conversion |
5fd8f738 SN |
460 | * @state: flags to keep track of user configuration |
461 | * @fimc_dev: the FIMC device this context applies to | |
462 | * @m2m_ctx: memory-to-memory device context | |
e578588e | 463 | * @fh: v4l2 file handle |
131b6c61 SN |
464 | * @ctrl_handler: v4l2 controls handler |
465 | * @ctrl_rotate image rotation control | |
466 | * @ctrl_hflip horizontal flip control | |
467 | * @ctrl_vflip vartical flip control | |
468 | * @ctrls_rdy: true if the control handler is initialized | |
5fd8f738 SN |
469 | */ |
470 | struct fimc_ctx { | |
471 | spinlock_t slock; | |
472 | struct fimc_frame s_frame; | |
473 | struct fimc_frame d_frame; | |
474 | u32 out_order_1p; | |
475 | u32 out_order_2p; | |
476 | u32 in_order_1p; | |
477 | u32 in_order_2p; | |
478 | enum fimc_datapath in_path; | |
479 | enum fimc_datapath out_path; | |
480 | struct fimc_scaler scaler; | |
481 | struct fimc_effect effect; | |
482 | int rotation; | |
131b6c61 SN |
483 | unsigned int hflip:1; |
484 | unsigned int vflip:1; | |
5fd8f738 SN |
485 | u32 flags; |
486 | u32 state; | |
487 | struct fimc_dev *fimc_dev; | |
488 | struct v4l2_m2m_ctx *m2m_ctx; | |
e578588e | 489 | struct v4l2_fh fh; |
131b6c61 SN |
490 | struct v4l2_ctrl_handler ctrl_handler; |
491 | struct v4l2_ctrl *ctrl_rotate; | |
492 | struct v4l2_ctrl *ctrl_hflip; | |
493 | struct v4l2_ctrl *ctrl_vflip; | |
494 | bool ctrls_rdy; | |
5fd8f738 SN |
495 | }; |
496 | ||
e578588e SN |
497 | #define fh_to_ctx(__fh) container_of(__fh, struct fimc_ctx, fh) |
498 | ||
4ecbf5d1 SN |
499 | static inline bool fimc_capture_active(struct fimc_dev *fimc) |
500 | { | |
501 | unsigned long flags; | |
502 | bool ret; | |
503 | ||
504 | spin_lock_irqsave(&fimc->slock, flags); | |
505 | ret = !!(fimc->state & (1 << ST_CAPT_RUN) || | |
506 | fimc->state & (1 << ST_CAPT_PEND)); | |
507 | spin_unlock_irqrestore(&fimc->slock, flags); | |
508 | return ret; | |
509 | } | |
510 | ||
511 | static inline void fimc_ctx_state_lock_set(u32 state, struct fimc_ctx *ctx) | |
512 | { | |
513 | unsigned long flags; | |
514 | ||
515 | spin_lock_irqsave(&ctx->slock, flags); | |
516 | ctx->state |= state; | |
517 | spin_unlock_irqrestore(&ctx->slock, flags); | |
518 | } | |
519 | ||
520 | static inline bool fimc_ctx_state_is_set(u32 mask, struct fimc_ctx *ctx) | |
521 | { | |
522 | unsigned long flags; | |
523 | bool ret; | |
524 | ||
525 | spin_lock_irqsave(&ctx->slock, flags); | |
526 | ret = (ctx->state & mask) == mask; | |
527 | spin_unlock_irqrestore(&ctx->slock, flags); | |
528 | return ret; | |
529 | } | |
530 | ||
5fd8f738 SN |
531 | static inline int tiled_fmt(struct fimc_fmt *fmt) |
532 | { | |
ef7af59b | 533 | return fmt->fourcc == V4L2_PIX_FMT_NV12MT; |
5fd8f738 SN |
534 | } |
535 | ||
536 | static inline void fimc_hw_clear_irq(struct fimc_dev *dev) | |
537 | { | |
538 | u32 cfg = readl(dev->regs + S5P_CIGCTRL); | |
539 | cfg |= S5P_CIGCTRL_IRQ_CLR; | |
540 | writel(cfg, dev->regs + S5P_CIGCTRL); | |
541 | } | |
542 | ||
548aafcd | 543 | static inline void fimc_hw_enable_scaler(struct fimc_dev *dev, bool on) |
5fd8f738 SN |
544 | { |
545 | u32 cfg = readl(dev->regs + S5P_CISCCTRL); | |
548aafcd SN |
546 | if (on) |
547 | cfg |= S5P_CISCCTRL_SCALERSTART; | |
548 | else | |
549 | cfg &= ~S5P_CISCCTRL_SCALERSTART; | |
5fd8f738 SN |
550 | writel(cfg, dev->regs + S5P_CISCCTRL); |
551 | } | |
552 | ||
548aafcd | 553 | static inline void fimc_hw_activate_input_dma(struct fimc_dev *dev, bool on) |
5fd8f738 | 554 | { |
548aafcd SN |
555 | u32 cfg = readl(dev->regs + S5P_MSCTRL); |
556 | if (on) | |
557 | cfg |= S5P_MSCTRL_ENVID; | |
558 | else | |
559 | cfg &= ~S5P_MSCTRL_ENVID; | |
560 | writel(cfg, dev->regs + S5P_MSCTRL); | |
5fd8f738 SN |
561 | } |
562 | ||
563 | static inline void fimc_hw_dis_capture(struct fimc_dev *dev) | |
564 | { | |
565 | u32 cfg = readl(dev->regs + S5P_CIIMGCPT); | |
566 | cfg &= ~(S5P_CIIMGCPT_IMGCPTEN | S5P_CIIMGCPT_IMGCPTEN_SC); | |
567 | writel(cfg, dev->regs + S5P_CIIMGCPT); | |
568 | } | |
569 | ||
a7d5bbcf SN |
570 | /** |
571 | * fimc_hw_set_dma_seq - configure output DMA buffer sequence | |
572 | * @mask: each bit corresponds to one of 32 output buffer registers set | |
573 | * 1 to include buffer in the sequence, 0 to disable | |
574 | * | |
575 | * This function mask output DMA ring buffers, i.e. it allows to configure | |
576 | * which of the output buffer address registers will be used by the DMA | |
577 | * engine. | |
578 | */ | |
579 | static inline void fimc_hw_set_dma_seq(struct fimc_dev *dev, u32 mask) | |
580 | { | |
581 | writel(mask, dev->regs + S5P_CIFCNTSEQ); | |
582 | } | |
583 | ||
548aafcd SN |
584 | static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx, |
585 | enum v4l2_buf_type type) | |
03e30ca5 PO |
586 | { |
587 | struct fimc_frame *frame; | |
588 | ||
ef7af59b | 589 | if (V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE == type) { |
4ecbf5d1 | 590 | if (fimc_ctx_state_is_set(FIMC_CTX_M2M, ctx)) |
5f3cc447 SN |
591 | frame = &ctx->s_frame; |
592 | else | |
593 | return ERR_PTR(-EINVAL); | |
ef7af59b | 594 | } else if (V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE == type) { |
03e30ca5 PO |
595 | frame = &ctx->d_frame; |
596 | } else { | |
30c9939d | 597 | v4l2_err(ctx->fimc_dev->v4l2_dev, |
03e30ca5 PO |
598 | "Wrong buffer/video queue type (%d)\n", type); |
599 | return ERR_PTR(-EINVAL); | |
600 | } | |
601 | ||
602 | return frame; | |
603 | } | |
604 | ||
798174ab | 605 | /* Return an index to the buffer actually being written. */ |
5f3cc447 SN |
606 | static inline u32 fimc_hw_get_frame_index(struct fimc_dev *dev) |
607 | { | |
798174ab SN |
608 | u32 reg; |
609 | ||
610 | if (dev->variant->has_cistatus2) { | |
611 | reg = readl(dev->regs + S5P_CISTATUS2) & 0x3F; | |
612 | return reg > 0 ? --reg : reg; | |
613 | } else { | |
614 | reg = readl(dev->regs + S5P_CISTATUS); | |
615 | return (reg & S5P_CISTATUS_FRAMECNT_MASK) >> | |
616 | S5P_CISTATUS_FRAMECNT_SHIFT; | |
617 | } | |
5f3cc447 SN |
618 | } |
619 | ||
5fd8f738 SN |
620 | /* -----------------------------------------------------*/ |
621 | /* fimc-reg.c */ | |
548aafcd | 622 | void fimc_hw_reset(struct fimc_dev *fimc); |
5fd8f738 SN |
623 | void fimc_hw_set_rotation(struct fimc_ctx *ctx); |
624 | void fimc_hw_set_target_format(struct fimc_ctx *ctx); | |
625 | void fimc_hw_set_out_dma(struct fimc_ctx *ctx); | |
548aafcd SN |
626 | void fimc_hw_en_lastirq(struct fimc_dev *fimc, int enable); |
627 | void fimc_hw_en_irq(struct fimc_dev *fimc, int enable); | |
b241c6d6 HK |
628 | void fimc_hw_set_prescaler(struct fimc_ctx *ctx); |
629 | void fimc_hw_set_mainscaler(struct fimc_ctx *ctx); | |
5fd8f738 SN |
630 | void fimc_hw_en_capture(struct fimc_ctx *ctx); |
631 | void fimc_hw_set_effect(struct fimc_ctx *ctx); | |
632 | void fimc_hw_set_in_dma(struct fimc_ctx *ctx); | |
633 | void fimc_hw_set_input_path(struct fimc_ctx *ctx); | |
634 | void fimc_hw_set_output_path(struct fimc_ctx *ctx); | |
548aafcd SN |
635 | void fimc_hw_set_input_addr(struct fimc_dev *fimc, struct fimc_addr *paddr); |
636 | void fimc_hw_set_output_addr(struct fimc_dev *fimc, struct fimc_addr *paddr, | |
ef7af59b | 637 | int index); |
5f3cc447 | 638 | int fimc_hw_set_camera_source(struct fimc_dev *fimc, |
df7e09a3 | 639 | struct s5p_fimc_isp_info *cam); |
5f3cc447 SN |
640 | int fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f); |
641 | int fimc_hw_set_camera_polarity(struct fimc_dev *fimc, | |
df7e09a3 | 642 | struct s5p_fimc_isp_info *cam); |
5f3cc447 | 643 | int fimc_hw_set_camera_type(struct fimc_dev *fimc, |
df7e09a3 | 644 | struct s5p_fimc_isp_info *cam); |
5f3cc447 SN |
645 | |
646 | /* -----------------------------------------------------*/ | |
647 | /* fimc-core.c */ | |
ef7af59b SN |
648 | int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv, |
649 | struct v4l2_fmtdesc *f); | |
e578588e | 650 | int fimc_try_fmt_mplane(struct fimc_ctx *ctx, struct v4l2_format *f); |
5f3cc447 | 651 | int fimc_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr); |
131b6c61 SN |
652 | int fimc_ctrls_create(struct fimc_ctx *ctx); |
653 | void fimc_ctrls_delete(struct fimc_ctx *ctx); | |
654 | void fimc_ctrls_activate(struct fimc_ctx *ctx, bool active); | |
e578588e | 655 | int fimc_fill_format(struct fimc_frame *frame, struct v4l2_format *f); |
5f3cc447 | 656 | |
cf52df8a SN |
657 | struct fimc_fmt *fimc_find_format(u32 *pixelformat, u32 *mbus_code, |
658 | unsigned int mask, int index); | |
5f3cc447 | 659 | |
1b09f292 | 660 | int fimc_check_scaler_ratio(int sw, int sh, int dw, int dh, int rot); |
5f3cc447 SN |
661 | int fimc_set_scaler_info(struct fimc_ctx *ctx); |
662 | int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags); | |
2dab38e2 | 663 | int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb, |
5f3cc447 | 664 | struct fimc_frame *frame, struct fimc_addr *paddr); |
9e803a04 SN |
665 | void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f); |
666 | void fimc_set_yuv_order(struct fimc_ctx *ctx); | |
667 | ||
30c9939d SN |
668 | int fimc_register_m2m_device(struct fimc_dev *fimc, |
669 | struct v4l2_device *v4l2_dev); | |
670 | void fimc_unregister_m2m_device(struct fimc_dev *fimc); | |
d3953223 SN |
671 | int fimc_register_driver(void); |
672 | void fimc_unregister_driver(void); | |
5f3cc447 SN |
673 | |
674 | /* -----------------------------------------------------*/ | |
675 | /* fimc-capture.c */ | |
30c9939d SN |
676 | int fimc_register_capture_device(struct fimc_dev *fimc, |
677 | struct v4l2_device *v4l2_dev); | |
5f3cc447 | 678 | void fimc_unregister_capture_device(struct fimc_dev *fimc); |
131b6c61 | 679 | int fimc_capture_ctrls_create(struct fimc_dev *fimc); |
5f3cc447 SN |
680 | int fimc_vid_cap_buf_queue(struct fimc_dev *fimc, |
681 | struct fimc_vid_buffer *fimc_vb); | |
e9e21083 SN |
682 | int fimc_capture_suspend(struct fimc_dev *fimc); |
683 | int fimc_capture_resume(struct fimc_dev *fimc); | |
548aafcd SN |
684 | |
685 | /* Locking: the caller holds fimc->slock */ | |
686 | static inline void fimc_activate_capture(struct fimc_ctx *ctx) | |
687 | { | |
688 | fimc_hw_enable_scaler(ctx->fimc_dev, ctx->scaler.enabled); | |
689 | fimc_hw_en_capture(ctx); | |
690 | } | |
691 | ||
692 | static inline void fimc_deactivate_capture(struct fimc_dev *fimc) | |
693 | { | |
694 | fimc_hw_en_lastirq(fimc, true); | |
695 | fimc_hw_dis_capture(fimc); | |
696 | fimc_hw_enable_scaler(fimc, false); | |
697 | fimc_hw_en_lastirq(fimc, false); | |
698 | } | |
5fd8f738 | 699 | |
5f3cc447 | 700 | /* |
2dab38e2 SN |
701 | * Add buf to the capture active buffers queue. |
702 | * Locking: Need to be called with fimc_dev::slock held. | |
5f3cc447 SN |
703 | */ |
704 | static inline void active_queue_add(struct fimc_vid_cap *vid_cap, | |
2dab38e2 | 705 | struct fimc_vid_buffer *buf) |
5f3cc447 | 706 | { |
2dab38e2 | 707 | list_add_tail(&buf->list, &vid_cap->active_buf_q); |
5f3cc447 SN |
708 | vid_cap->active_buf_cnt++; |
709 | } | |
710 | ||
711 | /* | |
712 | * Pop a video buffer from the capture active buffers queue | |
2dab38e2 | 713 | * Locking: Need to be called with fimc_dev::slock held. |
5f3cc447 SN |
714 | */ |
715 | static inline struct fimc_vid_buffer * | |
716 | active_queue_pop(struct fimc_vid_cap *vid_cap) | |
717 | { | |
718 | struct fimc_vid_buffer *buf; | |
719 | buf = list_entry(vid_cap->active_buf_q.next, | |
2dab38e2 SN |
720 | struct fimc_vid_buffer, list); |
721 | list_del(&buf->list); | |
5f3cc447 SN |
722 | vid_cap->active_buf_cnt--; |
723 | return buf; | |
724 | } | |
725 | ||
726 | /* Add video buffer to the capture pending buffers queue */ | |
727 | static inline void fimc_pending_queue_add(struct fimc_vid_cap *vid_cap, | |
728 | struct fimc_vid_buffer *buf) | |
729 | { | |
2dab38e2 | 730 | list_add_tail(&buf->list, &vid_cap->pending_buf_q); |
5f3cc447 SN |
731 | } |
732 | ||
733 | /* Add video buffer to the capture pending buffers queue */ | |
734 | static inline struct fimc_vid_buffer * | |
735 | pending_queue_pop(struct fimc_vid_cap *vid_cap) | |
736 | { | |
737 | struct fimc_vid_buffer *buf; | |
738 | buf = list_entry(vid_cap->pending_buf_q.next, | |
2dab38e2 SN |
739 | struct fimc_vid_buffer, list); |
740 | list_del(&buf->list); | |
5f3cc447 SN |
741 | return buf; |
742 | } | |
743 | ||
5fd8f738 | 744 | #endif /* FIMC_CORE_H_ */ |