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[media] v4l2: Add polarity flag definitions for the parallel bus FIELD signal
[deliverable/linux.git] / drivers / media / video / s5p-fimc / fimc-reg.c
CommitLineData
5fd8f738
SN		 1/*
2 * Register interface file for Samsung Camera Interface (FIMC) driver
3 *
4 * Copyright (c) 2010 Samsung Electronics
5 *
6 * Sylwester Nawrocki, s.nawrocki@samsung.com
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/io.h>
14#include <linux/delay.h>
15#include <mach/map.h>
df7e09a3 16#include <media/s5p_fimc.h>
5fd8f738
SN		 17
18#include "fimc-core.h"
19
20
21void fimc_hw_reset(struct fimc_dev *dev)
22{
23 u32 cfg;
24
25 cfg = readl(dev->regs + S5P_CISRCFMT);
26 cfg |= S5P_CISRCFMT_ITU601_8BIT;
27 writel(cfg, dev->regs + S5P_CISRCFMT);
28
29 /* Software reset. */
30 cfg = readl(dev->regs + S5P_CIGCTRL);
31 cfg |= (S5P_CIGCTRL_SWRST | S5P_CIGCTRL_IRQ_LEVEL);
32 writel(cfg, dev->regs + S5P_CIGCTRL);
e9e21083 33 udelay(10);
5fd8f738
SN		 34
35 cfg = readl(dev->regs + S5P_CIGCTRL);
36 cfg &= ~S5P_CIGCTRL_SWRST;
37 writel(cfg, dev->regs + S5P_CIGCTRL);
5fd8f738
SN		 38}
39
ac75934c 40static u32 fimc_hw_get_in_flip(struct fimc_ctx *ctx)
5fd8f738
SN		 41{
42 u32 flip = S5P_MSCTRL_FLIP_NORMAL;
43
131b6c61 44 if (ctx->hflip)
5fd8f738 45 flip = S5P_MSCTRL_FLIP_X_MIRROR;
131b6c61 46 if (ctx->vflip)
5fd8f738 47 flip = S5P_MSCTRL_FLIP_Y_MIRROR;
131b6c61 48
ac75934c
SN		 49 if (ctx->rotation <= 90)
50 return flip;
5fd8f738 51
ac75934c 52 return (flip ^ S5P_MSCTRL_FLIP_180) & S5P_MSCTRL_FLIP_180;
5fd8f738
SN		 53}
54
ac75934c 55static u32 fimc_hw_get_target_flip(struct fimc_ctx *ctx)
5fd8f738
SN		 56{
57 u32 flip = S5P_CITRGFMT_FLIP_NORMAL;
58
131b6c61
SN		 59 if (ctx->hflip)
60 flip |= S5P_CITRGFMT_FLIP_X_MIRROR;
61 if (ctx->vflip)
62 flip |= S5P_CITRGFMT_FLIP_Y_MIRROR;
63
ac75934c
SN		 64 if (ctx->rotation <= 90)
65 return flip;
66
67 return (flip ^ S5P_CITRGFMT_FLIP_180) & S5P_CITRGFMT_FLIP_180;
5fd8f738
SN		 68}
69
47654df8
SN		 70void fimc_hw_set_rotation(struct fimc_ctx *ctx)
71{
72 u32 cfg, flip;
73 struct fimc_dev *dev = ctx->fimc_dev;
74
75 cfg = readl(dev->regs + S5P_CITRGFMT);
76 cfg &= ~(S5P_CITRGFMT_INROT90 | S5P_CITRGFMT_OUTROT90 |
ac75934c 77 S5P_CITRGFMT_FLIP_180);
47654df8
SN		 78
79 /*
80 * The input and output rotator cannot work simultaneously.
81 * Use the output rotator in output DMA mode or the input rotator
82 * in direct fifo output mode.
83 */
84 if (ctx->rotation == 90 || ctx->rotation == 270) {
47654df8 85 if (ctx->out_path == FIMC_LCDFIFO)
ac75934c 86 cfg |= S5P_CITRGFMT_INROT90;
47654df8 87 else
ac75934c 88 cfg |= S5P_CITRGFMT_OUTROT90;
47654df8 89 }
47654df8 90
ac75934c
SN		 91 if (ctx->out_path == FIMC_DMA) {
92 cfg |= fimc_hw_get_target_flip(ctx);
93 writel(cfg, dev->regs + S5P_CITRGFMT);
94 } else {
95 /* LCD FIFO path */
96 flip = readl(dev->regs + S5P_MSCTRL);
97 flip &= ~S5P_MSCTRL_FLIP_MASK;
98 flip |= fimc_hw_get_in_flip(ctx);
99 writel(flip, dev->regs + S5P_MSCTRL);
100 }
47654df8
SN		 101}
102
5fd8f738
SN		 103void fimc_hw_set_target_format(struct fimc_ctx *ctx)
104{
105 u32 cfg;
106 struct fimc_dev *dev = ctx->fimc_dev;
107 struct fimc_frame *frame = &ctx->d_frame;
108
109 dbg("w= %d, h= %d color: %d", frame->width,
110 frame->height, frame->fmt->color);
111
112 cfg = readl(dev->regs + S5P_CITRGFMT);
113 cfg &= ~(S5P_CITRGFMT_FMT_MASK | S5P_CITRGFMT_HSIZE_MASK |
114 S5P_CITRGFMT_VSIZE_MASK);
115
116 switch (frame->fmt->color) {
ac75934c 117 case S5P_FIMC_RGB565...S5P_FIMC_RGB888:
5fd8f738
SN		 118 cfg |= S5P_CITRGFMT_RGB;
119 break;
120 case S5P_FIMC_YCBCR420:
121 cfg |= S5P_CITRGFMT_YCBCR420;
122 break;
ac75934c 123 case S5P_FIMC_YCBYCR422...S5P_FIMC_CRYCBY422:
ef7af59b 124 if (frame->fmt->colplanes == 1)
5fd8f738
SN		 125 cfg |= S5P_CITRGFMT_YCBCR422_1P;
126 else
127 cfg |= S5P_CITRGFMT_YCBCR422;
128 break;
129 default:
130 break;
131 }
132
47654df8
SN		 133 if (ctx->rotation == 90 || ctx->rotation == 270) {
134 cfg |= S5P_CITRGFMT_HSIZE(frame->height);
135 cfg |= S5P_CITRGFMT_VSIZE(frame->width);
136 } else {
5fd8f738 137
47654df8
SN		 138 cfg |= S5P_CITRGFMT_HSIZE(frame->width);
139 cfg |= S5P_CITRGFMT_VSIZE(frame->height);
5fd8f738 140 }
47654df8 141
5fd8f738
SN		 142 writel(cfg, dev->regs + S5P_CITRGFMT);
143
144 cfg = readl(dev->regs + S5P_CITAREA) & ~S5P_CITAREA_MASK;
145 cfg |= (frame->width * frame->height);
146 writel(cfg, dev->regs + S5P_CITAREA);
147}
148
149static void fimc_hw_set_out_dma_size(struct fimc_ctx *ctx)
150{
151 struct fimc_dev *dev = ctx->fimc_dev;
152 struct fimc_frame *frame = &ctx->d_frame;
47654df8 153 u32 cfg;
5fd8f738 154
47654df8
SN		 155 cfg = S5P_ORIG_SIZE_HOR(frame->f_width);
156 cfg |= S5P_ORIG_SIZE_VER(frame->f_height);
5fd8f738 157 writel(cfg, dev->regs + S5P_ORGOSIZE);
5f3cc447
SN		 158
159 /* Select color space conversion equation (HD/SD size).*/
160 cfg = readl(dev->regs + S5P_CIGCTRL);
161 if (frame->f_width >= 1280) /* HD */
162 cfg |= S5P_CIGCTRL_CSC_ITU601_709;
163 else /* SD */
164 cfg &= ~S5P_CIGCTRL_CSC_ITU601_709;
165 writel(cfg, dev->regs + S5P_CIGCTRL);
166
5fd8f738
SN		 167}
168
169void fimc_hw_set_out_dma(struct fimc_ctx *ctx)
170{
171 u32 cfg;
172 struct fimc_dev *dev = ctx->fimc_dev;
173 struct fimc_frame *frame = &ctx->d_frame;
174 struct fimc_dma_offset *offset = &frame->dma_offset;
175
176 /* Set the input dma offsets. */
177 cfg = 0;
178 cfg |= S5P_CIO_OFFS_HOR(offset->y_h);
179 cfg |= S5P_CIO_OFFS_VER(offset->y_v);
180 writel(cfg, dev->regs + S5P_CIOYOFF);
181
182 cfg = 0;
183 cfg |= S5P_CIO_OFFS_HOR(offset->cb_h);
184 cfg |= S5P_CIO_OFFS_VER(offset->cb_v);
185 writel(cfg, dev->regs + S5P_CIOCBOFF);
186
187 cfg = 0;
188 cfg |= S5P_CIO_OFFS_HOR(offset->cr_h);
189 cfg |= S5P_CIO_OFFS_VER(offset->cr_v);
190 writel(cfg, dev->regs + S5P_CIOCROFF);
191
192 fimc_hw_set_out_dma_size(ctx);
193
194 /* Configure chroma components order. */
195 cfg = readl(dev->regs + S5P_CIOCTRL);
196
197 cfg &= ~(S5P_CIOCTRL_ORDER2P_MASK | S5P_CIOCTRL_ORDER422_MASK |
198 S5P_CIOCTRL_YCBCR_PLANE_MASK);
199
ef7af59b 200 if (frame->fmt->colplanes == 1)
5fd8f738 201 cfg |= ctx->out_order_1p;
ef7af59b 202 else if (frame->fmt->colplanes == 2)
5fd8f738 203 cfg |= ctx->out_order_2p | S5P_CIOCTRL_YCBCR_2PLANE;
ef7af59b 204 else if (frame->fmt->colplanes == 3)
5fd8f738
SN		 205 cfg |= S5P_CIOCTRL_YCBCR_3PLANE;
206
207 writel(cfg, dev->regs + S5P_CIOCTRL);
208}
209
210static void fimc_hw_en_autoload(struct fimc_dev *dev, int enable)
211{
212 u32 cfg = readl(dev->regs + S5P_ORGISIZE);
213 if (enable)
214 cfg |= S5P_CIREAL_ISIZE_AUTOLOAD_EN;
215 else
216 cfg &= ~S5P_CIREAL_ISIZE_AUTOLOAD_EN;
217 writel(cfg, dev->regs + S5P_ORGISIZE);
218}
219
220void fimc_hw_en_lastirq(struct fimc_dev *dev, int enable)
221{
5f3cc447 222 u32 cfg = readl(dev->regs + S5P_CIOCTRL);
5fd8f738
SN		 223 if (enable)
224 cfg |= S5P_CIOCTRL_LASTIRQ_ENABLE;
225 else
226 cfg &= ~S5P_CIOCTRL_LASTIRQ_ENABLE;
227 writel(cfg, dev->regs + S5P_CIOCTRL);
5fd8f738
SN		 228}
229
b241c6d6 230void fimc_hw_set_prescaler(struct fimc_ctx *ctx)
5fd8f738
SN		 231{
232 struct fimc_dev *dev = ctx->fimc_dev;
233 struct fimc_scaler *sc = &ctx->scaler;
548aafcd 234 u32 cfg, shfactor;
5fd8f738
SN		 235
236 shfactor = 10 - (sc->hfactor + sc->vfactor);
237
548aafcd 238 cfg = S5P_CISCPRERATIO_SHFACTOR(shfactor);
5fd8f738
SN		 239 cfg |= S5P_CISCPRERATIO_HOR(sc->pre_hratio);
240 cfg |= S5P_CISCPRERATIO_VER(sc->pre_vratio);
241 writel(cfg, dev->regs + S5P_CISCPRERATIO);
242
548aafcd 243 cfg = S5P_CISCPREDST_WIDTH(sc->pre_dst_width);
5fd8f738
SN		 244 cfg |= S5P_CISCPREDST_HEIGHT(sc->pre_dst_height);
245 writel(cfg, dev->regs + S5P_CISCPREDST);
246}
247
b241c6d6 248static void fimc_hw_set_scaler(struct fimc_ctx *ctx)
5fd8f738
SN		 249{
250 struct fimc_dev *dev = ctx->fimc_dev;
251 struct fimc_scaler *sc = &ctx->scaler;
252 struct fimc_frame *src_frame = &ctx->s_frame;
253 struct fimc_frame *dst_frame = &ctx->d_frame;
254 u32 cfg = 0;
255
256 if (!(ctx->flags & FIMC_COLOR_RANGE_NARROW))
257 cfg |= (S5P_CISCCTRL_CSCR2Y_WIDE | S5P_CISCCTRL_CSCY2R_WIDE);
258
259 if (!sc->enabled)
260 cfg |= S5P_CISCCTRL_SCALERBYPASS;
261
262 if (sc->scaleup_h)
263 cfg |= S5P_CISCCTRL_SCALEUP_H;
264
265 if (sc->scaleup_v)
266 cfg |= S5P_CISCCTRL_SCALEUP_V;
267
268 if (sc->copy_mode)
269 cfg |= S5P_CISCCTRL_ONE2ONE;
270
271
272 if (ctx->in_path == FIMC_DMA) {
273 if (src_frame->fmt->color == S5P_FIMC_RGB565)
274 cfg |= S5P_CISCCTRL_INRGB_FMT_RGB565;
275 else if (src_frame->fmt->color == S5P_FIMC_RGB666)
276 cfg |= S5P_CISCCTRL_INRGB_FMT_RGB666;
277 else if (src_frame->fmt->color == S5P_FIMC_RGB888)
278 cfg |= S5P_CISCCTRL_INRGB_FMT_RGB888;
279 }
280
281 if (ctx->out_path == FIMC_DMA) {
282 if (dst_frame->fmt->color == S5P_FIMC_RGB565)
283 cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB565;
284 else if (dst_frame->fmt->color == S5P_FIMC_RGB666)
285 cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB666;
286 else if (dst_frame->fmt->color == S5P_FIMC_RGB888)
287 cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB888;
288 } else {
289 cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB888;
290
291 if (ctx->flags & FIMC_SCAN_MODE_INTERLACED)
292 cfg |= S5P_CISCCTRL_INTERLACE;
293 }
294
b241c6d6
HK		 295 writel(cfg, dev->regs + S5P_CISCCTRL);
296}
297
298void fimc_hw_set_mainscaler(struct fimc_ctx *ctx)
299{
300 struct fimc_dev *dev = ctx->fimc_dev;
70f66ea2 301 struct samsung_fimc_variant *variant = dev->variant;
b241c6d6
HK		 302 struct fimc_scaler *sc = &ctx->scaler;
303 u32 cfg;
304
305 dbg("main_hratio= 0x%X main_vratio= 0x%X",
306 sc->main_hratio, sc->main_vratio);
307
308 fimc_hw_set_scaler(ctx);
309
310 cfg = readl(dev->regs + S5P_CISCCTRL);
b241c6d6 311
70f66ea2
SN		 312 if (variant->has_mainscaler_ext) {
313 cfg &= ~(S5P_CISCCTRL_MHRATIO_MASK | S5P_CISCCTRL_MVRATIO_MASK);
314 cfg |= S5P_CISCCTRL_MHRATIO_EXT(sc->main_hratio);
315 cfg |= S5P_CISCCTRL_MVRATIO_EXT(sc->main_vratio);
316 writel(cfg, dev->regs + S5P_CISCCTRL);
b241c6d6 317
70f66ea2 318 cfg = readl(dev->regs + S5P_CIEXTEN);
b241c6d6 319
70f66ea2
SN		 320 cfg &= ~(S5P_CIEXTEN_MVRATIO_EXT_MASK |
321 S5P_CIEXTEN_MHRATIO_EXT_MASK);
322 cfg |= S5P_CIEXTEN_MHRATIO_EXT(sc->main_hratio);
323 cfg |= S5P_CIEXTEN_MVRATIO_EXT(sc->main_vratio);
324 writel(cfg, dev->regs + S5P_CIEXTEN);
325 } else {
326 cfg &= ~(S5P_CISCCTRL_MHRATIO_MASK | S5P_CISCCTRL_MVRATIO_MASK);
327 cfg |= S5P_CISCCTRL_MHRATIO(sc->main_hratio);
328 cfg |= S5P_CISCCTRL_MVRATIO(sc->main_vratio);
329 writel(cfg, dev->regs + S5P_CISCCTRL);
330 }
5fd8f738
SN		 331}
332
333void fimc_hw_en_capture(struct fimc_ctx *ctx)
334{
335 struct fimc_dev *dev = ctx->fimc_dev;
5fd8f738 336
5f3cc447
SN		 337 u32 cfg = readl(dev->regs + S5P_CIIMGCPT);
338
339 if (ctx->out_path == FIMC_DMA) {
340 /* one shot mode */
341 cfg |= S5P_CIIMGCPT_CPT_FREN_ENABLE | S5P_CIIMGCPT_IMGCPTEN;
342 } else {
25985edc 343 /* Continuous frame capture mode (freerun). */
5f3cc447
SN		 344 cfg &= ~(S5P_CIIMGCPT_CPT_FREN_ENABLE |
345 S5P_CIIMGCPT_CPT_FRMOD_CNT);
346 cfg |= S5P_CIIMGCPT_IMGCPTEN;
347 }
5fd8f738
SN		 348
349 if (ctx->scaler.enabled)
350 cfg |= S5P_CIIMGCPT_IMGCPTEN_SC;
351
352 writel(cfg | S5P_CIIMGCPT_IMGCPTEN, dev->regs + S5P_CIIMGCPT);
353}
354
ee7160e5 355void fimc_hw_set_effect(struct fimc_ctx *ctx, bool active)
5fd8f738
SN		 356{
357 struct fimc_dev *dev = ctx->fimc_dev;
358 struct fimc_effect *effect = &ctx->effect;
ee7160e5 359 u32 cfg = 0;
5fd8f738 360
ee7160e5
SN		 361 if (active) {
362 cfg |= S5P_CIIMGEFF_IE_SC_AFTER | S5P_CIIMGEFF_IE_ENABLE;
363 cfg |= effect->type;
364 if (effect->type == S5P_FIMC_EFFECT_ARBITRARY) {
365 cfg |= S5P_CIIMGEFF_PAT_CB(effect->pat_cb);
366 cfg |= S5P_CIIMGEFF_PAT_CR(effect->pat_cr);
367 }
5fd8f738
SN		 368 }
369
370 writel(cfg, dev->regs + S5P_CIIMGEFF);
371}
372
373static void fimc_hw_set_in_dma_size(struct fimc_ctx *ctx)
374{
375 struct fimc_dev *dev = ctx->fimc_dev;
376 struct fimc_frame *frame = &ctx->s_frame;
377 u32 cfg_o = 0;
378 u32 cfg_r = 0;
379
380 if (FIMC_LCDFIFO == ctx->out_path)
548aafcd 381 cfg_r |= S5P_CIREAL_ISIZE_AUTOLOAD_EN;
5fd8f738
SN		 382
383 cfg_o |= S5P_ORIG_SIZE_HOR(frame->f_width);
384 cfg_o |= S5P_ORIG_SIZE_VER(frame->f_height);
385 cfg_r |= S5P_CIREAL_ISIZE_WIDTH(frame->width);
386 cfg_r |= S5P_CIREAL_ISIZE_HEIGHT(frame->height);
387
388 writel(cfg_o, dev->regs + S5P_ORGISIZE);
389 writel(cfg_r, dev->regs + S5P_CIREAL_ISIZE);
390}
391
392void fimc_hw_set_in_dma(struct fimc_ctx *ctx)
393{
394 struct fimc_dev *dev = ctx->fimc_dev;
395 struct fimc_frame *frame = &ctx->s_frame;
396 struct fimc_dma_offset *offset = &frame->dma_offset;
548aafcd 397 u32 cfg;
5fd8f738
SN		 398
399 /* Set the pixel offsets. */
548aafcd 400 cfg = S5P_CIO_OFFS_HOR(offset->y_h);
5fd8f738
SN		 401 cfg |= S5P_CIO_OFFS_VER(offset->y_v);
402 writel(cfg, dev->regs + S5P_CIIYOFF);
403
548aafcd 404 cfg = S5P_CIO_OFFS_HOR(offset->cb_h);
5fd8f738
SN		 405 cfg |= S5P_CIO_OFFS_VER(offset->cb_v);
406 writel(cfg, dev->regs + S5P_CIICBOFF);
407
548aafcd 408 cfg = S5P_CIO_OFFS_HOR(offset->cr_h);
5fd8f738
SN		 409 cfg |= S5P_CIO_OFFS_VER(offset->cr_v);
410 writel(cfg, dev->regs + S5P_CIICROFF);
411
412 /* Input original and real size. */
413 fimc_hw_set_in_dma_size(ctx);
414
548aafcd 415 /* Use DMA autoload only in FIFO mode. */
5fd8f738
SN		 416 fimc_hw_en_autoload(dev, ctx->out_path == FIMC_LCDFIFO);
417
418 /* Set the input DMA to process single frame only. */
419 cfg = readl(dev->regs + S5P_MSCTRL);
ac75934c 420 cfg &= ~(S5P_MSCTRL_INFORMAT_MASK
5fd8f738
SN		 421 | S5P_MSCTRL_IN_BURST_COUNT_MASK
422 | S5P_MSCTRL_INPUT_MASK
423 | S5P_MSCTRL_C_INT_IN_MASK
424 | S5P_MSCTRL_2P_IN_ORDER_MASK);
425
5bbe425e
HK		 426 cfg |= (S5P_MSCTRL_IN_BURST_COUNT(4)
427 | S5P_MSCTRL_INPUT_MEMORY
428 | S5P_MSCTRL_FIFO_CTRL_FULL);
5fd8f738
SN		 429
430 switch (frame->fmt->color) {
d9160afd 431 case S5P_FIMC_RGB565...S5P_FIMC_RGB888:
5fd8f738
SN		 432 cfg |= S5P_MSCTRL_INFORMAT_RGB;
433 break;
434 case S5P_FIMC_YCBCR420:
435 cfg |= S5P_MSCTRL_INFORMAT_YCBCR420;
436
ef7af59b 437 if (frame->fmt->colplanes == 2)
5fd8f738
SN		 438 cfg |= ctx->in_order_2p | S5P_MSCTRL_C_INT_IN_2PLANE;
439 else
440 cfg |= S5P_MSCTRL_C_INT_IN_3PLANE;
441
442 break;
d9160afd 443 case S5P_FIMC_YCBYCR422...S5P_FIMC_CRYCBY422:
ef7af59b 444 if (frame->fmt->colplanes == 1) {
5fd8f738
SN		 445 cfg |= ctx->in_order_1p
446 | S5P_MSCTRL_INFORMAT_YCBCR422_1P;
447 } else {
448 cfg |= S5P_MSCTRL_INFORMAT_YCBCR422;
449
ef7af59b 450 if (frame->fmt->colplanes == 2)
5fd8f738
SN		 451 cfg |= ctx->in_order_2p
452 | S5P_MSCTRL_C_INT_IN_2PLANE;
453 else
454 cfg |= S5P_MSCTRL_C_INT_IN_3PLANE;
455 }
456 break;
457 default:
458 break;
459 }
460
5fd8f738
SN		 461 writel(cfg, dev->regs + S5P_MSCTRL);
462
463 /* Input/output DMA linear/tiled mode. */
464 cfg = readl(dev->regs + S5P_CIDMAPARAM);
465 cfg &= ~S5P_CIDMAPARAM_TILE_MASK;
466
467 if (tiled_fmt(ctx->s_frame.fmt))
468 cfg |= S5P_CIDMAPARAM_R_64X32;
469
470 if (tiled_fmt(ctx->d_frame.fmt))
471 cfg |= S5P_CIDMAPARAM_W_64X32;
472
473 writel(cfg, dev->regs + S5P_CIDMAPARAM);
474}
475
476
477void fimc_hw_set_input_path(struct fimc_ctx *ctx)
478{
479 struct fimc_dev *dev = ctx->fimc_dev;
480
481 u32 cfg = readl(dev->regs + S5P_MSCTRL);
482 cfg &= ~S5P_MSCTRL_INPUT_MASK;
483
484 if (ctx->in_path == FIMC_DMA)
485 cfg |= S5P_MSCTRL_INPUT_MEMORY;
486 else
487 cfg |= S5P_MSCTRL_INPUT_EXTCAM;
488
489 writel(cfg, dev->regs + S5P_MSCTRL);
490}
491
492void fimc_hw_set_output_path(struct fimc_ctx *ctx)
493{
494 struct fimc_dev *dev = ctx->fimc_dev;
495
496 u32 cfg = readl(dev->regs + S5P_CISCCTRL);
497 cfg &= ~S5P_CISCCTRL_LCDPATHEN_FIFO;
498 if (ctx->out_path == FIMC_LCDFIFO)
499 cfg |= S5P_CISCCTRL_LCDPATHEN_FIFO;
500 writel(cfg, dev->regs + S5P_CISCCTRL);
501}
502
503void fimc_hw_set_input_addr(struct fimc_dev *dev, struct fimc_addr *paddr)
504{
548aafcd 505 u32 cfg = readl(dev->regs + S5P_CIREAL_ISIZE);
5fd8f738
SN		 506 cfg |= S5P_CIREAL_ISIZE_ADDR_CH_DIS;
507 writel(cfg, dev->regs + S5P_CIREAL_ISIZE);
508
77e62082
SN		 509 writel(paddr->y, dev->regs + S5P_CIIYSA(0));
510 writel(paddr->cb, dev->regs + S5P_CIICBSA(0));
511 writel(paddr->cr, dev->regs + S5P_CIICRSA(0));
5fd8f738
SN		 512
513 cfg &= ~S5P_CIREAL_ISIZE_ADDR_CH_DIS;
514 writel(cfg, dev->regs + S5P_CIREAL_ISIZE);
515}
516
548aafcd
SN		 517void fimc_hw_set_output_addr(struct fimc_dev *dev,
518 struct fimc_addr *paddr, int index)
5fd8f738 519{
548aafcd
SN		 520 int i = (index == -1) ? 0 : index;
521 do {
5fd8f738
SN		 522 writel(paddr->y, dev->regs + S5P_CIOYSA(i));
523 writel(paddr->cb, dev->regs + S5P_CIOCBSA(i));
524 writel(paddr->cr, dev->regs + S5P_CIOCRSA(i));
548aafcd
SN		 525 dbg("dst_buf[%d]: 0x%X, cb: 0x%X, cr: 0x%X",
526 i, paddr->y, paddr->cb, paddr->cr);
527 } while (index == -1 && ++i < FIMC_MAX_OUT_BUFS);
5fd8f738 528}
5f3cc447
SN		 529
530int fimc_hw_set_camera_polarity(struct fimc_dev *fimc,
df7e09a3 531 struct s5p_fimc_isp_info *cam)
5f3cc447
SN		 532{
533 u32 cfg = readl(fimc->regs + S5P_CIGCTRL);
534
535 cfg &= ~(S5P_CIGCTRL_INVPOLPCLK | S5P_CIGCTRL_INVPOLVSYNC |
536 S5P_CIGCTRL_INVPOLHREF | S5P_CIGCTRL_INVPOLHSYNC);
537
538 if (cam->flags & FIMC_CLK_INV_PCLK)
539 cfg |= S5P_CIGCTRL_INVPOLPCLK;
540
541 if (cam->flags & FIMC_CLK_INV_VSYNC)
542 cfg |= S5P_CIGCTRL_INVPOLVSYNC;
543
544 if (cam->flags & FIMC_CLK_INV_HREF)
545 cfg |= S5P_CIGCTRL_INVPOLHREF;
546
547 if (cam->flags & FIMC_CLK_INV_HSYNC)
548 cfg |= S5P_CIGCTRL_INVPOLHSYNC;
549
550 writel(cfg, fimc->regs + S5P_CIGCTRL);
551
552 return 0;
553}
554
555int fimc_hw_set_camera_source(struct fimc_dev *fimc,
df7e09a3 556 struct s5p_fimc_isp_info *cam)
5f3cc447
SN		 557{
558 struct fimc_frame *f = &fimc->vid_cap.ctx->s_frame;
559 u32 cfg = 0;
3d0ce7ed
SN		 560 u32 bus_width;
561 int i;
562
563 static const struct {
564 u32 pixelcode;
565 u32 cisrcfmt;
566 u16 bus_width;
567 } pix_desc[] = {
568 { V4L2_MBUS_FMT_YUYV8_2X8, S5P_CISRCFMT_ORDER422_YCBYCR, 8 },
569 { V4L2_MBUS_FMT_YVYU8_2X8, S5P_CISRCFMT_ORDER422_YCRYCB, 8 },
570 { V4L2_MBUS_FMT_VYUY8_2X8, S5P_CISRCFMT_ORDER422_CRYCBY, 8 },
571 { V4L2_MBUS_FMT_UYVY8_2X8, S5P_CISRCFMT_ORDER422_CBYCRY, 8 },
572 /* TODO: Add pixel codes for 16-bit bus width */
573 };
5f3cc447
SN		 574
575 if (cam->bus_type == FIMC_ITU_601 || cam->bus_type == FIMC_ITU_656) {
3d0ce7ed 576 for (i = 0; i < ARRAY_SIZE(pix_desc); i++) {
237e0265 577 if (fimc->vid_cap.mf.code == pix_desc[i].pixelcode) {
3d0ce7ed
SN		 578 cfg = pix_desc[i].cisrcfmt;
579 bus_width = pix_desc[i].bus_width;
580 break;
581 }
582 }
5f3cc447 583
3d0ce7ed 584 if (i == ARRAY_SIZE(pix_desc)) {
30c9939d 585 v4l2_err(fimc->vid_cap.vfd,
3d0ce7ed 586 "Camera color format not supported: %d\n",
237e0265 587 fimc->vid_cap.mf.code);
5f3cc447
SN		 588 return -EINVAL;
589 }
590
591 if (cam->bus_type == FIMC_ITU_601) {
3d0ce7ed 592 if (bus_width == 8)
5f3cc447 593 cfg |= S5P_CISRCFMT_ITU601_8BIT;
3d0ce7ed 594 else if (bus_width == 16)
5f3cc447 595 cfg |= S5P_CISRCFMT_ITU601_16BIT;
5f3cc447 596 } /* else defaults to ITU-R BT.656 8-bit */
ee7160e5
SN		 597 } else if (cam->bus_type == FIMC_MIPI_CSI2) {
598 if (fimc_fmt_is_jpeg(f->fmt->color))
599 cfg |= S5P_CISRCFMT_ITU601_8BIT;
5f3cc447
SN		 600 }
601
602 cfg |= S5P_CISRCFMT_HSIZE(f->o_width) | S5P_CISRCFMT_VSIZE(f->o_height);
603 writel(cfg, fimc->regs + S5P_CISRCFMT);
604 return 0;
605}
606
607
608int fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f)
609{
610 u32 hoff2, voff2;
611
612 u32 cfg = readl(fimc->regs + S5P_CIWDOFST);
613
614 cfg &= ~(S5P_CIWDOFST_HOROFF_MASK | S5P_CIWDOFST_VEROFF_MASK);
615 cfg |= S5P_CIWDOFST_OFF_EN |
616 S5P_CIWDOFST_HOROFF(f->offs_h) |
617 S5P_CIWDOFST_VEROFF(f->offs_v);
618
619 writel(cfg, fimc->regs + S5P_CIWDOFST);
620
621 /* See CIWDOFSTn register description in the datasheet for details. */
622 hoff2 = f->o_width - f->width - f->offs_h;
623 voff2 = f->o_height - f->height - f->offs_v;
624 cfg = S5P_CIWDOFST2_HOROFF(hoff2) | S5P_CIWDOFST2_VEROFF(voff2);
625
626 writel(cfg, fimc->regs + S5P_CIWDOFST2);
627 return 0;
628}
629
630int fimc_hw_set_camera_type(struct fimc_dev *fimc,
df7e09a3 631 struct s5p_fimc_isp_info *cam)
5f3cc447
SN		 632{
633 u32 cfg, tmp;
634 struct fimc_vid_cap *vid_cap = &fimc->vid_cap;
635
636 cfg = readl(fimc->regs + S5P_CIGCTRL);
637
638 /* Select ITU B interface, disable Writeback path and test pattern. */
639 cfg &= ~(S5P_CIGCTRL_TESTPAT_MASK | S5P_CIGCTRL_SELCAM_ITU_A |
640 S5P_CIGCTRL_SELCAM_MIPI | S5P_CIGCTRL_CAMIF_SELWB |
ee7160e5 641 S5P_CIGCTRL_SELCAM_MIPI_A | S5P_CIGCTRL_CAM_JPEG);
5f3cc447
SN		 642
643 if (cam->bus_type == FIMC_MIPI_CSI2) {
644 cfg |= S5P_CIGCTRL_SELCAM_MIPI;
645
646 if (cam->mux_id == 0)
647 cfg |= S5P_CIGCTRL_SELCAM_MIPI_A;
648
649 /* TODO: add remaining supported formats. */
ee7160e5
SN		 650 switch (vid_cap->mf.code) {
651 case V4L2_MBUS_FMT_VYUY8_2X8:
5f3cc447 652 tmp = S5P_CSIIMGFMT_YCBCR422_8BIT;
ee7160e5
SN		 653 break;
654 case V4L2_MBUS_FMT_JPEG_1X8:
655 tmp = S5P_CSIIMGFMT_USER(1);
656 cfg |= S5P_CIGCTRL_CAM_JPEG;
657 break;
658 default:
30c9939d
SN		 659 v4l2_err(fimc->vid_cap.vfd,
660 "Not supported camera pixel format: %d",
237e0265 661 vid_cap->mf.code);
5f3cc447
SN		 662 return -EINVAL;
663 }
e0eec9af
SN		 664 tmp |= (cam->csi_data_align == 32) << 8;
665
666 writel(tmp, fimc->regs + S5P_CSIIMGFMT);
5f3cc447
SN		 667
668 } else if (cam->bus_type == FIMC_ITU_601 ||
e0eec9af 669 cam->bus_type == FIMC_ITU_656) {
5f3cc447
SN		 670 if (cam->mux_id == 0) /* ITU-A, ITU-B: 0, 1 */
671 cfg |= S5P_CIGCTRL_SELCAM_ITU_A;
672 } else if (cam->bus_type == FIMC_LCD_WB) {
673 cfg |= S5P_CIGCTRL_CAMIF_SELWB;
674 } else {
675 err("invalid camera bus type selected\n");
676 return -EINVAL;
677 }
678 writel(cfg, fimc->regs + S5P_CIGCTRL);
679
680 return 0;
681}
Linux kernel - Deliverables
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