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[media] s5p-fimc: Prefix format enumerations with FIMC_FMT_
[deliverable/linux.git] / drivers / media / video / s5p-fimc / fimc-reg.c
CommitLineData
5fd8f738
SN		 1/*
2 * Register interface file for Samsung Camera Interface (FIMC) driver
3 *
4 * Copyright (c) 2010 Samsung Electronics
5 *
6 * Sylwester Nawrocki, s.nawrocki@samsung.com
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/io.h>
14#include <linux/delay.h>
df7e09a3 15#include <media/s5p_fimc.h>
5fd8f738 16
c83a1ff0 17#include "fimc-reg.h"
5fd8f738
SN		 18#include "fimc-core.h"
19
20
21void fimc_hw_reset(struct fimc_dev *dev)
22{
23 u32 cfg;
24
c83a1ff0
SN		 25 cfg = readl(dev->regs + FIMC_REG_CISRCFMT);
26 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT;
27 writel(cfg, dev->regs + FIMC_REG_CISRCFMT);
5fd8f738
SN		 28
29 /* Software reset. */
c83a1ff0
SN		 30 cfg = readl(dev->regs + FIMC_REG_CIGCTRL);
31 cfg |= (FIMC_REG_CIGCTRL_SWRST | FIMC_REG_CIGCTRL_IRQ_LEVEL);
32 writel(cfg, dev->regs + FIMC_REG_CIGCTRL);
e9e21083 33 udelay(10);
5fd8f738 34
c83a1ff0
SN		 35 cfg = readl(dev->regs + FIMC_REG_CIGCTRL);
36 cfg &= ~FIMC_REG_CIGCTRL_SWRST;
37 writel(cfg, dev->regs + FIMC_REG_CIGCTRL);
2c1bb62e
SN		 38
39 if (dev->variant->out_buf_count > 4)
40 fimc_hw_set_dma_seq(dev, 0xF);
5fd8f738
SN		 41}
42
ac75934c 43static u32 fimc_hw_get_in_flip(struct fimc_ctx *ctx)
5fd8f738 44{
c83a1ff0 45 u32 flip = FIMC_REG_MSCTRL_FLIP_NORMAL;
5fd8f738 46
131b6c61 47 if (ctx->hflip)
c83a1ff0 48 flip = FIMC_REG_MSCTRL_FLIP_X_MIRROR;
131b6c61 49 if (ctx->vflip)
c83a1ff0 50 flip = FIMC_REG_MSCTRL_FLIP_Y_MIRROR;
131b6c61 51
ac75934c
SN		 52 if (ctx->rotation <= 90)
53 return flip;
5fd8f738 54
c83a1ff0 55 return (flip ^ FIMC_REG_MSCTRL_FLIP_180) & FIMC_REG_MSCTRL_FLIP_180;
5fd8f738
SN		 56}
57
ac75934c 58static u32 fimc_hw_get_target_flip(struct fimc_ctx *ctx)
5fd8f738 59{
c83a1ff0 60 u32 flip = FIMC_REG_CITRGFMT_FLIP_NORMAL;
5fd8f738 61
131b6c61 62 if (ctx->hflip)
c83a1ff0 63 flip |= FIMC_REG_CITRGFMT_FLIP_X_MIRROR;
131b6c61 64 if (ctx->vflip)
c83a1ff0 65 flip |= FIMC_REG_CITRGFMT_FLIP_Y_MIRROR;
131b6c61 66
ac75934c
SN		 67 if (ctx->rotation <= 90)
68 return flip;
69
c83a1ff0 70 return (flip ^ FIMC_REG_CITRGFMT_FLIP_180) & FIMC_REG_CITRGFMT_FLIP_180;
5fd8f738
SN		 71}
72
47654df8
SN		 73void fimc_hw_set_rotation(struct fimc_ctx *ctx)
74{
75 u32 cfg, flip;
76 struct fimc_dev *dev = ctx->fimc_dev;
77
c83a1ff0
SN		 78 cfg = readl(dev->regs + FIMC_REG_CITRGFMT);
79 cfg &= ~(FIMC_REG_CITRGFMT_INROT90 | FIMC_REG_CITRGFMT_OUTROT90 |
80 FIMC_REG_CITRGFMT_FLIP_180);
47654df8
SN		 81
82 /*
83 * The input and output rotator cannot work simultaneously.
84 * Use the output rotator in output DMA mode or the input rotator
85 * in direct fifo output mode.
86 */
87 if (ctx->rotation == 90 || ctx->rotation == 270) {
3d112d9a 88 if (ctx->out_path == FIMC_IO_LCDFIFO)
c83a1ff0 89 cfg |= FIMC_REG_CITRGFMT_INROT90;
47654df8 90 else
c83a1ff0 91 cfg |= FIMC_REG_CITRGFMT_OUTROT90;
47654df8 92 }
47654df8 93
3d112d9a 94 if (ctx->out_path == FIMC_IO_DMA) {
ac75934c 95 cfg |= fimc_hw_get_target_flip(ctx);
c83a1ff0 96 writel(cfg, dev->regs + FIMC_REG_CITRGFMT);
ac75934c
SN		 97 } else {
98 /* LCD FIFO path */
c83a1ff0
SN		 99 flip = readl(dev->regs + FIMC_REG_MSCTRL);
100 flip &= ~FIMC_REG_MSCTRL_FLIP_MASK;
ac75934c 101 flip |= fimc_hw_get_in_flip(ctx);
c83a1ff0 102 writel(flip, dev->regs + FIMC_REG_MSCTRL);
ac75934c 103 }
47654df8
SN		 104}
105
5fd8f738
SN		 106void fimc_hw_set_target_format(struct fimc_ctx *ctx)
107{
108 u32 cfg;
109 struct fimc_dev *dev = ctx->fimc_dev;
110 struct fimc_frame *frame = &ctx->d_frame;
111
112 dbg("w= %d, h= %d color: %d", frame->width,
c83a1ff0 113 frame->height, frame->fmt->color);
5fd8f738 114
c83a1ff0
SN		 115 cfg = readl(dev->regs + FIMC_REG_CITRGFMT);
116 cfg &= ~(FIMC_REG_CITRGFMT_FMT_MASK | FIMC_REG_CITRGFMT_HSIZE_MASK |
117 FIMC_REG_CITRGFMT_VSIZE_MASK);
5fd8f738
SN		 118
119 switch (frame->fmt->color) {
3d112d9a 120 case FIMC_FMT_RGB444...FIMC_FMT_RGB888:
c83a1ff0 121 cfg |= FIMC_REG_CITRGFMT_RGB;
5fd8f738 122 break;
3d112d9a 123 case FIMC_FMT_YCBCR420:
c83a1ff0 124 cfg |= FIMC_REG_CITRGFMT_YCBCR420;
5fd8f738 125 break;
3d112d9a 126 case FIMC_FMT_YCBYCR422...FIMC_FMT_CRYCBY422:
ef7af59b 127 if (frame->fmt->colplanes == 1)
c83a1ff0 128 cfg |= FIMC_REG_CITRGFMT_YCBCR422_1P;
5fd8f738 129 else
c83a1ff0 130 cfg |= FIMC_REG_CITRGFMT_YCBCR422;
5fd8f738
SN		 131 break;
132 default:
133 break;
134 }
135
c83a1ff0
SN		 136 if (ctx->rotation == 90 || ctx->rotation == 270)
137 cfg |= (frame->height << 16) | frame->width;
138 else
139 cfg |= (frame->width << 16) | frame->height;
47654df8 140
c83a1ff0 141 writel(cfg, dev->regs + FIMC_REG_CITRGFMT);
5fd8f738 142
c83a1ff0
SN		 143 cfg = readl(dev->regs + FIMC_REG_CITAREA);
144 cfg &= ~FIMC_REG_CITAREA_MASK;
5fd8f738 145 cfg |= (frame->width * frame->height);
c83a1ff0 146 writel(cfg, dev->regs + FIMC_REG_CITAREA);
5fd8f738
SN		 147}
148
149static void fimc_hw_set_out_dma_size(struct fimc_ctx *ctx)
150{
151 struct fimc_dev *dev = ctx->fimc_dev;
152 struct fimc_frame *frame = &ctx->d_frame;
47654df8 153 u32 cfg;
5fd8f738 154
c83a1ff0
SN		 155 cfg = (frame->f_height << 16) | frame->f_width;
156 writel(cfg, dev->regs + FIMC_REG_ORGOSIZE);
5f3cc447
SN		 157
158 /* Select color space conversion equation (HD/SD size).*/
c83a1ff0 159 cfg = readl(dev->regs + FIMC_REG_CIGCTRL);
5f3cc447 160 if (frame->f_width >= 1280) /* HD */
c83a1ff0 161 cfg |= FIMC_REG_CIGCTRL_CSC_ITU601_709;
5f3cc447 162 else /* SD */
c83a1ff0
SN		 163 cfg &= ~FIMC_REG_CIGCTRL_CSC_ITU601_709;
164 writel(cfg, dev->regs + FIMC_REG_CIGCTRL);
5f3cc447 165
5fd8f738
SN		 166}
167
168void fimc_hw_set_out_dma(struct fimc_ctx *ctx)
169{
5fd8f738
SN		 170 struct fimc_dev *dev = ctx->fimc_dev;
171 struct fimc_frame *frame = &ctx->d_frame;
172 struct fimc_dma_offset *offset = &frame->dma_offset;
dafb9c70 173 struct fimc_fmt *fmt = frame->fmt;
c83a1ff0 174 u32 cfg;
5fd8f738
SN		 175
176 /* Set the input dma offsets. */
c83a1ff0
SN		 177 cfg = (offset->y_v << 16) | offset->y_h;
178 writel(cfg, dev->regs + FIMC_REG_CIOYOFF);
5fd8f738 179
c83a1ff0
SN		 180 cfg = (offset->cb_v << 16) | offset->cb_h;
181 writel(cfg, dev->regs + FIMC_REG_CIOCBOFF);
5fd8f738 182
c83a1ff0
SN		 183 cfg = (offset->cr_v << 16) | offset->cr_h;
184 writel(cfg, dev->regs + FIMC_REG_CIOCROFF);
5fd8f738
SN		 185
186 fimc_hw_set_out_dma_size(ctx);
187
188 /* Configure chroma components order. */
c83a1ff0 189 cfg = readl(dev->regs + FIMC_REG_CIOCTRL);
5fd8f738 190
c83a1ff0
SN		 191 cfg &= ~(FIMC_REG_CIOCTRL_ORDER2P_MASK |
192 FIMC_REG_CIOCTRL_ORDER422_MASK |
193 FIMC_REG_CIOCTRL_YCBCR_PLANE_MASK |
194 FIMC_REG_CIOCTRL_RGB16FMT_MASK);
5fd8f738 195
dafb9c70 196 if (fmt->colplanes == 1)
5fd8f738 197 cfg |= ctx->out_order_1p;
dafb9c70 198 else if (fmt->colplanes == 2)
c83a1ff0 199 cfg |= ctx->out_order_2p | FIMC_REG_CIOCTRL_YCBCR_2PLANE;
dafb9c70 200 else if (fmt->colplanes == 3)
c83a1ff0 201 cfg |= FIMC_REG_CIOCTRL_YCBCR_3PLANE;
5fd8f738 202
3d112d9a 203 if (fmt->color == FIMC_FMT_RGB565)
c83a1ff0 204 cfg |= FIMC_REG_CIOCTRL_RGB565;
3d112d9a 205 else if (fmt->color == FIMC_FMT_RGB555)
c83a1ff0 206 cfg |= FIMC_REG_CIOCTRL_ARGB1555;
3d112d9a 207 else if (fmt->color == FIMC_FMT_RGB444)
c83a1ff0 208 cfg |= FIMC_REG_CIOCTRL_ARGB4444;
dafb9c70 209
c83a1ff0 210 writel(cfg, dev->regs + FIMC_REG_CIOCTRL);
5fd8f738
SN		 211}
212
213static void fimc_hw_en_autoload(struct fimc_dev *dev, int enable)
214{
c83a1ff0 215 u32 cfg = readl(dev->regs + FIMC_REG_ORGISIZE);
5fd8f738 216 if (enable)
c83a1ff0 217 cfg |= FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN;
5fd8f738 218 else
c83a1ff0
SN		 219 cfg &= ~FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN;
220 writel(cfg, dev->regs + FIMC_REG_ORGISIZE);
5fd8f738
SN		 221}
222
223void fimc_hw_en_lastirq(struct fimc_dev *dev, int enable)
224{
c83a1ff0 225 u32 cfg = readl(dev->regs + FIMC_REG_CIOCTRL);
5fd8f738 226 if (enable)
c83a1ff0 227 cfg |= FIMC_REG_CIOCTRL_LASTIRQ_ENABLE;
5fd8f738 228 else
c83a1ff0
SN		 229 cfg &= ~FIMC_REG_CIOCTRL_LASTIRQ_ENABLE;
230 writel(cfg, dev->regs + FIMC_REG_CIOCTRL);
5fd8f738
SN		 231}
232
b241c6d6 233void fimc_hw_set_prescaler(struct fimc_ctx *ctx)
5fd8f738
SN		 234{
235 struct fimc_dev *dev = ctx->fimc_dev;
236 struct fimc_scaler *sc = &ctx->scaler;
548aafcd 237 u32 cfg, shfactor;
5fd8f738
SN		 238
239 shfactor = 10 - (sc->hfactor + sc->vfactor);
c83a1ff0 240 cfg = shfactor << 28;
5fd8f738 241
c83a1ff0
SN		 242 cfg |= (sc->pre_hratio << 16) | sc->pre_vratio;
243 writel(cfg, dev->regs + FIMC_REG_CISCPRERATIO);
5fd8f738 244
c83a1ff0
SN		 245 cfg = (sc->pre_dst_width << 16) | sc->pre_dst_height;
246 writel(cfg, dev->regs + FIMC_REG_CISCPREDST);
5fd8f738
SN		 247}
248
b241c6d6 249static void fimc_hw_set_scaler(struct fimc_ctx *ctx)
5fd8f738
SN		 250{
251 struct fimc_dev *dev = ctx->fimc_dev;
252 struct fimc_scaler *sc = &ctx->scaler;
253 struct fimc_frame *src_frame = &ctx->s_frame;
254 struct fimc_frame *dst_frame = &ctx->d_frame;
2c1bb62e 255
c83a1ff0 256 u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL);
2c1bb62e 257
c83a1ff0
SN		 258 cfg &= ~(FIMC_REG_CISCCTRL_CSCR2Y_WIDE | FIMC_REG_CISCCTRL_CSCY2R_WIDE |
259 FIMC_REG_CISCCTRL_SCALEUP_H | FIMC_REG_CISCCTRL_SCALEUP_V |
260 FIMC_REG_CISCCTRL_SCALERBYPASS | FIMC_REG_CISCCTRL_ONE2ONE |
261 FIMC_REG_CISCCTRL_INRGB_FMT_MASK | FIMC_REG_CISCCTRL_OUTRGB_FMT_MASK |
262 FIMC_REG_CISCCTRL_INTERLACE | FIMC_REG_CISCCTRL_RGB_EXT);
5fd8f738
SN		 263
264 if (!(ctx->flags & FIMC_COLOR_RANGE_NARROW))
c83a1ff0
SN		 265 cfg |= (FIMC_REG_CISCCTRL_CSCR2Y_WIDE |
266 FIMC_REG_CISCCTRL_CSCY2R_WIDE);
5fd8f738
SN		 267
268 if (!sc->enabled)
c83a1ff0 269 cfg |= FIMC_REG_CISCCTRL_SCALERBYPASS;
5fd8f738
SN		 270
271 if (sc->scaleup_h)
c83a1ff0 272 cfg |= FIMC_REG_CISCCTRL_SCALEUP_H;
5fd8f738
SN		 273
274 if (sc->scaleup_v)
c83a1ff0 275 cfg |= FIMC_REG_CISCCTRL_SCALEUP_V;
5fd8f738
SN		 276
277 if (sc->copy_mode)
c83a1ff0 278 cfg |= FIMC_REG_CISCCTRL_ONE2ONE;
5fd8f738 279
3d112d9a 280 if (ctx->in_path == FIMC_IO_DMA) {
dafb9c70 281 switch (src_frame->fmt->color) {
3d112d9a 282 case FIMC_FMT_RGB565:
c83a1ff0 283 cfg |= FIMC_REG_CISCCTRL_INRGB_FMT_RGB565;
dafb9c70 284 break;
3d112d9a 285 case FIMC_FMT_RGB666:
c83a1ff0 286 cfg |= FIMC_REG_CISCCTRL_INRGB_FMT_RGB666;
dafb9c70 287 break;
3d112d9a 288 case FIMC_FMT_RGB888:
c83a1ff0 289 cfg |= FIMC_REG_CISCCTRL_INRGB_FMT_RGB888;
dafb9c70
SN		 290 break;
291 }
5fd8f738
SN		 292 }
293
3d112d9a 294 if (ctx->out_path == FIMC_IO_DMA) {
dafb9c70
SN		 295 u32 color = dst_frame->fmt->color;
296
3d112d9a 297 if (color >= FIMC_FMT_RGB444 && color <= FIMC_FMT_RGB565)
c83a1ff0 298 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB565;
3d112d9a 299 else if (color == FIMC_FMT_RGB666)
c83a1ff0 300 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB666;
3d112d9a 301 else if (color == FIMC_FMT_RGB888)
c83a1ff0 302 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB888;
5fd8f738 303 } else {
c83a1ff0 304 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB888;
5fd8f738
SN		 305
306 if (ctx->flags & FIMC_SCAN_MODE_INTERLACED)
c83a1ff0 307 cfg |= FIMC_REG_CISCCTRL_INTERLACE;
5fd8f738
SN		 308 }
309
c83a1ff0 310 writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
b241c6d6
HK		 311}
312
313void fimc_hw_set_mainscaler(struct fimc_ctx *ctx)
314{
315 struct fimc_dev *dev = ctx->fimc_dev;
70f66ea2 316 struct samsung_fimc_variant *variant = dev->variant;
b241c6d6
HK		 317 struct fimc_scaler *sc = &ctx->scaler;
318 u32 cfg;
319
320 dbg("main_hratio= 0x%X main_vratio= 0x%X",
c83a1ff0 321 sc->main_hratio, sc->main_vratio);
b241c6d6
HK		 322
323 fimc_hw_set_scaler(ctx);
324
c83a1ff0
SN		 325 cfg = readl(dev->regs + FIMC_REG_CISCCTRL);
326 cfg &= ~(FIMC_REG_CISCCTRL_MHRATIO_MASK |
327 FIMC_REG_CISCCTRL_MVRATIO_MASK);
b241c6d6 328
70f66ea2 329 if (variant->has_mainscaler_ext) {
c83a1ff0
SN		 330 cfg |= FIMC_REG_CISCCTRL_MHRATIO_EXT(sc->main_hratio);
331 cfg |= FIMC_REG_CISCCTRL_MVRATIO_EXT(sc->main_vratio);
332 writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
b241c6d6 333
c83a1ff0 334 cfg = readl(dev->regs + FIMC_REG_CIEXTEN);
b241c6d6 335
c83a1ff0
SN		 336 cfg &= ~(FIMC_REG_CIEXTEN_MVRATIO_EXT_MASK |
337 FIMC_REG_CIEXTEN_MHRATIO_EXT_MASK);
338 cfg |= FIMC_REG_CIEXTEN_MHRATIO_EXT(sc->main_hratio);
339 cfg |= FIMC_REG_CIEXTEN_MVRATIO_EXT(sc->main_vratio);
340 writel(cfg, dev->regs + FIMC_REG_CIEXTEN);
70f66ea2 341 } else {
c83a1ff0
SN		 342 cfg |= FIMC_REG_CISCCTRL_MHRATIO(sc->main_hratio);
343 cfg |= FIMC_REG_CISCCTRL_MVRATIO(sc->main_vratio);
344 writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
70f66ea2 345 }
5fd8f738
SN		 346}
347
348void fimc_hw_en_capture(struct fimc_ctx *ctx)
349{
350 struct fimc_dev *dev = ctx->fimc_dev;
5fd8f738 351
c83a1ff0 352 u32 cfg = readl(dev->regs + FIMC_REG_CIIMGCPT);
5f3cc447 353
3d112d9a 354 if (ctx->out_path == FIMC_IO_DMA) {
5f3cc447 355 /* one shot mode */
c83a1ff0
SN		 356 cfg |= FIMC_REG_CIIMGCPT_CPT_FREN_ENABLE |
357 FIMC_REG_CIIMGCPT_IMGCPTEN;
5f3cc447 358 } else {
25985edc 359 /* Continuous frame capture mode (freerun). */
c83a1ff0
SN		 360 cfg &= ~(FIMC_REG_CIIMGCPT_CPT_FREN_ENABLE |
361 FIMC_REG_CIIMGCPT_CPT_FRMOD_CNT);
362 cfg |= FIMC_REG_CIIMGCPT_IMGCPTEN;
5f3cc447 363 }
5fd8f738
SN		 364
365 if (ctx->scaler.enabled)
c83a1ff0 366 cfg |= FIMC_REG_CIIMGCPT_IMGCPTEN_SC;
5fd8f738 367
c83a1ff0
SN		 368 cfg |= FIMC_REG_CIIMGCPT_IMGCPTEN;
369 writel(cfg, dev->regs + FIMC_REG_CIIMGCPT);
5fd8f738
SN		 370}
371
ee7160e5 372void fimc_hw_set_effect(struct fimc_ctx *ctx, bool active)
5fd8f738
SN		 373{
374 struct fimc_dev *dev = ctx->fimc_dev;
375 struct fimc_effect *effect = &ctx->effect;
ee7160e5 376 u32 cfg = 0;
5fd8f738 377
ee7160e5 378 if (active) {
c83a1ff0
SN		 379 cfg |= FIMC_REG_CIIMGEFF_IE_SC_AFTER |
380 FIMC_REG_CIIMGEFF_IE_ENABLE;
ee7160e5 381 cfg |= effect->type;
c83a1ff0
SN		 382 if (effect->type == FIMC_REG_CIIMGEFF_FIN_ARBITRARY)
383 cfg |= (effect->pat_cb << 13) | effect->pat_cr;
5fd8f738
SN		 384 }
385
c83a1ff0 386 writel(cfg, dev->regs + FIMC_REG_CIIMGEFF);
5fd8f738
SN		 387}
388
dafb9c70
SN		 389void fimc_hw_set_rgb_alpha(struct fimc_ctx *ctx)
390{
391 struct fimc_dev *dev = ctx->fimc_dev;
392 struct fimc_frame *frame = &ctx->d_frame;
393 u32 cfg;
394
395 if (!(frame->fmt->flags & FMT_HAS_ALPHA))
396 return;
397
c83a1ff0
SN		 398 cfg = readl(dev->regs + FIMC_REG_CIOCTRL);
399 cfg &= ~FIMC_REG_CIOCTRL_ALPHA_OUT_MASK;
dafb9c70 400 cfg |= (frame->alpha << 4);
c83a1ff0 401 writel(cfg, dev->regs + FIMC_REG_CIOCTRL);
dafb9c70
SN		 402}
403
5fd8f738
SN		 404static void fimc_hw_set_in_dma_size(struct fimc_ctx *ctx)
405{
406 struct fimc_dev *dev = ctx->fimc_dev;
407 struct fimc_frame *frame = &ctx->s_frame;
408 u32 cfg_o = 0;
409 u32 cfg_r = 0;
410
3d112d9a 411 if (FIMC_IO_LCDFIFO == ctx->out_path)
c83a1ff0 412 cfg_r |= FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN;
5fd8f738 413
c83a1ff0
SN		 414 cfg_o |= (frame->f_height << 16) | frame->f_width;
415 cfg_r |= (frame->height << 16) | frame->width;
5fd8f738 416
c83a1ff0
SN		 417 writel(cfg_o, dev->regs + FIMC_REG_ORGISIZE);
418 writel(cfg_r, dev->regs + FIMC_REG_CIREAL_ISIZE);
5fd8f738
SN		 419}
420
421void fimc_hw_set_in_dma(struct fimc_ctx *ctx)
422{
423 struct fimc_dev *dev = ctx->fimc_dev;
424 struct fimc_frame *frame = &ctx->s_frame;
425 struct fimc_dma_offset *offset = &frame->dma_offset;
548aafcd 426 u32 cfg;
5fd8f738
SN		 427
428 /* Set the pixel offsets. */
c83a1ff0
SN		 429 cfg = (offset->y_v << 16) | offset->y_h;
430 writel(cfg, dev->regs + FIMC_REG_CIIYOFF);
5fd8f738 431
c83a1ff0
SN		 432 cfg = (offset->cb_v << 16) | offset->cb_h;
433 writel(cfg, dev->regs + FIMC_REG_CIICBOFF);
5fd8f738 434
c83a1ff0
SN		 435 cfg = (offset->cr_v << 16) | offset->cr_h;
436 writel(cfg, dev->regs + FIMC_REG_CIICROFF);
5fd8f738
SN		 437
438 /* Input original and real size. */
439 fimc_hw_set_in_dma_size(ctx);
440
548aafcd 441 /* Use DMA autoload only in FIFO mode. */
3d112d9a 442 fimc_hw_en_autoload(dev, ctx->out_path == FIMC_IO_LCDFIFO);
5fd8f738
SN		 443
444 /* Set the input DMA to process single frame only. */
c83a1ff0
SN		 445 cfg = readl(dev->regs + FIMC_REG_MSCTRL);
446 cfg &= ~(FIMC_REG_MSCTRL_INFORMAT_MASK
447 | FIMC_REG_MSCTRL_IN_BURST_COUNT_MASK
448 | FIMC_REG_MSCTRL_INPUT_MASK
449 | FIMC_REG_MSCTRL_C_INT_IN_MASK
450 | FIMC_REG_MSCTRL_2P_IN_ORDER_MASK);
5fd8f738 451
c83a1ff0
SN		 452 cfg |= (FIMC_REG_MSCTRL_IN_BURST_COUNT(4)
453 | FIMC_REG_MSCTRL_INPUT_MEMORY
454 | FIMC_REG_MSCTRL_FIFO_CTRL_FULL);
5fd8f738
SN		 455
456 switch (frame->fmt->color) {
3d112d9a 457 case FIMC_FMT_RGB565...FIMC_FMT_RGB888:
c83a1ff0 458 cfg |= FIMC_REG_MSCTRL_INFORMAT_RGB;
5fd8f738 459 break;
3d112d9a 460 case FIMC_FMT_YCBCR420:
c83a1ff0 461 cfg |= FIMC_REG_MSCTRL_INFORMAT_YCBCR420;
5fd8f738 462
ef7af59b 463 if (frame->fmt->colplanes == 2)
c83a1ff0 464 cfg |= ctx->in_order_2p | FIMC_REG_MSCTRL_C_INT_IN_2PLANE;
5fd8f738 465 else
c83a1ff0 466 cfg |= FIMC_REG_MSCTRL_C_INT_IN_3PLANE;
5fd8f738
SN		 467
468 break;
3d112d9a 469 case FIMC_FMT_YCBYCR422...FIMC_FMT_CRYCBY422:
ef7af59b 470 if (frame->fmt->colplanes == 1) {
5fd8f738 471 cfg |= ctx->in_order_1p
c83a1ff0 472 | FIMC_REG_MSCTRL_INFORMAT_YCBCR422_1P;
5fd8f738 473 } else {
c83a1ff0 474 cfg |= FIMC_REG_MSCTRL_INFORMAT_YCBCR422;
5fd8f738 475
ef7af59b 476 if (frame->fmt->colplanes == 2)
5fd8f738 477 cfg |= ctx->in_order_2p
c83a1ff0 478 | FIMC_REG_MSCTRL_C_INT_IN_2PLANE;
5fd8f738 479 else
c83a1ff0 480 cfg |= FIMC_REG_MSCTRL_C_INT_IN_3PLANE;
5fd8f738
SN		 481 }
482 break;
483 default:
484 break;
485 }
486
c83a1ff0 487 writel(cfg, dev->regs + FIMC_REG_MSCTRL);
5fd8f738
SN		 488
489 /* Input/output DMA linear/tiled mode. */
c83a1ff0
SN		 490 cfg = readl(dev->regs + FIMC_REG_CIDMAPARAM);
491 cfg &= ~FIMC_REG_CIDMAPARAM_TILE_MASK;
5fd8f738
SN		 492
493 if (tiled_fmt(ctx->s_frame.fmt))
c83a1ff0 494 cfg |= FIMC_REG_CIDMAPARAM_R_64X32;
5fd8f738
SN		 495
496 if (tiled_fmt(ctx->d_frame.fmt))
c83a1ff0 497 cfg |= FIMC_REG_CIDMAPARAM_W_64X32;
5fd8f738 498
c83a1ff0 499 writel(cfg, dev->regs + FIMC_REG_CIDMAPARAM);
5fd8f738
SN		 500}
501
502
503void fimc_hw_set_input_path(struct fimc_ctx *ctx)
504{
505 struct fimc_dev *dev = ctx->fimc_dev;
506
c83a1ff0
SN		 507 u32 cfg = readl(dev->regs + FIMC_REG_MSCTRL);
508 cfg &= ~FIMC_REG_MSCTRL_INPUT_MASK;
5fd8f738 509
3d112d9a 510 if (ctx->in_path == FIMC_IO_DMA)
c83a1ff0 511 cfg |= FIMC_REG_MSCTRL_INPUT_MEMORY;
5fd8f738 512 else
c83a1ff0 513 cfg |= FIMC_REG_MSCTRL_INPUT_EXTCAM;
5fd8f738 514
c83a1ff0 515 writel(cfg, dev->regs + FIMC_REG_MSCTRL);
5fd8f738
SN		 516}
517
518void fimc_hw_set_output_path(struct fimc_ctx *ctx)
519{
520 struct fimc_dev *dev = ctx->fimc_dev;
521
c83a1ff0
SN		 522 u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL);
523 cfg &= ~FIMC_REG_CISCCTRL_LCDPATHEN_FIFO;
3d112d9a 524 if (ctx->out_path == FIMC_IO_LCDFIFO)
c83a1ff0
SN		 525 cfg |= FIMC_REG_CISCCTRL_LCDPATHEN_FIFO;
526 writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
5fd8f738
SN		 527}
528
529void fimc_hw_set_input_addr(struct fimc_dev *dev, struct fimc_addr *paddr)
530{
c83a1ff0
SN		 531 u32 cfg = readl(dev->regs + FIMC_REG_CIREAL_ISIZE);
532 cfg |= FIMC_REG_CIREAL_ISIZE_ADDR_CH_DIS;
533 writel(cfg, dev->regs + FIMC_REG_CIREAL_ISIZE);
5fd8f738 534
c83a1ff0
SN		 535 writel(paddr->y, dev->regs + FIMC_REG_CIIYSA(0));
536 writel(paddr->cb, dev->regs + FIMC_REG_CIICBSA(0));
537 writel(paddr->cr, dev->regs + FIMC_REG_CIICRSA(0));
5fd8f738 538
c83a1ff0
SN		 539 cfg &= ~FIMC_REG_CIREAL_ISIZE_ADDR_CH_DIS;
540 writel(cfg, dev->regs + FIMC_REG_CIREAL_ISIZE);
5fd8f738
SN		 541}
542
548aafcd
SN		 543void fimc_hw_set_output_addr(struct fimc_dev *dev,
544 struct fimc_addr *paddr, int index)
5fd8f738 545{
548aafcd
SN		 546 int i = (index == -1) ? 0 : index;
547 do {
c83a1ff0
SN		 548 writel(paddr->y, dev->regs + FIMC_REG_CIOYSA(i));
549 writel(paddr->cb, dev->regs + FIMC_REG_CIOCBSA(i));
550 writel(paddr->cr, dev->regs + FIMC_REG_CIOCRSA(i));
548aafcd
SN		 551 dbg("dst_buf[%d]: 0x%X, cb: 0x%X, cr: 0x%X",
552 i, paddr->y, paddr->cb, paddr->cr);
553 } while (index == -1 && ++i < FIMC_MAX_OUT_BUFS);
5fd8f738 554}
5f3cc447
SN		 555
556int fimc_hw_set_camera_polarity(struct fimc_dev *fimc,
df7e09a3 557 struct s5p_fimc_isp_info *cam)
5f3cc447 558{
c83a1ff0 559 u32 cfg = readl(fimc->regs + FIMC_REG_CIGCTRL);
5f3cc447 560
c83a1ff0
SN		 561 cfg &= ~(FIMC_REG_CIGCTRL_INVPOLPCLK | FIMC_REG_CIGCTRL_INVPOLVSYNC |
562 FIMC_REG_CIGCTRL_INVPOLHREF | FIMC_REG_CIGCTRL_INVPOLHSYNC |
563 FIMC_REG_CIGCTRL_INVPOLFIELD);
5f3cc447 564
12ecf56d 565 if (cam->flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
c83a1ff0 566 cfg |= FIMC_REG_CIGCTRL_INVPOLPCLK;
5f3cc447 567
12ecf56d 568 if (cam->flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
c83a1ff0 569 cfg |= FIMC_REG_CIGCTRL_INVPOLVSYNC;
5f3cc447 570
12ecf56d 571 if (cam->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
c83a1ff0 572 cfg |= FIMC_REG_CIGCTRL_INVPOLHREF;
5f3cc447 573
12ecf56d 574 if (cam->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
c83a1ff0 575 cfg |= FIMC_REG_CIGCTRL_INVPOLHSYNC;
5f3cc447 576
12ecf56d 577 if (cam->flags & V4L2_MBUS_FIELD_EVEN_LOW)
c83a1ff0 578 cfg |= FIMC_REG_CIGCTRL_INVPOLFIELD;
12ecf56d 579
c83a1ff0 580 writel(cfg, fimc->regs + FIMC_REG_CIGCTRL);
5f3cc447
SN		 581
582 return 0;
583}
584
c83a1ff0
SN		 585struct mbus_pixfmt_desc {
586 u32 pixelcode;
587 u32 cisrcfmt;
588 u16 bus_width;
589};
590
591static const struct mbus_pixfmt_desc pix_desc[] = {
592 { V4L2_MBUS_FMT_YUYV8_2X8, FIMC_REG_CISRCFMT_ORDER422_YCBYCR, 8 },
593 { V4L2_MBUS_FMT_YVYU8_2X8, FIMC_REG_CISRCFMT_ORDER422_YCRYCB, 8 },
594 { V4L2_MBUS_FMT_VYUY8_2X8, FIMC_REG_CISRCFMT_ORDER422_CRYCBY, 8 },
595 { V4L2_MBUS_FMT_UYVY8_2X8, FIMC_REG_CISRCFMT_ORDER422_CBYCRY, 8 },
596};
597
5f3cc447 598int fimc_hw_set_camera_source(struct fimc_dev *fimc,
df7e09a3 599 struct s5p_fimc_isp_info *cam)
5f3cc447
SN		 600{
601 struct fimc_frame *f = &fimc->vid_cap.ctx->s_frame;
602 u32 cfg = 0;
3d0ce7ed
SN		 603 u32 bus_width;
604 int i;
605
5f3cc447 606 if (cam->bus_type == FIMC_ITU_601 || cam->bus_type == FIMC_ITU_656) {
3d0ce7ed 607 for (i = 0; i < ARRAY_SIZE(pix_desc); i++) {
237e0265 608 if (fimc->vid_cap.mf.code == pix_desc[i].pixelcode) {
3d0ce7ed
SN		 609 cfg = pix_desc[i].cisrcfmt;
610 bus_width = pix_desc[i].bus_width;
611 break;
612 }
613 }
5f3cc447 614
3d0ce7ed 615 if (i == ARRAY_SIZE(pix_desc)) {
30c9939d 616 v4l2_err(fimc->vid_cap.vfd,
3d0ce7ed 617 "Camera color format not supported: %d\n",
237e0265 618 fimc->vid_cap.mf.code);
5f3cc447
SN		 619 return -EINVAL;
620 }
621
622 if (cam->bus_type == FIMC_ITU_601) {
3d0ce7ed 623 if (bus_width == 8)
c83a1ff0 624 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT;
3d0ce7ed 625 else if (bus_width == 16)
c83a1ff0 626 cfg |= FIMC_REG_CISRCFMT_ITU601_16BIT;
5f3cc447 627 } /* else defaults to ITU-R BT.656 8-bit */
ee7160e5
SN		 628 } else if (cam->bus_type == FIMC_MIPI_CSI2) {
629 if (fimc_fmt_is_jpeg(f->fmt->color))
c83a1ff0 630 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT;
5f3cc447
SN		 631 }
632
c83a1ff0
SN		 633 cfg |= (f->o_width << 16) | f->o_height;
634 writel(cfg, fimc->regs + FIMC_REG_CISRCFMT);
5f3cc447
SN		 635 return 0;
636}
637
c83a1ff0 638void fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f)
5f3cc447
SN		 639{
640 u32 hoff2, voff2;
641
c83a1ff0 642 u32 cfg = readl(fimc->regs + FIMC_REG_CIWDOFST);
5f3cc447 643
c83a1ff0
SN		 644 cfg &= ~(FIMC_REG_CIWDOFST_HOROFF_MASK | FIMC_REG_CIWDOFST_VEROFF_MASK);
645 cfg |= FIMC_REG_CIWDOFST_OFF_EN |
646 (f->offs_h << 16) | f->offs_v;
5f3cc447 647
c83a1ff0 648 writel(cfg, fimc->regs + FIMC_REG_CIWDOFST);
5f3cc447
SN		 649
650 /* See CIWDOFSTn register description in the datasheet for details. */
651 hoff2 = f->o_width - f->width - f->offs_h;
652 voff2 = f->o_height - f->height - f->offs_v;
c83a1ff0
SN		 653 cfg = (hoff2 << 16) | voff2;
654 writel(cfg, fimc->regs + FIMC_REG_CIWDOFST2);
5f3cc447
SN		 655}
656
657int fimc_hw_set_camera_type(struct fimc_dev *fimc,
df7e09a3 658 struct s5p_fimc_isp_info *cam)
5f3cc447
SN		 659{
660 u32 cfg, tmp;
661 struct fimc_vid_cap *vid_cap = &fimc->vid_cap;
20676a4c 662 u32 csis_data_alignment = 32;
5f3cc447 663
c83a1ff0 664 cfg = readl(fimc->regs + FIMC_REG_CIGCTRL);
5f3cc447
SN		 665
666 /* Select ITU B interface, disable Writeback path and test pattern. */
c83a1ff0
SN		 667 cfg &= ~(FIMC_REG_CIGCTRL_TESTPAT_MASK | FIMC_REG_CIGCTRL_SELCAM_ITU_A |
668 FIMC_REG_CIGCTRL_SELCAM_MIPI | FIMC_REG_CIGCTRL_CAMIF_SELWB |
669 FIMC_REG_CIGCTRL_SELCAM_MIPI_A | FIMC_REG_CIGCTRL_CAM_JPEG);
5f3cc447
SN		 670
671 if (cam->bus_type == FIMC_MIPI_CSI2) {
c83a1ff0 672 cfg |= FIMC_REG_CIGCTRL_SELCAM_MIPI;
5f3cc447
SN		 673
674 if (cam->mux_id == 0)
c83a1ff0 675 cfg |= FIMC_REG_CIGCTRL_SELCAM_MIPI_A;
5f3cc447
SN		 676
677 /* TODO: add remaining supported formats. */
ee7160e5
SN		 678 switch (vid_cap->mf.code) {
679 case V4L2_MBUS_FMT_VYUY8_2X8:
c83a1ff0 680 tmp = FIMC_REG_CSIIMGFMT_YCBCR422_8BIT;
ee7160e5
SN		 681 break;
682 case V4L2_MBUS_FMT_JPEG_1X8:
c83a1ff0
SN		 683 tmp = FIMC_REG_CSIIMGFMT_USER(1);
684 cfg |= FIMC_REG_CIGCTRL_CAM_JPEG;
ee7160e5
SN		 685 break;
686 default:
30c9939d
SN		 687 v4l2_err(fimc->vid_cap.vfd,
688 "Not supported camera pixel format: %d",
237e0265 689 vid_cap->mf.code);
5f3cc447
SN		 690 return -EINVAL;
691 }
20676a4c 692 tmp |= (csis_data_alignment == 32) << 8;
e0eec9af 693
c83a1ff0 694 writel(tmp, fimc->regs + FIMC_REG_CSIIMGFMT);
5f3cc447
SN		 695
696 } else if (cam->bus_type == FIMC_ITU_601 ||
e0eec9af 697 cam->bus_type == FIMC_ITU_656) {
5f3cc447 698 if (cam->mux_id == 0) /* ITU-A, ITU-B: 0, 1 */
c83a1ff0 699 cfg |= FIMC_REG_CIGCTRL_SELCAM_ITU_A;
5f3cc447 700 } else if (cam->bus_type == FIMC_LCD_WB) {
c83a1ff0 701 cfg |= FIMC_REG_CIGCTRL_CAMIF_SELWB;
5f3cc447
SN		 702 } else {
703 err("invalid camera bus type selected\n");
704 return -EINVAL;
705 }
c83a1ff0 706 writel(cfg, fimc->regs + FIMC_REG_CIGCTRL);
5f3cc447
SN		 707
708 return 0;
709}
c83a1ff0
SN		 710
711void fimc_hw_clear_irq(struct fimc_dev *dev)
712{
713 u32 cfg = readl(dev->regs + FIMC_REG_CIGCTRL);
714 cfg |= FIMC_REG_CIGCTRL_IRQ_CLR;
715 writel(cfg, dev->regs + FIMC_REG_CIGCTRL);
716}
717
718void fimc_hw_enable_scaler(struct fimc_dev *dev, bool on)
719{
720 u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL);
721 if (on)
722 cfg |= FIMC_REG_CISCCTRL_SCALERSTART;
723 else
724 cfg &= ~FIMC_REG_CISCCTRL_SCALERSTART;
725 writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
726}
727
728void fimc_hw_activate_input_dma(struct fimc_dev *dev, bool on)
729{
730 u32 cfg = readl(dev->regs + FIMC_REG_MSCTRL);
731 if (on)
732 cfg |= FIMC_REG_MSCTRL_ENVID;
733 else
734 cfg &= ~FIMC_REG_MSCTRL_ENVID;
735 writel(cfg, dev->regs + FIMC_REG_MSCTRL);
736}
737
738void fimc_hw_dis_capture(struct fimc_dev *dev)
739{
740 u32 cfg = readl(dev->regs + FIMC_REG_CIIMGCPT);
741 cfg &= ~(FIMC_REG_CIIMGCPT_IMGCPTEN | FIMC_REG_CIIMGCPT_IMGCPTEN_SC);
742 writel(cfg, dev->regs + FIMC_REG_CIIMGCPT);
743}
744
745/* Return an index to the buffer actually being written. */
746u32 fimc_hw_get_frame_index(struct fimc_dev *dev)
747{
748 u32 reg;
749
750 if (dev->variant->has_cistatus2) {
751 reg = readl(dev->regs + FIMC_REG_CISTATUS2) & 0x3F;
752 return reg > 0 ? --reg : reg;
753 }
754
755 reg = readl(dev->regs + FIMC_REG_CISTATUS);
756
757 return (reg & FIMC_REG_CISTATUS_FRAMECNT_MASK) >>
758 FIMC_REG_CISTATUS_FRAMECNT_SHIFT;
759}
760
761/* Locking: the caller holds fimc->slock */
762void fimc_activate_capture(struct fimc_ctx *ctx)
763{
764 fimc_hw_enable_scaler(ctx->fimc_dev, ctx->scaler.enabled);
765 fimc_hw_en_capture(ctx);
766}
767
768void fimc_deactivate_capture(struct fimc_dev *fimc)
769{
770 fimc_hw_en_lastirq(fimc, true);
771 fimc_hw_dis_capture(fimc);
772 fimc_hw_enable_scaler(fimc, false);
773 fimc_hw_en_lastirq(fimc, false);
774}
Linux kernel - Deliverables
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