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b5f1220d SN |
1 | /* |
2 | * Samsung S5P/EXYNOS4 SoC series MIPI-CSI receiver driver | |
3 | * | |
4 | * Copyright (C) 2011 Samsung Electronics Co., Ltd. | |
5 | * Contact: Sylwester Nawrocki, <s.nawrocki@samsung.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/clk.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/device.h> | |
15 | #include <linux/errno.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/irq.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/memory.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/pm_runtime.h> | |
24 | #include <linux/regulator/consumer.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/spinlock.h> | |
27 | #include <linux/videodev2.h> | |
28 | #include <media/v4l2-subdev.h> | |
29 | #include <plat/mipi_csis.h> | |
30 | #include "mipi-csis.h" | |
31 | ||
32 | static int debug; | |
33 | module_param(debug, int, 0644); | |
34 | MODULE_PARM_DESC(debug, "Debug level (0-1)"); | |
35 | ||
36 | /* Register map definition */ | |
37 | ||
38 | /* CSIS global control */ | |
39 | #define S5PCSIS_CTRL 0x00 | |
40 | #define S5PCSIS_CTRL_DPDN_DEFAULT (0 << 31) | |
41 | #define S5PCSIS_CTRL_DPDN_SWAP (1 << 31) | |
42 | #define S5PCSIS_CTRL_ALIGN_32BIT (1 << 20) | |
43 | #define S5PCSIS_CTRL_UPDATE_SHADOW (1 << 16) | |
44 | #define S5PCSIS_CTRL_WCLK_EXTCLK (1 << 8) | |
45 | #define S5PCSIS_CTRL_RESET (1 << 4) | |
46 | #define S5PCSIS_CTRL_ENABLE (1 << 0) | |
47 | ||
48 | /* D-PHY control */ | |
49 | #define S5PCSIS_DPHYCTRL 0x04 | |
50 | #define S5PCSIS_DPHYCTRL_HSS_MASK (0x1f << 27) | |
51 | #define S5PCSIS_DPHYCTRL_ENABLE (0x1f << 0) | |
52 | ||
53 | #define S5PCSIS_CONFIG 0x08 | |
54 | #define S5PCSIS_CFG_FMT_YCBCR422_8BIT (0x1e << 2) | |
55 | #define S5PCSIS_CFG_FMT_RAW8 (0x2a << 2) | |
56 | #define S5PCSIS_CFG_FMT_RAW10 (0x2b << 2) | |
57 | #define S5PCSIS_CFG_FMT_RAW12 (0x2c << 2) | |
58 | /* User defined formats, x = 1...4 */ | |
59 | #define S5PCSIS_CFG_FMT_USER(x) ((0x30 + x - 1) << 2) | |
60 | #define S5PCSIS_CFG_FMT_MASK (0x3f << 2) | |
61 | #define S5PCSIS_CFG_NR_LANE_MASK 3 | |
62 | ||
63 | /* Interrupt mask. */ | |
64 | #define S5PCSIS_INTMSK 0x10 | |
65 | #define S5PCSIS_INTMSK_EN_ALL 0xf000003f | |
66 | #define S5PCSIS_INTSRC 0x14 | |
67 | ||
68 | /* Pixel resolution */ | |
69 | #define S5PCSIS_RESOL 0x2c | |
70 | #define CSIS_MAX_PIX_WIDTH 0xffff | |
71 | #define CSIS_MAX_PIX_HEIGHT 0xffff | |
72 | ||
73 | enum { | |
74 | CSIS_CLK_MUX, | |
75 | CSIS_CLK_GATE, | |
76 | }; | |
77 | ||
78 | static char *csi_clock_name[] = { | |
79 | [CSIS_CLK_MUX] = "sclk_csis", | |
80 | [CSIS_CLK_GATE] = "csis", | |
81 | }; | |
82 | #define NUM_CSIS_CLOCKS ARRAY_SIZE(csi_clock_name) | |
83 | ||
438df3eb SN |
84 | static const char * const csis_supply_name[] = { |
85 | "vdd11", /* 1.1V or 1.2V (s5pc100) MIPI CSI suppply */ | |
86 | "vdd18", /* VDD 1.8V and MIPI CSI PLL supply */ | |
87 | }; | |
88 | #define CSIS_NUM_SUPPLIES ARRAY_SIZE(csis_supply_name) | |
89 | ||
b5f1220d SN |
90 | enum { |
91 | ST_POWERED = 1, | |
92 | ST_STREAMING = 2, | |
93 | ST_SUSPENDED = 4, | |
94 | }; | |
95 | ||
96 | /** | |
97 | * struct csis_state - the driver's internal state data structure | |
98 | * @lock: mutex serializing the subdev and power management operations, | |
99 | * protecting @format and @flags members | |
100 | * @pads: CSIS pads array | |
101 | * @sd: v4l2_subdev associated with CSIS device instance | |
102 | * @pdev: CSIS platform device | |
103 | * @regs_res: requested I/O register memory resource | |
104 | * @regs: mmaped I/O registers memory | |
105 | * @clock: CSIS clocks | |
106 | * @irq: requested s5p-mipi-csis irq number | |
107 | * @flags: the state variable for power and streaming control | |
108 | * @csis_fmt: current CSIS pixel format | |
109 | * @format: common media bus format for the source and sink pad | |
110 | */ | |
111 | struct csis_state { | |
112 | struct mutex lock; | |
113 | struct media_pad pads[CSIS_PADS_NUM]; | |
114 | struct v4l2_subdev sd; | |
115 | struct platform_device *pdev; | |
116 | struct resource *regs_res; | |
117 | void __iomem *regs; | |
438df3eb | 118 | struct regulator_bulk_data supplies[CSIS_NUM_SUPPLIES]; |
b5f1220d SN |
119 | struct clk *clock[NUM_CSIS_CLOCKS]; |
120 | int irq; | |
b5f1220d SN |
121 | u32 flags; |
122 | const struct csis_pix_format *csis_fmt; | |
123 | struct v4l2_mbus_framefmt format; | |
124 | }; | |
125 | ||
126 | /** | |
127 | * struct csis_pix_format - CSIS pixel format description | |
128 | * @pix_width_alignment: horizontal pixel alignment, width will be | |
129 | * multiple of 2^pix_width_alignment | |
130 | * @code: corresponding media bus code | |
131 | * @fmt_reg: S5PCSIS_CONFIG register value | |
132 | */ | |
133 | struct csis_pix_format { | |
134 | unsigned int pix_width_alignment; | |
135 | enum v4l2_mbus_pixelcode code; | |
136 | u32 fmt_reg; | |
137 | }; | |
138 | ||
139 | static const struct csis_pix_format s5pcsis_formats[] = { | |
140 | { | |
141 | .code = V4L2_MBUS_FMT_VYUY8_2X8, | |
142 | .fmt_reg = S5PCSIS_CFG_FMT_YCBCR422_8BIT, | |
143 | }, { | |
144 | .code = V4L2_MBUS_FMT_JPEG_1X8, | |
145 | .fmt_reg = S5PCSIS_CFG_FMT_USER(1), | |
146 | }, | |
147 | }; | |
148 | ||
149 | #define s5pcsis_write(__csis, __r, __v) writel(__v, __csis->regs + __r) | |
150 | #define s5pcsis_read(__csis, __r) readl(__csis->regs + __r) | |
151 | ||
152 | static struct csis_state *sd_to_csis_state(struct v4l2_subdev *sdev) | |
153 | { | |
154 | return container_of(sdev, struct csis_state, sd); | |
155 | } | |
156 | ||
157 | static const struct csis_pix_format *find_csis_format( | |
158 | struct v4l2_mbus_framefmt *mf) | |
159 | { | |
160 | int i; | |
161 | ||
162 | for (i = 0; i < ARRAY_SIZE(s5pcsis_formats); i++) | |
163 | if (mf->code == s5pcsis_formats[i].code) | |
164 | return &s5pcsis_formats[i]; | |
165 | return NULL; | |
166 | } | |
167 | ||
168 | static void s5pcsis_enable_interrupts(struct csis_state *state, bool on) | |
169 | { | |
170 | u32 val = s5pcsis_read(state, S5PCSIS_INTMSK); | |
171 | ||
172 | val = on ? val | S5PCSIS_INTMSK_EN_ALL : | |
173 | val & ~S5PCSIS_INTMSK_EN_ALL; | |
174 | s5pcsis_write(state, S5PCSIS_INTMSK, val); | |
175 | } | |
176 | ||
177 | static void s5pcsis_reset(struct csis_state *state) | |
178 | { | |
179 | u32 val = s5pcsis_read(state, S5PCSIS_CTRL); | |
180 | ||
181 | s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_RESET); | |
182 | udelay(10); | |
183 | } | |
184 | ||
185 | static void s5pcsis_system_enable(struct csis_state *state, int on) | |
186 | { | |
187 | u32 val; | |
188 | ||
189 | val = s5pcsis_read(state, S5PCSIS_CTRL); | |
190 | if (on) | |
191 | val |= S5PCSIS_CTRL_ENABLE; | |
192 | else | |
193 | val &= ~S5PCSIS_CTRL_ENABLE; | |
194 | s5pcsis_write(state, S5PCSIS_CTRL, val); | |
195 | ||
196 | val = s5pcsis_read(state, S5PCSIS_DPHYCTRL); | |
197 | if (on) | |
198 | val |= S5PCSIS_DPHYCTRL_ENABLE; | |
199 | else | |
200 | val &= ~S5PCSIS_DPHYCTRL_ENABLE; | |
201 | s5pcsis_write(state, S5PCSIS_DPHYCTRL, val); | |
202 | } | |
203 | ||
204 | /* Called with the state.lock mutex held */ | |
205 | static void __s5pcsis_set_format(struct csis_state *state) | |
206 | { | |
207 | struct v4l2_mbus_framefmt *mf = &state->format; | |
208 | u32 val; | |
209 | ||
210 | v4l2_dbg(1, debug, &state->sd, "fmt: %d, %d x %d\n", | |
211 | mf->code, mf->width, mf->height); | |
212 | ||
213 | /* Color format */ | |
214 | val = s5pcsis_read(state, S5PCSIS_CONFIG); | |
215 | val = (val & ~S5PCSIS_CFG_FMT_MASK) | state->csis_fmt->fmt_reg; | |
216 | s5pcsis_write(state, S5PCSIS_CONFIG, val); | |
217 | ||
218 | /* Pixel resolution */ | |
219 | val = (mf->width << 16) | mf->height; | |
220 | s5pcsis_write(state, S5PCSIS_RESOL, val); | |
221 | } | |
222 | ||
223 | static void s5pcsis_set_hsync_settle(struct csis_state *state, int settle) | |
224 | { | |
225 | u32 val = s5pcsis_read(state, S5PCSIS_DPHYCTRL); | |
226 | ||
227 | val = (val & ~S5PCSIS_DPHYCTRL_HSS_MASK) | (settle << 27); | |
228 | s5pcsis_write(state, S5PCSIS_DPHYCTRL, val); | |
229 | } | |
230 | ||
231 | static void s5pcsis_set_params(struct csis_state *state) | |
232 | { | |
233 | struct s5p_platform_mipi_csis *pdata = state->pdev->dev.platform_data; | |
234 | u32 val; | |
235 | ||
236 | val = s5pcsis_read(state, S5PCSIS_CONFIG); | |
237 | val = (val & ~S5PCSIS_CFG_NR_LANE_MASK) | (pdata->lanes - 1); | |
238 | s5pcsis_write(state, S5PCSIS_CONFIG, val); | |
239 | ||
240 | __s5pcsis_set_format(state); | |
241 | s5pcsis_set_hsync_settle(state, pdata->hs_settle); | |
242 | ||
243 | val = s5pcsis_read(state, S5PCSIS_CTRL); | |
244 | if (pdata->alignment == 32) | |
245 | val |= S5PCSIS_CTRL_ALIGN_32BIT; | |
246 | else /* 24-bits */ | |
247 | val &= ~S5PCSIS_CTRL_ALIGN_32BIT; | |
248 | /* Not using external clock. */ | |
249 | val &= ~S5PCSIS_CTRL_WCLK_EXTCLK; | |
250 | s5pcsis_write(state, S5PCSIS_CTRL, val); | |
251 | ||
252 | /* Update the shadow register. */ | |
253 | val = s5pcsis_read(state, S5PCSIS_CTRL); | |
254 | s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_UPDATE_SHADOW); | |
255 | } | |
256 | ||
257 | static void s5pcsis_clk_put(struct csis_state *state) | |
258 | { | |
259 | int i; | |
260 | ||
261 | for (i = 0; i < NUM_CSIS_CLOCKS; i++) | |
262 | if (!IS_ERR_OR_NULL(state->clock[i])) | |
263 | clk_put(state->clock[i]); | |
264 | } | |
265 | ||
266 | static int s5pcsis_clk_get(struct csis_state *state) | |
267 | { | |
268 | struct device *dev = &state->pdev->dev; | |
269 | int i; | |
270 | ||
271 | for (i = 0; i < NUM_CSIS_CLOCKS; i++) { | |
272 | state->clock[i] = clk_get(dev, csi_clock_name[i]); | |
273 | if (IS_ERR(state->clock[i])) { | |
274 | s5pcsis_clk_put(state); | |
275 | dev_err(dev, "failed to get clock: %s\n", | |
276 | csi_clock_name[i]); | |
277 | return -ENXIO; | |
278 | } | |
279 | } | |
280 | return 0; | |
281 | } | |
282 | ||
283 | static int s5pcsis_s_power(struct v4l2_subdev *sd, int on) | |
284 | { | |
285 | struct csis_state *state = sd_to_csis_state(sd); | |
286 | struct device *dev = &state->pdev->dev; | |
287 | ||
288 | if (on) | |
289 | return pm_runtime_get_sync(dev); | |
290 | ||
291 | return pm_runtime_put_sync(dev); | |
292 | } | |
293 | ||
294 | static void s5pcsis_start_stream(struct csis_state *state) | |
295 | { | |
296 | s5pcsis_reset(state); | |
297 | s5pcsis_set_params(state); | |
298 | s5pcsis_system_enable(state, true); | |
299 | s5pcsis_enable_interrupts(state, true); | |
300 | } | |
301 | ||
302 | static void s5pcsis_stop_stream(struct csis_state *state) | |
303 | { | |
304 | s5pcsis_enable_interrupts(state, false); | |
305 | s5pcsis_system_enable(state, false); | |
306 | } | |
307 | ||
308 | /* v4l2_subdev operations */ | |
309 | static int s5pcsis_s_stream(struct v4l2_subdev *sd, int enable) | |
310 | { | |
311 | struct csis_state *state = sd_to_csis_state(sd); | |
312 | int ret = 0; | |
313 | ||
314 | v4l2_dbg(1, debug, sd, "%s: %d, state: 0x%x\n", | |
315 | __func__, enable, state->flags); | |
316 | ||
317 | if (enable) { | |
318 | ret = pm_runtime_get_sync(&state->pdev->dev); | |
319 | if (ret && ret != 1) | |
320 | return ret; | |
321 | } | |
322 | mutex_lock(&state->lock); | |
323 | if (enable) { | |
324 | if (state->flags & ST_SUSPENDED) { | |
325 | ret = -EBUSY; | |
326 | goto unlock; | |
327 | } | |
328 | s5pcsis_start_stream(state); | |
329 | state->flags |= ST_STREAMING; | |
330 | } else { | |
331 | s5pcsis_stop_stream(state); | |
332 | state->flags &= ~ST_STREAMING; | |
333 | } | |
334 | unlock: | |
335 | mutex_unlock(&state->lock); | |
336 | if (!enable) | |
337 | pm_runtime_put(&state->pdev->dev); | |
338 | ||
339 | return ret == 1 ? 0 : ret; | |
340 | } | |
341 | ||
342 | static int s5pcsis_enum_mbus_code(struct v4l2_subdev *sd, | |
343 | struct v4l2_subdev_fh *fh, | |
344 | struct v4l2_subdev_mbus_code_enum *code) | |
345 | { | |
346 | if (code->index >= ARRAY_SIZE(s5pcsis_formats)) | |
347 | return -EINVAL; | |
348 | ||
349 | code->code = s5pcsis_formats[code->index].code; | |
350 | return 0; | |
351 | } | |
352 | ||
353 | static struct csis_pix_format const *s5pcsis_try_format( | |
354 | struct v4l2_mbus_framefmt *mf) | |
355 | { | |
356 | struct csis_pix_format const *csis_fmt; | |
357 | ||
358 | csis_fmt = find_csis_format(mf); | |
359 | if (csis_fmt == NULL) | |
360 | csis_fmt = &s5pcsis_formats[0]; | |
361 | ||
362 | mf->code = csis_fmt->code; | |
363 | v4l_bound_align_image(&mf->width, 1, CSIS_MAX_PIX_WIDTH, | |
364 | csis_fmt->pix_width_alignment, | |
365 | &mf->height, 1, CSIS_MAX_PIX_HEIGHT, 1, | |
366 | 0); | |
367 | return csis_fmt; | |
368 | } | |
369 | ||
370 | static struct v4l2_mbus_framefmt *__s5pcsis_get_format( | |
371 | struct csis_state *state, struct v4l2_subdev_fh *fh, | |
372 | u32 pad, enum v4l2_subdev_format_whence which) | |
373 | { | |
374 | if (which == V4L2_SUBDEV_FORMAT_TRY) | |
375 | return fh ? v4l2_subdev_get_try_format(fh, pad) : NULL; | |
376 | ||
377 | return &state->format; | |
378 | } | |
379 | ||
380 | static int s5pcsis_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, | |
381 | struct v4l2_subdev_format *fmt) | |
382 | { | |
383 | struct csis_state *state = sd_to_csis_state(sd); | |
384 | struct csis_pix_format const *csis_fmt; | |
385 | struct v4l2_mbus_framefmt *mf; | |
386 | ||
387 | if (fmt->pad != CSIS_PAD_SOURCE && fmt->pad != CSIS_PAD_SINK) | |
388 | return -EINVAL; | |
389 | ||
390 | mf = __s5pcsis_get_format(state, fh, fmt->pad, fmt->which); | |
391 | ||
392 | if (fmt->pad == CSIS_PAD_SOURCE) { | |
393 | if (mf) { | |
394 | mutex_lock(&state->lock); | |
395 | fmt->format = *mf; | |
396 | mutex_unlock(&state->lock); | |
397 | } | |
398 | return 0; | |
399 | } | |
400 | csis_fmt = s5pcsis_try_format(&fmt->format); | |
401 | if (mf) { | |
402 | mutex_lock(&state->lock); | |
403 | *mf = fmt->format; | |
404 | if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) | |
405 | state->csis_fmt = csis_fmt; | |
406 | mutex_unlock(&state->lock); | |
407 | } | |
408 | return 0; | |
409 | } | |
410 | ||
411 | static int s5pcsis_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh, | |
412 | struct v4l2_subdev_format *fmt) | |
413 | { | |
414 | struct csis_state *state = sd_to_csis_state(sd); | |
415 | struct v4l2_mbus_framefmt *mf; | |
416 | ||
417 | if (fmt->pad != CSIS_PAD_SOURCE && fmt->pad != CSIS_PAD_SINK) | |
418 | return -EINVAL; | |
419 | ||
420 | mf = __s5pcsis_get_format(state, fh, fmt->pad, fmt->which); | |
421 | if (!mf) | |
422 | return -EINVAL; | |
423 | ||
424 | mutex_lock(&state->lock); | |
425 | fmt->format = *mf; | |
426 | mutex_unlock(&state->lock); | |
427 | return 0; | |
428 | } | |
429 | ||
6cf1056f SN |
430 | static int s5pcsis_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) |
431 | { | |
432 | struct v4l2_mbus_framefmt *format = v4l2_subdev_get_try_format(fh, 0); | |
433 | ||
434 | format->colorspace = V4L2_COLORSPACE_JPEG; | |
435 | format->code = s5pcsis_formats[0].code; | |
436 | format->width = S5PCSIS_DEF_PIX_WIDTH; | |
437 | format->height = S5PCSIS_DEF_PIX_HEIGHT; | |
438 | format->field = V4L2_FIELD_NONE; | |
439 | ||
440 | return 0; | |
441 | } | |
442 | ||
443 | static const struct v4l2_subdev_internal_ops s5pcsis_sd_internal_ops = { | |
444 | .open = s5pcsis_open, | |
445 | }; | |
446 | ||
b5f1220d SN |
447 | static struct v4l2_subdev_core_ops s5pcsis_core_ops = { |
448 | .s_power = s5pcsis_s_power, | |
449 | }; | |
450 | ||
451 | static struct v4l2_subdev_pad_ops s5pcsis_pad_ops = { | |
452 | .enum_mbus_code = s5pcsis_enum_mbus_code, | |
453 | .get_fmt = s5pcsis_get_fmt, | |
454 | .set_fmt = s5pcsis_set_fmt, | |
455 | }; | |
456 | ||
457 | static struct v4l2_subdev_video_ops s5pcsis_video_ops = { | |
458 | .s_stream = s5pcsis_s_stream, | |
459 | }; | |
460 | ||
461 | static struct v4l2_subdev_ops s5pcsis_subdev_ops = { | |
462 | .core = &s5pcsis_core_ops, | |
463 | .pad = &s5pcsis_pad_ops, | |
464 | .video = &s5pcsis_video_ops, | |
465 | }; | |
466 | ||
467 | static irqreturn_t s5pcsis_irq_handler(int irq, void *dev_id) | |
468 | { | |
469 | struct csis_state *state = dev_id; | |
470 | u32 val; | |
471 | ||
472 | /* Just clear the interrupt pending bits. */ | |
473 | val = s5pcsis_read(state, S5PCSIS_INTSRC); | |
474 | s5pcsis_write(state, S5PCSIS_INTSRC, val); | |
475 | ||
476 | return IRQ_HANDLED; | |
477 | } | |
478 | ||
479 | static int __devinit s5pcsis_probe(struct platform_device *pdev) | |
480 | { | |
481 | struct s5p_platform_mipi_csis *pdata; | |
482 | struct resource *mem_res; | |
483 | struct resource *regs_res; | |
484 | struct csis_state *state; | |
485 | int ret = -ENOMEM; | |
438df3eb | 486 | int i; |
b5f1220d SN |
487 | |
488 | state = kzalloc(sizeof(*state), GFP_KERNEL); | |
489 | if (!state) | |
490 | return -ENOMEM; | |
491 | ||
492 | mutex_init(&state->lock); | |
493 | state->pdev = pdev; | |
494 | ||
495 | pdata = pdev->dev.platform_data; | |
496 | if (pdata == NULL || pdata->phy_enable == NULL) { | |
497 | dev_err(&pdev->dev, "Platform data not fully specified\n"); | |
498 | goto e_free; | |
499 | } | |
500 | ||
501 | if ((pdev->id == 1 && pdata->lanes > CSIS1_MAX_LANES) || | |
502 | pdata->lanes > CSIS0_MAX_LANES) { | |
503 | ret = -EINVAL; | |
504 | dev_err(&pdev->dev, "Unsupported number of data lanes: %d\n", | |
505 | pdata->lanes); | |
506 | goto e_free; | |
507 | } | |
508 | ||
509 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
510 | if (!mem_res) { | |
511 | dev_err(&pdev->dev, "Failed to get IO memory region\n"); | |
512 | goto e_free; | |
513 | } | |
514 | ||
515 | regs_res = request_mem_region(mem_res->start, resource_size(mem_res), | |
516 | pdev->name); | |
517 | if (!regs_res) { | |
518 | dev_err(&pdev->dev, "Failed to request IO memory region\n"); | |
519 | goto e_free; | |
520 | } | |
521 | state->regs_res = regs_res; | |
522 | ||
523 | state->regs = ioremap(mem_res->start, resource_size(mem_res)); | |
524 | if (!state->regs) { | |
525 | dev_err(&pdev->dev, "Failed to remap IO region\n"); | |
526 | goto e_reqmem; | |
527 | } | |
528 | ||
529 | ret = s5pcsis_clk_get(state); | |
530 | if (ret) | |
531 | goto e_unmap; | |
532 | ||
533 | clk_enable(state->clock[CSIS_CLK_MUX]); | |
534 | if (pdata->clk_rate) | |
535 | clk_set_rate(state->clock[CSIS_CLK_MUX], pdata->clk_rate); | |
536 | else | |
537 | dev_WARN(&pdev->dev, "No clock frequency specified!\n"); | |
538 | ||
539 | state->irq = platform_get_irq(pdev, 0); | |
540 | if (state->irq < 0) { | |
541 | ret = state->irq; | |
542 | dev_err(&pdev->dev, "Failed to get irq\n"); | |
543 | goto e_clkput; | |
544 | } | |
545 | ||
438df3eb SN |
546 | for (i = 0; i < CSIS_NUM_SUPPLIES; i++) |
547 | state->supplies[i].supply = csis_supply_name[i]; | |
548 | ||
549 | ret = regulator_bulk_get(&pdev->dev, CSIS_NUM_SUPPLIES, | |
550 | state->supplies); | |
551 | if (ret) | |
552 | goto e_clkput; | |
b5f1220d SN |
553 | |
554 | ret = request_irq(state->irq, s5pcsis_irq_handler, 0, | |
555 | dev_name(&pdev->dev), state); | |
556 | if (ret) { | |
557 | dev_err(&pdev->dev, "request_irq failed\n"); | |
558 | goto e_regput; | |
559 | } | |
560 | ||
561 | v4l2_subdev_init(&state->sd, &s5pcsis_subdev_ops); | |
562 | state->sd.owner = THIS_MODULE; | |
563 | strlcpy(state->sd.name, dev_name(&pdev->dev), sizeof(state->sd.name)); | |
6cf1056f | 564 | state->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; |
b5f1220d SN |
565 | state->csis_fmt = &s5pcsis_formats[0]; |
566 | ||
6cf1056f SN |
567 | state->format.code = s5pcsis_formats[0].code; |
568 | state->format.width = S5PCSIS_DEF_PIX_WIDTH; | |
569 | state->format.height = S5PCSIS_DEF_PIX_HEIGHT; | |
570 | ||
b5f1220d SN |
571 | state->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK; |
572 | state->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; | |
573 | ret = media_entity_init(&state->sd.entity, | |
574 | CSIS_PADS_NUM, state->pads, 0); | |
575 | if (ret < 0) | |
576 | goto e_irqfree; | |
577 | ||
578 | /* This allows to retrieve the platform device id by the host driver */ | |
579 | v4l2_set_subdevdata(&state->sd, pdev); | |
580 | ||
581 | /* .. and a pointer to the subdev. */ | |
582 | platform_set_drvdata(pdev, &state->sd); | |
583 | ||
b5f1220d SN |
584 | pm_runtime_enable(&pdev->dev); |
585 | ||
586 | return 0; | |
587 | ||
588 | e_irqfree: | |
589 | free_irq(state->irq, state); | |
590 | e_regput: | |
438df3eb | 591 | regulator_bulk_free(CSIS_NUM_SUPPLIES, state->supplies); |
b5f1220d SN |
592 | e_clkput: |
593 | clk_disable(state->clock[CSIS_CLK_MUX]); | |
594 | s5pcsis_clk_put(state); | |
595 | e_unmap: | |
596 | iounmap(state->regs); | |
597 | e_reqmem: | |
598 | release_mem_region(regs_res->start, resource_size(regs_res)); | |
599 | e_free: | |
600 | kfree(state); | |
601 | return ret; | |
602 | } | |
603 | ||
d4d4e3c9 | 604 | static int s5pcsis_pm_suspend(struct device *dev, bool runtime) |
b5f1220d SN |
605 | { |
606 | struct s5p_platform_mipi_csis *pdata = dev->platform_data; | |
607 | struct platform_device *pdev = to_platform_device(dev); | |
608 | struct v4l2_subdev *sd = platform_get_drvdata(pdev); | |
609 | struct csis_state *state = sd_to_csis_state(sd); | |
c68956c1 | 610 | int ret = 0; |
b5f1220d SN |
611 | |
612 | v4l2_dbg(1, debug, sd, "%s: flags: 0x%x\n", | |
613 | __func__, state->flags); | |
614 | ||
615 | mutex_lock(&state->lock); | |
616 | if (state->flags & ST_POWERED) { | |
617 | s5pcsis_stop_stream(state); | |
618 | ret = pdata->phy_enable(state->pdev, false); | |
619 | if (ret) | |
620 | goto unlock; | |
438df3eb SN |
621 | ret = regulator_bulk_disable(CSIS_NUM_SUPPLIES, |
622 | state->supplies); | |
623 | if (ret) | |
624 | goto unlock; | |
b5f1220d SN |
625 | clk_disable(state->clock[CSIS_CLK_GATE]); |
626 | state->flags &= ~ST_POWERED; | |
d4d4e3c9 SN |
627 | if (!runtime) |
628 | state->flags |= ST_SUSPENDED; | |
b5f1220d | 629 | } |
b5f1220d SN |
630 | unlock: |
631 | mutex_unlock(&state->lock); | |
632 | return ret ? -EAGAIN : 0; | |
633 | } | |
634 | ||
d4d4e3c9 | 635 | static int s5pcsis_pm_resume(struct device *dev, bool runtime) |
b5f1220d SN |
636 | { |
637 | struct s5p_platform_mipi_csis *pdata = dev->platform_data; | |
638 | struct platform_device *pdev = to_platform_device(dev); | |
639 | struct v4l2_subdev *sd = platform_get_drvdata(pdev); | |
640 | struct csis_state *state = sd_to_csis_state(sd); | |
641 | int ret = 0; | |
642 | ||
643 | v4l2_dbg(1, debug, sd, "%s: flags: 0x%x\n", | |
644 | __func__, state->flags); | |
645 | ||
646 | mutex_lock(&state->lock); | |
d4d4e3c9 | 647 | if (!runtime && !(state->flags & ST_SUSPENDED)) |
b5f1220d SN |
648 | goto unlock; |
649 | ||
650 | if (!(state->flags & ST_POWERED)) { | |
438df3eb SN |
651 | ret = regulator_bulk_enable(CSIS_NUM_SUPPLIES, |
652 | state->supplies); | |
b5f1220d SN |
653 | if (ret) |
654 | goto unlock; | |
b5f1220d SN |
655 | ret = pdata->phy_enable(state->pdev, true); |
656 | if (!ret) { | |
657 | state->flags |= ST_POWERED; | |
438df3eb SN |
658 | } else { |
659 | regulator_bulk_disable(CSIS_NUM_SUPPLIES, | |
660 | state->supplies); | |
b5f1220d SN |
661 | goto unlock; |
662 | } | |
663 | clk_enable(state->clock[CSIS_CLK_GATE]); | |
664 | } | |
665 | if (state->flags & ST_STREAMING) | |
666 | s5pcsis_start_stream(state); | |
667 | ||
668 | state->flags &= ~ST_SUSPENDED; | |
669 | unlock: | |
670 | mutex_unlock(&state->lock); | |
671 | return ret ? -EAGAIN : 0; | |
672 | } | |
673 | ||
674 | #ifdef CONFIG_PM_SLEEP | |
d4d4e3c9 | 675 | static int s5pcsis_suspend(struct device *dev) |
b5f1220d | 676 | { |
d4d4e3c9 | 677 | return s5pcsis_pm_suspend(dev, false); |
b5f1220d SN |
678 | } |
679 | ||
d4d4e3c9 | 680 | static int s5pcsis_resume(struct device *dev) |
b5f1220d | 681 | { |
d4d4e3c9 SN |
682 | return s5pcsis_pm_resume(dev, false); |
683 | } | |
684 | #endif | |
b5f1220d | 685 | |
d4d4e3c9 SN |
686 | #ifdef CONFIG_PM_RUNTIME |
687 | static int s5pcsis_runtime_suspend(struct device *dev) | |
688 | { | |
689 | return s5pcsis_pm_suspend(dev, true); | |
690 | } | |
b5f1220d | 691 | |
d4d4e3c9 SN |
692 | static int s5pcsis_runtime_resume(struct device *dev) |
693 | { | |
694 | return s5pcsis_pm_resume(dev, true); | |
b5f1220d SN |
695 | } |
696 | #endif | |
697 | ||
698 | static int __devexit s5pcsis_remove(struct platform_device *pdev) | |
699 | { | |
700 | struct v4l2_subdev *sd = platform_get_drvdata(pdev); | |
701 | struct csis_state *state = sd_to_csis_state(sd); | |
702 | struct resource *res = state->regs_res; | |
703 | ||
704 | pm_runtime_disable(&pdev->dev); | |
705 | s5pcsis_suspend(&pdev->dev); | |
706 | clk_disable(state->clock[CSIS_CLK_MUX]); | |
707 | pm_runtime_set_suspended(&pdev->dev); | |
708 | ||
709 | s5pcsis_clk_put(state); | |
438df3eb | 710 | regulator_bulk_free(CSIS_NUM_SUPPLIES, state->supplies); |
b5f1220d SN |
711 | |
712 | media_entity_cleanup(&state->sd.entity); | |
713 | free_irq(state->irq, state); | |
714 | iounmap(state->regs); | |
715 | release_mem_region(res->start, resource_size(res)); | |
716 | kfree(state); | |
717 | ||
718 | return 0; | |
719 | } | |
720 | ||
721 | static const struct dev_pm_ops s5pcsis_pm_ops = { | |
d4d4e3c9 SN |
722 | SET_RUNTIME_PM_OPS(s5pcsis_runtime_suspend, s5pcsis_runtime_resume, |
723 | NULL) | |
724 | SET_SYSTEM_SLEEP_PM_OPS(s5pcsis_suspend, s5pcsis_resume) | |
b5f1220d SN |
725 | }; |
726 | ||
727 | static struct platform_driver s5pcsis_driver = { | |
728 | .probe = s5pcsis_probe, | |
729 | .remove = __devexit_p(s5pcsis_remove), | |
730 | .driver = { | |
731 | .name = CSIS_DRIVER_NAME, | |
732 | .owner = THIS_MODULE, | |
733 | .pm = &s5pcsis_pm_ops, | |
734 | }, | |
735 | }; | |
736 | ||
737 | static int __init s5pcsis_init(void) | |
738 | { | |
739 | return platform_driver_probe(&s5pcsis_driver, s5pcsis_probe); | |
740 | } | |
741 | ||
742 | static void __exit s5pcsis_exit(void) | |
743 | { | |
744 | platform_driver_unregister(&s5pcsis_driver); | |
745 | } | |
746 | ||
747 | module_init(s5pcsis_init); | |
748 | module_exit(s5pcsis_exit); | |
749 | ||
750 | MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>"); | |
751 | MODULE_DESCRIPTION("S5P/EXYNOS4 MIPI CSI receiver driver"); | |
752 | MODULE_LICENSE("GPL"); |