Merge branch 'x86-debug-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / drivers / media / video / s5p-mfc / regs-mfc.h
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1/*
2 * Register definition file for Samsung MFC V5.1 Interface (FIMV) driver
3 *
4 * Kamil Debski, Copyright (c) 2010 Samsung Electronics
5 * http://www.samsung.com/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#ifndef _REGS_FIMV_H
13#define _REGS_FIMV_H
14
15#define S5P_FIMV_REG_SIZE (S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR)
16#define S5P_FIMV_REG_COUNT ((S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR) / 4)
17
18/* Number of bits that the buffer address should be shifted for particular
19 * MFC buffers. */
20#define S5P_FIMV_START_ADDR 0x0000
21#define S5P_FIMV_END_ADDR 0xe008
22
23#define S5P_FIMV_SW_RESET 0x0000
24#define S5P_FIMV_RISC_HOST_INT 0x0008
25
26/* Command from HOST to RISC */
27#define S5P_FIMV_HOST2RISC_CMD 0x0030
28#define S5P_FIMV_HOST2RISC_ARG1 0x0034
29#define S5P_FIMV_HOST2RISC_ARG2 0x0038
30#define S5P_FIMV_HOST2RISC_ARG3 0x003c
31#define S5P_FIMV_HOST2RISC_ARG4 0x0040
32
33/* Command from RISC to HOST */
34#define S5P_FIMV_RISC2HOST_CMD 0x0044
35#define S5P_FIMV_RISC2HOST_CMD_MASK 0x1FFFF
36#define S5P_FIMV_RISC2HOST_ARG1 0x0048
37#define S5P_FIMV_RISC2HOST_ARG2 0x004c
38#define S5P_FIMV_RISC2HOST_ARG3 0x0050
39#define S5P_FIMV_RISC2HOST_ARG4 0x0054
40
41#define S5P_FIMV_FW_VERSION 0x0058
42#define S5P_FIMV_SYS_MEM_SZ 0x005c
43#define S5P_FIMV_FW_STATUS 0x0080
44
45/* Memory controller register */
46#define S5P_FIMV_MC_DRAMBASE_ADR_A 0x0508
47#define S5P_FIMV_MC_DRAMBASE_ADR_B 0x050c
48#define S5P_FIMV_MC_STATUS 0x0510
49
50/* Common register */
51#define S5P_FIMV_COMMON_BASE_A 0x0600
52#define S5P_FIMV_COMMON_BASE_B 0x0700
53
54/* Decoder */
55#define S5P_FIMV_DEC_CHROMA_ADR (S5P_FIMV_COMMON_BASE_A)
56#define S5P_FIMV_DEC_LUMA_ADR (S5P_FIMV_COMMON_BASE_B)
57
58/* H.264 decoding */
59#define S5P_FIMV_H264_VERT_NB_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x8c)
60 /* vertical neighbor motion vector */
61#define S5P_FIMV_H264_NB_IP_ADR (S5P_FIMV_COMMON_BASE_A + 0x90)
62 /* neighbor pixels for intra pred */
63#define S5P_FIMV_H264_MV_ADR (S5P_FIMV_COMMON_BASE_B + 0x80)
64 /* H264 motion vector */
65
66/* MPEG4 decoding */
67#define S5P_FIMV_MPEG4_NB_DCAC_ADR (S5P_FIMV_COMMON_BASE_A + 0x8c)
68 /* neighbor AC/DC coeff. */
69#define S5P_FIMV_MPEG4_UP_NB_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x90)
70 /* upper neighbor motion vector */
71#define S5P_FIMV_MPEG4_SA_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x94)
72 /* subseq. anchor motion vector */
73#define S5P_FIMV_MPEG4_OT_LINE_ADR (S5P_FIMV_COMMON_BASE_A + 0x98)
74 /* overlap transform line */
75#define S5P_FIMV_MPEG4_SP_ADR (S5P_FIMV_COMMON_BASE_A + 0xa8)
76 /* syntax parser */
77
78/* H.263 decoding */
79#define S5P_FIMV_H263_NB_DCAC_ADR (S5P_FIMV_COMMON_BASE_A + 0x8c)
80#define S5P_FIMV_H263_UP_NB_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x90)
81#define S5P_FIMV_H263_SA_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x94)
82#define S5P_FIMV_H263_OT_LINE_ADR (S5P_FIMV_COMMON_BASE_A + 0x98)
83
84/* VC-1 decoding */
85#define S5P_FIMV_VC1_NB_DCAC_ADR (S5P_FIMV_COMMON_BASE_A + 0x8c)
86#define S5P_FIMV_VC1_UP_NB_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x90)
87#define S5P_FIMV_VC1_SA_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x94)
88#define S5P_FIMV_VC1_OT_LINE_ADR (S5P_FIMV_COMMON_BASE_A + 0x98)
89#define S5P_FIMV_VC1_BITPLANE3_ADR (S5P_FIMV_COMMON_BASE_A + 0x9c)
90 /* bitplane3 */
91#define S5P_FIMV_VC1_BITPLANE2_ADR (S5P_FIMV_COMMON_BASE_A + 0xa0)
92 /* bitplane2 */
93#define S5P_FIMV_VC1_BITPLANE1_ADR (S5P_FIMV_COMMON_BASE_A + 0xa4)
94 /* bitplane1 */
95
96/* Encoder */
97#define S5P_FIMV_ENC_REF0_LUMA_ADR (S5P_FIMV_COMMON_BASE_A + 0x1c)
98#define S5P_FIMV_ENC_REF1_LUMA_ADR (S5P_FIMV_COMMON_BASE_A + 0x20)
99 /* reconstructed luma */
100#define S5P_FIMV_ENC_REF0_CHROMA_ADR (S5P_FIMV_COMMON_BASE_B)
101#define S5P_FIMV_ENC_REF1_CHROMA_ADR (S5P_FIMV_COMMON_BASE_B + 0x04)
102 /* reconstructed chroma */
103#define S5P_FIMV_ENC_REF2_LUMA_ADR (S5P_FIMV_COMMON_BASE_B + 0x10)
104#define S5P_FIMV_ENC_REF2_CHROMA_ADR (S5P_FIMV_COMMON_BASE_B + 0x08)
105#define S5P_FIMV_ENC_REF3_LUMA_ADR (S5P_FIMV_COMMON_BASE_B + 0x14)
106#define S5P_FIMV_ENC_REF3_CHROMA_ADR (S5P_FIMV_COMMON_BASE_B + 0x0c)
107
108/* H.264 encoding */
109#define S5P_FIMV_H264_UP_MV_ADR (S5P_FIMV_COMMON_BASE_A)
110 /* upper motion vector */
111#define S5P_FIMV_H264_NBOR_INFO_ADR (S5P_FIMV_COMMON_BASE_A + 0x04)
112 /* entropy engine's neighbor info. */
113#define S5P_FIMV_H264_UP_INTRA_MD_ADR (S5P_FIMV_COMMON_BASE_A + 0x08)
114 /* upper intra MD */
115#define S5P_FIMV_H264_COZERO_FLAG_ADR (S5P_FIMV_COMMON_BASE_A + 0x10)
116 /* direct cozero flag */
117#define S5P_FIMV_H264_UP_INTRA_PRED_ADR (S5P_FIMV_COMMON_BASE_B + 0x40)
118 /* upper intra PRED */
119
120/* H.263 encoding */
121#define S5P_FIMV_H263_UP_MV_ADR (S5P_FIMV_COMMON_BASE_A)
122 /* upper motion vector */
123#define S5P_FIMV_H263_ACDC_COEF_ADR (S5P_FIMV_COMMON_BASE_A + 0x04)
124 /* upper Q coeff. */
125
126/* MPEG4 encoding */
127#define S5P_FIMV_MPEG4_UP_MV_ADR (S5P_FIMV_COMMON_BASE_A)
128 /* upper motion vector */
129#define S5P_FIMV_MPEG4_ACDC_COEF_ADR (S5P_FIMV_COMMON_BASE_A + 0x04)
130 /* upper Q coeff. */
131#define S5P_FIMV_MPEG4_COZERO_FLAG_ADR (S5P_FIMV_COMMON_BASE_A + 0x10)
132 /* direct cozero flag */
133
134#define S5P_FIMV_ENC_REF_B_LUMA_ADR 0x062c /* ref B Luma addr */
135#define S5P_FIMV_ENC_REF_B_CHROMA_ADR 0x0630 /* ref B Chroma addr */
136
137#define S5P_FIMV_ENC_CUR_LUMA_ADR 0x0718 /* current Luma addr */
138#define S5P_FIMV_ENC_CUR_CHROMA_ADR 0x071C /* current Chroma addr */
139
140/* Codec common register */
141#define S5P_FIMV_ENC_HSIZE_PX 0x0818 /* frame width at encoder */
142#define S5P_FIMV_ENC_VSIZE_PX 0x081c /* frame height at encoder */
143#define S5P_FIMV_ENC_PROFILE 0x0830 /* profile register */
144#define S5P_FIMV_ENC_PROFILE_H264_MAIN 0
145#define S5P_FIMV_ENC_PROFILE_H264_HIGH 1
146#define S5P_FIMV_ENC_PROFILE_H264_BASELINE 2
147#define S5P_FIMV_ENC_PROFILE_MPEG4_SIMPLE 0
148#define S5P_FIMV_ENC_PROFILE_MPEG4_ADVANCED_SIMPLE 1
149#define S5P_FIMV_ENC_PIC_STRUCT 0x083c /* picture field/frame flag */
150#define S5P_FIMV_ENC_LF_CTRL 0x0848 /* loop filter control */
151#define S5P_FIMV_ENC_ALPHA_OFF 0x084c /* loop filter alpha offset */
152#define S5P_FIMV_ENC_BETA_OFF 0x0850 /* loop filter beta offset */
153#define S5P_FIMV_MR_BUSIF_CTRL 0x0854 /* hidden, bus interface ctrl */
154#define S5P_FIMV_ENC_PXL_CACHE_CTRL 0x0a00 /* pixel cache control */
155
156/* Channel & stream interface register */
157#define S5P_FIMV_SI_RTN_CHID 0x2000 /* Return CH inst ID register */
158#define S5P_FIMV_SI_CH0_INST_ID 0x2040 /* codec instance ID */
159#define S5P_FIMV_SI_CH1_INST_ID 0x2080 /* codec instance ID */
160/* Decoder */
161#define S5P_FIMV_SI_VRESOL 0x2004 /* vertical res of decoder */
162#define S5P_FIMV_SI_HRESOL 0x2008 /* horizontal res of decoder */
163#define S5P_FIMV_SI_BUF_NUMBER 0x200c /* number of frames in the
164 decoded pic */
165#define S5P_FIMV_SI_DISPLAY_Y_ADR 0x2010 /* luma addr of displayed pic */
166#define S5P_FIMV_SI_DISPLAY_C_ADR 0x2014 /* chroma addrof displayed pic */
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168#define S5P_FIMV_SI_CONSUMED_BYTES 0x2018 /* Consumed number of bytes to
169 decode a frame */
170#define S5P_FIMV_SI_DISPLAY_STATUS 0x201c /* status of decoded picture */
171
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172#define S5P_FIMV_SI_DECODE_Y_ADR 0x2024 /* luma addr of decoded pic */
173#define S5P_FIMV_SI_DECODE_C_ADR 0x2028 /* chroma addrof decoded pic */
174#define S5P_FIMV_SI_DECODE_STATUS 0x202c /* status of decoded picture */
175
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176#define S5P_FIMV_SI_CH0_SB_ST_ADR 0x2044 /* start addr of stream buf */
177#define S5P_FIMV_SI_CH0_SB_FRM_SIZE 0x2048 /* size of stream buf */
178#define S5P_FIMV_SI_CH0_DESC_ADR 0x204c /* addr of descriptor buf */
179#define S5P_FIMV_SI_CH0_CPB_SIZE 0x2058 /* max size of coded pic. buf */
180#define S5P_FIMV_SI_CH0_DESC_SIZE 0x205c /* max size of descriptor buf */
181
182#define S5P_FIMV_SI_CH1_SB_ST_ADR 0x2084 /* start addr of stream buf */
183#define S5P_FIMV_SI_CH1_SB_FRM_SIZE 0x2088 /* size of stream buf */
184#define S5P_FIMV_SI_CH1_DESC_ADR 0x208c /* addr of descriptor buf */
185#define S5P_FIMV_SI_CH1_CPB_SIZE 0x2098 /* max size of coded pic. buf */
186#define S5P_FIMV_SI_CH1_DESC_SIZE 0x209c /* max size of descriptor buf */
187
188#define S5P_FIMV_CRC_LUMA0 0x2030 /* luma crc data per frame
189 (top field) */
190#define S5P_FIMV_CRC_CHROMA0 0x2034 /* chroma crc data per frame
191 (top field) */
192#define S5P_FIMV_CRC_LUMA1 0x2038 /* luma crc data per bottom
193 field */
194#define S5P_FIMV_CRC_CHROMA1 0x203c /* chroma crc data per bottom
195 field */
196
197/* Display status */
198#define S5P_FIMV_DEC_STATUS_DECODING_ONLY 0
199#define S5P_FIMV_DEC_STATUS_DECODING_DISPLAY 1
200#define S5P_FIMV_DEC_STATUS_DISPLAY_ONLY 2
201#define S5P_FIMV_DEC_STATUS_DECODING_EMPTY 3
202#define S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK 7
203#define S5P_FIMV_DEC_STATUS_PROGRESSIVE (0<<3)
204#define S5P_FIMV_DEC_STATUS_INTERLACE (1<<3)
205#define S5P_FIMV_DEC_STATUS_INTERLACE_MASK (1<<3)
206#define S5P_FIMV_DEC_STATUS_CRC_NUMBER_TWO (0<<4)
207#define S5P_FIMV_DEC_STATUS_CRC_NUMBER_FOUR (1<<4)
208#define S5P_FIMV_DEC_STATUS_CRC_NUMBER_MASK (1<<4)
209#define S5P_FIMV_DEC_STATUS_CRC_GENERATED (1<<5)
210#define S5P_FIMV_DEC_STATUS_CRC_NOT_GENERATED (0<<5)
211#define S5P_FIMV_DEC_STATUS_CRC_MASK (1<<5)
212
213#define S5P_FIMV_DEC_STATUS_RESOLUTION_MASK (3<<4)
214#define S5P_FIMV_DEC_STATUS_RESOLUTION_INC (1<<4)
215#define S5P_FIMV_DEC_STATUS_RESOLUTION_DEC (2<<4)
216
217/* Decode frame address */
218#define S5P_FIMV_DECODE_Y_ADR 0x2024
219#define S5P_FIMV_DECODE_C_ADR 0x2028
220
221/* Decoded frame tpe */
222#define S5P_FIMV_DECODE_FRAME_TYPE 0x2020
223#define S5P_FIMV_DECODE_FRAME_MASK 7
224
225#define S5P_FIMV_DECODE_FRAME_SKIPPED 0
226#define S5P_FIMV_DECODE_FRAME_I_FRAME 1
227#define S5P_FIMV_DECODE_FRAME_P_FRAME 2
228#define S5P_FIMV_DECODE_FRAME_B_FRAME 3
229#define S5P_FIMV_DECODE_FRAME_OTHER_FRAME 4
230
231/* Sizes of buffers required for decoding */
232#define S5P_FIMV_DEC_NB_IP_SIZE (32 * 1024)
233#define S5P_FIMV_DEC_VERT_NB_MV_SIZE (16 * 1024)
234#define S5P_FIMV_DEC_NB_DCAC_SIZE (16 * 1024)
235#define S5P_FIMV_DEC_UPNB_MV_SIZE (68 * 1024)
236#define S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE (136 * 1024)
237#define S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE (32 * 1024)
238#define S5P_FIMV_DEC_VC1_BITPLANE_SIZE (2 * 1024)
239#define S5P_FIMV_DEC_STX_PARSER_SIZE (68 * 1024)
240
241#define S5P_FIMV_DEC_BUF_ALIGN (8 * 1024)
242#define S5P_FIMV_ENC_BUF_ALIGN (8 * 1024)
243#define S5P_FIMV_NV12M_HALIGN 16
244#define S5P_FIMV_NV12M_LVALIGN 16
245#define S5P_FIMV_NV12M_CVALIGN 8
246#define S5P_FIMV_NV12MT_HALIGN 128
247#define S5P_FIMV_NV12MT_VALIGN 32
248#define S5P_FIMV_NV12M_SALIGN 2048
249#define S5P_FIMV_NV12MT_SALIGN 8192
250
251/* Sizes of buffers required for encoding */
252#define S5P_FIMV_ENC_UPMV_SIZE 0x10000
253#define S5P_FIMV_ENC_COLFLG_SIZE 0x10000
254#define S5P_FIMV_ENC_INTRAMD_SIZE 0x10000
255#define S5P_FIMV_ENC_INTRAPRED_SIZE 0x4000
256#define S5P_FIMV_ENC_NBORINFO_SIZE 0x10000
257#define S5P_FIMV_ENC_ACDCCOEF_SIZE 0x10000
258
259/* Encoder */
260#define S5P_FIMV_ENC_SI_STRM_SIZE 0x2004 /* stream size */
261#define S5P_FIMV_ENC_SI_PIC_CNT 0x2008 /* picture count */
262#define S5P_FIMV_ENC_SI_WRITE_PTR 0x200c /* write pointer */
263#define S5P_FIMV_ENC_SI_SLICE_TYPE 0x2010 /* slice type(I/P/B/IDR) */
264#define S5P_FIMV_ENC_SI_SLICE_TYPE_NON_CODED 0
265#define S5P_FIMV_ENC_SI_SLICE_TYPE_I 1
266#define S5P_FIMV_ENC_SI_SLICE_TYPE_P 2
267#define S5P_FIMV_ENC_SI_SLICE_TYPE_B 3
268#define S5P_FIMV_ENC_SI_SLICE_TYPE_SKIPPED 4
269#define S5P_FIMV_ENC_SI_SLICE_TYPE_OTHERS 5
270#define S5P_FIMV_ENCODED_Y_ADDR 0x2014 /* the addr of the encoded
271 luma pic */
272#define S5P_FIMV_ENCODED_C_ADDR 0x2018 /* the addr of the encoded
273 chroma pic */
274
275#define S5P_FIMV_ENC_SI_CH0_SB_ADR 0x2044 /* addr of stream buf */
276#define S5P_FIMV_ENC_SI_CH0_SB_SIZE 0x204c /* size of stream buf */
277#define S5P_FIMV_ENC_SI_CH0_CUR_Y_ADR 0x2050 /* current Luma addr */
278#define S5P_FIMV_ENC_SI_CH0_CUR_C_ADR 0x2054 /* current Chroma addr */
279#define S5P_FIMV_ENC_SI_CH0_FRAME_INS 0x2058 /* frame insertion */
280
281#define S5P_FIMV_ENC_SI_CH1_SB_ADR 0x2084 /* addr of stream buf */
282#define S5P_FIMV_ENC_SI_CH1_SB_SIZE 0x208c /* size of stream buf */
283#define S5P_FIMV_ENC_SI_CH1_CUR_Y_ADR 0x2090 /* current Luma addr */
284#define S5P_FIMV_ENC_SI_CH1_CUR_C_ADR 0x2094 /* current Chroma addr */
285#define S5P_FIMV_ENC_SI_CH1_FRAME_INS 0x2098 /* frame insertion */
286
287#define S5P_FIMV_ENC_PIC_TYPE_CTRL 0xc504 /* pic type level control */
288#define S5P_FIMV_ENC_B_RECON_WRITE_ON 0xc508 /* B frame recon write ctrl */
289#define S5P_FIMV_ENC_MSLICE_CTRL 0xc50c /* multi slice control */
290#define S5P_FIMV_ENC_MSLICE_MB 0xc510 /* MB number in the one slice */
291#define S5P_FIMV_ENC_MSLICE_BIT 0xc514 /* bit count for one slice */
292#define S5P_FIMV_ENC_CIR_CTRL 0xc518 /* number of intra refresh MB */
293#define S5P_FIMV_ENC_MAP_FOR_CUR 0xc51c /* linear or tiled mode */
294#define S5P_FIMV_ENC_PADDING_CTRL 0xc520 /* padding control */
295
296#define S5P_FIMV_ENC_RC_CONFIG 0xc5a0 /* RC config */
297#define S5P_FIMV_ENC_RC_BIT_RATE 0xc5a8 /* bit rate */
298#define S5P_FIMV_ENC_RC_QBOUND 0xc5ac /* max/min QP */
299#define S5P_FIMV_ENC_RC_RPARA 0xc5b0 /* rate control reaction coeff */
300#define S5P_FIMV_ENC_RC_MB_CTRL 0xc5b4 /* MB adaptive scaling */
301
302/* Encoder for H264 only */
303#define S5P_FIMV_ENC_H264_ENTROPY_MODE 0xd004 /* CAVLC or CABAC */
304#define S5P_FIMV_ENC_H264_ALPHA_OFF 0xd008 /* loop filter alpha offset */
305#define S5P_FIMV_ENC_H264_BETA_OFF 0xd00c /* loop filter beta offset */
306#define S5P_FIMV_ENC_H264_NUM_OF_REF 0xd010 /* number of reference for P/B */
307#define S5P_FIMV_ENC_H264_TRANS_FLAG 0xd034 /* 8x8 transform flag in PPS &
308 high profile */
309
310#define S5P_FIMV_ENC_RC_FRAME_RATE 0xd0d0 /* frame rate */
311
312/* Encoder for MPEG4 only */
313#define S5P_FIMV_ENC_MPEG4_QUART_PXL 0xe008 /* qpel interpolation ctrl */
314
315/* Additional */
316#define S5P_FIMV_SI_CH0_DPB_CONF_CTRL 0x2068 /* DPB Config Control Register */
317#define S5P_FIMV_SLICE_INT_MASK 1
318#define S5P_FIMV_SLICE_INT_SHIFT 31
319#define S5P_FIMV_DDELAY_ENA_SHIFT 30
320#define S5P_FIMV_DDELAY_VAL_MASK 0xff
321#define S5P_FIMV_DDELAY_VAL_SHIFT 16
322#define S5P_FIMV_DPB_COUNT_MASK 0xffff
323#define S5P_FIMV_DPB_FLUSH_MASK 1
324#define S5P_FIMV_DPB_FLUSH_SHIFT 14
325
326
327#define S5P_FIMV_SI_CH0_RELEASE_BUF 0x2060 /* DPB release buffer register */
328#define S5P_FIMV_SI_CH0_HOST_WR_ADR 0x2064 /* address of shared memory */
329
330/* Codec numbers */
331#define S5P_FIMV_CODEC_NONE -1
332
333#define S5P_FIMV_CODEC_H264_DEC 0
334#define S5P_FIMV_CODEC_VC1_DEC 1
335#define S5P_FIMV_CODEC_MPEG4_DEC 2
336#define S5P_FIMV_CODEC_MPEG2_DEC 3
337#define S5P_FIMV_CODEC_H263_DEC 4
338#define S5P_FIMV_CODEC_VC1RCV_DEC 5
339
340#define S5P_FIMV_CODEC_H264_ENC 16
341#define S5P_FIMV_CODEC_MPEG4_ENC 17
342#define S5P_FIMV_CODEC_H263_ENC 18
343
344/* Channel Control Register */
345#define S5P_FIMV_CH_SEQ_HEADER 1
346#define S5P_FIMV_CH_FRAME_START 2
347#define S5P_FIMV_CH_LAST_FRAME 3
348#define S5P_FIMV_CH_INIT_BUFS 4
349#define S5P_FIMV_CH_FRAME_START_REALLOC 5
350#define S5P_FIMV_CH_MASK 7
351#define S5P_FIMV_CH_SHIFT 16
352
353
354/* Host to RISC command */
355#define S5P_FIMV_H2R_CMD_EMPTY 0
356#define S5P_FIMV_H2R_CMD_OPEN_INSTANCE 1
357#define S5P_FIMV_H2R_CMD_CLOSE_INSTANCE 2
358#define S5P_FIMV_H2R_CMD_SYS_INIT 3
359#define S5P_FIMV_H2R_CMD_FLUSH 4
360#define S5P_FIMV_H2R_CMD_SLEEP 5
361#define S5P_FIMV_H2R_CMD_WAKEUP 6
362
363#define S5P_FIMV_R2H_CMD_EMPTY 0
364#define S5P_FIMV_R2H_CMD_OPEN_INSTANCE_RET 1
365#define S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET 2
366#define S5P_FIMV_R2H_CMD_RSV_RET 3
367#define S5P_FIMV_R2H_CMD_SEQ_DONE_RET 4
368#define S5P_FIMV_R2H_CMD_FRAME_DONE_RET 5
369#define S5P_FIMV_R2H_CMD_SLICE_DONE_RET 6
370#define S5P_FIMV_R2H_CMD_ENC_COMPLETE_RET 7
371#define S5P_FIMV_R2H_CMD_SYS_INIT_RET 8
372#define S5P_FIMV_R2H_CMD_FW_STATUS_RET 9
373#define S5P_FIMV_R2H_CMD_SLEEP_RET 10
374#define S5P_FIMV_R2H_CMD_WAKEUP_RET 11
375#define S5P_FIMV_R2H_CMD_FLUSH_RET 12
376#define S5P_FIMV_R2H_CMD_INIT_BUFFERS_RET 15
377#define S5P_FIMV_R2H_CMD_EDFU_INIT_RET 16
378#define S5P_FIMV_R2H_CMD_ERR_RET 32
379
380/* Error handling defines */
381#define S5P_FIMV_ERR_WARNINGS_START 145
382#define S5P_FIMV_ERR_DEC_MASK 0xFFFF
383#define S5P_FIMV_ERR_DEC_SHIFT 0
384#define S5P_FIMV_ERR_DSPL_MASK 0xFFFF0000
385#define S5P_FIMV_ERR_DSPL_SHIFT 16
386
387/* Shared memory registers' offsets */
388
389/* An offset of the start position in the stream when
390 * the start position is not aligned */
391#define S5P_FIMV_SHARED_CROP_INFO_H 0x0020
392#define S5P_FIMV_SHARED_CROP_LEFT_MASK 0xFFFF
393#define S5P_FIMV_SHARED_CROP_LEFT_SHIFT 0
394#define S5P_FIMV_SHARED_CROP_RIGHT_MASK 0xFFFF0000
395#define S5P_FIMV_SHARED_CROP_RIGHT_SHIFT 16
396#define S5P_FIMV_SHARED_CROP_INFO_V 0x0024
397#define S5P_FIMV_SHARED_CROP_TOP_MASK 0xFFFF
398#define S5P_FIMV_SHARED_CROP_TOP_SHIFT 0
399#define S5P_FIMV_SHARED_CROP_BOTTOM_MASK 0xFFFF0000
400#define S5P_FIMV_SHARED_CROP_BOTTOM_SHIFT 16
401#define S5P_FIMV_SHARED_SET_FRAME_TAG 0x0004
402#define S5P_FIMV_SHARED_GET_FRAME_TAG_TOP 0x0008
403#define S5P_FIMV_SHARED_GET_FRAME_TAG_BOT 0x000C
404#define S5P_FIMV_SHARED_START_BYTE_NUM 0x0018
405#define S5P_FIMV_SHARED_RC_VOP_TIMING 0x0030
406#define S5P_FIMV_SHARED_LUMA_DPB_SIZE 0x0064
407#define S5P_FIMV_SHARED_CHROMA_DPB_SIZE 0x0068
408#define S5P_FIMV_SHARED_MV_SIZE 0x006C
409#define S5P_FIMV_SHARED_PIC_TIME_TOP 0x0010
410#define S5P_FIMV_SHARED_PIC_TIME_BOTTOM 0x0014
411#define S5P_FIMV_SHARED_EXT_ENC_CONTROL 0x0028
412#define S5P_FIMV_SHARED_P_B_FRAME_QP 0x0070
413#define S5P_FIMV_SHARED_ASPECT_RATIO_IDC 0x0074
414#define S5P_FIMV_SHARED_EXTENDED_SAR 0x0078
415#define S5P_FIMV_SHARED_H264_I_PERIOD 0x009C
416#define S5P_FIMV_SHARED_RC_CONTROL_CONFIG 0x00A0
417
418#endif /* _REGS_FIMV_H */
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