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af935746 KD |
1 | /* |
2 | * drivers/media/video/samsung/mfc5/s5p_mfc_opr.c | |
3 | * | |
4 | * Samsung MFC (Multi Function Codec - FIMV) driver | |
5 | * This file contains hw related functions. | |
6 | * | |
7 | * Kamil Debski, Copyright (c) 2011 Samsung Electronics | |
8 | * http://www.samsung.com/ | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include "regs-mfc.h" | |
16 | #include "s5p_mfc_cmd.h" | |
17 | #include "s5p_mfc_common.h" | |
18 | #include "s5p_mfc_ctrl.h" | |
19 | #include "s5p_mfc_debug.h" | |
20 | #include "s5p_mfc_intr.h" | |
21 | #include "s5p_mfc_opr.h" | |
22 | #include "s5p_mfc_pm.h" | |
23 | #include "s5p_mfc_shm.h" | |
24 | #include <asm/cacheflush.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/dma-mapping.h> | |
27 | #include <linux/err.h> | |
28 | #include <linux/firmware.h> | |
29 | #include <linux/io.h> | |
30 | #include <linux/jiffies.h> | |
31 | #include <linux/mm.h> | |
32 | #include <linux/sched.h> | |
33 | ||
34 | #define OFFSETA(x) (((x) - dev->bank1) >> MFC_OFFSET_SHIFT) | |
35 | #define OFFSETB(x) (((x) - dev->bank2) >> MFC_OFFSET_SHIFT) | |
36 | ||
37 | /* Allocate temporary buffers for decoding */ | |
38 | int s5p_mfc_alloc_dec_temp_buffers(struct s5p_mfc_ctx *ctx) | |
39 | { | |
40 | void *desc_virt; | |
41 | struct s5p_mfc_dev *dev = ctx->dev; | |
42 | ||
43 | ctx->desc_buf = vb2_dma_contig_memops.alloc( | |
44 | dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], DESC_BUF_SIZE); | |
45 | if (IS_ERR_VALUE((int)ctx->desc_buf)) { | |
1259762f | 46 | ctx->desc_buf = NULL; |
af935746 KD |
47 | mfc_err("Allocating DESC buffer failed\n"); |
48 | return -ENOMEM; | |
49 | } | |
50 | ctx->desc_phys = s5p_mfc_mem_cookie( | |
51 | dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], ctx->desc_buf); | |
52 | BUG_ON(ctx->desc_phys & ((1 << MFC_BANK1_ALIGN_ORDER) - 1)); | |
53 | desc_virt = vb2_dma_contig_memops.vaddr(ctx->desc_buf); | |
54 | if (desc_virt == NULL) { | |
55 | vb2_dma_contig_memops.put(ctx->desc_buf); | |
56 | ctx->desc_phys = 0; | |
1259762f | 57 | ctx->desc_buf = NULL; |
af935746 KD |
58 | mfc_err("Remapping DESC buffer failed\n"); |
59 | return -ENOMEM; | |
60 | } | |
61 | memset(desc_virt, 0, DESC_BUF_SIZE); | |
62 | wmb(); | |
63 | return 0; | |
64 | } | |
65 | ||
66 | /* Release temporary buffers for decoding */ | |
67 | void s5p_mfc_release_dec_desc_buffer(struct s5p_mfc_ctx *ctx) | |
68 | { | |
69 | if (ctx->desc_phys) { | |
70 | vb2_dma_contig_memops.put(ctx->desc_buf); | |
71 | ctx->desc_phys = 0; | |
1259762f | 72 | ctx->desc_buf = NULL; |
af935746 KD |
73 | } |
74 | } | |
75 | ||
76 | /* Allocate codec buffers */ | |
77 | int s5p_mfc_alloc_codec_buffers(struct s5p_mfc_ctx *ctx) | |
78 | { | |
79 | struct s5p_mfc_dev *dev = ctx->dev; | |
80 | unsigned int enc_ref_y_size = 0; | |
81 | unsigned int enc_ref_c_size = 0; | |
82 | unsigned int guard_width, guard_height; | |
83 | ||
84 | if (ctx->type == MFCINST_DECODER) { | |
85 | mfc_debug(2, "Luma size:%d Chroma size:%d MV size:%d\n", | |
86 | ctx->luma_size, ctx->chroma_size, ctx->mv_size); | |
87 | mfc_debug(2, "Totals bufs: %d\n", ctx->total_dpb_count); | |
88 | } else if (ctx->type == MFCINST_ENCODER) { | |
89 | enc_ref_y_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN) | |
90 | * ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN); | |
91 | enc_ref_y_size = ALIGN(enc_ref_y_size, S5P_FIMV_NV12MT_SALIGN); | |
92 | ||
93 | if (ctx->codec_mode == S5P_FIMV_CODEC_H264_ENC) { | |
94 | enc_ref_c_size = ALIGN(ctx->img_width, | |
95 | S5P_FIMV_NV12MT_HALIGN) | |
96 | * ALIGN(ctx->img_height >> 1, | |
97 | S5P_FIMV_NV12MT_VALIGN); | |
98 | enc_ref_c_size = ALIGN(enc_ref_c_size, | |
99 | S5P_FIMV_NV12MT_SALIGN); | |
100 | } else { | |
101 | guard_width = ALIGN(ctx->img_width + 16, | |
102 | S5P_FIMV_NV12MT_HALIGN); | |
103 | guard_height = ALIGN((ctx->img_height >> 1) + 4, | |
104 | S5P_FIMV_NV12MT_VALIGN); | |
105 | enc_ref_c_size = ALIGN(guard_width * guard_height, | |
106 | S5P_FIMV_NV12MT_SALIGN); | |
107 | } | |
108 | mfc_debug(2, "recon luma size: %d chroma size: %d\n", | |
109 | enc_ref_y_size, enc_ref_c_size); | |
110 | } else { | |
111 | return -EINVAL; | |
112 | } | |
113 | /* Codecs have different memory requirements */ | |
114 | switch (ctx->codec_mode) { | |
115 | case S5P_FIMV_CODEC_H264_DEC: | |
116 | ctx->bank1_size = | |
117 | ALIGN(S5P_FIMV_DEC_NB_IP_SIZE + | |
118 | S5P_FIMV_DEC_VERT_NB_MV_SIZE, | |
119 | S5P_FIMV_DEC_BUF_ALIGN); | |
120 | ctx->bank2_size = ctx->total_dpb_count * ctx->mv_size; | |
121 | break; | |
122 | case S5P_FIMV_CODEC_MPEG4_DEC: | |
123 | ctx->bank1_size = | |
124 | ALIGN(S5P_FIMV_DEC_NB_DCAC_SIZE + | |
125 | S5P_FIMV_DEC_UPNB_MV_SIZE + | |
126 | S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE + | |
127 | S5P_FIMV_DEC_STX_PARSER_SIZE + | |
128 | S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE, | |
129 | S5P_FIMV_DEC_BUF_ALIGN); | |
130 | ctx->bank2_size = 0; | |
131 | break; | |
132 | case S5P_FIMV_CODEC_VC1RCV_DEC: | |
133 | case S5P_FIMV_CODEC_VC1_DEC: | |
134 | ctx->bank1_size = | |
135 | ALIGN(S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE + | |
136 | S5P_FIMV_DEC_UPNB_MV_SIZE + | |
137 | S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE + | |
138 | S5P_FIMV_DEC_NB_DCAC_SIZE + | |
139 | 3 * S5P_FIMV_DEC_VC1_BITPLANE_SIZE, | |
140 | S5P_FIMV_DEC_BUF_ALIGN); | |
141 | ctx->bank2_size = 0; | |
142 | break; | |
143 | case S5P_FIMV_CODEC_MPEG2_DEC: | |
144 | ctx->bank1_size = 0; | |
145 | ctx->bank2_size = 0; | |
146 | break; | |
147 | case S5P_FIMV_CODEC_H263_DEC: | |
148 | ctx->bank1_size = | |
149 | ALIGN(S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE + | |
150 | S5P_FIMV_DEC_UPNB_MV_SIZE + | |
151 | S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE + | |
152 | S5P_FIMV_DEC_NB_DCAC_SIZE, | |
153 | S5P_FIMV_DEC_BUF_ALIGN); | |
154 | ctx->bank2_size = 0; | |
155 | break; | |
156 | case S5P_FIMV_CODEC_H264_ENC: | |
157 | ctx->bank1_size = (enc_ref_y_size * 2) + | |
158 | S5P_FIMV_ENC_UPMV_SIZE + | |
159 | S5P_FIMV_ENC_COLFLG_SIZE + | |
160 | S5P_FIMV_ENC_INTRAMD_SIZE + | |
161 | S5P_FIMV_ENC_NBORINFO_SIZE; | |
162 | ctx->bank2_size = (enc_ref_y_size * 2) + | |
163 | (enc_ref_c_size * 4) + | |
164 | S5P_FIMV_ENC_INTRAPRED_SIZE; | |
165 | break; | |
166 | case S5P_FIMV_CODEC_MPEG4_ENC: | |
167 | ctx->bank1_size = (enc_ref_y_size * 2) + | |
168 | S5P_FIMV_ENC_UPMV_SIZE + | |
169 | S5P_FIMV_ENC_COLFLG_SIZE + | |
170 | S5P_FIMV_ENC_ACDCCOEF_SIZE; | |
171 | ctx->bank2_size = (enc_ref_y_size * 2) + | |
172 | (enc_ref_c_size * 4); | |
173 | break; | |
174 | case S5P_FIMV_CODEC_H263_ENC: | |
175 | ctx->bank1_size = (enc_ref_y_size * 2) + | |
176 | S5P_FIMV_ENC_UPMV_SIZE + | |
177 | S5P_FIMV_ENC_ACDCCOEF_SIZE; | |
178 | ctx->bank2_size = (enc_ref_y_size * 2) + | |
179 | (enc_ref_c_size * 4); | |
180 | break; | |
181 | default: | |
182 | break; | |
183 | } | |
184 | /* Allocate only if memory from bank 1 is necessary */ | |
185 | if (ctx->bank1_size > 0) { | |
186 | ctx->bank1_buf = vb2_dma_contig_memops.alloc( | |
187 | dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], ctx->bank1_size); | |
188 | if (IS_ERR(ctx->bank1_buf)) { | |
1259762f | 189 | ctx->bank1_buf = NULL; |
af935746 KD |
190 | printk(KERN_ERR |
191 | "Buf alloc for decoding failed (port A)\n"); | |
192 | return -ENOMEM; | |
193 | } | |
194 | ctx->bank1_phys = s5p_mfc_mem_cookie( | |
195 | dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], ctx->bank1_buf); | |
196 | BUG_ON(ctx->bank1_phys & ((1 << MFC_BANK1_ALIGN_ORDER) - 1)); | |
197 | } | |
198 | /* Allocate only if memory from bank 2 is necessary */ | |
199 | if (ctx->bank2_size > 0) { | |
200 | ctx->bank2_buf = vb2_dma_contig_memops.alloc( | |
201 | dev->alloc_ctx[MFC_BANK2_ALLOC_CTX], ctx->bank2_size); | |
202 | if (IS_ERR(ctx->bank2_buf)) { | |
1259762f | 203 | ctx->bank2_buf = NULL; |
af935746 KD |
204 | mfc_err("Buf alloc for decoding failed (port B)\n"); |
205 | return -ENOMEM; | |
206 | } | |
207 | ctx->bank2_phys = s5p_mfc_mem_cookie( | |
208 | dev->alloc_ctx[MFC_BANK2_ALLOC_CTX], ctx->bank2_buf); | |
209 | BUG_ON(ctx->bank2_phys & ((1 << MFC_BANK2_ALIGN_ORDER) - 1)); | |
210 | } | |
211 | return 0; | |
212 | } | |
213 | ||
214 | /* Release buffers allocated for codec */ | |
215 | void s5p_mfc_release_codec_buffers(struct s5p_mfc_ctx *ctx) | |
216 | { | |
217 | if (ctx->bank1_buf) { | |
218 | vb2_dma_contig_memops.put(ctx->bank1_buf); | |
1259762f | 219 | ctx->bank1_buf = NULL; |
af935746 KD |
220 | ctx->bank1_phys = 0; |
221 | ctx->bank1_size = 0; | |
222 | } | |
223 | if (ctx->bank2_buf) { | |
224 | vb2_dma_contig_memops.put(ctx->bank2_buf); | |
1259762f | 225 | ctx->bank2_buf = NULL; |
af935746 KD |
226 | ctx->bank2_phys = 0; |
227 | ctx->bank2_size = 0; | |
228 | } | |
229 | } | |
230 | ||
231 | /* Allocate memory for instance data buffer */ | |
232 | int s5p_mfc_alloc_instance_buffer(struct s5p_mfc_ctx *ctx) | |
233 | { | |
234 | void *context_virt; | |
235 | struct s5p_mfc_dev *dev = ctx->dev; | |
236 | ||
237 | if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC || | |
238 | ctx->codec_mode == S5P_FIMV_CODEC_H264_ENC) | |
239 | ctx->ctx_size = MFC_H264_CTX_BUF_SIZE; | |
240 | else | |
241 | ctx->ctx_size = MFC_CTX_BUF_SIZE; | |
242 | ctx->ctx_buf = vb2_dma_contig_memops.alloc( | |
243 | dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], ctx->ctx_size); | |
244 | if (IS_ERR(ctx->ctx_buf)) { | |
245 | mfc_err("Allocating context buffer failed\n"); | |
246 | ctx->ctx_phys = 0; | |
1259762f | 247 | ctx->ctx_buf = NULL; |
af935746 KD |
248 | return -ENOMEM; |
249 | } | |
250 | ctx->ctx_phys = s5p_mfc_mem_cookie( | |
251 | dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], ctx->ctx_buf); | |
252 | BUG_ON(ctx->ctx_phys & ((1 << MFC_BANK1_ALIGN_ORDER) - 1)); | |
253 | ctx->ctx_ofs = OFFSETA(ctx->ctx_phys); | |
254 | context_virt = vb2_dma_contig_memops.vaddr(ctx->ctx_buf); | |
255 | if (context_virt == NULL) { | |
256 | mfc_err("Remapping instance buffer failed\n"); | |
257 | vb2_dma_contig_memops.put(ctx->ctx_buf); | |
258 | ctx->ctx_phys = 0; | |
1259762f | 259 | ctx->ctx_buf = NULL; |
af935746 KD |
260 | return -ENOMEM; |
261 | } | |
262 | /* Zero content of the allocated memory */ | |
263 | memset(context_virt, 0, ctx->ctx_size); | |
264 | wmb(); | |
265 | if (s5p_mfc_init_shm(ctx) < 0) { | |
266 | vb2_dma_contig_memops.put(ctx->ctx_buf); | |
267 | ctx->ctx_phys = 0; | |
1259762f | 268 | ctx->ctx_buf = NULL; |
af935746 KD |
269 | return -ENOMEM; |
270 | } | |
271 | return 0; | |
272 | } | |
273 | ||
274 | /* Release instance buffer */ | |
275 | void s5p_mfc_release_instance_buffer(struct s5p_mfc_ctx *ctx) | |
276 | { | |
277 | if (ctx->ctx_buf) { | |
278 | vb2_dma_contig_memops.put(ctx->ctx_buf); | |
279 | ctx->ctx_phys = 0; | |
1259762f | 280 | ctx->ctx_buf = NULL; |
af935746 KD |
281 | } |
282 | if (ctx->shm_alloc) { | |
283 | vb2_dma_contig_memops.put(ctx->shm_alloc); | |
1259762f SK |
284 | ctx->shm_alloc = NULL; |
285 | ctx->shm = NULL; | |
af935746 KD |
286 | } |
287 | } | |
288 | ||
289 | /* Set registers for decoding temporary buffers */ | |
290 | void s5p_mfc_set_dec_desc_buffer(struct s5p_mfc_ctx *ctx) | |
291 | { | |
292 | struct s5p_mfc_dev *dev = ctx->dev; | |
293 | ||
294 | mfc_write(dev, OFFSETA(ctx->desc_phys), S5P_FIMV_SI_CH0_DESC_ADR); | |
295 | mfc_write(dev, DESC_BUF_SIZE, S5P_FIMV_SI_CH0_DESC_SIZE); | |
296 | } | |
297 | ||
298 | /* Set registers for shared buffer */ | |
a13bba4f | 299 | static void s5p_mfc_set_shared_buffer(struct s5p_mfc_ctx *ctx) |
af935746 KD |
300 | { |
301 | struct s5p_mfc_dev *dev = ctx->dev; | |
302 | mfc_write(dev, ctx->shm_ofs, S5P_FIMV_SI_CH0_HOST_WR_ADR); | |
303 | } | |
304 | ||
305 | /* Set registers for decoding stream buffer */ | |
306 | int s5p_mfc_set_dec_stream_buffer(struct s5p_mfc_ctx *ctx, int buf_addr, | |
307 | unsigned int start_num_byte, unsigned int buf_size) | |
308 | { | |
309 | struct s5p_mfc_dev *dev = ctx->dev; | |
310 | ||
311 | mfc_write(dev, OFFSETA(buf_addr), S5P_FIMV_SI_CH0_SB_ST_ADR); | |
312 | mfc_write(dev, ctx->dec_src_buf_size, S5P_FIMV_SI_CH0_CPB_SIZE); | |
313 | mfc_write(dev, buf_size, S5P_FIMV_SI_CH0_SB_FRM_SIZE); | |
314 | s5p_mfc_write_shm(ctx, start_num_byte, START_BYTE_NUM); | |
315 | return 0; | |
316 | } | |
317 | ||
318 | /* Set decoding frame buffer */ | |
319 | int s5p_mfc_set_dec_frame_buffer(struct s5p_mfc_ctx *ctx) | |
320 | { | |
321 | unsigned int frame_size, i; | |
322 | unsigned int frame_size_ch, frame_size_mv; | |
323 | struct s5p_mfc_dev *dev = ctx->dev; | |
324 | unsigned int dpb; | |
325 | size_t buf_addr1, buf_addr2; | |
326 | int buf_size1, buf_size2; | |
327 | ||
328 | buf_addr1 = ctx->bank1_phys; | |
329 | buf_size1 = ctx->bank1_size; | |
330 | buf_addr2 = ctx->bank2_phys; | |
331 | buf_size2 = ctx->bank2_size; | |
332 | dpb = mfc_read(dev, S5P_FIMV_SI_CH0_DPB_CONF_CTRL) & | |
333 | ~S5P_FIMV_DPB_COUNT_MASK; | |
334 | mfc_write(dev, ctx->total_dpb_count | dpb, | |
335 | S5P_FIMV_SI_CH0_DPB_CONF_CTRL); | |
336 | s5p_mfc_set_shared_buffer(ctx); | |
337 | switch (ctx->codec_mode) { | |
338 | case S5P_FIMV_CODEC_H264_DEC: | |
339 | mfc_write(dev, OFFSETA(buf_addr1), | |
340 | S5P_FIMV_H264_VERT_NB_MV_ADR); | |
341 | buf_addr1 += S5P_FIMV_DEC_VERT_NB_MV_SIZE; | |
342 | buf_size1 -= S5P_FIMV_DEC_VERT_NB_MV_SIZE; | |
343 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H264_NB_IP_ADR); | |
344 | buf_addr1 += S5P_FIMV_DEC_NB_IP_SIZE; | |
345 | buf_size1 -= S5P_FIMV_DEC_NB_IP_SIZE; | |
346 | break; | |
347 | case S5P_FIMV_CODEC_MPEG4_DEC: | |
348 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_NB_DCAC_ADR); | |
349 | buf_addr1 += S5P_FIMV_DEC_NB_DCAC_SIZE; | |
350 | buf_size1 -= S5P_FIMV_DEC_NB_DCAC_SIZE; | |
351 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_UP_NB_MV_ADR); | |
352 | buf_addr1 += S5P_FIMV_DEC_UPNB_MV_SIZE; | |
353 | buf_size1 -= S5P_FIMV_DEC_UPNB_MV_SIZE; | |
354 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_SA_MV_ADR); | |
355 | buf_addr1 += S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE; | |
356 | buf_size1 -= S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE; | |
357 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_SP_ADR); | |
358 | buf_addr1 += S5P_FIMV_DEC_STX_PARSER_SIZE; | |
359 | buf_size1 -= S5P_FIMV_DEC_STX_PARSER_SIZE; | |
360 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_OT_LINE_ADR); | |
361 | buf_addr1 += S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE; | |
362 | buf_size1 -= S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE; | |
363 | break; | |
364 | case S5P_FIMV_CODEC_H263_DEC: | |
365 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_OT_LINE_ADR); | |
366 | buf_addr1 += S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE; | |
367 | buf_size1 -= S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE; | |
368 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_UP_NB_MV_ADR); | |
369 | buf_addr1 += S5P_FIMV_DEC_UPNB_MV_SIZE; | |
370 | buf_size1 -= S5P_FIMV_DEC_UPNB_MV_SIZE; | |
371 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_SA_MV_ADR); | |
372 | buf_addr1 += S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE; | |
373 | buf_size1 -= S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE; | |
374 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_NB_DCAC_ADR); | |
375 | buf_addr1 += S5P_FIMV_DEC_NB_DCAC_SIZE; | |
376 | buf_size1 -= S5P_FIMV_DEC_NB_DCAC_SIZE; | |
377 | break; | |
378 | case S5P_FIMV_CODEC_VC1_DEC: | |
379 | case S5P_FIMV_CODEC_VC1RCV_DEC: | |
380 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_NB_DCAC_ADR); | |
381 | buf_addr1 += S5P_FIMV_DEC_NB_DCAC_SIZE; | |
382 | buf_size1 -= S5P_FIMV_DEC_NB_DCAC_SIZE; | |
383 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_OT_LINE_ADR); | |
384 | buf_addr1 += S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE; | |
385 | buf_size1 -= S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE; | |
386 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_UP_NB_MV_ADR); | |
387 | buf_addr1 += S5P_FIMV_DEC_UPNB_MV_SIZE; | |
388 | buf_size1 -= S5P_FIMV_DEC_UPNB_MV_SIZE; | |
389 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_SA_MV_ADR); | |
390 | buf_addr1 += S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE; | |
391 | buf_size1 -= S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE; | |
392 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_BITPLANE3_ADR); | |
393 | buf_addr1 += S5P_FIMV_DEC_VC1_BITPLANE_SIZE; | |
394 | buf_size1 -= S5P_FIMV_DEC_VC1_BITPLANE_SIZE; | |
395 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_BITPLANE2_ADR); | |
396 | buf_addr1 += S5P_FIMV_DEC_VC1_BITPLANE_SIZE; | |
397 | buf_size1 -= S5P_FIMV_DEC_VC1_BITPLANE_SIZE; | |
398 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_BITPLANE1_ADR); | |
399 | buf_addr1 += S5P_FIMV_DEC_VC1_BITPLANE_SIZE; | |
400 | buf_size1 -= S5P_FIMV_DEC_VC1_BITPLANE_SIZE; | |
401 | break; | |
402 | case S5P_FIMV_CODEC_MPEG2_DEC: | |
403 | break; | |
404 | default: | |
405 | mfc_err("Unknown codec for decoding (%x)\n", | |
406 | ctx->codec_mode); | |
407 | return -EINVAL; | |
408 | break; | |
409 | } | |
410 | frame_size = ctx->luma_size; | |
411 | frame_size_ch = ctx->chroma_size; | |
412 | frame_size_mv = ctx->mv_size; | |
413 | mfc_debug(2, "Frm size: %d ch: %d mv: %d\n", frame_size, frame_size_ch, | |
414 | frame_size_mv); | |
415 | for (i = 0; i < ctx->total_dpb_count; i++) { | |
416 | /* Bank2 */ | |
417 | mfc_debug(2, "Luma %d: %x\n", i, | |
418 | ctx->dst_bufs[i].cookie.raw.luma); | |
419 | mfc_write(dev, OFFSETB(ctx->dst_bufs[i].cookie.raw.luma), | |
420 | S5P_FIMV_DEC_LUMA_ADR + i * 4); | |
421 | mfc_debug(2, "\tChroma %d: %x\n", i, | |
422 | ctx->dst_bufs[i].cookie.raw.chroma); | |
423 | mfc_write(dev, OFFSETA(ctx->dst_bufs[i].cookie.raw.chroma), | |
424 | S5P_FIMV_DEC_CHROMA_ADR + i * 4); | |
425 | if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC) { | |
426 | mfc_debug(2, "\tBuf2: %x, size: %d\n", | |
427 | buf_addr2, buf_size2); | |
428 | mfc_write(dev, OFFSETB(buf_addr2), | |
429 | S5P_FIMV_H264_MV_ADR + i * 4); | |
430 | buf_addr2 += frame_size_mv; | |
431 | buf_size2 -= frame_size_mv; | |
432 | } | |
433 | } | |
434 | mfc_debug(2, "Buf1: %u, buf_size1: %d\n", buf_addr1, buf_size1); | |
435 | mfc_debug(2, "Buf 1/2 size after: %d/%d (frames %d)\n", | |
436 | buf_size1, buf_size2, ctx->total_dpb_count); | |
437 | if (buf_size1 < 0 || buf_size2 < 0) { | |
438 | mfc_debug(2, "Not enough memory has been allocated\n"); | |
439 | return -ENOMEM; | |
440 | } | |
441 | s5p_mfc_write_shm(ctx, frame_size, ALLOC_LUMA_DPB_SIZE); | |
442 | s5p_mfc_write_shm(ctx, frame_size_ch, ALLOC_CHROMA_DPB_SIZE); | |
443 | if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC) | |
444 | s5p_mfc_write_shm(ctx, frame_size_mv, ALLOC_MV_SIZE); | |
445 | mfc_write(dev, ((S5P_FIMV_CH_INIT_BUFS & S5P_FIMV_CH_MASK) | |
446 | << S5P_FIMV_CH_SHIFT) | (ctx->inst_no), | |
447 | S5P_FIMV_SI_CH0_INST_ID); | |
448 | return 0; | |
449 | } | |
450 | ||
451 | /* Set registers for encoding stream buffer */ | |
452 | int s5p_mfc_set_enc_stream_buffer(struct s5p_mfc_ctx *ctx, | |
453 | unsigned long addr, unsigned int size) | |
454 | { | |
455 | struct s5p_mfc_dev *dev = ctx->dev; | |
456 | ||
457 | mfc_write(dev, OFFSETA(addr), S5P_FIMV_ENC_SI_CH0_SB_ADR); | |
458 | mfc_write(dev, size, S5P_FIMV_ENC_SI_CH0_SB_SIZE); | |
459 | return 0; | |
460 | } | |
461 | ||
462 | void s5p_mfc_set_enc_frame_buffer(struct s5p_mfc_ctx *ctx, | |
463 | unsigned long y_addr, unsigned long c_addr) | |
464 | { | |
465 | struct s5p_mfc_dev *dev = ctx->dev; | |
466 | ||
467 | mfc_write(dev, OFFSETB(y_addr), S5P_FIMV_ENC_SI_CH0_CUR_Y_ADR); | |
468 | mfc_write(dev, OFFSETB(c_addr), S5P_FIMV_ENC_SI_CH0_CUR_C_ADR); | |
469 | } | |
470 | ||
471 | void s5p_mfc_get_enc_frame_buffer(struct s5p_mfc_ctx *ctx, | |
472 | unsigned long *y_addr, unsigned long *c_addr) | |
473 | { | |
474 | struct s5p_mfc_dev *dev = ctx->dev; | |
475 | ||
476 | *y_addr = dev->bank2 + (mfc_read(dev, S5P_FIMV_ENCODED_Y_ADDR) | |
477 | << MFC_OFFSET_SHIFT); | |
478 | *c_addr = dev->bank2 + (mfc_read(dev, S5P_FIMV_ENCODED_C_ADDR) | |
479 | << MFC_OFFSET_SHIFT); | |
480 | } | |
481 | ||
482 | /* Set encoding ref & codec buffer */ | |
483 | int s5p_mfc_set_enc_ref_buffer(struct s5p_mfc_ctx *ctx) | |
484 | { | |
485 | struct s5p_mfc_dev *dev = ctx->dev; | |
486 | size_t buf_addr1, buf_addr2; | |
487 | size_t buf_size1, buf_size2; | |
488 | unsigned int enc_ref_y_size, enc_ref_c_size; | |
489 | unsigned int guard_width, guard_height; | |
490 | int i; | |
491 | ||
492 | buf_addr1 = ctx->bank1_phys; | |
493 | buf_size1 = ctx->bank1_size; | |
494 | buf_addr2 = ctx->bank2_phys; | |
495 | buf_size2 = ctx->bank2_size; | |
496 | enc_ref_y_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN) | |
497 | * ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN); | |
498 | enc_ref_y_size = ALIGN(enc_ref_y_size, S5P_FIMV_NV12MT_SALIGN); | |
499 | if (ctx->codec_mode == S5P_FIMV_CODEC_H264_ENC) { | |
500 | enc_ref_c_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN) | |
501 | * ALIGN((ctx->img_height >> 1), S5P_FIMV_NV12MT_VALIGN); | |
502 | enc_ref_c_size = ALIGN(enc_ref_c_size, S5P_FIMV_NV12MT_SALIGN); | |
503 | } else { | |
504 | guard_width = ALIGN(ctx->img_width + 16, | |
505 | S5P_FIMV_NV12MT_HALIGN); | |
506 | guard_height = ALIGN((ctx->img_height >> 1) + 4, | |
507 | S5P_FIMV_NV12MT_VALIGN); | |
508 | enc_ref_c_size = ALIGN(guard_width * guard_height, | |
509 | S5P_FIMV_NV12MT_SALIGN); | |
510 | } | |
511 | mfc_debug(2, "buf_size1: %d, buf_size2: %d\n", buf_size1, buf_size2); | |
512 | switch (ctx->codec_mode) { | |
513 | case S5P_FIMV_CODEC_H264_ENC: | |
514 | for (i = 0; i < 2; i++) { | |
515 | mfc_write(dev, OFFSETA(buf_addr1), | |
516 | S5P_FIMV_ENC_REF0_LUMA_ADR + (4 * i)); | |
517 | buf_addr1 += enc_ref_y_size; | |
518 | buf_size1 -= enc_ref_y_size; | |
519 | ||
520 | mfc_write(dev, OFFSETB(buf_addr2), | |
521 | S5P_FIMV_ENC_REF2_LUMA_ADR + (4 * i)); | |
522 | buf_addr2 += enc_ref_y_size; | |
523 | buf_size2 -= enc_ref_y_size; | |
524 | } | |
525 | for (i = 0; i < 4; i++) { | |
526 | mfc_write(dev, OFFSETB(buf_addr2), | |
527 | S5P_FIMV_ENC_REF0_CHROMA_ADR + (4 * i)); | |
528 | buf_addr2 += enc_ref_c_size; | |
529 | buf_size2 -= enc_ref_c_size; | |
530 | } | |
531 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H264_UP_MV_ADR); | |
532 | buf_addr1 += S5P_FIMV_ENC_UPMV_SIZE; | |
533 | buf_size1 -= S5P_FIMV_ENC_UPMV_SIZE; | |
534 | mfc_write(dev, OFFSETA(buf_addr1), | |
535 | S5P_FIMV_H264_COZERO_FLAG_ADR); | |
536 | buf_addr1 += S5P_FIMV_ENC_COLFLG_SIZE; | |
537 | buf_size1 -= S5P_FIMV_ENC_COLFLG_SIZE; | |
538 | mfc_write(dev, OFFSETA(buf_addr1), | |
539 | S5P_FIMV_H264_UP_INTRA_MD_ADR); | |
540 | buf_addr1 += S5P_FIMV_ENC_INTRAMD_SIZE; | |
541 | buf_size1 -= S5P_FIMV_ENC_INTRAMD_SIZE; | |
542 | mfc_write(dev, OFFSETB(buf_addr2), | |
543 | S5P_FIMV_H264_UP_INTRA_PRED_ADR); | |
544 | buf_addr2 += S5P_FIMV_ENC_INTRAPRED_SIZE; | |
545 | buf_size2 -= S5P_FIMV_ENC_INTRAPRED_SIZE; | |
546 | mfc_write(dev, OFFSETA(buf_addr1), | |
547 | S5P_FIMV_H264_NBOR_INFO_ADR); | |
548 | buf_addr1 += S5P_FIMV_ENC_NBORINFO_SIZE; | |
549 | buf_size1 -= S5P_FIMV_ENC_NBORINFO_SIZE; | |
550 | mfc_debug(2, "buf_size1: %d, buf_size2: %d\n", | |
551 | buf_size1, buf_size2); | |
552 | break; | |
553 | case S5P_FIMV_CODEC_MPEG4_ENC: | |
554 | for (i = 0; i < 2; i++) { | |
555 | mfc_write(dev, OFFSETA(buf_addr1), | |
556 | S5P_FIMV_ENC_REF0_LUMA_ADR + (4 * i)); | |
557 | buf_addr1 += enc_ref_y_size; | |
558 | buf_size1 -= enc_ref_y_size; | |
559 | mfc_write(dev, OFFSETB(buf_addr2), | |
560 | S5P_FIMV_ENC_REF2_LUMA_ADR + (4 * i)); | |
561 | buf_addr2 += enc_ref_y_size; | |
562 | buf_size2 -= enc_ref_y_size; | |
563 | } | |
564 | for (i = 0; i < 4; i++) { | |
565 | mfc_write(dev, OFFSETB(buf_addr2), | |
566 | S5P_FIMV_ENC_REF0_CHROMA_ADR + (4 * i)); | |
567 | buf_addr2 += enc_ref_c_size; | |
568 | buf_size2 -= enc_ref_c_size; | |
569 | } | |
570 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_UP_MV_ADR); | |
571 | buf_addr1 += S5P_FIMV_ENC_UPMV_SIZE; | |
572 | buf_size1 -= S5P_FIMV_ENC_UPMV_SIZE; | |
573 | mfc_write(dev, OFFSETA(buf_addr1), | |
574 | S5P_FIMV_MPEG4_COZERO_FLAG_ADR); | |
575 | buf_addr1 += S5P_FIMV_ENC_COLFLG_SIZE; | |
576 | buf_size1 -= S5P_FIMV_ENC_COLFLG_SIZE; | |
577 | mfc_write(dev, OFFSETA(buf_addr1), | |
578 | S5P_FIMV_MPEG4_ACDC_COEF_ADR); | |
579 | buf_addr1 += S5P_FIMV_ENC_ACDCCOEF_SIZE; | |
580 | buf_size1 -= S5P_FIMV_ENC_ACDCCOEF_SIZE; | |
581 | mfc_debug(2, "buf_size1: %d, buf_size2: %d\n", | |
582 | buf_size1, buf_size2); | |
583 | break; | |
584 | case S5P_FIMV_CODEC_H263_ENC: | |
585 | for (i = 0; i < 2; i++) { | |
586 | mfc_write(dev, OFFSETA(buf_addr1), | |
587 | S5P_FIMV_ENC_REF0_LUMA_ADR + (4 * i)); | |
588 | buf_addr1 += enc_ref_y_size; | |
589 | buf_size1 -= enc_ref_y_size; | |
590 | mfc_write(dev, OFFSETB(buf_addr2), | |
591 | S5P_FIMV_ENC_REF2_LUMA_ADR + (4 * i)); | |
592 | buf_addr2 += enc_ref_y_size; | |
593 | buf_size2 -= enc_ref_y_size; | |
594 | } | |
595 | for (i = 0; i < 4; i++) { | |
596 | mfc_write(dev, OFFSETB(buf_addr2), | |
597 | S5P_FIMV_ENC_REF0_CHROMA_ADR + (4 * i)); | |
598 | buf_addr2 += enc_ref_c_size; | |
599 | buf_size2 -= enc_ref_c_size; | |
600 | } | |
601 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_UP_MV_ADR); | |
602 | buf_addr1 += S5P_FIMV_ENC_UPMV_SIZE; | |
603 | buf_size1 -= S5P_FIMV_ENC_UPMV_SIZE; | |
604 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_ACDC_COEF_ADR); | |
605 | buf_addr1 += S5P_FIMV_ENC_ACDCCOEF_SIZE; | |
606 | buf_size1 -= S5P_FIMV_ENC_ACDCCOEF_SIZE; | |
607 | mfc_debug(2, "buf_size1: %d, buf_size2: %d\n", | |
608 | buf_size1, buf_size2); | |
609 | break; | |
610 | default: | |
611 | mfc_err("Unknown codec set for encoding: %d\n", | |
612 | ctx->codec_mode); | |
613 | return -EINVAL; | |
614 | } | |
615 | return 0; | |
616 | } | |
617 | ||
618 | static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx) | |
619 | { | |
620 | struct s5p_mfc_dev *dev = ctx->dev; | |
621 | struct s5p_mfc_enc_params *p = &ctx->enc_params; | |
622 | unsigned int reg; | |
623 | unsigned int shm; | |
624 | ||
625 | /* width */ | |
626 | mfc_write(dev, ctx->img_width, S5P_FIMV_ENC_HSIZE_PX); | |
627 | /* height */ | |
628 | mfc_write(dev, ctx->img_height, S5P_FIMV_ENC_VSIZE_PX); | |
629 | /* pictype : enable, IDR period */ | |
630 | reg = mfc_read(dev, S5P_FIMV_ENC_PIC_TYPE_CTRL); | |
631 | reg |= (1 << 18); | |
632 | reg &= ~(0xFFFF); | |
633 | reg |= p->gop_size; | |
634 | mfc_write(dev, reg, S5P_FIMV_ENC_PIC_TYPE_CTRL); | |
635 | mfc_write(dev, 0, S5P_FIMV_ENC_B_RECON_WRITE_ON); | |
636 | /* multi-slice control */ | |
637 | /* multi-slice MB number or bit size */ | |
638 | mfc_write(dev, p->slice_mode, S5P_FIMV_ENC_MSLICE_CTRL); | |
639 | if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) { | |
640 | mfc_write(dev, p->slice_mb, S5P_FIMV_ENC_MSLICE_MB); | |
641 | } else if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) { | |
642 | mfc_write(dev, p->slice_bit, S5P_FIMV_ENC_MSLICE_BIT); | |
643 | } else { | |
644 | mfc_write(dev, 0, S5P_FIMV_ENC_MSLICE_MB); | |
645 | mfc_write(dev, 0, S5P_FIMV_ENC_MSLICE_BIT); | |
646 | } | |
647 | /* cyclic intra refresh */ | |
648 | mfc_write(dev, p->intra_refresh_mb, S5P_FIMV_ENC_CIR_CTRL); | |
649 | /* memory structure cur. frame */ | |
650 | if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) | |
651 | mfc_write(dev, 0, S5P_FIMV_ENC_MAP_FOR_CUR); | |
652 | else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT) | |
653 | mfc_write(dev, 3, S5P_FIMV_ENC_MAP_FOR_CUR); | |
654 | /* padding control & value */ | |
655 | reg = mfc_read(dev, S5P_FIMV_ENC_PADDING_CTRL); | |
656 | if (p->pad) { | |
657 | /** enable */ | |
658 | reg |= (1 << 31); | |
659 | /** cr value */ | |
660 | reg &= ~(0xFF << 16); | |
661 | reg |= (p->pad_cr << 16); | |
662 | /** cb value */ | |
663 | reg &= ~(0xFF << 8); | |
664 | reg |= (p->pad_cb << 8); | |
665 | /** y value */ | |
666 | reg &= ~(0xFF); | |
667 | reg |= (p->pad_luma); | |
668 | } else { | |
669 | /** disable & all value clear */ | |
670 | reg = 0; | |
671 | } | |
672 | mfc_write(dev, reg, S5P_FIMV_ENC_PADDING_CTRL); | |
673 | /* rate control config. */ | |
674 | reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG); | |
675 | /** frame-level rate control */ | |
676 | reg &= ~(0x1 << 9); | |
677 | reg |= (p->rc_frame << 9); | |
678 | mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG); | |
679 | /* bit rate */ | |
680 | if (p->rc_frame) | |
681 | mfc_write(dev, p->rc_bitrate, | |
682 | S5P_FIMV_ENC_RC_BIT_RATE); | |
683 | else | |
684 | mfc_write(dev, 0, S5P_FIMV_ENC_RC_BIT_RATE); | |
685 | /* reaction coefficient */ | |
686 | if (p->rc_frame) | |
687 | mfc_write(dev, p->rc_reaction_coeff, S5P_FIMV_ENC_RC_RPARA); | |
688 | shm = s5p_mfc_read_shm(ctx, EXT_ENC_CONTROL); | |
689 | /* seq header ctrl */ | |
690 | shm &= ~(0x1 << 3); | |
691 | shm |= (p->seq_hdr_mode << 3); | |
692 | /* frame skip mode */ | |
693 | shm &= ~(0x3 << 1); | |
694 | shm |= (p->frame_skip_mode << 1); | |
695 | s5p_mfc_write_shm(ctx, shm, EXT_ENC_CONTROL); | |
696 | /* fixed target bit */ | |
697 | s5p_mfc_write_shm(ctx, p->fixed_target_bit, RC_CONTROL_CONFIG); | |
698 | return 0; | |
699 | } | |
700 | ||
701 | static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx) | |
702 | { | |
703 | struct s5p_mfc_dev *dev = ctx->dev; | |
704 | struct s5p_mfc_enc_params *p = &ctx->enc_params; | |
705 | struct s5p_mfc_h264_enc_params *p_264 = &p->codec.h264; | |
706 | unsigned int reg; | |
707 | unsigned int shm; | |
708 | ||
709 | s5p_mfc_set_enc_params(ctx); | |
710 | /* pictype : number of B */ | |
711 | reg = mfc_read(dev, S5P_FIMV_ENC_PIC_TYPE_CTRL); | |
712 | /* num_b_frame - 0 ~ 2 */ | |
713 | reg &= ~(0x3 << 16); | |
714 | reg |= (p->num_b_frame << 16); | |
715 | mfc_write(dev, reg, S5P_FIMV_ENC_PIC_TYPE_CTRL); | |
716 | /* profile & level */ | |
717 | reg = mfc_read(dev, S5P_FIMV_ENC_PROFILE); | |
718 | /* level */ | |
719 | reg &= ~(0xFF << 8); | |
720 | reg |= (p_264->level << 8); | |
721 | /* profile - 0 ~ 2 */ | |
722 | reg &= ~(0x3F); | |
723 | reg |= p_264->profile; | |
724 | mfc_write(dev, reg, S5P_FIMV_ENC_PROFILE); | |
725 | /* interlace */ | |
726 | mfc_write(dev, p->interlace, S5P_FIMV_ENC_PIC_STRUCT); | |
727 | /* height */ | |
728 | if (p->interlace) | |
729 | mfc_write(dev, ctx->img_height >> 1, S5P_FIMV_ENC_VSIZE_PX); | |
730 | /* loopfilter ctrl */ | |
731 | mfc_write(dev, p_264->loop_filter_mode, S5P_FIMV_ENC_LF_CTRL); | |
732 | /* loopfilter alpha offset */ | |
733 | if (p_264->loop_filter_alpha < 0) { | |
734 | reg = 0x10; | |
735 | reg |= (0xFF - p_264->loop_filter_alpha) + 1; | |
736 | } else { | |
737 | reg = 0x00; | |
738 | reg |= (p_264->loop_filter_alpha & 0xF); | |
739 | } | |
740 | mfc_write(dev, reg, S5P_FIMV_ENC_ALPHA_OFF); | |
741 | /* loopfilter beta offset */ | |
742 | if (p_264->loop_filter_beta < 0) { | |
743 | reg = 0x10; | |
744 | reg |= (0xFF - p_264->loop_filter_beta) + 1; | |
745 | } else { | |
746 | reg = 0x00; | |
747 | reg |= (p_264->loop_filter_beta & 0xF); | |
748 | } | |
749 | mfc_write(dev, reg, S5P_FIMV_ENC_BETA_OFF); | |
750 | /* entropy coding mode */ | |
751 | if (p_264->entropy_mode == V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC) | |
752 | mfc_write(dev, 1, S5P_FIMV_ENC_H264_ENTROPY_MODE); | |
753 | else | |
754 | mfc_write(dev, 0, S5P_FIMV_ENC_H264_ENTROPY_MODE); | |
755 | /* number of ref. picture */ | |
756 | reg = mfc_read(dev, S5P_FIMV_ENC_H264_NUM_OF_REF); | |
757 | /* num of ref. pictures of P */ | |
758 | reg &= ~(0x3 << 5); | |
759 | reg |= (p_264->num_ref_pic_4p << 5); | |
760 | /* max number of ref. pictures */ | |
761 | reg &= ~(0x1F); | |
762 | reg |= p_264->max_ref_pic; | |
763 | mfc_write(dev, reg, S5P_FIMV_ENC_H264_NUM_OF_REF); | |
764 | /* 8x8 transform enable */ | |
765 | mfc_write(dev, p_264->_8x8_transform, S5P_FIMV_ENC_H264_TRANS_FLAG); | |
766 | /* rate control config. */ | |
767 | reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG); | |
768 | /* macroblock level rate control */ | |
769 | reg &= ~(0x1 << 8); | |
770 | reg |= (p_264->rc_mb << 8); | |
771 | /* frame QP */ | |
772 | reg &= ~(0x3F); | |
773 | reg |= p_264->rc_frame_qp; | |
774 | mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG); | |
775 | /* frame rate */ | |
776 | if (p->rc_frame && p->rc_framerate_denom) | |
777 | mfc_write(dev, p->rc_framerate_num * 1000 | |
778 | / p->rc_framerate_denom, S5P_FIMV_ENC_RC_FRAME_RATE); | |
779 | else | |
780 | mfc_write(dev, 0, S5P_FIMV_ENC_RC_FRAME_RATE); | |
781 | /* max & min value of QP */ | |
782 | reg = mfc_read(dev, S5P_FIMV_ENC_RC_QBOUND); | |
783 | /* max QP */ | |
784 | reg &= ~(0x3F << 8); | |
785 | reg |= (p_264->rc_max_qp << 8); | |
786 | /* min QP */ | |
787 | reg &= ~(0x3F); | |
788 | reg |= p_264->rc_min_qp; | |
789 | mfc_write(dev, reg, S5P_FIMV_ENC_RC_QBOUND); | |
790 | /* macroblock adaptive scaling features */ | |
791 | if (p_264->rc_mb) { | |
792 | reg = mfc_read(dev, S5P_FIMV_ENC_RC_MB_CTRL); | |
793 | /* dark region */ | |
794 | reg &= ~(0x1 << 3); | |
795 | reg |= (p_264->rc_mb_dark << 3); | |
796 | /* smooth region */ | |
797 | reg &= ~(0x1 << 2); | |
798 | reg |= (p_264->rc_mb_smooth << 2); | |
799 | /* static region */ | |
800 | reg &= ~(0x1 << 1); | |
801 | reg |= (p_264->rc_mb_static << 1); | |
802 | /* high activity region */ | |
803 | reg &= ~(0x1); | |
804 | reg |= p_264->rc_mb_activity; | |
805 | mfc_write(dev, reg, S5P_FIMV_ENC_RC_MB_CTRL); | |
806 | } | |
807 | if (!p->rc_frame && | |
808 | !p_264->rc_mb) { | |
809 | shm = s5p_mfc_read_shm(ctx, P_B_FRAME_QP); | |
810 | shm &= ~(0xFFF); | |
811 | shm |= ((p_264->rc_b_frame_qp & 0x3F) << 6); | |
812 | shm |= (p_264->rc_p_frame_qp & 0x3F); | |
813 | s5p_mfc_write_shm(ctx, shm, P_B_FRAME_QP); | |
814 | } | |
815 | /* extended encoder ctrl */ | |
816 | shm = s5p_mfc_read_shm(ctx, EXT_ENC_CONTROL); | |
817 | /* AR VUI control */ | |
818 | shm &= ~(0x1 << 15); | |
819 | shm |= (p_264->vui_sar << 1); | |
820 | s5p_mfc_write_shm(ctx, shm, EXT_ENC_CONTROL); | |
821 | if (p_264->vui_sar) { | |
822 | /* aspect ration IDC */ | |
823 | shm = s5p_mfc_read_shm(ctx, SAMPLE_ASPECT_RATIO_IDC); | |
824 | shm &= ~(0xFF); | |
825 | shm |= p_264->vui_sar_idc; | |
826 | s5p_mfc_write_shm(ctx, shm, SAMPLE_ASPECT_RATIO_IDC); | |
827 | if (p_264->vui_sar_idc == 0xFF) { | |
828 | /* sample AR info */ | |
829 | shm = s5p_mfc_read_shm(ctx, EXTENDED_SAR); | |
830 | shm &= ~(0xFFFFFFFF); | |
831 | shm |= p_264->vui_ext_sar_width << 16; | |
832 | shm |= p_264->vui_ext_sar_height; | |
833 | s5p_mfc_write_shm(ctx, shm, EXTENDED_SAR); | |
834 | } | |
835 | } | |
836 | /* intra picture period for H.264 */ | |
837 | shm = s5p_mfc_read_shm(ctx, H264_I_PERIOD); | |
838 | /* control */ | |
839 | shm &= ~(0x1 << 16); | |
840 | shm |= (p_264->open_gop << 16); | |
841 | /* value */ | |
842 | if (p_264->open_gop) { | |
843 | shm &= ~(0xFFFF); | |
844 | shm |= p_264->open_gop_size; | |
845 | } | |
846 | s5p_mfc_write_shm(ctx, shm, H264_I_PERIOD); | |
847 | /* extended encoder ctrl */ | |
848 | shm = s5p_mfc_read_shm(ctx, EXT_ENC_CONTROL); | |
849 | /* vbv buffer size */ | |
850 | if (p->frame_skip_mode == | |
851 | V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { | |
852 | shm &= ~(0xFFFF << 16); | |
853 | shm |= (p_264->cpb_size << 16); | |
854 | } | |
855 | s5p_mfc_write_shm(ctx, shm, EXT_ENC_CONTROL); | |
856 | return 0; | |
857 | } | |
858 | ||
859 | static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx) | |
860 | { | |
861 | struct s5p_mfc_dev *dev = ctx->dev; | |
862 | struct s5p_mfc_enc_params *p = &ctx->enc_params; | |
863 | struct s5p_mfc_mpeg4_enc_params *p_mpeg4 = &p->codec.mpeg4; | |
864 | unsigned int reg; | |
865 | unsigned int shm; | |
866 | unsigned int framerate; | |
867 | ||
868 | s5p_mfc_set_enc_params(ctx); | |
869 | /* pictype : number of B */ | |
870 | reg = mfc_read(dev, S5P_FIMV_ENC_PIC_TYPE_CTRL); | |
871 | /* num_b_frame - 0 ~ 2 */ | |
872 | reg &= ~(0x3 << 16); | |
873 | reg |= (p->num_b_frame << 16); | |
874 | mfc_write(dev, reg, S5P_FIMV_ENC_PIC_TYPE_CTRL); | |
875 | /* profile & level */ | |
876 | reg = mfc_read(dev, S5P_FIMV_ENC_PROFILE); | |
877 | /* level */ | |
878 | reg &= ~(0xFF << 8); | |
879 | reg |= (p_mpeg4->level << 8); | |
880 | /* profile - 0 ~ 2 */ | |
881 | reg &= ~(0x3F); | |
882 | reg |= p_mpeg4->profile; | |
883 | mfc_write(dev, reg, S5P_FIMV_ENC_PROFILE); | |
884 | /* quarter_pixel */ | |
885 | mfc_write(dev, p_mpeg4->quarter_pixel, S5P_FIMV_ENC_MPEG4_QUART_PXL); | |
886 | /* qp */ | |
887 | if (!p->rc_frame) { | |
888 | shm = s5p_mfc_read_shm(ctx, P_B_FRAME_QP); | |
889 | shm &= ~(0xFFF); | |
890 | shm |= ((p_mpeg4->rc_b_frame_qp & 0x3F) << 6); | |
891 | shm |= (p_mpeg4->rc_p_frame_qp & 0x3F); | |
892 | s5p_mfc_write_shm(ctx, shm, P_B_FRAME_QP); | |
893 | } | |
894 | /* frame rate */ | |
895 | if (p->rc_frame) { | |
896 | if (p->rc_framerate_denom > 0) { | |
897 | framerate = p->rc_framerate_num * 1000 / | |
898 | p->rc_framerate_denom; | |
899 | mfc_write(dev, framerate, | |
900 | S5P_FIMV_ENC_RC_FRAME_RATE); | |
901 | shm = s5p_mfc_read_shm(ctx, RC_VOP_TIMING); | |
902 | shm &= ~(0xFFFFFFFF); | |
903 | shm |= (1 << 31); | |
904 | shm |= ((p->rc_framerate_num & 0x7FFF) << 16); | |
905 | shm |= (p->rc_framerate_denom & 0xFFFF); | |
906 | s5p_mfc_write_shm(ctx, shm, RC_VOP_TIMING); | |
907 | } | |
908 | } else { | |
909 | mfc_write(dev, 0, S5P_FIMV_ENC_RC_FRAME_RATE); | |
910 | } | |
911 | /* rate control config. */ | |
912 | reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG); | |
913 | /* frame QP */ | |
914 | reg &= ~(0x3F); | |
915 | reg |= p_mpeg4->rc_frame_qp; | |
916 | mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG); | |
917 | /* max & min value of QP */ | |
918 | reg = mfc_read(dev, S5P_FIMV_ENC_RC_QBOUND); | |
919 | /* max QP */ | |
920 | reg &= ~(0x3F << 8); | |
921 | reg |= (p_mpeg4->rc_max_qp << 8); | |
922 | /* min QP */ | |
923 | reg &= ~(0x3F); | |
924 | reg |= p_mpeg4->rc_min_qp; | |
925 | mfc_write(dev, reg, S5P_FIMV_ENC_RC_QBOUND); | |
926 | /* extended encoder ctrl */ | |
927 | shm = s5p_mfc_read_shm(ctx, EXT_ENC_CONTROL); | |
928 | /* vbv buffer size */ | |
929 | if (p->frame_skip_mode == | |
930 | V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { | |
931 | shm &= ~(0xFFFF << 16); | |
932 | shm |= (p->vbv_size << 16); | |
933 | } | |
934 | s5p_mfc_write_shm(ctx, shm, EXT_ENC_CONTROL); | |
935 | return 0; | |
936 | } | |
937 | ||
938 | static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx) | |
939 | { | |
940 | struct s5p_mfc_dev *dev = ctx->dev; | |
941 | struct s5p_mfc_enc_params *p = &ctx->enc_params; | |
942 | struct s5p_mfc_mpeg4_enc_params *p_h263 = &p->codec.mpeg4; | |
943 | unsigned int reg; | |
944 | unsigned int shm; | |
945 | ||
946 | s5p_mfc_set_enc_params(ctx); | |
947 | /* qp */ | |
948 | if (!p->rc_frame) { | |
949 | shm = s5p_mfc_read_shm(ctx, P_B_FRAME_QP); | |
950 | shm &= ~(0xFFF); | |
951 | shm |= (p_h263->rc_p_frame_qp & 0x3F); | |
952 | s5p_mfc_write_shm(ctx, shm, P_B_FRAME_QP); | |
953 | } | |
954 | /* frame rate */ | |
955 | if (p->rc_frame && p->rc_framerate_denom) | |
956 | mfc_write(dev, p->rc_framerate_num * 1000 | |
957 | / p->rc_framerate_denom, S5P_FIMV_ENC_RC_FRAME_RATE); | |
958 | else | |
959 | mfc_write(dev, 0, S5P_FIMV_ENC_RC_FRAME_RATE); | |
960 | /* rate control config. */ | |
961 | reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG); | |
962 | /* frame QP */ | |
963 | reg &= ~(0x3F); | |
964 | reg |= p_h263->rc_frame_qp; | |
965 | mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG); | |
966 | /* max & min value of QP */ | |
967 | reg = mfc_read(dev, S5P_FIMV_ENC_RC_QBOUND); | |
968 | /* max QP */ | |
969 | reg &= ~(0x3F << 8); | |
970 | reg |= (p_h263->rc_max_qp << 8); | |
971 | /* min QP */ | |
972 | reg &= ~(0x3F); | |
973 | reg |= p_h263->rc_min_qp; | |
974 | mfc_write(dev, reg, S5P_FIMV_ENC_RC_QBOUND); | |
975 | /* extended encoder ctrl */ | |
976 | shm = s5p_mfc_read_shm(ctx, EXT_ENC_CONTROL); | |
977 | /* vbv buffer size */ | |
978 | if (p->frame_skip_mode == | |
979 | V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { | |
980 | shm &= ~(0xFFFF << 16); | |
981 | shm |= (p->vbv_size << 16); | |
982 | } | |
983 | s5p_mfc_write_shm(ctx, shm, EXT_ENC_CONTROL); | |
984 | return 0; | |
985 | } | |
986 | ||
987 | /* Initialize decoding */ | |
988 | int s5p_mfc_init_decode(struct s5p_mfc_ctx *ctx) | |
989 | { | |
990 | struct s5p_mfc_dev *dev = ctx->dev; | |
991 | ||
992 | s5p_mfc_set_shared_buffer(ctx); | |
993 | /* Setup loop filter, for decoding this is only valid for MPEG4 */ | |
994 | if (ctx->codec_mode == S5P_FIMV_CODEC_MPEG4_DEC) | |
995 | mfc_write(dev, ctx->loop_filter_mpeg4, S5P_FIMV_ENC_LF_CTRL); | |
996 | else | |
997 | mfc_write(dev, 0, S5P_FIMV_ENC_LF_CTRL); | |
998 | mfc_write(dev, ((ctx->slice_interface & S5P_FIMV_SLICE_INT_MASK) << | |
999 | S5P_FIMV_SLICE_INT_SHIFT) | (ctx->display_delay_enable << | |
1000 | S5P_FIMV_DDELAY_ENA_SHIFT) | ((ctx->display_delay & | |
1001 | S5P_FIMV_DDELAY_VAL_MASK) << S5P_FIMV_DDELAY_VAL_SHIFT), | |
1002 | S5P_FIMV_SI_CH0_DPB_CONF_CTRL); | |
1003 | mfc_write(dev, | |
1004 | ((S5P_FIMV_CH_SEQ_HEADER & S5P_FIMV_CH_MASK) << S5P_FIMV_CH_SHIFT) | |
1005 | | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID); | |
1006 | return 0; | |
1007 | } | |
1008 | ||
1009 | static void s5p_mfc_set_flush(struct s5p_mfc_ctx *ctx, int flush) | |
1010 | { | |
1011 | struct s5p_mfc_dev *dev = ctx->dev; | |
1012 | unsigned int dpb; | |
1013 | ||
1014 | if (flush) | |
1015 | dpb = mfc_read(dev, S5P_FIMV_SI_CH0_DPB_CONF_CTRL) | ( | |
1016 | S5P_FIMV_DPB_FLUSH_MASK << S5P_FIMV_DPB_FLUSH_SHIFT); | |
1017 | else | |
1018 | dpb = mfc_read(dev, S5P_FIMV_SI_CH0_DPB_CONF_CTRL) & | |
1019 | ~(S5P_FIMV_DPB_FLUSH_MASK << S5P_FIMV_DPB_FLUSH_SHIFT); | |
1020 | mfc_write(dev, dpb, S5P_FIMV_SI_CH0_DPB_CONF_CTRL); | |
1021 | } | |
1022 | ||
1023 | /* Decode a single frame */ | |
1024 | int s5p_mfc_decode_one_frame(struct s5p_mfc_ctx *ctx, | |
1025 | enum s5p_mfc_decode_arg last_frame) | |
1026 | { | |
1027 | struct s5p_mfc_dev *dev = ctx->dev; | |
1028 | ||
1029 | mfc_write(dev, ctx->dec_dst_flag, S5P_FIMV_SI_CH0_RELEASE_BUF); | |
1030 | s5p_mfc_set_shared_buffer(ctx); | |
1031 | s5p_mfc_set_flush(ctx, ctx->dpb_flush_flag); | |
1032 | /* Issue different commands to instance basing on whether it | |
1033 | * is the last frame or not. */ | |
1034 | switch (last_frame) { | |
1035 | case MFC_DEC_FRAME: | |
1036 | mfc_write(dev, ((S5P_FIMV_CH_FRAME_START & S5P_FIMV_CH_MASK) << | |
1037 | S5P_FIMV_CH_SHIFT) | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID); | |
1038 | break; | |
1039 | case MFC_DEC_LAST_FRAME: | |
1040 | mfc_write(dev, ((S5P_FIMV_CH_LAST_FRAME & S5P_FIMV_CH_MASK) << | |
1041 | S5P_FIMV_CH_SHIFT) | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID); | |
1042 | break; | |
1043 | case MFC_DEC_RES_CHANGE: | |
1044 | mfc_write(dev, ((S5P_FIMV_CH_FRAME_START_REALLOC & | |
1045 | S5P_FIMV_CH_MASK) << S5P_FIMV_CH_SHIFT) | (ctx->inst_no), | |
1046 | S5P_FIMV_SI_CH0_INST_ID); | |
1047 | break; | |
1048 | } | |
1049 | mfc_debug(2, "Decoding a usual frame\n"); | |
1050 | return 0; | |
1051 | } | |
1052 | ||
1053 | int s5p_mfc_init_encode(struct s5p_mfc_ctx *ctx) | |
1054 | { | |
1055 | struct s5p_mfc_dev *dev = ctx->dev; | |
1056 | ||
1057 | if (ctx->codec_mode == S5P_FIMV_CODEC_H264_ENC) | |
1058 | s5p_mfc_set_enc_params_h264(ctx); | |
1059 | else if (ctx->codec_mode == S5P_FIMV_CODEC_MPEG4_ENC) | |
1060 | s5p_mfc_set_enc_params_mpeg4(ctx); | |
1061 | else if (ctx->codec_mode == S5P_FIMV_CODEC_H263_ENC) | |
1062 | s5p_mfc_set_enc_params_h263(ctx); | |
1063 | else { | |
1064 | mfc_err("Unknown codec for encoding (%x)\n", | |
1065 | ctx->codec_mode); | |
1066 | return -EINVAL; | |
1067 | } | |
1068 | s5p_mfc_set_shared_buffer(ctx); | |
1069 | mfc_write(dev, ((S5P_FIMV_CH_SEQ_HEADER << 16) & 0x70000) | | |
1070 | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID); | |
1071 | return 0; | |
1072 | } | |
1073 | ||
1074 | /* Encode a single frame */ | |
1075 | int s5p_mfc_encode_one_frame(struct s5p_mfc_ctx *ctx) | |
1076 | { | |
1077 | struct s5p_mfc_dev *dev = ctx->dev; | |
1078 | /* memory structure cur. frame */ | |
1079 | if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) | |
1080 | mfc_write(dev, 0, S5P_FIMV_ENC_MAP_FOR_CUR); | |
1081 | else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT) | |
1082 | mfc_write(dev, 3, S5P_FIMV_ENC_MAP_FOR_CUR); | |
1083 | s5p_mfc_set_shared_buffer(ctx); | |
1084 | mfc_write(dev, (S5P_FIMV_CH_FRAME_START << 16 & 0x70000) | | |
1085 | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID); | |
1086 | return 0; | |
1087 | } | |
1088 | ||
1089 | static int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev) | |
1090 | { | |
1091 | unsigned long flags; | |
1092 | int new_ctx; | |
1093 | int cnt; | |
1094 | ||
1095 | spin_lock_irqsave(&dev->condlock, flags); | |
1096 | new_ctx = (dev->curr_ctx + 1) % MFC_NUM_CONTEXTS; | |
1097 | cnt = 0; | |
1098 | while (!test_bit(new_ctx, &dev->ctx_work_bits)) { | |
1099 | new_ctx = (new_ctx + 1) % MFC_NUM_CONTEXTS; | |
1100 | if (++cnt > MFC_NUM_CONTEXTS) { | |
1101 | /* No contexts to run */ | |
1102 | spin_unlock_irqrestore(&dev->condlock, flags); | |
1103 | return -EAGAIN; | |
1104 | } | |
1105 | } | |
1106 | spin_unlock_irqrestore(&dev->condlock, flags); | |
1107 | return new_ctx; | |
1108 | } | |
1109 | ||
1110 | static void s5p_mfc_run_res_change(struct s5p_mfc_ctx *ctx) | |
1111 | { | |
1112 | struct s5p_mfc_dev *dev = ctx->dev; | |
1113 | ||
1114 | s5p_mfc_set_dec_stream_buffer(ctx, 0, 0, 0); | |
1115 | dev->curr_ctx = ctx->num; | |
1116 | s5p_mfc_clean_ctx_int_flags(ctx); | |
1117 | s5p_mfc_decode_one_frame(ctx, MFC_DEC_RES_CHANGE); | |
1118 | } | |
1119 | ||
1120 | static int s5p_mfc_run_dec_frame(struct s5p_mfc_ctx *ctx, int last_frame) | |
1121 | { | |
1122 | struct s5p_mfc_dev *dev = ctx->dev; | |
1123 | struct s5p_mfc_buf *temp_vb; | |
1124 | unsigned long flags; | |
1125 | unsigned int index; | |
1126 | ||
1127 | spin_lock_irqsave(&dev->irqlock, flags); | |
1128 | /* Frames are being decoded */ | |
1129 | if (list_empty(&ctx->src_queue)) { | |
1130 | mfc_debug(2, "No src buffers\n"); | |
1131 | spin_unlock_irqrestore(&dev->irqlock, flags); | |
1132 | return -EAGAIN; | |
1133 | } | |
1134 | /* Get the next source buffer */ | |
1135 | temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); | |
1136 | temp_vb->used = 1; | |
1137 | s5p_mfc_set_dec_stream_buffer(ctx, | |
ba7fcb0c | 1138 | vb2_dma_contig_plane_dma_addr(temp_vb->b, 0), ctx->consumed_stream, |
af935746 KD |
1139 | temp_vb->b->v4l2_planes[0].bytesused); |
1140 | spin_unlock_irqrestore(&dev->irqlock, flags); | |
1141 | index = temp_vb->b->v4l2_buf.index; | |
1142 | dev->curr_ctx = ctx->num; | |
1143 | s5p_mfc_clean_ctx_int_flags(ctx); | |
1144 | if (temp_vb->b->v4l2_planes[0].bytesused == 0) { | |
1145 | last_frame = MFC_DEC_LAST_FRAME; | |
1146 | mfc_debug(2, "Setting ctx->state to FINISHING\n"); | |
1147 | ctx->state = MFCINST_FINISHING; | |
1148 | } | |
1149 | s5p_mfc_decode_one_frame(ctx, last_frame); | |
1150 | return 0; | |
1151 | } | |
1152 | ||
1153 | static int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx) | |
1154 | { | |
1155 | struct s5p_mfc_dev *dev = ctx->dev; | |
1156 | unsigned long flags; | |
1157 | struct s5p_mfc_buf *dst_mb; | |
1158 | struct s5p_mfc_buf *src_mb; | |
1159 | unsigned long src_y_addr, src_c_addr, dst_addr; | |
1160 | unsigned int dst_size; | |
1161 | ||
1162 | spin_lock_irqsave(&dev->irqlock, flags); | |
1163 | if (list_empty(&ctx->src_queue)) { | |
1164 | mfc_debug(2, "no src buffers\n"); | |
1165 | spin_unlock_irqrestore(&dev->irqlock, flags); | |
1166 | return -EAGAIN; | |
1167 | } | |
1168 | if (list_empty(&ctx->dst_queue)) { | |
1169 | mfc_debug(2, "no dst buffers\n"); | |
1170 | spin_unlock_irqrestore(&dev->irqlock, flags); | |
1171 | return -EAGAIN; | |
1172 | } | |
1173 | src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); | |
1174 | src_mb->used = 1; | |
ba7fcb0c MS |
1175 | src_y_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 0); |
1176 | src_c_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 1); | |
af935746 KD |
1177 | s5p_mfc_set_enc_frame_buffer(ctx, src_y_addr, src_c_addr); |
1178 | dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list); | |
1179 | dst_mb->used = 1; | |
ba7fcb0c | 1180 | dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0); |
af935746 KD |
1181 | dst_size = vb2_plane_size(dst_mb->b, 0); |
1182 | s5p_mfc_set_enc_stream_buffer(ctx, dst_addr, dst_size); | |
1183 | spin_unlock_irqrestore(&dev->irqlock, flags); | |
1184 | dev->curr_ctx = ctx->num; | |
1185 | s5p_mfc_clean_ctx_int_flags(ctx); | |
1186 | s5p_mfc_encode_one_frame(ctx); | |
1187 | return 0; | |
1188 | } | |
1189 | ||
1190 | static void s5p_mfc_run_init_dec(struct s5p_mfc_ctx *ctx) | |
1191 | { | |
1192 | struct s5p_mfc_dev *dev = ctx->dev; | |
1193 | unsigned long flags; | |
1194 | struct s5p_mfc_buf *temp_vb; | |
1195 | ||
1196 | /* Initializing decoding - parsing header */ | |
1197 | spin_lock_irqsave(&dev->irqlock, flags); | |
1198 | mfc_debug(2, "Preparing to init decoding\n"); | |
1199 | temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); | |
1200 | s5p_mfc_set_dec_desc_buffer(ctx); | |
1201 | mfc_debug(2, "Header size: %d\n", temp_vb->b->v4l2_planes[0].bytesused); | |
1202 | s5p_mfc_set_dec_stream_buffer(ctx, | |
ba7fcb0c | 1203 | vb2_dma_contig_plane_dma_addr(temp_vb->b, 0), |
af935746 KD |
1204 | 0, temp_vb->b->v4l2_planes[0].bytesused); |
1205 | spin_unlock_irqrestore(&dev->irqlock, flags); | |
1206 | dev->curr_ctx = ctx->num; | |
1207 | s5p_mfc_clean_ctx_int_flags(ctx); | |
1208 | s5p_mfc_init_decode(ctx); | |
1209 | } | |
1210 | ||
1211 | static void s5p_mfc_run_init_enc(struct s5p_mfc_ctx *ctx) | |
1212 | { | |
1213 | struct s5p_mfc_dev *dev = ctx->dev; | |
1214 | unsigned long flags; | |
1215 | struct s5p_mfc_buf *dst_mb; | |
1216 | unsigned long dst_addr; | |
1217 | unsigned int dst_size; | |
1218 | ||
1219 | s5p_mfc_set_enc_ref_buffer(ctx); | |
1220 | spin_lock_irqsave(&dev->irqlock, flags); | |
1221 | dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list); | |
ba7fcb0c | 1222 | dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0); |
af935746 KD |
1223 | dst_size = vb2_plane_size(dst_mb->b, 0); |
1224 | s5p_mfc_set_enc_stream_buffer(ctx, dst_addr, dst_size); | |
1225 | spin_unlock_irqrestore(&dev->irqlock, flags); | |
1226 | dev->curr_ctx = ctx->num; | |
1227 | s5p_mfc_clean_ctx_int_flags(ctx); | |
1228 | s5p_mfc_init_encode(ctx); | |
1229 | } | |
1230 | ||
1231 | static int s5p_mfc_run_init_dec_buffers(struct s5p_mfc_ctx *ctx) | |
1232 | { | |
1233 | struct s5p_mfc_dev *dev = ctx->dev; | |
1234 | unsigned long flags; | |
1235 | struct s5p_mfc_buf *temp_vb; | |
1236 | int ret; | |
1237 | ||
1238 | /* | |
1239 | * Header was parsed now starting processing | |
1240 | * First set the output frame buffers | |
1241 | */ | |
1242 | if (ctx->capture_state != QUEUE_BUFS_MMAPED) { | |
1243 | mfc_err("It seems that not all destionation buffers were " | |
1244 | "mmaped\nMFC requires that all destination are mmaped " | |
1245 | "before starting processing\n"); | |
1246 | return -EAGAIN; | |
1247 | } | |
1248 | spin_lock_irqsave(&dev->irqlock, flags); | |
1249 | if (list_empty(&ctx->src_queue)) { | |
1250 | mfc_err("Header has been deallocated in the middle of" | |
1251 | " initialization\n"); | |
1252 | spin_unlock_irqrestore(&dev->irqlock, flags); | |
1253 | return -EIO; | |
1254 | } | |
1255 | temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); | |
1256 | mfc_debug(2, "Header size: %d\n", temp_vb->b->v4l2_planes[0].bytesused); | |
1257 | s5p_mfc_set_dec_stream_buffer(ctx, | |
ba7fcb0c | 1258 | vb2_dma_contig_plane_dma_addr(temp_vb->b, 0), |
af935746 KD |
1259 | 0, temp_vb->b->v4l2_planes[0].bytesused); |
1260 | spin_unlock_irqrestore(&dev->irqlock, flags); | |
1261 | dev->curr_ctx = ctx->num; | |
1262 | s5p_mfc_clean_ctx_int_flags(ctx); | |
1263 | ret = s5p_mfc_set_dec_frame_buffer(ctx); | |
1264 | if (ret) { | |
1265 | mfc_err("Failed to alloc frame mem\n"); | |
1266 | ctx->state = MFCINST_ERROR; | |
1267 | } | |
1268 | return ret; | |
1269 | } | |
1270 | ||
1271 | /* Try running an operation on hardware */ | |
1272 | void s5p_mfc_try_run(struct s5p_mfc_dev *dev) | |
1273 | { | |
1274 | struct s5p_mfc_ctx *ctx; | |
1275 | int new_ctx; | |
1276 | unsigned int ret = 0; | |
1277 | ||
1278 | if (test_bit(0, &dev->enter_suspend)) { | |
1279 | mfc_debug(1, "Entering suspend so do not schedule any jobs\n"); | |
1280 | return; | |
1281 | } | |
1282 | /* Check whether hardware is not running */ | |
1283 | if (test_and_set_bit(0, &dev->hw_lock) != 0) { | |
1284 | /* This is perfectly ok, the scheduled ctx should wait */ | |
1285 | mfc_debug(1, "Couldn't lock HW\n"); | |
1286 | return; | |
1287 | } | |
1288 | /* Choose the context to run */ | |
1289 | new_ctx = s5p_mfc_get_new_ctx(dev); | |
1290 | if (new_ctx < 0) { | |
1291 | /* No contexts to run */ | |
1292 | if (test_and_clear_bit(0, &dev->hw_lock) == 0) { | |
1293 | mfc_err("Failed to unlock hardware\n"); | |
1294 | return; | |
1295 | } | |
1296 | mfc_debug(1, "No ctx is scheduled to be run\n"); | |
1297 | return; | |
1298 | } | |
1299 | ctx = dev->ctx[new_ctx]; | |
1300 | /* Got context to run in ctx */ | |
1301 | /* | |
1302 | * Last frame has already been sent to MFC. | |
1303 | * Now obtaining frames from MFC buffer | |
1304 | */ | |
1305 | s5p_mfc_clock_on(); | |
1306 | if (ctx->type == MFCINST_DECODER) { | |
1307 | s5p_mfc_set_dec_desc_buffer(ctx); | |
1308 | switch (ctx->state) { | |
1309 | case MFCINST_FINISHING: | |
1310 | s5p_mfc_run_dec_frame(ctx, MFC_DEC_LAST_FRAME); | |
1311 | break; | |
1312 | case MFCINST_RUNNING: | |
1313 | ret = s5p_mfc_run_dec_frame(ctx, MFC_DEC_FRAME); | |
1314 | break; | |
1315 | case MFCINST_INIT: | |
1316 | s5p_mfc_clean_ctx_int_flags(ctx); | |
1317 | ret = s5p_mfc_open_inst_cmd(ctx); | |
1318 | break; | |
1319 | case MFCINST_RETURN_INST: | |
1320 | s5p_mfc_clean_ctx_int_flags(ctx); | |
1321 | ret = s5p_mfc_close_inst_cmd(ctx); | |
1322 | break; | |
1323 | case MFCINST_GOT_INST: | |
1324 | s5p_mfc_run_init_dec(ctx); | |
1325 | break; | |
1326 | case MFCINST_HEAD_PARSED: | |
1327 | ret = s5p_mfc_run_init_dec_buffers(ctx); | |
1328 | mfc_debug(1, "head parsed\n"); | |
1329 | break; | |
1330 | case MFCINST_RES_CHANGE_INIT: | |
1331 | s5p_mfc_run_res_change(ctx); | |
1332 | break; | |
1333 | case MFCINST_RES_CHANGE_FLUSH: | |
1334 | s5p_mfc_run_dec_frame(ctx, MFC_DEC_FRAME); | |
1335 | break; | |
1336 | case MFCINST_RES_CHANGE_END: | |
1337 | mfc_debug(2, "Finished remaining frames after resolution change\n"); | |
1338 | ctx->capture_state = QUEUE_FREE; | |
1339 | mfc_debug(2, "Will re-init the codec\n"); | |
1340 | s5p_mfc_run_init_dec(ctx); | |
1341 | break; | |
1342 | default: | |
1343 | ret = -EAGAIN; | |
1344 | } | |
1345 | } else if (ctx->type == MFCINST_ENCODER) { | |
1346 | switch (ctx->state) { | |
1347 | case MFCINST_FINISHING: | |
1348 | case MFCINST_RUNNING: | |
1349 | ret = s5p_mfc_run_enc_frame(ctx); | |
1350 | break; | |
1351 | case MFCINST_INIT: | |
1352 | s5p_mfc_clean_ctx_int_flags(ctx); | |
1353 | ret = s5p_mfc_open_inst_cmd(ctx); | |
1354 | break; | |
1355 | case MFCINST_RETURN_INST: | |
1356 | s5p_mfc_clean_ctx_int_flags(ctx); | |
1357 | ret = s5p_mfc_close_inst_cmd(ctx); | |
1358 | break; | |
1359 | case MFCINST_GOT_INST: | |
1360 | s5p_mfc_run_init_enc(ctx); | |
1361 | break; | |
1362 | default: | |
1363 | ret = -EAGAIN; | |
1364 | } | |
1365 | } else { | |
1366 | mfc_err("Invalid context type: %d\n", ctx->type); | |
1367 | ret = -EAGAIN; | |
1368 | } | |
1369 | ||
1370 | if (ret) { | |
1371 | /* Free hardware lock */ | |
1372 | if (test_and_clear_bit(0, &dev->hw_lock) == 0) | |
1373 | mfc_err("Failed to unlock hardware\n"); | |
1374 | ||
1375 | /* This is in deed imporant, as no operation has been | |
1376 | * scheduled, reduce the clock count as no one will | |
1377 | * ever do this, because no interrupt related to this try_run | |
1378 | * will ever come from hardware. */ | |
1379 | s5p_mfc_clock_off(); | |
1380 | } | |
1381 | } | |
1382 | ||
1383 | ||
1384 | void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq) | |
1385 | { | |
1386 | struct s5p_mfc_buf *b; | |
1387 | int i; | |
1388 | ||
1389 | while (!list_empty(lh)) { | |
1390 | b = list_entry(lh->next, struct s5p_mfc_buf, list); | |
1391 | for (i = 0; i < b->b->num_planes; i++) | |
1392 | vb2_set_plane_payload(b->b, i, 0); | |
1393 | vb2_buffer_done(b->b, VB2_BUF_STATE_ERROR); | |
1394 | list_del(&b->list); | |
1395 | } | |
1396 | } | |
1397 |