[deliverable/linux.git] / drivers / media / video / saa7191.c

/*
 *  saa7191.c - Philips SAA7191 video decoder driver
 *
 *  Copyright (C) 2003 Ladislav Michl <ladis@linux-mips.org>
 *  Copyright (C) 2004,2005 Mikael Nousiainen <tmnousia@cc.hut.fi>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  published by the Free Software Foundation.
 */

#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/major.h>
#include <linux/module.h>
#include <linux/mm.h>
#include <linux/slab.h>

#include <linux/videodev2.h>
#include <linux/i2c.h>
#include <media/v4l2-device.h>
#include <media/v4l2-chip-ident.h>

#include "saa7191.h"

#define SAA7191_MODULE_VERSION	"0.0.5"

MODULE_DESCRIPTION("Philips SAA7191 video decoder driver");
MODULE_VERSION(SAA7191_MODULE_VERSION);
MODULE_AUTHOR("Mikael Nousiainen <tmnousia@cc.hut.fi>");
MODULE_LICENSE("GPL");


// #define SAA7191_DEBUG

#ifdef SAA7191_DEBUG
#define dprintk(x...) printk("SAA7191: " x);
#else
#define dprintk(x...)
#endif

#define SAA7191_SYNC_COUNT	30
#define SAA7191_SYNC_DELAY	100	/* milliseconds */

struct saa7191 {
	struct v4l2_subdev sd;

	/* the register values are stored here as the actual
	 * I2C-registers are write-only */
	u8 reg[25];

	int input;
	v4l2_std_id norm;
};

static inline struct saa7191 *to_saa7191(struct v4l2_subdev *sd)
{
	return container_of(sd, struct saa7191, sd);
}

static const u8 initseq[] = {
	0,	/* Subaddress */

	0x50,	/* (0x50) SAA7191_REG_IDEL */

	/* 50 Hz signal timing */
	0x30,	/* (0x30) SAA7191_REG_HSYB */
	0x00,	/* (0x00) SAA7191_REG_HSYS */
	0xe8,	/* (0xe8) SAA7191_REG_HCLB */
	0xb6,	/* (0xb6) SAA7191_REG_HCLS */
	0xf4,	/* (0xf4) SAA7191_REG_HPHI */

	/* control */
	SAA7191_LUMA_APER_1,	/* (0x01) SAA7191_REG_LUMA - CVBS mode */
	0x00,	/* (0x00) SAA7191_REG_HUEC */
	0xf8,	/* (0xf8) SAA7191_REG_CKTQ */
	0xf8,	/* (0xf8) SAA7191_REG_CKTS */
	0x90,	/* (0x90) SAA7191_REG_PLSE */
	0x90,	/* (0x90) SAA7191_REG_SESE */
	0x00,	/* (0x00) SAA7191_REG_GAIN */
	SAA7191_STDC_NFEN | SAA7191_STDC_HRMV,	/* (0x0c) SAA7191_REG_STDC
						 * - not SECAM,
						 * slow time constant */
	SAA7191_IOCK_OEDC | SAA7191_IOCK_OEHS | SAA7191_IOCK_OEVS
	| SAA7191_IOCK_OEDY,	/* (0x78) SAA7191_REG_IOCK
				 * - chroma from CVBS, GPSW1 & 2 off */
	SAA7191_CTL3_AUFD | SAA7191_CTL3_SCEN | SAA7191_CTL3_OFTS
	| SAA7191_CTL3_YDEL0,	/* (0x99) SAA7191_REG_CTL3
				 * - automatic field detection */
	0x00,	/* (0x00) SAA7191_REG_CTL4 */
	0x2c,	/* (0x2c) SAA7191_REG_CHCV - PAL nominal value */
	0x00,	/* unused */
	0x00,	/* unused */

	/* 60 Hz signal timing */
	0x34,	/* (0x34) SAA7191_REG_HS6B */
	0x0a,	/* (0x0a) SAA7191_REG_HS6S */
	0xf4,	/* (0xf4) SAA7191_REG_HC6B */
	0xce,	/* (0xce) SAA7191_REG_HC6S */
	0xf4,	/* (0xf4) SAA7191_REG_HP6I */
};

/* SAA7191 register handling */

static u8 saa7191_read_reg(struct v4l2_subdev *sd, u8 reg)
{
	return to_saa7191(sd)->reg[reg];
}

static int saa7191_read_status(struct v4l2_subdev *sd, u8 *value)
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);
	int ret;

	ret = i2c_master_recv(client, value, 1);
	if (ret < 0) {
		printk(KERN_ERR "SAA7191: saa7191_read_status(): read failed\n");
		return ret;
	}

	return 0;
}


static int saa7191_write_reg(struct v4l2_subdev *sd, u8 reg, u8 value)
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);

	to_saa7191(sd)->reg[reg] = value;
	return i2c_smbus_write_byte_data(client, reg, value);
}

/* the first byte of data must be the first subaddress number (register) */
static int saa7191_write_block(struct v4l2_subdev *sd,
			       u8 length, const u8 *data)
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);
	struct saa7191 *decoder = to_saa7191(sd);
	int i;
	int ret;

	for (i = 0; i < (length - 1); i++) {
		decoder->reg[data[0] + i] = data[i + 1];
	}

	ret = i2c_master_send(client, data, length);
	if (ret < 0) {
		printk(KERN_ERR "SAA7191: saa7191_write_block(): "
		       "write failed\n");
		return ret;
	}

	return 0;
}

/* Helper functions */

static int saa7191_s_routing(struct v4l2_subdev *sd,
			     u32 input, u32 output, u32 config)
{
	struct saa7191 *decoder = to_saa7191(sd);
	u8 luma = saa7191_read_reg(sd, SAA7191_REG_LUMA);
	u8 iock = saa7191_read_reg(sd, SAA7191_REG_IOCK);
	int err;

	switch (input) {
	case SAA7191_INPUT_COMPOSITE: /* Set Composite input */
		iock &= ~(SAA7191_IOCK_CHRS | SAA7191_IOCK_GPSW1
			  | SAA7191_IOCK_GPSW2);
		/* Chrominance trap active */
		luma &= ~SAA7191_LUMA_BYPS;
		break;
	case SAA7191_INPUT_SVIDEO: /* Set S-Video input */
		iock |= SAA7191_IOCK_CHRS | SAA7191_IOCK_GPSW2;
		/* Chrominance trap bypassed */
		luma |= SAA7191_LUMA_BYPS;
		break;
	default:
		return -EINVAL;
	}

	err = saa7191_write_reg(sd, SAA7191_REG_LUMA, luma);
	if (err)
		return -EIO;
	err = saa7191_write_reg(sd, SAA7191_REG_IOCK, iock);
	if (err)
		return -EIO;

	decoder->input = input;

	return 0;
}

static int saa7191_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
{
	struct saa7191 *decoder = to_saa7191(sd);
	u8 stdc = saa7191_read_reg(sd, SAA7191_REG_STDC);
	u8 ctl3 = saa7191_read_reg(sd, SAA7191_REG_CTL3);
	u8 chcv = saa7191_read_reg(sd, SAA7191_REG_CHCV);
	int err;

	if (norm & V4L2_STD_PAL) {
		stdc &= ~SAA7191_STDC_SECS;
		ctl3 &= ~(SAA7191_CTL3_AUFD | SAA7191_CTL3_FSEL);
		chcv = SAA7191_CHCV_PAL;
	} else if (norm & V4L2_STD_NTSC) {
		stdc &= ~SAA7191_STDC_SECS;
		ctl3 &= ~SAA7191_CTL3_AUFD;
		ctl3 |= SAA7191_CTL3_FSEL;
		chcv = SAA7191_CHCV_NTSC;
	} else if (norm & V4L2_STD_SECAM) {
		stdc |= SAA7191_STDC_SECS;
		ctl3 &= ~(SAA7191_CTL3_AUFD | SAA7191_CTL3_FSEL);
		chcv = SAA7191_CHCV_PAL;
	} else {
		return -EINVAL;
	}

	err = saa7191_write_reg(sd, SAA7191_REG_CTL3, ctl3);
	if (err)
		return -EIO;
	err = saa7191_write_reg(sd, SAA7191_REG_STDC, stdc);
	if (err)
		return -EIO;
	err = saa7191_write_reg(sd, SAA7191_REG_CHCV, chcv);
	if (err)
		return -EIO;

	decoder->norm = norm;

	dprintk("ctl3: %02x stdc: %02x chcv: %02x\n", ctl3,
		stdc, chcv);
	dprintk("norm: %llx\n", norm);

	return 0;
}

static int saa7191_wait_for_signal(struct v4l2_subdev *sd, u8 *status)
{
	int i = 0;

	dprintk("Checking for signal...\n");

	for (i = 0; i < SAA7191_SYNC_COUNT; i++) {
		if (saa7191_read_status(sd, status))
			return -EIO;

		if (((*status) & SAA7191_STATUS_HLCK) == 0) {
			dprintk("Signal found\n");
			return 0;
		}

		msleep(SAA7191_SYNC_DELAY);
	}

	dprintk("No signal\n");

	return -EBUSY;
}

static int saa7191_querystd(struct v4l2_subdev *sd, v4l2_std_id *norm)
{
	struct saa7191 *decoder = to_saa7191(sd);
	u8 stdc = saa7191_read_reg(sd, SAA7191_REG_STDC);
	u8 ctl3 = saa7191_read_reg(sd, SAA7191_REG_CTL3);
	u8 status;
	v4l2_std_id old_norm = decoder->norm;
	int err = 0;

	dprintk("SAA7191 extended signal auto-detection...\n");

	*norm = V4L2_STD_NTSC | V4L2_STD_PAL | V4L2_STD_SECAM;
	stdc &= ~SAA7191_STDC_SECS;
	ctl3 &= ~(SAA7191_CTL3_FSEL);

	err = saa7191_write_reg(sd, SAA7191_REG_STDC, stdc);
	if (err) {
		err = -EIO;
		goto out;
	}
	err = saa7191_write_reg(sd, SAA7191_REG_CTL3, ctl3);
	if (err) {
		err = -EIO;
		goto out;
	}

	ctl3 |= SAA7191_CTL3_AUFD;
	err = saa7191_write_reg(sd, SAA7191_REG_CTL3, ctl3);
	if (err) {
		err = -EIO;
		goto out;
	}

	msleep(SAA7191_SYNC_DELAY);

	err = saa7191_wait_for_signal(sd, &status);
	if (err)
		goto out;

	if (status & SAA7191_STATUS_FIDT) {
		/* 60Hz signal -> NTSC */
		dprintk("60Hz signal: NTSC\n");
		*norm = V4L2_STD_NTSC;
		return 0;
	}

	/* 50Hz signal */
	dprintk("50Hz signal: Trying PAL...\n");

	/* try PAL first */
	err = saa7191_s_std(sd, V4L2_STD_PAL);
	if (err)
		goto out;

	msleep(SAA7191_SYNC_DELAY);

	err = saa7191_wait_for_signal(sd, &status);
	if (err)
		goto out;

	/* not 50Hz ? */
	if (status & SAA7191_STATUS_FIDT) {
		dprintk("No 50Hz signal\n");
		saa7191_s_std(sd, old_norm);
		return -EAGAIN;
	}

	if (status & SAA7191_STATUS_CODE) {
		dprintk("PAL\n");
		*norm = V4L2_STD_PAL;
		return saa7191_s_std(sd, old_norm);
	}

	dprintk("No color detected with PAL - Trying SECAM...\n");

	/* no color detected ? -> try SECAM */
	err = saa7191_s_std(sd, V4L2_STD_SECAM);
	if (err)
		goto out;

	msleep(SAA7191_SYNC_DELAY);

	err = saa7191_wait_for_signal(sd, &status);
	if (err)
		goto out;

	/* not 50Hz ? */
	if (status & SAA7191_STATUS_FIDT) {
		dprintk("No 50Hz signal\n");
		err = -EAGAIN;
		goto out;
	}

	if (status & SAA7191_STATUS_CODE) {
		/* Color detected -> SECAM */
		dprintk("SECAM\n");
		*norm = V4L2_STD_SECAM;
		return saa7191_s_std(sd, old_norm);
	}

	dprintk("No color detected with SECAM - Going back to PAL.\n");

out:
	return saa7191_s_std(sd, old_norm);
}

static int saa7191_autodetect_norm(struct v4l2_subdev *sd)
{
	u8 status;

	dprintk("SAA7191 signal auto-detection...\n");

	dprintk("Reading status...\n");

	if (saa7191_read_status(sd, &status))
		return -EIO;

	dprintk("Checking for signal...\n");

	/* no signal ? */
	if (status & SAA7191_STATUS_HLCK) {
		dprintk("No signal\n");
		return -EBUSY;
	}

	dprintk("Signal found\n");

	if (status & SAA7191_STATUS_FIDT) {
		/* 60hz signal -> NTSC */
		dprintk("NTSC\n");
		return saa7191_s_std(sd, V4L2_STD_NTSC);
	} else {
		/* 50hz signal -> PAL */
		dprintk("PAL\n");
		return saa7191_s_std(sd, V4L2_STD_PAL);
	}
}

static int saa7191_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
{
	u8 reg;
	int ret = 0;

	switch (ctrl->id) {
	case SAA7191_CONTROL_BANDPASS:
	case SAA7191_CONTROL_BANDPASS_WEIGHT:
	case SAA7191_CONTROL_CORING:
		reg = saa7191_read_reg(sd, SAA7191_REG_LUMA);
		switch (ctrl->id) {
		case SAA7191_CONTROL_BANDPASS:
			ctrl->value = ((s32)reg & SAA7191_LUMA_BPSS_MASK)
				>> SAA7191_LUMA_BPSS_SHIFT;
			break;
		case SAA7191_CONTROL_BANDPASS_WEIGHT:
			ctrl->value = ((s32)reg & SAA7191_LUMA_APER_MASK)
				>> SAA7191_LUMA_APER_SHIFT;
			break;
		case SAA7191_CONTROL_CORING:
			ctrl->value = ((s32)reg & SAA7191_LUMA_CORI_MASK)
				>> SAA7191_LUMA_CORI_SHIFT;
			break;
		}
		break;
	case SAA7191_CONTROL_FORCE_COLOUR:
	case SAA7191_CONTROL_CHROMA_GAIN:
		reg = saa7191_read_reg(sd, SAA7191_REG_GAIN);
		if (ctrl->id == SAA7191_CONTROL_FORCE_COLOUR)
			ctrl->value = ((s32)reg & SAA7191_GAIN_COLO) ? 1 : 0;
		else
			ctrl->value = ((s32)reg & SAA7191_GAIN_LFIS_MASK)
				>> SAA7191_GAIN_LFIS_SHIFT;
		break;
	case V4L2_CID_HUE:
		reg = saa7191_read_reg(sd, SAA7191_REG_HUEC);
		if (reg < 0x80)
			reg += 0x80;
		else
			reg -= 0x80;
		ctrl->value = (s32)reg;
		break;
	case SAA7191_CONTROL_VTRC:
		reg = saa7191_read_reg(sd, SAA7191_REG_STDC);
		ctrl->value = ((s32)reg & SAA7191_STDC_VTRC) ? 1 : 0;
		break;
	case SAA7191_CONTROL_LUMA_DELAY:
		reg = saa7191_read_reg(sd, SAA7191_REG_CTL3);
		ctrl->value = ((s32)reg & SAA7191_CTL3_YDEL_MASK)
			>> SAA7191_CTL3_YDEL_SHIFT;
		if (ctrl->value >= 4)
			ctrl->value -= 8;
		break;
	case SAA7191_CONTROL_VNR:
		reg = saa7191_read_reg(sd, SAA7191_REG_CTL4);
		ctrl->value = ((s32)reg & SAA7191_CTL4_VNOI_MASK)
			>> SAA7191_CTL4_VNOI_SHIFT;
		break;
	default:
		ret = -EINVAL;
	}

	return ret;
}

static int saa7191_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
{
	u8 reg;
	int ret = 0;

	switch (ctrl->id) {
	case SAA7191_CONTROL_BANDPASS:
	case SAA7191_CONTROL_BANDPASS_WEIGHT:
	case SAA7191_CONTROL_CORING:
		reg = saa7191_read_reg(sd, SAA7191_REG_LUMA);
		switch (ctrl->id) {
		case SAA7191_CONTROL_BANDPASS:
			reg &= ~SAA7191_LUMA_BPSS_MASK;
			reg |= (ctrl->value << SAA7191_LUMA_BPSS_SHIFT)
				& SAA7191_LUMA_BPSS_MASK;
			break;
		case SAA7191_CONTROL_BANDPASS_WEIGHT:
			reg &= ~SAA7191_LUMA_APER_MASK;
			reg |= (ctrl->value << SAA7191_LUMA_APER_SHIFT)
				& SAA7191_LUMA_APER_MASK;
			break;
		case SAA7191_CONTROL_CORING:
			reg &= ~SAA7191_LUMA_CORI_MASK;
			reg |= (ctrl->value << SAA7191_LUMA_CORI_SHIFT)
				& SAA7191_LUMA_CORI_MASK;
			break;
		}
		ret = saa7191_write_reg(sd, SAA7191_REG_LUMA, reg);
		break;
	case SAA7191_CONTROL_FORCE_COLOUR:
	case SAA7191_CONTROL_CHROMA_GAIN:
		reg = saa7191_read_reg(sd, SAA7191_REG_GAIN);
		if (ctrl->id == SAA7191_CONTROL_FORCE_COLOUR) {
			if (ctrl->value)
				reg |= SAA7191_GAIN_COLO;
			else
				reg &= ~SAA7191_GAIN_COLO;
		} else {
			reg &= ~SAA7191_GAIN_LFIS_MASK;
			reg |= (ctrl->value << SAA7191_GAIN_LFIS_SHIFT)
				& SAA7191_GAIN_LFIS_MASK;
		}
		ret = saa7191_write_reg(sd, SAA7191_REG_GAIN, reg);
		break;
	case V4L2_CID_HUE:
		reg = ctrl->value & 0xff;
		if (reg < 0x80)
			reg += 0x80;
		else
			reg -= 0x80;
		ret = saa7191_write_reg(sd, SAA7191_REG_HUEC, reg);
		break;
	case SAA7191_CONTROL_VTRC:
		reg = saa7191_read_reg(sd, SAA7191_REG_STDC);
		if (ctrl->value)
			reg |= SAA7191_STDC_VTRC;
		else
			reg &= ~SAA7191_STDC_VTRC;
		ret = saa7191_write_reg(sd, SAA7191_REG_STDC, reg);
		break;
	case SAA7191_CONTROL_LUMA_DELAY: {
		s32 value = ctrl->value;
		if (value < 0)
			value += 8;
		reg = saa7191_read_reg(sd, SAA7191_REG_CTL3);
		reg &= ~SAA7191_CTL3_YDEL_MASK;
		reg |= (value << SAA7191_CTL3_YDEL_SHIFT)
			& SAA7191_CTL3_YDEL_MASK;
		ret = saa7191_write_reg(sd, SAA7191_REG_CTL3, reg);
		break;
	}
	case SAA7191_CONTROL_VNR:
		reg = saa7191_read_reg(sd, SAA7191_REG_CTL4);
		reg &= ~SAA7191_CTL4_VNOI_MASK;
		reg |= (ctrl->value << SAA7191_CTL4_VNOI_SHIFT)
			& SAA7191_CTL4_VNOI_MASK;
		ret = saa7191_write_reg(sd, SAA7191_REG_CTL4, reg);
		break;
	default:
		ret = -EINVAL;
	}

	return ret;
}

/* I2C-interface */

static int saa7191_g_input_status(struct v4l2_subdev *sd, u32 *status)
{
	u8 status_reg;
	int res = V4L2_IN_ST_NO_SIGNAL;

	if (saa7191_read_status(sd, &status_reg))
		return -EIO;
	if ((status_reg & SAA7191_STATUS_HLCK) == 0)
		res = 0;
	if (!(status_reg & SAA7191_STATUS_CODE))
		res |= V4L2_IN_ST_NO_COLOR;
	*status = res;
	return 0;
}


static int saa7191_g_chip_ident(struct v4l2_subdev *sd,
		struct v4l2_dbg_chip_ident *chip)
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);

	return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_SAA7191, 0);
}

/* ----------------------------------------------------------------------- */

static const struct v4l2_subdev_core_ops saa7191_core_ops = {
	.g_chip_ident = saa7191_g_chip_ident,
	.g_ctrl = saa7191_g_ctrl,
	.s_ctrl = saa7191_s_ctrl,
	.s_std = saa7191_s_std,
};

static const struct v4l2_subdev_video_ops saa7191_video_ops = {
	.s_routing = saa7191_s_routing,
	.querystd = saa7191_querystd,
	.g_input_status = saa7191_g_input_status,
};

static const struct v4l2_subdev_ops saa7191_ops = {
	.core = &saa7191_core_ops,
	.video = &saa7191_video_ops,
};

static int saa7191_probe(struct i2c_client *client,
			  const struct i2c_device_id *id)
{
	int err = 0;
	struct saa7191 *decoder;
	struct v4l2_subdev *sd;

	v4l_info(client, "chip found @ 0x%x (%s)\n",
			client->addr << 1, client->adapter->name);

	decoder = kzalloc(sizeof(*decoder), GFP_KERNEL);
	if (!decoder)
		return -ENOMEM;

	sd = &decoder->sd;
	v4l2_i2c_subdev_init(sd, client, &saa7191_ops);

	err = saa7191_write_block(sd, sizeof(initseq), initseq);
	if (err) {
		printk(KERN_ERR "SAA7191 initialization failed\n");
		kfree(decoder);
		return err;
	}

	printk(KERN_INFO "SAA7191 initialized\n");

	decoder->input = SAA7191_INPUT_COMPOSITE;
	decoder->norm = V4L2_STD_PAL;

	err = saa7191_autodetect_norm(sd);
	if (err && (err != -EBUSY))
		printk(KERN_ERR "SAA7191: Signal auto-detection failed\n");

	return 0;
}

static int saa7191_remove(struct i2c_client *client)
{
	struct v4l2_subdev *sd = i2c_get_clientdata(client);

	v4l2_device_unregister_subdev(sd);
	kfree(to_saa7191(sd));
	return 0;
}

static const struct i2c_device_id saa7191_id[] = {
	{ "saa7191", 0 },
	{ }
};
MODULE_DEVICE_TABLE(i2c, saa7191_id);

static struct i2c_driver saa7191_driver = {
	.driver = {
		.owner	= THIS_MODULE,
		.name	= "saa7191",
	},
	.probe		= saa7191_probe,
	.remove		= saa7191_remove,
	.id_table	= saa7191_id,
};

module_i2c_driver(saa7191_driver);
Commit	Line	Data
d203a7ec RB	1	/*
	2	* saa7191.c - Philips SAA7191 video decoder driver
	3	*
	4	* Copyright (C) 2003 Ladislav Michl <ladis@linux-mips.org>
	5	* Copyright (C) 2004,2005 Mikael Nousiainen <tmnousia@cc.hut.fi>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
d203a7ec RB	12	#include <linux/delay.h>
	13	#include <linux/errno.h>
	14	#include <linux/fs.h>
495515b3	15	#include <linux/init.h>
d203a7ec RB	16	#include <linux/kernel.h>
d203a7ec RB	17	#include <linux/major.h>
495515b3	18	#include <linux/module.h>
d203a7ec	19	#include <linux/mm.h>
495515b3	20	#include <linux/slab.h>
d203a7ec	21
cf4e9484	22	#include <linux/videodev2.h>
d203a7ec	23	#include <linux/i2c.h>
8340ff43 HV	24	#include <media/v4l2-device.h>
8340ff43 HV	25	#include <media/v4l2-chip-ident.h>
d203a7ec RB	26
	27	#include "saa7191.h"
	28
a637a114	29	#define SAA7191_MODULE_VERSION "0.0.5"
d203a7ec RB	30
	31	MODULE_DESCRIPTION("Philips SAA7191 video decoder driver");
	32	MODULE_VERSION(SAA7191_MODULE_VERSION);
	33	MODULE_AUTHOR("Mikael Nousiainen <tmnousia@cc.hut.fi>");
	34	MODULE_LICENSE("GPL");
	35
babb7dc7	36
a637a114 LM	37	// #define SAA7191_DEBUG
	38
	39	#ifdef SAA7191_DEBUG
	40	#define dprintk(x...) printk("SAA7191: " x);
	41	#else
	42	#define dprintk(x...)
	43	#endif
	44
	45	#define SAA7191_SYNC_COUNT 30
	46	#define SAA7191_SYNC_DELAY 100 /* milliseconds */
	47
d203a7ec	48	struct saa7191 {
8340ff43	49	struct v4l2_subdev sd;
d203a7ec RB	50
	51	/* the register values are stored here as the actual
	52	* I2C-registers are write-only */
a637a114	53	u8 reg[25];
d203a7ec	54
a637a114	55	int input;
cf4e9484	56	v4l2_std_id norm;
d203a7ec RB	57	};
d203a7ec RB	58
8340ff43 HV	59	static inline struct saa7191 to_saa7191(struct v4l2_subdev sd)
	60	{
	61	return container_of(sd, struct saa7191, sd);
	62	}
	63
a637a114	64	static const u8 initseq[] = {
d203a7ec	65	0, /* Subaddress */
a637a114 LM	66
	67	0x50, /* (0x50) SAA7191_REG_IDEL */
	68
	69	/* 50 Hz signal timing */
	70	0x30, /* (0x30) SAA7191_REG_HSYB */
	71	0x00, /* (0x00) SAA7191_REG_HSYS */
	72	0xe8, /* (0xe8) SAA7191_REG_HCLB */
	73	0xb6, /* (0xb6) SAA7191_REG_HCLS */
	74	0xf4, /* (0xf4) SAA7191_REG_HPHI */
	75
	76	/* control */
	77	SAA7191_LUMA_APER_1, /* (0x01) SAA7191_REG_LUMA - CVBS mode */
	78	0x00, /* (0x00) SAA7191_REG_HUEC */
	79	0xf8, /* (0xf8) SAA7191_REG_CKTQ */
	80	0xf8, /* (0xf8) SAA7191_REG_CKTS */
	81	0x90, /* (0x90) SAA7191_REG_PLSE */
	82	0x90, /* (0x90) SAA7191_REG_SESE */
	83	0x00, /* (0x00) SAA7191_REG_GAIN */
	84	SAA7191_STDC_NFEN \| SAA7191_STDC_HRMV, /* (0x0c) SAA7191_REG_STDC
	85	* - not SECAM,
	86	* slow time constant */
	87	SAA7191_IOCK_OEDC \| SAA7191_IOCK_OEHS \| SAA7191_IOCK_OEVS
	88	\| SAA7191_IOCK_OEDY, /* (0x78) SAA7191_REG_IOCK
	89	* - chroma from CVBS, GPSW1 & 2 off */
	90	SAA7191_CTL3_AUFD \| SAA7191_CTL3_SCEN \| SAA7191_CTL3_OFTS
	91	\| SAA7191_CTL3_YDEL0, /* (0x99) SAA7191_REG_CTL3
	92	* - automatic field detection */
	93	0x00, /* (0x00) SAA7191_REG_CTL4 */
	94	0x2c, /* (0x2c) SAA7191_REG_CHCV - PAL nominal value */
d203a7ec RB	95	0x00, /* unused */
d203a7ec RB	96	0x00, /* unused */
a637a114 LM	97
	98	/* 60 Hz signal timing */
	99	0x34, /* (0x34) SAA7191_REG_HS6B */
	100	0x0a, /* (0x0a) SAA7191_REG_HS6S */
	101	0xf4, /* (0xf4) SAA7191_REG_HC6B */
	102	0xce, /* (0xce) SAA7191_REG_HC6S */
	103	0xf4, /* (0xf4) SAA7191_REG_HP6I */
d203a7ec RB	104	};
	105
	106	/* SAA7191 register handling */
	107
8340ff43	108	static u8 saa7191_read_reg(struct v4l2_subdev *sd, u8 reg)
d203a7ec	109	{
8340ff43	110	return to_saa7191(sd)->reg[reg];
d203a7ec RB	111	}
d203a7ec RB	112
8340ff43	113	static int saa7191_read_status(struct v4l2_subdev sd, u8 value)
d203a7ec	114	{
8340ff43	115	struct i2c_client *client = v4l2_get_subdevdata(sd);
d203a7ec RB	116	int ret;
	117
	118	ret = i2c_master_recv(client, value, 1);
	119	if (ret < 0) {
a637a114	120	printk(KERN_ERR "SAA7191: saa7191_read_status(): read failed\n");
d203a7ec RB	121	return ret;
	122	}
	123
	124	return 0;
	125	}
	126
	127
8340ff43	128	static int saa7191_write_reg(struct v4l2_subdev *sd, u8 reg, u8 value)
d203a7ec	129	{
8340ff43 HV	130	struct i2c_client *client = v4l2_get_subdevdata(sd);
	131
	132	to_saa7191(sd)->reg[reg] = value;
d203a7ec RB	133	return i2c_smbus_write_byte_data(client, reg, value);
	134	}
	135
	136	/* the first byte of data must be the first subaddress number (register) */
8340ff43	137	static int saa7191_write_block(struct v4l2_subdev *sd,
f5ab272b	138	u8 length, const u8 *data)
d203a7ec	139	{
8340ff43 HV	140	struct i2c_client *client = v4l2_get_subdevdata(sd);
8340ff43 HV	141	struct saa7191 *decoder = to_saa7191(sd);
d203a7ec RB	142	int i;
	143	int ret;
	144
d203a7ec RB	145	for (i = 0; i < (length - 1); i++) {
	146	decoder->reg[data[0] + i] = data[i + 1];
	147	}
	148
	149	ret = i2c_master_send(client, data, length);
	150	if (ret < 0) {
	151	printk(KERN_ERR "SAA7191: saa7191_write_block(): "
a637a114	152	"write failed\n");
d203a7ec RB	153	return ret;
	154	}
	155
	156	return 0;
	157	}
	158
	159	/* Helper functions */
	160
8340ff43	161	static int saa7191_s_routing(struct v4l2_subdev *sd,
5325b427	162	u32 input, u32 output, u32 config)
d203a7ec	163	{
8340ff43 HV	164	struct saa7191 *decoder = to_saa7191(sd);
	165	u8 luma = saa7191_read_reg(sd, SAA7191_REG_LUMA);
	166	u8 iock = saa7191_read_reg(sd, SAA7191_REG_IOCK);
d203a7ec RB	167	int err;
d203a7ec RB	168
5325b427	169	switch (input) {
d203a7ec RB	170	case SAA7191_INPUT_COMPOSITE: /* Set Composite input */
	171	iock &= ~(SAA7191_IOCK_CHRS \| SAA7191_IOCK_GPSW1
	172	\| SAA7191_IOCK_GPSW2);
	173	/* Chrominance trap active */
	174	luma &= ~SAA7191_LUMA_BYPS;
	175	break;
	176	case SAA7191_INPUT_SVIDEO: /* Set S-Video input */
	177	iock \|= SAA7191_IOCK_CHRS \| SAA7191_IOCK_GPSW2;
	178	/* Chrominance trap bypassed */
	179	luma \|= SAA7191_LUMA_BYPS;
	180	break;
	181	default:
	182	return -EINVAL;
	183	}
	184
8340ff43	185	err = saa7191_write_reg(sd, SAA7191_REG_LUMA, luma);
d203a7ec RB	186	if (err)
d203a7ec RB	187	return -EIO;
8340ff43	188	err = saa7191_write_reg(sd, SAA7191_REG_IOCK, iock);
d203a7ec RB	189	if (err)
	190	return -EIO;
	191
5325b427	192	decoder->input = input;
a637a114	193
d203a7ec RB	194	return 0;
	195	}
	196
8340ff43	197	static int saa7191_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
d203a7ec	198	{
8340ff43 HV	199	struct saa7191 *decoder = to_saa7191(sd);
	200	u8 stdc = saa7191_read_reg(sd, SAA7191_REG_STDC);
	201	u8 ctl3 = saa7191_read_reg(sd, SAA7191_REG_CTL3);
	202	u8 chcv = saa7191_read_reg(sd, SAA7191_REG_CHCV);
d203a7ec RB	203	int err;
d203a7ec RB	204
cf4e9484	205	if (norm & V4L2_STD_PAL) {
d203a7ec RB	206	stdc &= ~SAA7191_STDC_SECS;
	207	ctl3 &= ~(SAA7191_CTL3_AUFD \| SAA7191_CTL3_FSEL);
	208	chcv = SAA7191_CHCV_PAL;
cf4e9484	209	} else if (norm & V4L2_STD_NTSC) {
d203a7ec RB	210	stdc &= ~SAA7191_STDC_SECS;
	211	ctl3 &= ~SAA7191_CTL3_AUFD;
	212	ctl3 \|= SAA7191_CTL3_FSEL;
	213	chcv = SAA7191_CHCV_NTSC;
cf4e9484	214	} else if (norm & V4L2_STD_SECAM) {
d203a7ec RB	215	stdc \|= SAA7191_STDC_SECS;
	216	ctl3 &= ~(SAA7191_CTL3_AUFD \| SAA7191_CTL3_FSEL);
	217	chcv = SAA7191_CHCV_PAL;
cf4e9484	218	} else {
d203a7ec RB	219	return -EINVAL;
	220	}
	221
8340ff43	222	err = saa7191_write_reg(sd, SAA7191_REG_CTL3, ctl3);
d203a7ec RB	223	if (err)
d203a7ec RB	224	return -EIO;
8340ff43	225	err = saa7191_write_reg(sd, SAA7191_REG_STDC, stdc);
d203a7ec RB	226	if (err)
d203a7ec RB	227	return -EIO;
8340ff43	228	err = saa7191_write_reg(sd, SAA7191_REG_CHCV, chcv);
d203a7ec RB	229	if (err)
	230	return -EIO;
	231
	232	decoder->norm = norm;
	233
a637a114 LM	234	dprintk("ctl3: %02x stdc: %02x chcv: %02x\n", ctl3,
a637a114 LM	235	stdc, chcv);
cf4e9484	236	dprintk("norm: %llx\n", norm);
a637a114	237
d203a7ec RB	238	return 0;
	239	}
	240
8340ff43	241	static int saa7191_wait_for_signal(struct v4l2_subdev sd, u8 status)
d203a7ec	242	{
a637a114	243	int i = 0;
d203a7ec	244
a637a114 LM	245	dprintk("Checking for signal...\n");
	246
	247	for (i = 0; i < SAA7191_SYNC_COUNT; i++) {
8340ff43	248	if (saa7191_read_status(sd, status))
a637a114 LM	249	return -EIO;
	250
	251	if (((*status) & SAA7191_STATUS_HLCK) == 0) {
	252	dprintk("Signal found\n");
	253	return 0;
	254	}
	255
	256	msleep(SAA7191_SYNC_DELAY);
d203a7ec	257	}
d203a7ec	258
a637a114	259	dprintk("No signal\n");
d203a7ec	260
a637a114	261	return -EBUSY;
d203a7ec RB	262	}
d203a7ec RB	263
8340ff43	264	static int saa7191_querystd(struct v4l2_subdev sd, v4l2_std_id norm)
d203a7ec	265	{
8340ff43 HV	266	struct saa7191 *decoder = to_saa7191(sd);
	267	u8 stdc = saa7191_read_reg(sd, SAA7191_REG_STDC);
	268	u8 ctl3 = saa7191_read_reg(sd, SAA7191_REG_CTL3);
a637a114	269	u8 status;
cf4e9484	270	v4l2_std_id old_norm = decoder->norm;
a637a114	271	int err = 0;
d203a7ec	272
a637a114 LM	273	dprintk("SAA7191 extended signal auto-detection...\n");
a637a114 LM	274
cf4e9484	275	*norm = V4L2_STD_NTSC \| V4L2_STD_PAL \| V4L2_STD_SECAM;
a637a114 LM	276	stdc &= ~SAA7191_STDC_SECS;
	277	ctl3 &= ~(SAA7191_CTL3_FSEL);
	278
8340ff43	279	err = saa7191_write_reg(sd, SAA7191_REG_STDC, stdc);
a637a114 LM	280	if (err) {
	281	err = -EIO;
	282	goto out;
	283	}
8340ff43	284	err = saa7191_write_reg(sd, SAA7191_REG_CTL3, ctl3);
a637a114 LM	285	if (err) {
	286	err = -EIO;
	287	goto out;
	288	}
	289
	290	ctl3 \|= SAA7191_CTL3_AUFD;
8340ff43	291	err = saa7191_write_reg(sd, SAA7191_REG_CTL3, ctl3);
a637a114 LM	292	if (err) {
	293	err = -EIO;
	294	goto out;
	295	}
	296
	297	msleep(SAA7191_SYNC_DELAY);
	298
8340ff43	299	err = saa7191_wait_for_signal(sd, &status);
a637a114 LM	300	if (err)
	301	goto out;
	302
	303	if (status & SAA7191_STATUS_FIDT) {
	304	/* 60Hz signal -> NTSC */
	305	dprintk("60Hz signal: NTSC\n");
cf4e9484 HV	306	*norm = V4L2_STD_NTSC;
cf4e9484 HV	307	return 0;
a637a114 LM	308	}
	309
	310	/* 50Hz signal */
	311	dprintk("50Hz signal: Trying PAL...\n");
	312
	313	/* try PAL first */
8340ff43	314	err = saa7191_s_std(sd, V4L2_STD_PAL);
a637a114 LM	315	if (err)
	316	goto out;
	317
	318	msleep(SAA7191_SYNC_DELAY);
	319
8340ff43	320	err = saa7191_wait_for_signal(sd, &status);
a637a114 LM	321	if (err)
	322	goto out;
	323
	324	/* not 50Hz ? */
	325	if (status & SAA7191_STATUS_FIDT) {
	326	dprintk("No 50Hz signal\n");
8340ff43	327	saa7191_s_std(sd, old_norm);
cf4e9484	328	return -EAGAIN;
a637a114 LM	329	}
	330
	331	if (status & SAA7191_STATUS_CODE) {
	332	dprintk("PAL\n");
cf4e9484	333	*norm = V4L2_STD_PAL;
8340ff43	334	return saa7191_s_std(sd, old_norm);
a637a114 LM	335	}
	336
	337	dprintk("No color detected with PAL - Trying SECAM...\n");
	338
	339	/* no color detected ? -> try SECAM */
8340ff43	340	err = saa7191_s_std(sd, V4L2_STD_SECAM);
a637a114 LM	341	if (err)
	342	goto out;
	343
	344	msleep(SAA7191_SYNC_DELAY);
	345
8340ff43	346	err = saa7191_wait_for_signal(sd, &status);
a637a114 LM	347	if (err)
	348	goto out;
	349
	350	/* not 50Hz ? */
	351	if (status & SAA7191_STATUS_FIDT) {
	352	dprintk("No 50Hz signal\n");
	353	err = -EAGAIN;
	354	goto out;
	355	}
	356
	357	if (status & SAA7191_STATUS_CODE) {
	358	/* Color detected -> SECAM */
	359	dprintk("SECAM\n");
cf4e9484	360	*norm = V4L2_STD_SECAM;
8340ff43	361	return saa7191_s_std(sd, old_norm);
a637a114 LM	362	}
	363
	364	dprintk("No color detected with SECAM - Going back to PAL.\n");
	365
a637a114	366	out:
8340ff43	367	return saa7191_s_std(sd, old_norm);
a637a114 LM	368	}
a637a114 LM	369
8340ff43	370	static int saa7191_autodetect_norm(struct v4l2_subdev *sd)
a637a114 LM	371	{
	372	u8 status;
	373
	374	dprintk("SAA7191 signal auto-detection...\n");
	375
	376	dprintk("Reading status...\n");
	377
8340ff43	378	if (saa7191_read_status(sd, &status))
a637a114 LM	379	return -EIO;
	380
	381	dprintk("Checking for signal...\n");
	382
	383	/* no signal ? */
	384	if (status & SAA7191_STATUS_HLCK) {
	385	dprintk("No signal\n");
	386	return -EBUSY;
	387	}
	388
	389	dprintk("Signal found\n");
	390
	391	if (status & SAA7191_STATUS_FIDT) {
	392	/* 60hz signal -> NTSC */
	393	dprintk("NTSC\n");
8340ff43	394	return saa7191_s_std(sd, V4L2_STD_NTSC);
a637a114 LM	395	} else {
	396	/* 50hz signal -> PAL */
	397	dprintk("PAL\n");
8340ff43	398	return saa7191_s_std(sd, V4L2_STD_PAL);
a637a114 LM	399	}
	400	}
	401
8340ff43	402	static int saa7191_g_ctrl(struct v4l2_subdev sd, struct v4l2_control ctrl)
a637a114 LM	403	{
	404	u8 reg;
	405	int ret = 0;
	406
cf4e9484	407	switch (ctrl->id) {
a637a114 LM	408	case SAA7191_CONTROL_BANDPASS:
	409	case SAA7191_CONTROL_BANDPASS_WEIGHT:
	410	case SAA7191_CONTROL_CORING:
8340ff43	411	reg = saa7191_read_reg(sd, SAA7191_REG_LUMA);
cf4e9484	412	switch (ctrl->id) {
a637a114 LM	413	case SAA7191_CONTROL_BANDPASS:
	414	ctrl->value = ((s32)reg & SAA7191_LUMA_BPSS_MASK)
	415	>> SAA7191_LUMA_BPSS_SHIFT;
	416	break;
	417	case SAA7191_CONTROL_BANDPASS_WEIGHT:
	418	ctrl->value = ((s32)reg & SAA7191_LUMA_APER_MASK)
	419	>> SAA7191_LUMA_APER_SHIFT;
	420	break;
	421	case SAA7191_CONTROL_CORING:
	422	ctrl->value = ((s32)reg & SAA7191_LUMA_CORI_MASK)
	423	>> SAA7191_LUMA_CORI_SHIFT;
	424	break;
d203a7ec	425	}
a637a114 LM	426	break;
	427	case SAA7191_CONTROL_FORCE_COLOUR:
	428	case SAA7191_CONTROL_CHROMA_GAIN:
8340ff43	429	reg = saa7191_read_reg(sd, SAA7191_REG_GAIN);
cf4e9484	430	if (ctrl->id == SAA7191_CONTROL_FORCE_COLOUR)
a637a114 LM	431	ctrl->value = ((s32)reg & SAA7191_GAIN_COLO) ? 1 : 0;
	432	else
	433	ctrl->value = ((s32)reg & SAA7191_GAIN_LFIS_MASK)
	434	>> SAA7191_GAIN_LFIS_SHIFT;
	435	break;
cf4e9484	436	case V4L2_CID_HUE:
8340ff43	437	reg = saa7191_read_reg(sd, SAA7191_REG_HUEC);
a637a114 LM	438	if (reg < 0x80)
	439	reg += 0x80;
	440	else
	441	reg -= 0x80;
	442	ctrl->value = (s32)reg;
	443	break;
	444	case SAA7191_CONTROL_VTRC:
8340ff43	445	reg = saa7191_read_reg(sd, SAA7191_REG_STDC);
a637a114 LM	446	ctrl->value = ((s32)reg & SAA7191_STDC_VTRC) ? 1 : 0;
	447	break;
	448	case SAA7191_CONTROL_LUMA_DELAY:
8340ff43	449	reg = saa7191_read_reg(sd, SAA7191_REG_CTL3);
a637a114 LM	450	ctrl->value = ((s32)reg & SAA7191_CTL3_YDEL_MASK)
	451	>> SAA7191_CTL3_YDEL_SHIFT;
	452	if (ctrl->value >= 4)
	453	ctrl->value -= 8;
	454	break;
	455	case SAA7191_CONTROL_VNR:
8340ff43	456	reg = saa7191_read_reg(sd, SAA7191_REG_CTL4);
a637a114 LM	457	ctrl->value = ((s32)reg & SAA7191_CTL4_VNOI_MASK)
	458	>> SAA7191_CTL4_VNOI_SHIFT;
	459	break;
	460	default:
	461	ret = -EINVAL;
	462	}
d203a7ec	463
a637a114 LM	464	return ret;
	465	}
	466
8340ff43	467	static int saa7191_s_ctrl(struct v4l2_subdev sd, struct v4l2_control ctrl)
a637a114 LM	468	{
	469	u8 reg;
	470	int ret = 0;
	471
cf4e9484	472	switch (ctrl->id) {
a637a114 LM	473	case SAA7191_CONTROL_BANDPASS:
	474	case SAA7191_CONTROL_BANDPASS_WEIGHT:
	475	case SAA7191_CONTROL_CORING:
8340ff43	476	reg = saa7191_read_reg(sd, SAA7191_REG_LUMA);
cf4e9484	477	switch (ctrl->id) {
a637a114 LM	478	case SAA7191_CONTROL_BANDPASS:
	479	reg &= ~SAA7191_LUMA_BPSS_MASK;
	480	reg \|= (ctrl->value << SAA7191_LUMA_BPSS_SHIFT)
	481	& SAA7191_LUMA_BPSS_MASK;
	482	break;
	483	case SAA7191_CONTROL_BANDPASS_WEIGHT:
	484	reg &= ~SAA7191_LUMA_APER_MASK;
	485	reg \|= (ctrl->value << SAA7191_LUMA_APER_SHIFT)
	486	& SAA7191_LUMA_APER_MASK;
	487	break;
	488	case SAA7191_CONTROL_CORING:
	489	reg &= ~SAA7191_LUMA_CORI_MASK;
	490	reg \|= (ctrl->value << SAA7191_LUMA_CORI_SHIFT)
	491	& SAA7191_LUMA_CORI_MASK;
	492	break;
	493	}
8340ff43	494	ret = saa7191_write_reg(sd, SAA7191_REG_LUMA, reg);
a637a114 LM	495	break;
	496	case SAA7191_CONTROL_FORCE_COLOUR:
	497	case SAA7191_CONTROL_CHROMA_GAIN:
8340ff43	498	reg = saa7191_read_reg(sd, SAA7191_REG_GAIN);
cf4e9484	499	if (ctrl->id == SAA7191_CONTROL_FORCE_COLOUR) {
a637a114 LM	500	if (ctrl->value)
	501	reg \|= SAA7191_GAIN_COLO;
	502	else
	503	reg &= ~SAA7191_GAIN_COLO;
	504	} else {
	505	reg &= ~SAA7191_GAIN_LFIS_MASK;
	506	reg \|= (ctrl->value << SAA7191_GAIN_LFIS_SHIFT)
	507	& SAA7191_GAIN_LFIS_MASK;
	508	}
8340ff43	509	ret = saa7191_write_reg(sd, SAA7191_REG_GAIN, reg);
a637a114	510	break;
cf4e9484	511	case V4L2_CID_HUE:
a637a114 LM	512	reg = ctrl->value & 0xff;
	513	if (reg < 0x80)
	514	reg += 0x80;
	515	else
	516	reg -= 0x80;
8340ff43	517	ret = saa7191_write_reg(sd, SAA7191_REG_HUEC, reg);
a637a114 LM	518	break;
a637a114 LM	519	case SAA7191_CONTROL_VTRC:
8340ff43	520	reg = saa7191_read_reg(sd, SAA7191_REG_STDC);
a637a114 LM	521	if (ctrl->value)
	522	reg \|= SAA7191_STDC_VTRC;
	523	else
	524	reg &= ~SAA7191_STDC_VTRC;
8340ff43	525	ret = saa7191_write_reg(sd, SAA7191_REG_STDC, reg);
a637a114 LM	526	break;
	527	case SAA7191_CONTROL_LUMA_DELAY: {
	528	s32 value = ctrl->value;
	529	if (value < 0)
	530	value += 8;
8340ff43	531	reg = saa7191_read_reg(sd, SAA7191_REG_CTL3);
a637a114 LM	532	reg &= ~SAA7191_CTL3_YDEL_MASK;
	533	reg \|= (value << SAA7191_CTL3_YDEL_SHIFT)
	534	& SAA7191_CTL3_YDEL_MASK;
8340ff43	535	ret = saa7191_write_reg(sd, SAA7191_REG_CTL3, reg);
a637a114 LM	536	break;
	537	}
	538	case SAA7191_CONTROL_VNR:
8340ff43	539	reg = saa7191_read_reg(sd, SAA7191_REG_CTL4);
a637a114 LM	540	reg &= ~SAA7191_CTL4_VNOI_MASK;
	541	reg \|= (ctrl->value << SAA7191_CTL4_VNOI_SHIFT)
	542	& SAA7191_CTL4_VNOI_MASK;
8340ff43	543	ret = saa7191_write_reg(sd, SAA7191_REG_CTL4, reg);
a637a114 LM	544	break;
	545	default:
	546	ret = -EINVAL;
d203a7ec RB	547	}
d203a7ec RB	548
a637a114	549	return ret;
d203a7ec RB	550	}
	551
	552	/* I2C-interface */
	553
8340ff43	554	static int saa7191_g_input_status(struct v4l2_subdev sd, u32 status)
d203a7ec	555	{
8340ff43 HV	556	u8 status_reg;
8340ff43 HV	557	int res = V4L2_IN_ST_NO_SIGNAL;
d203a7ec	558
8340ff43 HV	559	if (saa7191_read_status(sd, &status_reg))
	560	return -EIO;
	561	if ((status_reg & SAA7191_STATUS_HLCK) == 0)
	562	res = 0;
	563	if (!(status_reg & SAA7191_STATUS_CODE))
	564	res \|= V4L2_IN_ST_NO_COLOR;
	565	*status = res;
	566	return 0;
	567	}
d203a7ec	568
a637a114	569
8340ff43 HV	570	static int saa7191_g_chip_ident(struct v4l2_subdev *sd,
	571	struct v4l2_dbg_chip_ident *chip)
	572	{
	573	struct i2c_client *client = v4l2_get_subdevdata(sd);
a637a114	574
8340ff43 HV	575	return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_SAA7191, 0);
8340ff43 HV	576	}
d203a7ec	577
8340ff43	578	/* ----------------------------------------------------------------------- */
cf4e9484	579
8340ff43 HV	580	static const struct v4l2_subdev_core_ops saa7191_core_ops = {
	581	.g_chip_ident = saa7191_g_chip_ident,
	582	.g_ctrl = saa7191_g_ctrl,
	583	.s_ctrl = saa7191_s_ctrl,
8340ff43 HV	584	.s_std = saa7191_s_std,
8340ff43 HV	585	};
d203a7ec	586
8340ff43 HV	587	static const struct v4l2_subdev_video_ops saa7191_video_ops = {
	588	.s_routing = saa7191_s_routing,
	589	.querystd = saa7191_querystd,
	590	.g_input_status = saa7191_g_input_status,
	591	};
	592
	593	static const struct v4l2_subdev_ops saa7191_ops = {
	594	.core = &saa7191_core_ops,
	595	.video = &saa7191_video_ops,
	596	};
d203a7ec	597
babb7dc7 HV	598	static int saa7191_probe(struct i2c_client *client,
	599	const struct i2c_device_id *id)
	600	{
	601	int err = 0;
	602	struct saa7191 *decoder;
8340ff43	603	struct v4l2_subdev *sd;
d203a7ec	604
babb7dc7 HV	605	v4l_info(client, "chip found @ 0x%x (%s)\n",
	606	client->addr << 1, client->adapter->name);
	607
	608	decoder = kzalloc(sizeof(*decoder), GFP_KERNEL);
	609	if (!decoder)
	610	return -ENOMEM;
	611
8340ff43 HV	612	sd = &decoder->sd;
8340ff43 HV	613	v4l2_i2c_subdev_init(sd, client, &saa7191_ops);
babb7dc7	614
8340ff43	615	err = saa7191_write_block(sd, sizeof(initseq), initseq);
babb7dc7 HV	616	if (err) {
	617	printk(KERN_ERR "SAA7191 initialization failed\n");
	618	kfree(decoder);
	619	return err;
	620	}
	621
	622	printk(KERN_INFO "SAA7191 initialized\n");
	623
	624	decoder->input = SAA7191_INPUT_COMPOSITE;
cf4e9484	625	decoder->norm = V4L2_STD_PAL;
babb7dc7	626
8340ff43	627	err = saa7191_autodetect_norm(sd);
babb7dc7 HV	628	if (err && (err != -EBUSY))
	629	printk(KERN_ERR "SAA7191: Signal auto-detection failed\n");
	630
	631	return 0;
	632	}
	633
	634	static int saa7191_remove(struct i2c_client *client)
d203a7ec	635	{
8340ff43	636	struct v4l2_subdev *sd = i2c_get_clientdata(client);
babb7dc7	637
8340ff43 HV	638	v4l2_device_unregister_subdev(sd);
8340ff43 HV	639	kfree(to_saa7191(sd));
babb7dc7	640	return 0;
d203a7ec RB	641	}
d203a7ec RB	642
babb7dc7 HV	643	static const struct i2c_device_id saa7191_id[] = {
	644	{ "saa7191", 0 },
	645	{ }
	646	};
	647	MODULE_DEVICE_TABLE(i2c, saa7191_id);
	648
534d4f83 HV	649	static struct i2c_driver saa7191_driver = {
	650	.driver = {
	651	.owner = THIS_MODULE,
	652	.name = "saa7191",
	653	},
	654	.probe = saa7191_probe,
	655	.remove = saa7191_remove,
	656	.id_table = saa7191_id,
babb7dc7	657	};
534d4f83	658
c6e8d86f	659	module_i2c_driver(saa7191_driver);