[deliverable/linux.git] / drivers / media / video / saa7191.c

/*
 *  saa7191.c - Philips SAA7191 video decoder driver
 *
 *  Copyright (C) 2003 Ladislav Michl <ladis@linux-mips.org>
 *  Copyright (C) 2004,2005 Mikael Nousiainen <tmnousia@cc.hut.fi>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  published by the Free Software Foundation.
 */

#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/major.h>
#include <linux/module.h>
#include <linux/mm.h>
#include <linux/slab.h>

#include <linux/videodev2.h>
#include <linux/i2c.h>
#include <media/v4l2-device.h>
#include <media/v4l2-chip-ident.h>
#include <media/v4l2-i2c-drv.h>

#include "saa7191.h"

#define SAA7191_MODULE_VERSION	"0.0.5"

MODULE_DESCRIPTION("Philips SAA7191 video decoder driver");
MODULE_VERSION(SAA7191_MODULE_VERSION);
MODULE_AUTHOR("Mikael Nousiainen <tmnousia@cc.hut.fi>");
MODULE_LICENSE("GPL");


// #define SAA7191_DEBUG

#ifdef SAA7191_DEBUG
#define dprintk(x...) printk("SAA7191: " x);
#else
#define dprintk(x...)
#endif

#define SAA7191_SYNC_COUNT	30
#define SAA7191_SYNC_DELAY	100	/* milliseconds */

struct saa7191 {
	struct v4l2_subdev sd;

	/* the register values are stored here as the actual
	 * I2C-registers are write-only */
	u8 reg[25];

	int input;
	v4l2_std_id norm;
};

static inline struct saa7191 *to_saa7191(struct v4l2_subdev *sd)
{
	return container_of(sd, struct saa7191, sd);
}

static const u8 initseq[] = {
	0,	/* Subaddress */

	0x50,	/* (0x50) SAA7191_REG_IDEL */

	/* 50 Hz signal timing */
	0x30,	/* (0x30) SAA7191_REG_HSYB */
	0x00,	/* (0x00) SAA7191_REG_HSYS */
	0xe8,	/* (0xe8) SAA7191_REG_HCLB */
	0xb6,	/* (0xb6) SAA7191_REG_HCLS */
	0xf4,	/* (0xf4) SAA7191_REG_HPHI */

	/* control */
	SAA7191_LUMA_APER_1,	/* (0x01) SAA7191_REG_LUMA - CVBS mode */
	0x00,	/* (0x00) SAA7191_REG_HUEC */
	0xf8,	/* (0xf8) SAA7191_REG_CKTQ */
	0xf8,	/* (0xf8) SAA7191_REG_CKTS */
	0x90,	/* (0x90) SAA7191_REG_PLSE */
	0x90,	/* (0x90) SAA7191_REG_SESE */
	0x00,	/* (0x00) SAA7191_REG_GAIN */
	SAA7191_STDC_NFEN | SAA7191_STDC_HRMV,	/* (0x0c) SAA7191_REG_STDC
						 * - not SECAM,
						 * slow time constant */
	SAA7191_IOCK_OEDC | SAA7191_IOCK_OEHS | SAA7191_IOCK_OEVS
	| SAA7191_IOCK_OEDY,	/* (0x78) SAA7191_REG_IOCK
				 * - chroma from CVBS, GPSW1 & 2 off */
	SAA7191_CTL3_AUFD | SAA7191_CTL3_SCEN | SAA7191_CTL3_OFTS
	| SAA7191_CTL3_YDEL0,	/* (0x99) SAA7191_REG_CTL3
				 * - automatic field detection */
	0x00,	/* (0x00) SAA7191_REG_CTL4 */
	0x2c,	/* (0x2c) SAA7191_REG_CHCV - PAL nominal value */
	0x00,	/* unused */
	0x00,	/* unused */

	/* 60 Hz signal timing */
	0x34,	/* (0x34) SAA7191_REG_HS6B */
	0x0a,	/* (0x0a) SAA7191_REG_HS6S */
	0xf4,	/* (0xf4) SAA7191_REG_HC6B */
	0xce,	/* (0xce) SAA7191_REG_HC6S */
	0xf4,	/* (0xf4) SAA7191_REG_HP6I */
};

/* SAA7191 register handling */

static u8 saa7191_read_reg(struct v4l2_subdev *sd, u8 reg)
{
	return to_saa7191(sd)->reg[reg];
}

static int saa7191_read_status(struct v4l2_subdev *sd, u8 *value)
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);
	int ret;

	ret = i2c_master_recv(client, value, 1);
	if (ret < 0) {
		printk(KERN_ERR "SAA7191: saa7191_read_status(): read failed\n");
		return ret;
	}

	return 0;
}


static int saa7191_write_reg(struct v4l2_subdev *sd, u8 reg, u8 value)
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);

	to_saa7191(sd)->reg[reg] = value;
	return i2c_smbus_write_byte_data(client, reg, value);
}

/* the first byte of data must be the first subaddress number (register) */
static int saa7191_write_block(struct v4l2_subdev *sd,
			       u8 length, const u8 *data)
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);
	struct saa7191 *decoder = to_saa7191(sd);
	int i;
	int ret;

	for (i = 0; i < (length - 1); i++) {
		decoder->reg[data[0] + i] = data[i + 1];
	}

	ret = i2c_master_send(client, data, length);
	if (ret < 0) {
		printk(KERN_ERR "SAA7191: saa7191_write_block(): "
		       "write failed\n");
		return ret;
	}

	return 0;
}

/* Helper functions */

static int saa7191_s_routing(struct v4l2_subdev *sd,
				const struct v4l2_routing *route)
{
	struct saa7191 *decoder = to_saa7191(sd);
	u8 luma = saa7191_read_reg(sd, SAA7191_REG_LUMA);
	u8 iock = saa7191_read_reg(sd, SAA7191_REG_IOCK);
	int err;

	switch (route->input) {
	case SAA7191_INPUT_COMPOSITE: /* Set Composite input */
		iock &= ~(SAA7191_IOCK_CHRS | SAA7191_IOCK_GPSW1
			  | SAA7191_IOCK_GPSW2);
		/* Chrominance trap active */
		luma &= ~SAA7191_LUMA_BYPS;
		break;
	case SAA7191_INPUT_SVIDEO: /* Set S-Video input */
		iock |= SAA7191_IOCK_CHRS | SAA7191_IOCK_GPSW2;
		/* Chrominance trap bypassed */
		luma |= SAA7191_LUMA_BYPS;
		break;
	default:
		return -EINVAL;
	}

	err = saa7191_write_reg(sd, SAA7191_REG_LUMA, luma);
	if (err)
		return -EIO;
	err = saa7191_write_reg(sd, SAA7191_REG_IOCK, iock);
	if (err)
		return -EIO;

	decoder->input = route->input;

	return 0;
}

static int saa7191_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
{
	struct saa7191 *decoder = to_saa7191(sd);
	u8 stdc = saa7191_read_reg(sd, SAA7191_REG_STDC);
	u8 ctl3 = saa7191_read_reg(sd, SAA7191_REG_CTL3);
	u8 chcv = saa7191_read_reg(sd, SAA7191_REG_CHCV);
	int err;

	if (norm & V4L2_STD_PAL) {
		stdc &= ~SAA7191_STDC_SECS;
		ctl3 &= ~(SAA7191_CTL3_AUFD | SAA7191_CTL3_FSEL);
		chcv = SAA7191_CHCV_PAL;
	} else if (norm & V4L2_STD_NTSC) {
		stdc &= ~SAA7191_STDC_SECS;
		ctl3 &= ~SAA7191_CTL3_AUFD;
		ctl3 |= SAA7191_CTL3_FSEL;
		chcv = SAA7191_CHCV_NTSC;
	} else if (norm & V4L2_STD_SECAM) {
		stdc |= SAA7191_STDC_SECS;
		ctl3 &= ~(SAA7191_CTL3_AUFD | SAA7191_CTL3_FSEL);
		chcv = SAA7191_CHCV_PAL;
	} else {
		return -EINVAL;
	}

	err = saa7191_write_reg(sd, SAA7191_REG_CTL3, ctl3);
	if (err)
		return -EIO;
	err = saa7191_write_reg(sd, SAA7191_REG_STDC, stdc);
	if (err)
		return -EIO;
	err = saa7191_write_reg(sd, SAA7191_REG_CHCV, chcv);
	if (err)
		return -EIO;

	decoder->norm = norm;

	dprintk("ctl3: %02x stdc: %02x chcv: %02x\n", ctl3,
		stdc, chcv);
	dprintk("norm: %llx\n", norm);

	return 0;
}

static int saa7191_wait_for_signal(struct v4l2_subdev *sd, u8 *status)
{
	int i = 0;

	dprintk("Checking for signal...\n");

	for (i = 0; i < SAA7191_SYNC_COUNT; i++) {
		if (saa7191_read_status(sd, status))
			return -EIO;

		if (((*status) & SAA7191_STATUS_HLCK) == 0) {
			dprintk("Signal found\n");
			return 0;
		}

		msleep(SAA7191_SYNC_DELAY);
	}

	dprintk("No signal\n");

	return -EBUSY;
}

static int saa7191_querystd(struct v4l2_subdev *sd, v4l2_std_id *norm)
{
	struct saa7191 *decoder = to_saa7191(sd);
	u8 stdc = saa7191_read_reg(sd, SAA7191_REG_STDC);
	u8 ctl3 = saa7191_read_reg(sd, SAA7191_REG_CTL3);
	u8 status;
	v4l2_std_id old_norm = decoder->norm;
	int err = 0;

	dprintk("SAA7191 extended signal auto-detection...\n");

	*norm = V4L2_STD_NTSC | V4L2_STD_PAL | V4L2_STD_SECAM;
	stdc &= ~SAA7191_STDC_SECS;
	ctl3 &= ~(SAA7191_CTL3_FSEL);

	err = saa7191_write_reg(sd, SAA7191_REG_STDC, stdc);
	if (err) {
		err = -EIO;
		goto out;
	}
	err = saa7191_write_reg(sd, SAA7191_REG_CTL3, ctl3);
	if (err) {
		err = -EIO;
		goto out;
	}

	ctl3 |= SAA7191_CTL3_AUFD;
	err = saa7191_write_reg(sd, SAA7191_REG_CTL3, ctl3);
	if (err) {
		err = -EIO;
		goto out;
	}

	msleep(SAA7191_SYNC_DELAY);

	err = saa7191_wait_for_signal(sd, &status);
	if (err)
		goto out;

	if (status & SAA7191_STATUS_FIDT) {
		/* 60Hz signal -> NTSC */
		dprintk("60Hz signal: NTSC\n");
		*norm = V4L2_STD_NTSC;
		return 0;
	}

	/* 50Hz signal */
	dprintk("50Hz signal: Trying PAL...\n");

	/* try PAL first */
	err = saa7191_s_std(sd, V4L2_STD_PAL);
	if (err)
		goto out;

	msleep(SAA7191_SYNC_DELAY);

	err = saa7191_wait_for_signal(sd, &status);
	if (err)
		goto out;

	/* not 50Hz ? */
	if (status & SAA7191_STATUS_FIDT) {
		dprintk("No 50Hz signal\n");
		saa7191_s_std(sd, old_norm);
		return -EAGAIN;
	}

	if (status & SAA7191_STATUS_CODE) {
		dprintk("PAL\n");
		*norm = V4L2_STD_PAL;
		return saa7191_s_std(sd, old_norm);
	}

	dprintk("No color detected with PAL - Trying SECAM...\n");

	/* no color detected ? -> try SECAM */
	err = saa7191_s_std(sd, V4L2_STD_SECAM);
	if (err)
		goto out;

	msleep(SAA7191_SYNC_DELAY);

	err = saa7191_wait_for_signal(sd, &status);
	if (err)
		goto out;

	/* not 50Hz ? */
	if (status & SAA7191_STATUS_FIDT) {
		dprintk("No 50Hz signal\n");
		err = -EAGAIN;
		goto out;
	}

	if (status & SAA7191_STATUS_CODE) {
		/* Color detected -> SECAM */
		dprintk("SECAM\n");
		*norm = V4L2_STD_SECAM;
		return saa7191_s_std(sd, old_norm);
	}

	dprintk("No color detected with SECAM - Going back to PAL.\n");

out:
	return saa7191_s_std(sd, old_norm);
}

static int saa7191_autodetect_norm(struct v4l2_subdev *sd)
{
	u8 status;

	dprintk("SAA7191 signal auto-detection...\n");

	dprintk("Reading status...\n");

	if (saa7191_read_status(sd, &status))
		return -EIO;

	dprintk("Checking for signal...\n");

	/* no signal ? */
	if (status & SAA7191_STATUS_HLCK) {
		dprintk("No signal\n");
		return -EBUSY;
	}

	dprintk("Signal found\n");

	if (status & SAA7191_STATUS_FIDT) {
		/* 60hz signal -> NTSC */
		dprintk("NTSC\n");
		return saa7191_s_std(sd, V4L2_STD_NTSC);
	} else {
		/* 50hz signal -> PAL */
		dprintk("PAL\n");
		return saa7191_s_std(sd, V4L2_STD_PAL);
	}
}

static int saa7191_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
{
	u8 reg;
	int ret = 0;

	switch (ctrl->id) {
	case SAA7191_CONTROL_BANDPASS:
	case SAA7191_CONTROL_BANDPASS_WEIGHT:
	case SAA7191_CONTROL_CORING:
		reg = saa7191_read_reg(sd, SAA7191_REG_LUMA);
		switch (ctrl->id) {
		case SAA7191_CONTROL_BANDPASS:
			ctrl->value = ((s32)reg & SAA7191_LUMA_BPSS_MASK)
				>> SAA7191_LUMA_BPSS_SHIFT;
			break;
		case SAA7191_CONTROL_BANDPASS_WEIGHT:
			ctrl->value = ((s32)reg & SAA7191_LUMA_APER_MASK)
				>> SAA7191_LUMA_APER_SHIFT;
			break;
		case SAA7191_CONTROL_CORING:
			ctrl->value = ((s32)reg & SAA7191_LUMA_CORI_MASK)
				>> SAA7191_LUMA_CORI_SHIFT;
			break;
		}
		break;
	case SAA7191_CONTROL_FORCE_COLOUR:
	case SAA7191_CONTROL_CHROMA_GAIN:
		reg = saa7191_read_reg(sd, SAA7191_REG_GAIN);
		if (ctrl->id == SAA7191_CONTROL_FORCE_COLOUR)
			ctrl->value = ((s32)reg & SAA7191_GAIN_COLO) ? 1 : 0;
		else
			ctrl->value = ((s32)reg & SAA7191_GAIN_LFIS_MASK)
				>> SAA7191_GAIN_LFIS_SHIFT;
		break;
	case V4L2_CID_HUE:
		reg = saa7191_read_reg(sd, SAA7191_REG_HUEC);
		if (reg < 0x80)
			reg += 0x80;
		else
			reg -= 0x80;
		ctrl->value = (s32)reg;
		break;
	case SAA7191_CONTROL_VTRC:
		reg = saa7191_read_reg(sd, SAA7191_REG_STDC);
		ctrl->value = ((s32)reg & SAA7191_STDC_VTRC) ? 1 : 0;
		break;
	case SAA7191_CONTROL_LUMA_DELAY:
		reg = saa7191_read_reg(sd, SAA7191_REG_CTL3);
		ctrl->value = ((s32)reg & SAA7191_CTL3_YDEL_MASK)
			>> SAA7191_CTL3_YDEL_SHIFT;
		if (ctrl->value >= 4)
			ctrl->value -= 8;
		break;
	case SAA7191_CONTROL_VNR:
		reg = saa7191_read_reg(sd, SAA7191_REG_CTL4);
		ctrl->value = ((s32)reg & SAA7191_CTL4_VNOI_MASK)
			>> SAA7191_CTL4_VNOI_SHIFT;
		break;
	default:
		ret = -EINVAL;
	}

	return ret;
}

static int saa7191_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
{
	u8 reg;
	int ret = 0;

	switch (ctrl->id) {
	case SAA7191_CONTROL_BANDPASS:
	case SAA7191_CONTROL_BANDPASS_WEIGHT:
	case SAA7191_CONTROL_CORING:
		reg = saa7191_read_reg(sd, SAA7191_REG_LUMA);
		switch (ctrl->id) {
		case SAA7191_CONTROL_BANDPASS:
			reg &= ~SAA7191_LUMA_BPSS_MASK;
			reg |= (ctrl->value << SAA7191_LUMA_BPSS_SHIFT)
				& SAA7191_LUMA_BPSS_MASK;
			break;
		case SAA7191_CONTROL_BANDPASS_WEIGHT:
			reg &= ~SAA7191_LUMA_APER_MASK;
			reg |= (ctrl->value << SAA7191_LUMA_APER_SHIFT)
				& SAA7191_LUMA_APER_MASK;
			break;
		case SAA7191_CONTROL_CORING:
			reg &= ~SAA7191_LUMA_CORI_MASK;
			reg |= (ctrl->value << SAA7191_LUMA_CORI_SHIFT)
				& SAA7191_LUMA_CORI_MASK;
			break;
		}
		ret = saa7191_write_reg(sd, SAA7191_REG_LUMA, reg);
		break;
	case SAA7191_CONTROL_FORCE_COLOUR:
	case SAA7191_CONTROL_CHROMA_GAIN:
		reg = saa7191_read_reg(sd, SAA7191_REG_GAIN);
		if (ctrl->id == SAA7191_CONTROL_FORCE_COLOUR) {
			if (ctrl->value)
				reg |= SAA7191_GAIN_COLO;
			else
				reg &= ~SAA7191_GAIN_COLO;
		} else {
			reg &= ~SAA7191_GAIN_LFIS_MASK;
			reg |= (ctrl->value << SAA7191_GAIN_LFIS_SHIFT)
				& SAA7191_GAIN_LFIS_MASK;
		}
		ret = saa7191_write_reg(sd, SAA7191_REG_GAIN, reg);
		break;
	case V4L2_CID_HUE:
		reg = ctrl->value & 0xff;
		if (reg < 0x80)
			reg += 0x80;
		else
			reg -= 0x80;
		ret = saa7191_write_reg(sd, SAA7191_REG_HUEC, reg);
		break;
	case SAA7191_CONTROL_VTRC:
		reg = saa7191_read_reg(sd, SAA7191_REG_STDC);
		if (ctrl->value)
			reg |= SAA7191_STDC_VTRC;
		else
			reg &= ~SAA7191_STDC_VTRC;
		ret = saa7191_write_reg(sd, SAA7191_REG_STDC, reg);
		break;
	case SAA7191_CONTROL_LUMA_DELAY: {
		s32 value = ctrl->value;
		if (value < 0)
			value += 8;
		reg = saa7191_read_reg(sd, SAA7191_REG_CTL3);
		reg &= ~SAA7191_CTL3_YDEL_MASK;
		reg |= (value << SAA7191_CTL3_YDEL_SHIFT)
			& SAA7191_CTL3_YDEL_MASK;
		ret = saa7191_write_reg(sd, SAA7191_REG_CTL3, reg);
		break;
	}
	case SAA7191_CONTROL_VNR:
		reg = saa7191_read_reg(sd, SAA7191_REG_CTL4);
		reg &= ~SAA7191_CTL4_VNOI_MASK;
		reg |= (ctrl->value << SAA7191_CTL4_VNOI_SHIFT)
			& SAA7191_CTL4_VNOI_MASK;
		ret = saa7191_write_reg(sd, SAA7191_REG_CTL4, reg);
		break;
	default:
		ret = -EINVAL;
	}

	return ret;
}

/* I2C-interface */

static int saa7191_g_input_status(struct v4l2_subdev *sd, u32 *status)
{
	u8 status_reg;
	int res = V4L2_IN_ST_NO_SIGNAL;

	if (saa7191_read_status(sd, &status_reg))
		return -EIO;
	if ((status_reg & SAA7191_STATUS_HLCK) == 0)
		res = 0;
	if (!(status_reg & SAA7191_STATUS_CODE))
		res |= V4L2_IN_ST_NO_COLOR;
	*status = res;
	return 0;
}


static int saa7191_g_chip_ident(struct v4l2_subdev *sd,
		struct v4l2_dbg_chip_ident *chip)
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);

	return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_SAA7191, 0);
}

/* ----------------------------------------------------------------------- */

static const struct v4l2_subdev_core_ops saa7191_core_ops = {
	.g_chip_ident = saa7191_g_chip_ident,
	.g_ctrl = saa7191_g_ctrl,
	.s_ctrl = saa7191_s_ctrl,
};

static const struct v4l2_subdev_tuner_ops saa7191_tuner_ops = {
	.s_std = saa7191_s_std,
};

static const struct v4l2_subdev_video_ops saa7191_video_ops = {
	.s_routing = saa7191_s_routing,
	.querystd = saa7191_querystd,
	.g_input_status = saa7191_g_input_status,
};

static const struct v4l2_subdev_ops saa7191_ops = {
	.core = &saa7191_core_ops,
	.video = &saa7191_video_ops,
	.tuner = &saa7191_tuner_ops,
};

static int saa7191_probe(struct i2c_client *client,
			  const struct i2c_device_id *id)
{
	int err = 0;
	struct saa7191 *decoder;
	struct v4l2_subdev *sd;

	v4l_info(client, "chip found @ 0x%x (%s)\n",
			client->addr << 1, client->adapter->name);

	decoder = kzalloc(sizeof(*decoder), GFP_KERNEL);
	if (!decoder)
		return -ENOMEM;

	sd = &decoder->sd;
	v4l2_i2c_subdev_init(sd, client, &saa7191_ops);

	err = saa7191_write_block(sd, sizeof(initseq), initseq);
	if (err) {
		printk(KERN_ERR "SAA7191 initialization failed\n");
		kfree(decoder);
		return err;
	}

	printk(KERN_INFO "SAA7191 initialized\n");

	decoder->input = SAA7191_INPUT_COMPOSITE;
	decoder->norm = V4L2_STD_PAL;

	err = saa7191_autodetect_norm(sd);
	if (err && (err != -EBUSY))
		printk(KERN_ERR "SAA7191: Signal auto-detection failed\n");

	return 0;
}

static int saa7191_remove(struct i2c_client *client)
{
	struct v4l2_subdev *sd = i2c_get_clientdata(client);

	v4l2_device_unregister_subdev(sd);
	kfree(to_saa7191(sd));
	return 0;
}

static const struct i2c_device_id saa7191_id[] = {
	{ "saa7191", 0 },
	{ }
};
MODULE_DEVICE_TABLE(i2c, saa7191_id);

static struct v4l2_i2c_driver_data v4l2_i2c_data = {
	.name = "saa7191",
	.probe = saa7191_probe,
	.remove = saa7191_remove,
	.id_table = saa7191_id,
};
Commit	Line	Data
d203a7ec RB	1	/*
	2	* saa7191.c - Philips SAA7191 video decoder driver
	3	*
	4	* Copyright (C) 2003 Ladislav Michl <ladis@linux-mips.org>
	5	* Copyright (C) 2004,2005 Mikael Nousiainen <tmnousia@cc.hut.fi>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
d203a7ec RB	12	#include <linux/delay.h>
	13	#include <linux/errno.h>
	14	#include <linux/fs.h>
495515b3	15	#include <linux/init.h>
d203a7ec RB	16	#include <linux/kernel.h>
d203a7ec RB	17	#include <linux/major.h>
495515b3	18	#include <linux/module.h>
d203a7ec	19	#include <linux/mm.h>
495515b3	20	#include <linux/slab.h>
d203a7ec	21
cf4e9484	22	#include <linux/videodev2.h>
d203a7ec	23	#include <linux/i2c.h>
8340ff43 HV	24	#include <media/v4l2-device.h>
8340ff43 HV	25	#include <media/v4l2-chip-ident.h>
a0720d3b	26	#include <media/v4l2-i2c-drv.h>
d203a7ec RB	27
	28	#include "saa7191.h"
	29
a637a114	30	#define SAA7191_MODULE_VERSION "0.0.5"
d203a7ec RB	31
	32	MODULE_DESCRIPTION("Philips SAA7191 video decoder driver");
	33	MODULE_VERSION(SAA7191_MODULE_VERSION);
	34	MODULE_AUTHOR("Mikael Nousiainen <tmnousia@cc.hut.fi>");
	35	MODULE_LICENSE("GPL");
	36
babb7dc7	37
a637a114 LM	38	// #define SAA7191_DEBUG
	39
	40	#ifdef SAA7191_DEBUG
	41	#define dprintk(x...) printk("SAA7191: " x);
	42	#else
	43	#define dprintk(x...)
	44	#endif
	45
	46	#define SAA7191_SYNC_COUNT 30
	47	#define SAA7191_SYNC_DELAY 100 /* milliseconds */
	48
d203a7ec	49	struct saa7191 {
8340ff43	50	struct v4l2_subdev sd;
d203a7ec RB	51
	52	/* the register values are stored here as the actual
	53	* I2C-registers are write-only */
a637a114	54	u8 reg[25];
d203a7ec	55
a637a114	56	int input;
cf4e9484	57	v4l2_std_id norm;
d203a7ec RB	58	};
d203a7ec RB	59
8340ff43 HV	60	static inline struct saa7191 to_saa7191(struct v4l2_subdev sd)
	61	{
	62	return container_of(sd, struct saa7191, sd);
	63	}
	64
a637a114	65	static const u8 initseq[] = {
d203a7ec	66	0, /* Subaddress */
a637a114 LM	67
	68	0x50, /* (0x50) SAA7191_REG_IDEL */
	69
	70	/* 50 Hz signal timing */
	71	0x30, /* (0x30) SAA7191_REG_HSYB */
	72	0x00, /* (0x00) SAA7191_REG_HSYS */
	73	0xe8, /* (0xe8) SAA7191_REG_HCLB */
	74	0xb6, /* (0xb6) SAA7191_REG_HCLS */
	75	0xf4, /* (0xf4) SAA7191_REG_HPHI */
	76
	77	/* control */
	78	SAA7191_LUMA_APER_1, /* (0x01) SAA7191_REG_LUMA - CVBS mode */
	79	0x00, /* (0x00) SAA7191_REG_HUEC */
	80	0xf8, /* (0xf8) SAA7191_REG_CKTQ */
	81	0xf8, /* (0xf8) SAA7191_REG_CKTS */
	82	0x90, /* (0x90) SAA7191_REG_PLSE */
	83	0x90, /* (0x90) SAA7191_REG_SESE */
	84	0x00, /* (0x00) SAA7191_REG_GAIN */
	85	SAA7191_STDC_NFEN \| SAA7191_STDC_HRMV, /* (0x0c) SAA7191_REG_STDC
	86	* - not SECAM,
	87	* slow time constant */
	88	SAA7191_IOCK_OEDC \| SAA7191_IOCK_OEHS \| SAA7191_IOCK_OEVS
	89	\| SAA7191_IOCK_OEDY, /* (0x78) SAA7191_REG_IOCK
	90	* - chroma from CVBS, GPSW1 & 2 off */
	91	SAA7191_CTL3_AUFD \| SAA7191_CTL3_SCEN \| SAA7191_CTL3_OFTS
	92	\| SAA7191_CTL3_YDEL0, /* (0x99) SAA7191_REG_CTL3
	93	* - automatic field detection */
	94	0x00, /* (0x00) SAA7191_REG_CTL4 */
	95	0x2c, /* (0x2c) SAA7191_REG_CHCV - PAL nominal value */
d203a7ec RB	96	0x00, /* unused */
d203a7ec RB	97	0x00, /* unused */
a637a114 LM	98
	99	/* 60 Hz signal timing */
	100	0x34, /* (0x34) SAA7191_REG_HS6B */
	101	0x0a, /* (0x0a) SAA7191_REG_HS6S */
	102	0xf4, /* (0xf4) SAA7191_REG_HC6B */
	103	0xce, /* (0xce) SAA7191_REG_HC6S */
	104	0xf4, /* (0xf4) SAA7191_REG_HP6I */
d203a7ec RB	105	};
	106
	107	/* SAA7191 register handling */
	108
8340ff43	109	static u8 saa7191_read_reg(struct v4l2_subdev *sd, u8 reg)
d203a7ec	110	{
8340ff43	111	return to_saa7191(sd)->reg[reg];
d203a7ec RB	112	}
d203a7ec RB	113
8340ff43	114	static int saa7191_read_status(struct v4l2_subdev sd, u8 value)
d203a7ec	115	{
8340ff43	116	struct i2c_client *client = v4l2_get_subdevdata(sd);
d203a7ec RB	117	int ret;
	118
	119	ret = i2c_master_recv(client, value, 1);
	120	if (ret < 0) {
a637a114	121	printk(KERN_ERR "SAA7191: saa7191_read_status(): read failed\n");
d203a7ec RB	122	return ret;
	123	}
	124
	125	return 0;
	126	}
	127
	128
8340ff43	129	static int saa7191_write_reg(struct v4l2_subdev *sd, u8 reg, u8 value)
d203a7ec	130	{
8340ff43 HV	131	struct i2c_client *client = v4l2_get_subdevdata(sd);
	132
	133	to_saa7191(sd)->reg[reg] = value;
d203a7ec RB	134	return i2c_smbus_write_byte_data(client, reg, value);
	135	}
	136
	137	/* the first byte of data must be the first subaddress number (register) */
8340ff43	138	static int saa7191_write_block(struct v4l2_subdev *sd,
f5ab272b	139	u8 length, const u8 *data)
d203a7ec	140	{
8340ff43 HV	141	struct i2c_client *client = v4l2_get_subdevdata(sd);
8340ff43 HV	142	struct saa7191 *decoder = to_saa7191(sd);
d203a7ec RB	143	int i;
	144	int ret;
	145
d203a7ec RB	146	for (i = 0; i < (length - 1); i++) {
	147	decoder->reg[data[0] + i] = data[i + 1];
	148	}
	149
	150	ret = i2c_master_send(client, data, length);
	151	if (ret < 0) {
	152	printk(KERN_ERR "SAA7191: saa7191_write_block(): "
a637a114	153	"write failed\n");
d203a7ec RB	154	return ret;
	155	}
	156
	157	return 0;
	158	}
	159
	160	/* Helper functions */
	161
8340ff43 HV	162	static int saa7191_s_routing(struct v4l2_subdev *sd,
8340ff43 HV	163	const struct v4l2_routing *route)
d203a7ec	164	{
8340ff43 HV	165	struct saa7191 *decoder = to_saa7191(sd);
	166	u8 luma = saa7191_read_reg(sd, SAA7191_REG_LUMA);
	167	u8 iock = saa7191_read_reg(sd, SAA7191_REG_IOCK);
d203a7ec RB	168	int err;
d203a7ec RB	169
8340ff43	170	switch (route->input) {
d203a7ec RB	171	case SAA7191_INPUT_COMPOSITE: /* Set Composite input */
	172	iock &= ~(SAA7191_IOCK_CHRS \| SAA7191_IOCK_GPSW1
	173	\| SAA7191_IOCK_GPSW2);
	174	/* Chrominance trap active */
	175	luma &= ~SAA7191_LUMA_BYPS;
	176	break;
	177	case SAA7191_INPUT_SVIDEO: /* Set S-Video input */
	178	iock \|= SAA7191_IOCK_CHRS \| SAA7191_IOCK_GPSW2;
	179	/* Chrominance trap bypassed */
	180	luma \|= SAA7191_LUMA_BYPS;
	181	break;
	182	default:
	183	return -EINVAL;
	184	}
	185
8340ff43	186	err = saa7191_write_reg(sd, SAA7191_REG_LUMA, luma);
d203a7ec RB	187	if (err)
d203a7ec RB	188	return -EIO;
8340ff43	189	err = saa7191_write_reg(sd, SAA7191_REG_IOCK, iock);
d203a7ec RB	190	if (err)
	191	return -EIO;
	192
8340ff43	193	decoder->input = route->input;
a637a114	194
d203a7ec RB	195	return 0;
	196	}
	197
8340ff43	198	static int saa7191_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
d203a7ec	199	{
8340ff43 HV	200	struct saa7191 *decoder = to_saa7191(sd);
	201	u8 stdc = saa7191_read_reg(sd, SAA7191_REG_STDC);
	202	u8 ctl3 = saa7191_read_reg(sd, SAA7191_REG_CTL3);
	203	u8 chcv = saa7191_read_reg(sd, SAA7191_REG_CHCV);
d203a7ec RB	204	int err;
d203a7ec RB	205
cf4e9484	206	if (norm & V4L2_STD_PAL) {
d203a7ec RB	207	stdc &= ~SAA7191_STDC_SECS;
	208	ctl3 &= ~(SAA7191_CTL3_AUFD \| SAA7191_CTL3_FSEL);
	209	chcv = SAA7191_CHCV_PAL;
cf4e9484	210	} else if (norm & V4L2_STD_NTSC) {
d203a7ec RB	211	stdc &= ~SAA7191_STDC_SECS;
	212	ctl3 &= ~SAA7191_CTL3_AUFD;
	213	ctl3 \|= SAA7191_CTL3_FSEL;
	214	chcv = SAA7191_CHCV_NTSC;
cf4e9484	215	} else if (norm & V4L2_STD_SECAM) {
d203a7ec RB	216	stdc \|= SAA7191_STDC_SECS;
	217	ctl3 &= ~(SAA7191_CTL3_AUFD \| SAA7191_CTL3_FSEL);
	218	chcv = SAA7191_CHCV_PAL;
cf4e9484	219	} else {
d203a7ec RB	220	return -EINVAL;
	221	}
	222
8340ff43	223	err = saa7191_write_reg(sd, SAA7191_REG_CTL3, ctl3);
d203a7ec RB	224	if (err)
d203a7ec RB	225	return -EIO;
8340ff43	226	err = saa7191_write_reg(sd, SAA7191_REG_STDC, stdc);
d203a7ec RB	227	if (err)
d203a7ec RB	228	return -EIO;
8340ff43	229	err = saa7191_write_reg(sd, SAA7191_REG_CHCV, chcv);
d203a7ec RB	230	if (err)
	231	return -EIO;
	232
	233	decoder->norm = norm;
	234
a637a114 LM	235	dprintk("ctl3: %02x stdc: %02x chcv: %02x\n", ctl3,
a637a114 LM	236	stdc, chcv);
cf4e9484	237	dprintk("norm: %llx\n", norm);
a637a114	238
d203a7ec RB	239	return 0;
	240	}
	241
8340ff43	242	static int saa7191_wait_for_signal(struct v4l2_subdev sd, u8 status)
d203a7ec	243	{
a637a114	244	int i = 0;
d203a7ec	245
a637a114 LM	246	dprintk("Checking for signal...\n");
	247
	248	for (i = 0; i < SAA7191_SYNC_COUNT; i++) {
8340ff43	249	if (saa7191_read_status(sd, status))
a637a114 LM	250	return -EIO;
	251
	252	if (((*status) & SAA7191_STATUS_HLCK) == 0) {
	253	dprintk("Signal found\n");
	254	return 0;
	255	}
	256
	257	msleep(SAA7191_SYNC_DELAY);
d203a7ec	258	}
d203a7ec	259
a637a114	260	dprintk("No signal\n");
d203a7ec	261
a637a114	262	return -EBUSY;
d203a7ec RB	263	}
d203a7ec RB	264
8340ff43	265	static int saa7191_querystd(struct v4l2_subdev sd, v4l2_std_id norm)
d203a7ec	266	{
8340ff43 HV	267	struct saa7191 *decoder = to_saa7191(sd);
	268	u8 stdc = saa7191_read_reg(sd, SAA7191_REG_STDC);
	269	u8 ctl3 = saa7191_read_reg(sd, SAA7191_REG_CTL3);
a637a114	270	u8 status;
cf4e9484	271	v4l2_std_id old_norm = decoder->norm;
a637a114	272	int err = 0;
d203a7ec	273
a637a114 LM	274	dprintk("SAA7191 extended signal auto-detection...\n");
a637a114 LM	275
cf4e9484	276	*norm = V4L2_STD_NTSC \| V4L2_STD_PAL \| V4L2_STD_SECAM;
a637a114 LM	277	stdc &= ~SAA7191_STDC_SECS;
	278	ctl3 &= ~(SAA7191_CTL3_FSEL);
	279
8340ff43	280	err = saa7191_write_reg(sd, SAA7191_REG_STDC, stdc);
a637a114 LM	281	if (err) {
	282	err = -EIO;
	283	goto out;
	284	}
8340ff43	285	err = saa7191_write_reg(sd, SAA7191_REG_CTL3, ctl3);
a637a114 LM	286	if (err) {
	287	err = -EIO;
	288	goto out;
	289	}
	290
	291	ctl3 \|= SAA7191_CTL3_AUFD;
8340ff43	292	err = saa7191_write_reg(sd, SAA7191_REG_CTL3, ctl3);
a637a114 LM	293	if (err) {
	294	err = -EIO;
	295	goto out;
	296	}
	297
	298	msleep(SAA7191_SYNC_DELAY);
	299
8340ff43	300	err = saa7191_wait_for_signal(sd, &status);
a637a114 LM	301	if (err)
	302	goto out;
	303
	304	if (status & SAA7191_STATUS_FIDT) {
	305	/* 60Hz signal -> NTSC */
	306	dprintk("60Hz signal: NTSC\n");
cf4e9484 HV	307	*norm = V4L2_STD_NTSC;
cf4e9484 HV	308	return 0;
a637a114 LM	309	}
	310
	311	/* 50Hz signal */
	312	dprintk("50Hz signal: Trying PAL...\n");
	313
	314	/* try PAL first */
8340ff43	315	err = saa7191_s_std(sd, V4L2_STD_PAL);
a637a114 LM	316	if (err)
	317	goto out;
	318
	319	msleep(SAA7191_SYNC_DELAY);
	320
8340ff43	321	err = saa7191_wait_for_signal(sd, &status);
a637a114 LM	322	if (err)
	323	goto out;
	324
	325	/* not 50Hz ? */
	326	if (status & SAA7191_STATUS_FIDT) {
	327	dprintk("No 50Hz signal\n");
8340ff43	328	saa7191_s_std(sd, old_norm);
cf4e9484	329	return -EAGAIN;
a637a114 LM	330	}
	331
	332	if (status & SAA7191_STATUS_CODE) {
	333	dprintk("PAL\n");
cf4e9484	334	*norm = V4L2_STD_PAL;
8340ff43	335	return saa7191_s_std(sd, old_norm);
a637a114 LM	336	}
	337
	338	dprintk("No color detected with PAL - Trying SECAM...\n");
	339
	340	/* no color detected ? -> try SECAM */
8340ff43	341	err = saa7191_s_std(sd, V4L2_STD_SECAM);
a637a114 LM	342	if (err)
	343	goto out;
	344
	345	msleep(SAA7191_SYNC_DELAY);
	346
8340ff43	347	err = saa7191_wait_for_signal(sd, &status);
a637a114 LM	348	if (err)
	349	goto out;
	350
	351	/* not 50Hz ? */
	352	if (status & SAA7191_STATUS_FIDT) {
	353	dprintk("No 50Hz signal\n");
	354	err = -EAGAIN;
	355	goto out;
	356	}
	357
	358	if (status & SAA7191_STATUS_CODE) {
	359	/* Color detected -> SECAM */
	360	dprintk("SECAM\n");
cf4e9484	361	*norm = V4L2_STD_SECAM;
8340ff43	362	return saa7191_s_std(sd, old_norm);
a637a114 LM	363	}
	364
	365	dprintk("No color detected with SECAM - Going back to PAL.\n");
	366
a637a114	367	out:
8340ff43	368	return saa7191_s_std(sd, old_norm);
a637a114 LM	369	}
a637a114 LM	370
8340ff43	371	static int saa7191_autodetect_norm(struct v4l2_subdev *sd)
a637a114 LM	372	{
	373	u8 status;
	374
	375	dprintk("SAA7191 signal auto-detection...\n");
	376
	377	dprintk("Reading status...\n");
	378
8340ff43	379	if (saa7191_read_status(sd, &status))
a637a114 LM	380	return -EIO;
	381
	382	dprintk("Checking for signal...\n");
	383
	384	/* no signal ? */
	385	if (status & SAA7191_STATUS_HLCK) {
	386	dprintk("No signal\n");
	387	return -EBUSY;
	388	}
	389
	390	dprintk("Signal found\n");
	391
	392	if (status & SAA7191_STATUS_FIDT) {
	393	/* 60hz signal -> NTSC */
	394	dprintk("NTSC\n");
8340ff43	395	return saa7191_s_std(sd, V4L2_STD_NTSC);
a637a114 LM	396	} else {
	397	/* 50hz signal -> PAL */
	398	dprintk("PAL\n");
8340ff43	399	return saa7191_s_std(sd, V4L2_STD_PAL);
a637a114 LM	400	}
	401	}
	402
8340ff43	403	static int saa7191_g_ctrl(struct v4l2_subdev sd, struct v4l2_control ctrl)
a637a114 LM	404	{
	405	u8 reg;
	406	int ret = 0;
	407
cf4e9484	408	switch (ctrl->id) {
a637a114 LM	409	case SAA7191_CONTROL_BANDPASS:
	410	case SAA7191_CONTROL_BANDPASS_WEIGHT:
	411	case SAA7191_CONTROL_CORING:
8340ff43	412	reg = saa7191_read_reg(sd, SAA7191_REG_LUMA);
cf4e9484	413	switch (ctrl->id) {
a637a114 LM	414	case SAA7191_CONTROL_BANDPASS:
	415	ctrl->value = ((s32)reg & SAA7191_LUMA_BPSS_MASK)
	416	>> SAA7191_LUMA_BPSS_SHIFT;
	417	break;
	418	case SAA7191_CONTROL_BANDPASS_WEIGHT:
	419	ctrl->value = ((s32)reg & SAA7191_LUMA_APER_MASK)
	420	>> SAA7191_LUMA_APER_SHIFT;
	421	break;
	422	case SAA7191_CONTROL_CORING:
	423	ctrl->value = ((s32)reg & SAA7191_LUMA_CORI_MASK)
	424	>> SAA7191_LUMA_CORI_SHIFT;
	425	break;
d203a7ec	426	}
a637a114 LM	427	break;
	428	case SAA7191_CONTROL_FORCE_COLOUR:
	429	case SAA7191_CONTROL_CHROMA_GAIN:
8340ff43	430	reg = saa7191_read_reg(sd, SAA7191_REG_GAIN);
cf4e9484	431	if (ctrl->id == SAA7191_CONTROL_FORCE_COLOUR)
a637a114 LM	432	ctrl->value = ((s32)reg & SAA7191_GAIN_COLO) ? 1 : 0;
	433	else
	434	ctrl->value = ((s32)reg & SAA7191_GAIN_LFIS_MASK)
	435	>> SAA7191_GAIN_LFIS_SHIFT;
	436	break;
cf4e9484	437	case V4L2_CID_HUE:
8340ff43	438	reg = saa7191_read_reg(sd, SAA7191_REG_HUEC);
a637a114 LM	439	if (reg < 0x80)
	440	reg += 0x80;
	441	else
	442	reg -= 0x80;
	443	ctrl->value = (s32)reg;
	444	break;
	445	case SAA7191_CONTROL_VTRC:
8340ff43	446	reg = saa7191_read_reg(sd, SAA7191_REG_STDC);
a637a114 LM	447	ctrl->value = ((s32)reg & SAA7191_STDC_VTRC) ? 1 : 0;
	448	break;
	449	case SAA7191_CONTROL_LUMA_DELAY:
8340ff43	450	reg = saa7191_read_reg(sd, SAA7191_REG_CTL3);
a637a114 LM	451	ctrl->value = ((s32)reg & SAA7191_CTL3_YDEL_MASK)
	452	>> SAA7191_CTL3_YDEL_SHIFT;
	453	if (ctrl->value >= 4)
	454	ctrl->value -= 8;
	455	break;
	456	case SAA7191_CONTROL_VNR:
8340ff43	457	reg = saa7191_read_reg(sd, SAA7191_REG_CTL4);
a637a114 LM	458	ctrl->value = ((s32)reg & SAA7191_CTL4_VNOI_MASK)
	459	>> SAA7191_CTL4_VNOI_SHIFT;
	460	break;
	461	default:
	462	ret = -EINVAL;
	463	}
d203a7ec	464
a637a114 LM	465	return ret;
	466	}
	467
8340ff43	468	static int saa7191_s_ctrl(struct v4l2_subdev sd, struct v4l2_control ctrl)
a637a114 LM	469	{
	470	u8 reg;
	471	int ret = 0;
	472
cf4e9484	473	switch (ctrl->id) {
a637a114 LM	474	case SAA7191_CONTROL_BANDPASS:
	475	case SAA7191_CONTROL_BANDPASS_WEIGHT:
	476	case SAA7191_CONTROL_CORING:
8340ff43	477	reg = saa7191_read_reg(sd, SAA7191_REG_LUMA);
cf4e9484	478	switch (ctrl->id) {
a637a114 LM	479	case SAA7191_CONTROL_BANDPASS:
	480	reg &= ~SAA7191_LUMA_BPSS_MASK;
	481	reg \|= (ctrl->value << SAA7191_LUMA_BPSS_SHIFT)
	482	& SAA7191_LUMA_BPSS_MASK;
	483	break;
	484	case SAA7191_CONTROL_BANDPASS_WEIGHT:
	485	reg &= ~SAA7191_LUMA_APER_MASK;
	486	reg \|= (ctrl->value << SAA7191_LUMA_APER_SHIFT)
	487	& SAA7191_LUMA_APER_MASK;
	488	break;
	489	case SAA7191_CONTROL_CORING:
	490	reg &= ~SAA7191_LUMA_CORI_MASK;
	491	reg \|= (ctrl->value << SAA7191_LUMA_CORI_SHIFT)
	492	& SAA7191_LUMA_CORI_MASK;
	493	break;
	494	}
8340ff43	495	ret = saa7191_write_reg(sd, SAA7191_REG_LUMA, reg);
a637a114 LM	496	break;
	497	case SAA7191_CONTROL_FORCE_COLOUR:
	498	case SAA7191_CONTROL_CHROMA_GAIN:
8340ff43	499	reg = saa7191_read_reg(sd, SAA7191_REG_GAIN);
cf4e9484	500	if (ctrl->id == SAA7191_CONTROL_FORCE_COLOUR) {
a637a114 LM	501	if (ctrl->value)
	502	reg \|= SAA7191_GAIN_COLO;
	503	else
	504	reg &= ~SAA7191_GAIN_COLO;
	505	} else {
	506	reg &= ~SAA7191_GAIN_LFIS_MASK;
	507	reg \|= (ctrl->value << SAA7191_GAIN_LFIS_SHIFT)
	508	& SAA7191_GAIN_LFIS_MASK;
	509	}
8340ff43	510	ret = saa7191_write_reg(sd, SAA7191_REG_GAIN, reg);
a637a114	511	break;
cf4e9484	512	case V4L2_CID_HUE:
a637a114 LM	513	reg = ctrl->value & 0xff;
	514	if (reg < 0x80)
	515	reg += 0x80;
	516	else
	517	reg -= 0x80;
8340ff43	518	ret = saa7191_write_reg(sd, SAA7191_REG_HUEC, reg);
a637a114 LM	519	break;
a637a114 LM	520	case SAA7191_CONTROL_VTRC:
8340ff43	521	reg = saa7191_read_reg(sd, SAA7191_REG_STDC);
a637a114 LM	522	if (ctrl->value)
	523	reg \|= SAA7191_STDC_VTRC;
	524	else
	525	reg &= ~SAA7191_STDC_VTRC;
8340ff43	526	ret = saa7191_write_reg(sd, SAA7191_REG_STDC, reg);
a637a114 LM	527	break;
	528	case SAA7191_CONTROL_LUMA_DELAY: {
	529	s32 value = ctrl->value;
	530	if (value < 0)
	531	value += 8;
8340ff43	532	reg = saa7191_read_reg(sd, SAA7191_REG_CTL3);
a637a114 LM	533	reg &= ~SAA7191_CTL3_YDEL_MASK;
	534	reg \|= (value << SAA7191_CTL3_YDEL_SHIFT)
	535	& SAA7191_CTL3_YDEL_MASK;
8340ff43	536	ret = saa7191_write_reg(sd, SAA7191_REG_CTL3, reg);
a637a114 LM	537	break;
	538	}
	539	case SAA7191_CONTROL_VNR:
8340ff43	540	reg = saa7191_read_reg(sd, SAA7191_REG_CTL4);
a637a114 LM	541	reg &= ~SAA7191_CTL4_VNOI_MASK;
	542	reg \|= (ctrl->value << SAA7191_CTL4_VNOI_SHIFT)
	543	& SAA7191_CTL4_VNOI_MASK;
8340ff43	544	ret = saa7191_write_reg(sd, SAA7191_REG_CTL4, reg);
a637a114 LM	545	break;
	546	default:
	547	ret = -EINVAL;
d203a7ec RB	548	}
d203a7ec RB	549
a637a114	550	return ret;
d203a7ec RB	551	}
	552
	553	/* I2C-interface */
	554
8340ff43	555	static int saa7191_g_input_status(struct v4l2_subdev sd, u32 status)
d203a7ec	556	{
8340ff43 HV	557	u8 status_reg;
8340ff43 HV	558	int res = V4L2_IN_ST_NO_SIGNAL;
d203a7ec	559
8340ff43 HV	560	if (saa7191_read_status(sd, &status_reg))
	561	return -EIO;
	562	if ((status_reg & SAA7191_STATUS_HLCK) == 0)
	563	res = 0;
	564	if (!(status_reg & SAA7191_STATUS_CODE))
	565	res \|= V4L2_IN_ST_NO_COLOR;
	566	*status = res;
	567	return 0;
	568	}
d203a7ec	569
a637a114	570
8340ff43 HV	571	static int saa7191_g_chip_ident(struct v4l2_subdev *sd,
	572	struct v4l2_dbg_chip_ident *chip)
	573	{
	574	struct i2c_client *client = v4l2_get_subdevdata(sd);
a637a114	575
8340ff43 HV	576	return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_SAA7191, 0);
8340ff43 HV	577	}
d203a7ec	578
8340ff43	579	/* ----------------------------------------------------------------------- */
cf4e9484	580
8340ff43 HV	581	static const struct v4l2_subdev_core_ops saa7191_core_ops = {
	582	.g_chip_ident = saa7191_g_chip_ident,
	583	.g_ctrl = saa7191_g_ctrl,
	584	.s_ctrl = saa7191_s_ctrl,
	585	};
cf4e9484	586
8340ff43 HV	587	static const struct v4l2_subdev_tuner_ops saa7191_tuner_ops = {
	588	.s_std = saa7191_s_std,
	589	};
d203a7ec	590
8340ff43 HV	591	static const struct v4l2_subdev_video_ops saa7191_video_ops = {
	592	.s_routing = saa7191_s_routing,
	593	.querystd = saa7191_querystd,
	594	.g_input_status = saa7191_g_input_status,
	595	};
	596
	597	static const struct v4l2_subdev_ops saa7191_ops = {
	598	.core = &saa7191_core_ops,
	599	.video = &saa7191_video_ops,
fd3a0195	600	.tuner = &saa7191_tuner_ops,
8340ff43	601	};
d203a7ec	602
babb7dc7 HV	603	static int saa7191_probe(struct i2c_client *client,
	604	const struct i2c_device_id *id)
	605	{
	606	int err = 0;
	607	struct saa7191 *decoder;
8340ff43	608	struct v4l2_subdev *sd;
d203a7ec	609
babb7dc7 HV	610	v4l_info(client, "chip found @ 0x%x (%s)\n",
	611	client->addr << 1, client->adapter->name);
	612
	613	decoder = kzalloc(sizeof(*decoder), GFP_KERNEL);
	614	if (!decoder)
	615	return -ENOMEM;
	616
8340ff43 HV	617	sd = &decoder->sd;
8340ff43 HV	618	v4l2_i2c_subdev_init(sd, client, &saa7191_ops);
babb7dc7	619
8340ff43	620	err = saa7191_write_block(sd, sizeof(initseq), initseq);
babb7dc7 HV	621	if (err) {
	622	printk(KERN_ERR "SAA7191 initialization failed\n");
	623	kfree(decoder);
	624	return err;
	625	}
	626
	627	printk(KERN_INFO "SAA7191 initialized\n");
	628
	629	decoder->input = SAA7191_INPUT_COMPOSITE;
cf4e9484	630	decoder->norm = V4L2_STD_PAL;
babb7dc7	631
8340ff43	632	err = saa7191_autodetect_norm(sd);
babb7dc7 HV	633	if (err && (err != -EBUSY))
	634	printk(KERN_ERR "SAA7191: Signal auto-detection failed\n");
	635
	636	return 0;
	637	}
	638
	639	static int saa7191_remove(struct i2c_client *client)
d203a7ec	640	{
8340ff43	641	struct v4l2_subdev *sd = i2c_get_clientdata(client);
babb7dc7	642
8340ff43 HV	643	v4l2_device_unregister_subdev(sd);
8340ff43 HV	644	kfree(to_saa7191(sd));
babb7dc7	645	return 0;
d203a7ec RB	646	}
d203a7ec RB	647
babb7dc7 HV	648	static const struct i2c_device_id saa7191_id[] = {
	649	{ "saa7191", 0 },
	650	{ }
	651	};
	652	MODULE_DEVICE_TABLE(i2c, saa7191_id);
	653
	654	static struct v4l2_i2c_driver_data v4l2_i2c_data = {
	655	.name = "saa7191",
babb7dc7 HV	656	.probe = saa7191_probe,
babb7dc7 HV	657	.remove = saa7191_remove,
babb7dc7 HV	658	.id_table = saa7191_id,
babb7dc7 HV	659	};