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V4L/DVB (9618): tvaudio: add additional logic to avoid OOPS
[deliverable/linux.git] / drivers / media / video / tvaudio.c
CommitLineData
1da177e4
LT		 1/*
2 * experimental driver for simple i2c audio chips.
3 *
4 * Copyright (c) 2000 Gerd Knorr
5 * based on code by:
6 * Eric Sandeen (eric_sandeen@bigfoot.com)
7 * Steve VanDeBogart (vandebo@uclink.berkeley.edu)
8 * Greg Alexander (galexand@acm.org)
9 *
10 * This code is placed under the terms of the GNU General Public License
11 *
12 * OPTIONS:
13 * debug - set to 1 if you'd like to see debug messages
14 *
15 */
16
1da177e4 17#include <linux/module.h>
1da177e4
LT		 18#include <linux/kernel.h>
19#include <linux/sched.h>
20#include <linux/string.h>
21#include <linux/timer.h>
22#include <linux/delay.h>
23#include <linux/errno.h>
24#include <linux/slab.h>
25#include <linux/videodev.h>
26#include <linux/i2c.h>
1da177e4 27#include <linux/init.h>
bc282879 28#include <linux/kthread.h>
7dfb7103 29#include <linux/freezer.h>
1da177e4 30
8bf2f8e7 31#include <media/tvaudio.h>
5e453dc7 32#include <media/v4l2-common.h>
74cab31c 33#include <media/v4l2-chip-ident.h>
08e14054 34#include <media/v4l2-i2c-drv-legacy.h>
1da177e4 35
7c9b5048 36#include <media/i2c-addr.h>
1da177e4
LT		 37
38/* ---------------------------------------------------------------------- */
39/* insmod args */
40
ff699e6b 41static int debug; /* insmod parameter */
1da177e4
LT		 42module_param(debug, int, 0644);
43
44MODULE_DESCRIPTION("device driver for various i2c TV sound decoder / audiomux chips");
45MODULE_AUTHOR("Eric Sandeen, Steve VanDeBogart, Greg Alexander, Gerd Knorr");
46MODULE_LICENSE("GPL");
47
48#define UNSET (-1U)
18fc59e2 49
1da177e4
LT		 50/* ---------------------------------------------------------------------- */
51/* our structs */
52
53#define MAXREGS 64
54
55struct CHIPSTATE;
56typedef int (*getvalue)(int);
57typedef int (*checkit)(struct CHIPSTATE*);
58typedef int (*initialize)(struct CHIPSTATE*);
59typedef int (*getmode)(struct CHIPSTATE*);
60typedef void (*setmode)(struct CHIPSTATE*, int mode);
1da177e4
LT		 61
62/* i2c command */
63typedef struct AUDIOCMD {
64 int count; /* # of bytes to send */
65 unsigned char bytes[MAXREGS+1]; /* addr, data, data, ... */
66} audiocmd;
67
68/* chip description */
69struct CHIPDESC {
70 char *name; /* chip name */
1da177e4
LT		 71 int addr_lo, addr_hi; /* i2c address range */
72 int registers; /* # of registers */
73
74 int *insmodopt;
75 checkit checkit;
76 initialize initialize;
77 int flags;
78#define CHIP_HAS_VOLUME 1
79#define CHIP_HAS_BASSTREBLE 2
80#define CHIP_HAS_INPUTSEL 4
dd03e970 81#define CHIP_NEED_CHECKMODE 8
1da177e4
LT		 82
83 /* various i2c command sequences */
84 audiocmd init;
85
86 /* which register has which value */
87 int leftreg,rightreg,treblereg,bassreg;
88
89 /* initialize with (defaults to 65535/65535/32768/32768 */
90 int leftinit,rightinit,trebleinit,bassinit;
91
92 /* functions to convert the values (v4l -> chip) */
93 getvalue volfunc,treblefunc,bassfunc;
94
95 /* get/set mode */
96 getmode getmode;
97 setmode setmode;
98
1da177e4
LT		 99 /* input switch register + values for v4l inputs */
100 int inputreg;
8bf2f8e7 101 int inputmap[4];
1da177e4
LT		 102 int inputmute;
103 int inputmask;
104};
105static struct CHIPDESC chiplist[];
106
107/* current state of the chip */
108struct CHIPSTATE {
08e14054 109 struct i2c_client *c;
1da177e4
LT		 110
111 /* index into CHIPDESC array */
112 int type;
113
114 /* shadow register set */
115 audiocmd shadow;
116
117 /* current settings */
8bf2f8e7 118 __u16 left,right,treble,bass,muted,mode;
1da177e4 119 int prevmode;
8a854284 120 int radio;
8bf2f8e7 121 int input;
1da177e4
LT		 122
123 /* thread */
bc282879 124 struct task_struct *thread;
1da177e4 125 struct timer_list wt;
1da177e4 126 int watch_stereo;
8a4b275f 127 int audmode;
1da177e4
LT		 128};
129
1da177e4
LT		 130/* ---------------------------------------------------------------------- */
131/* i2c addresses */
132
133static unsigned short normal_i2c[] = {
09df1c16
MCC		 134 I2C_ADDR_TDA8425 >> 1,
135 I2C_ADDR_TEA6300 >> 1,
136 I2C_ADDR_TEA6420 >> 1,
137 I2C_ADDR_TDA9840 >> 1,
138 I2C_ADDR_TDA985x_L >> 1,
139 I2C_ADDR_TDA985x_H >> 1,
140 I2C_ADDR_TDA9874 >> 1,
141 I2C_ADDR_PIC16C54 >> 1,
1da177e4 142 I2C_CLIENT_END };
1da177e4
LT		 143I2C_CLIENT_INSMOD;
144
1da177e4
LT		 145/* ---------------------------------------------------------------------- */
146/* i2c I/O functions */
147
148static int chip_write(struct CHIPSTATE *chip, int subaddr, int val)
149{
150 unsigned char buffer[2];
151
152 if (-1 == subaddr) {
08e14054
HV		 153 v4l_dbg(1, debug, chip->c, "%s: chip_write: 0x%x\n",
154 chip->c->name, val);
1da177e4
LT		 155 chip->shadow.bytes[1] = val;
156 buffer[0] = val;
08e14054
HV		 157 if (1 != i2c_master_send(chip->c,buffer,1)) {
158 v4l_warn(chip->c, "%s: I/O error (write 0x%x)\n",
159 chip->c->name, val);
1da177e4
LT		 160 return -1;
161 }
162 } else {
08e14054
HV		 163 v4l_dbg(1, debug, chip->c, "%s: chip_write: reg%d=0x%x\n",
164 chip->c->name, subaddr, val);
1da177e4
LT		 165 chip->shadow.bytes[subaddr+1] = val;
166 buffer[0] = subaddr;
167 buffer[1] = val;
08e14054
HV		 168 if (2 != i2c_master_send(chip->c,buffer,2)) {
169 v4l_warn(chip->c, "%s: I/O error (write reg%d=0x%x)\n",
170 chip->c->name, subaddr, val);
1da177e4
LT		 171 return -1;
172 }
173 }
174 return 0;
175}
176
177static int chip_write_masked(struct CHIPSTATE *chip, int subaddr, int val, int mask)
178{
179 if (mask != 0) {
180 if (-1 == subaddr) {
181 val = (chip->shadow.bytes[1] & ~mask) | (val & mask);
182 } else {
183 val = (chip->shadow.bytes[subaddr+1] & ~mask) | (val & mask);
184 }
185 }
186 return chip_write(chip, subaddr, val);
187}
188
189static int chip_read(struct CHIPSTATE *chip)
190{
191 unsigned char buffer;
192
08e14054
HV		 193 if (1 != i2c_master_recv(chip->c,&buffer,1)) {
194 v4l_warn(chip->c, "%s: I/O error (read)\n",
195 chip->c->name);
1da177e4
LT		 196 return -1;
197 }
08e14054 198 v4l_dbg(1, debug, chip->c, "%s: chip_read: 0x%x\n",chip->c->name, buffer);
1da177e4
LT		 199 return buffer;
200}
201
202static int chip_read2(struct CHIPSTATE *chip, int subaddr)
203{
18fc59e2
MCC		 204 unsigned char write[1];
205 unsigned char read[1];
206 struct i2c_msg msgs[2] = {
08e14054
HV		 207 { chip->c->addr, 0, 1, write },
208 { chip->c->addr, I2C_M_RD, 1, read }
18fc59e2
MCC		 209 };
210 write[0] = subaddr;
1da177e4 211
08e14054
HV		 212 if (2 != i2c_transfer(chip->c->adapter,msgs,2)) {
213 v4l_warn(chip->c, "%s: I/O error (read2)\n", chip->c->name);
1da177e4
LT		 214 return -1;
215 }
08e14054
HV		 216 v4l_dbg(1, debug, chip->c, "%s: chip_read2: reg%d=0x%x\n",
217 chip->c->name, subaddr,read[0]);
1da177e4
LT		 218 return read[0];
219}
220
221static int chip_cmd(struct CHIPSTATE *chip, char *name, audiocmd *cmd)
222{
223 int i;
224
225 if (0 == cmd->count)
226 return 0;
227
228 /* update our shadow register set; print bytes if (debug > 0) */
08e14054
HV		 229 v4l_dbg(1, debug, chip->c, "%s: chip_cmd(%s): reg=%d, data:",
230 chip->c->name, name,cmd->bytes[0]);
1da177e4 231 for (i = 1; i < cmd->count; i++) {
18fc59e2
MCC		 232 if (debug)
233 printk(" 0x%x",cmd->bytes[i]);
1da177e4
LT		 234 chip->shadow.bytes[i+cmd->bytes[0]] = cmd->bytes[i];
235 }
18fc59e2
MCC		 236 if (debug)
237 printk("\n");
1da177e4
LT		 238
239 /* send data to the chip */
08e14054
HV		 240 if (cmd->count != i2c_master_send(chip->c,cmd->bytes,cmd->count)) {
241 v4l_warn(chip->c, "%s: I/O error (%s)\n", chip->c->name, name);
1da177e4
LT		 242 return -1;
243 }
244 return 0;
245}
246
247/* ---------------------------------------------------------------------- */
248/* kernel thread for doing i2c stuff asyncronly
249 * right now it is used only to check the audio mode (mono/stereo/whatever)
250 * some time after switching to another TV channel, then turn on stereo
251 * if available, ...
252 */
253
254static void chip_thread_wake(unsigned long data)
255{
18fc59e2 256 struct CHIPSTATE *chip = (struct CHIPSTATE*)data;
bc282879 257 wake_up_process(chip->thread);
1da177e4
LT		 258}
259
260static int chip_thread(void *data)
261{
18fc59e2 262 struct CHIPSTATE *chip = data;
1da177e4 263 struct CHIPDESC *desc = chiplist + chip->type;
dd03e970 264 int mode;
1da177e4 265
08e14054 266 v4l_dbg(1, debug, chip->c, "%s: thread started\n", chip->c->name);
83144186 267 set_freezable();
1da177e4 268 for (;;) {
bc282879
CLG		 269 set_current_state(TASK_INTERRUPTIBLE);
270 if (!kthread_should_stop())
1da177e4 271 schedule();
bc282879 272 set_current_state(TASK_RUNNING);
5e50e7a9 273 try_to_freeze();
bc282879 274 if (kthread_should_stop())
1da177e4 275 break;
08e14054 276 v4l_dbg(1, debug, chip->c, "%s: thread wakeup\n", chip->c->name);
1da177e4
LT		 277
278 /* don't do anything for radio or if mode != auto */
8a854284 279 if (chip->radio || chip->mode != 0)
1da177e4
LT		 280 continue;
281
282 /* have a look what's going on */
dd03e970
MCC		 283 mode = desc->getmode(chip);
284 if (mode == chip->prevmode)
285 continue;
286
287 /* chip detected a new audio mode - set it */
288 v4l_dbg(1, debug, chip->c, "%s: thread checkmode\n",
289 chip->c->name);
290
291 chip->prevmode = mode;
292
293 if (mode & V4L2_TUNER_MODE_STEREO)
294 desc->setmode(chip, V4L2_TUNER_MODE_STEREO);
295 if (mode & V4L2_TUNER_MODE_LANG1_LANG2)
296 desc->setmode(chip, V4L2_TUNER_MODE_STEREO);
297 else if (mode & V4L2_TUNER_MODE_LANG1)
298 desc->setmode(chip, V4L2_TUNER_MODE_LANG1);
299 else if (mode & V4L2_TUNER_MODE_LANG2)
300 desc->setmode(chip, V4L2_TUNER_MODE_LANG2);
301 else
302 desc->setmode(chip, V4L2_TUNER_MODE_MONO);
1da177e4
LT		 303
304 /* schedule next check */
09df5cbe 305 mod_timer(&chip->wt, jiffies+msecs_to_jiffies(2000));
1da177e4
LT		 306 }
307
08e14054 308 v4l_dbg(1, debug, chip->c, "%s: thread exiting\n", chip->c->name);
1da177e4
LT		 309 return 0;
310}
311
1da177e4
LT		 312/* ---------------------------------------------------------------------- */
313/* audio chip descriptions - defines+functions for tda9840 */
314
315#define TDA9840_SW 0x00
316#define TDA9840_LVADJ 0x02
317#define TDA9840_STADJ 0x03
318#define TDA9840_TEST 0x04
319
320#define TDA9840_MONO 0x10
321#define TDA9840_STEREO 0x2a
322#define TDA9840_DUALA 0x12
323#define TDA9840_DUALB 0x1e
324#define TDA9840_DUALAB 0x1a
325#define TDA9840_DUALBA 0x16
326#define TDA9840_EXTERNAL 0x7a
327
328#define TDA9840_DS_DUAL 0x20 /* Dual sound identified */
329#define TDA9840_ST_STEREO 0x40 /* Stereo sound identified */
330#define TDA9840_PONRES 0x80 /* Power-on reset detected if = 1 */
331
332#define TDA9840_TEST_INT1SN 0x1 /* Integration time 0.5s when set */
333#define TDA9840_TEST_INTFU 0x02 /* Disables integrator function */
334
335static int tda9840_getmode(struct CHIPSTATE *chip)
336{
337 int val, mode;
338
339 val = chip_read(chip);
dc3d75da 340 mode = V4L2_TUNER_MODE_MONO;
1da177e4 341 if (val & TDA9840_DS_DUAL)
dc3d75da 342 mode |= V4L2_TUNER_MODE_LANG1 | V4L2_TUNER_MODE_LANG2;
1da177e4 343 if (val & TDA9840_ST_STEREO)
dc3d75da 344 mode |= V4L2_TUNER_MODE_STEREO;
1da177e4 345
08e14054 346 v4l_dbg(1, debug, chip->c, "tda9840_getmode(): raw chip read: %d, return: %d\n",
18fc59e2 347 val, mode);
1da177e4
LT		 348 return mode;
349}
350
351static void tda9840_setmode(struct CHIPSTATE *chip, int mode)
352{
353 int update = 1;
354 int t = chip->shadow.bytes[TDA9840_SW + 1] & ~0x7e;
355
356 switch (mode) {
dc3d75da 357 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 358 t |= TDA9840_MONO;
359 break;
dc3d75da 360 case V4L2_TUNER_MODE_STEREO:
1da177e4
LT		 361 t |= TDA9840_STEREO;
362 break;
dc3d75da 363 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 364 t |= TDA9840_DUALA;
365 break;
dc3d75da 366 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 367 t |= TDA9840_DUALB;
368 break;
369 default:
370 update = 0;
371 }
372
373 if (update)
374 chip_write(chip, TDA9840_SW, t);
375}
376
94f9e56e
HV		 377static int tda9840_checkit(struct CHIPSTATE *chip)
378{
379 int rc;
380 rc = chip_read(chip);
381 /* lower 5 bits should be 0 */
382 return ((rc & 0x1f) == 0) ? 1 : 0;
383}
384
1da177e4
LT		 385/* ---------------------------------------------------------------------- */
386/* audio chip descriptions - defines+functions for tda985x */
387
388/* subaddresses for TDA9855 */
389#define TDA9855_VR 0x00 /* Volume, right */
390#define TDA9855_VL 0x01 /* Volume, left */
391#define TDA9855_BA 0x02 /* Bass */
392#define TDA9855_TR 0x03 /* Treble */
393#define TDA9855_SW 0x04 /* Subwoofer - not connected on DTV2000 */
394
395/* subaddresses for TDA9850 */
396#define TDA9850_C4 0x04 /* Control 1 for TDA9850 */
397
398/* subaddesses for both chips */
399#define TDA985x_C5 0x05 /* Control 2 for TDA9850, Control 1 for TDA9855 */
400#define TDA985x_C6 0x06 /* Control 3 for TDA9850, Control 2 for TDA9855 */
401#define TDA985x_C7 0x07 /* Control 4 for TDA9850, Control 3 for TDA9855 */
402#define TDA985x_A1 0x08 /* Alignment 1 for both chips */
403#define TDA985x_A2 0x09 /* Alignment 2 for both chips */
404#define TDA985x_A3 0x0a /* Alignment 3 for both chips */
405
406/* Masks for bits in TDA9855 subaddresses */
407/* 0x00 - VR in TDA9855 */
408/* 0x01 - VL in TDA9855 */
409/* lower 7 bits control gain from -71dB (0x28) to 16dB (0x7f)
410 * in 1dB steps - mute is 0x27 */
411
412
413/* 0x02 - BA in TDA9855 */
414/* lower 5 bits control bass gain from -12dB (0x06) to 16.5dB (0x19)
415 * in .5dB steps - 0 is 0x0E */
416
417
418/* 0x03 - TR in TDA9855 */
419/* 4 bits << 1 control treble gain from -12dB (0x3) to 12dB (0xb)
420 * in 3dB steps - 0 is 0x7 */
421
422/* Masks for bits in both chips' subaddresses */
423/* 0x04 - SW in TDA9855, C4/Control 1 in TDA9850 */
424/* Unique to TDA9855: */
425/* 4 bits << 2 control subwoofer/surround gain from -14db (0x1) to 14db (0xf)
426 * in 3dB steps - mute is 0x0 */
427
428/* Unique to TDA9850: */
429/* lower 4 bits control stereo noise threshold, over which stereo turns off
430 * set to values of 0x00 through 0x0f for Ster1 through Ster16 */
431
432
433/* 0x05 - C5 - Control 1 in TDA9855 , Control 2 in TDA9850*/
434/* Unique to TDA9855: */
435#define TDA9855_MUTE 1<<7 /* GMU, Mute at outputs */
436#define TDA9855_AVL 1<<6 /* AVL, Automatic Volume Level */
437#define TDA9855_LOUD 1<<5 /* Loudness, 1==off */
438#define TDA9855_SUR 1<<3 /* Surround / Subwoofer 1==.5(L-R) 0==.5(L+R) */
439 /* Bits 0 to 3 select various combinations
4ac97914
MCC		 440 * of line in and line out, only the
441 * interesting ones are defined */
1da177e4
LT		 442#define TDA9855_EXT 1<<2 /* Selects inputs LIR and LIL. Pins 41 & 12 */
443#define TDA9855_INT 0 /* Selects inputs LOR and LOL. (internal) */
444
445/* Unique to TDA9850: */
446/* lower 4 bits contol SAP noise threshold, over which SAP turns off
447 * set to values of 0x00 through 0x0f for SAP1 through SAP16 */
448
449
450/* 0x06 - C6 - Control 2 in TDA9855, Control 3 in TDA9850 */
451/* Common to TDA9855 and TDA9850: */
452#define TDA985x_SAP 3<<6 /* Selects SAP output, mute if not received */
453#define TDA985x_STEREO 1<<6 /* Selects Stereo ouput, mono if not received */
454#define TDA985x_MONO 0 /* Forces Mono output */
455#define TDA985x_LMU 1<<3 /* Mute (LOR/LOL for 9855, OUTL/OUTR for 9850) */
456
457/* Unique to TDA9855: */
458#define TDA9855_TZCM 1<<5 /* If set, don't mute till zero crossing */
459#define TDA9855_VZCM 1<<4 /* If set, don't change volume till zero crossing*/
460#define TDA9855_LINEAR 0 /* Linear Stereo */
461#define TDA9855_PSEUDO 1 /* Pseudo Stereo */
462#define TDA9855_SPAT_30 2 /* Spatial Stereo, 30% anti-phase crosstalk */
463#define TDA9855_SPAT_50 3 /* Spatial Stereo, 52% anti-phase crosstalk */
464#define TDA9855_E_MONO 7 /* Forced mono - mono select elseware, so useless*/
465
466/* 0x07 - C7 - Control 3 in TDA9855, Control 4 in TDA9850 */
467/* Common to both TDA9855 and TDA9850: */
468/* lower 4 bits control input gain from -3.5dB (0x0) to 4dB (0xF)
469 * in .5dB steps - 0dB is 0x7 */
470
471/* 0x08, 0x09 - A1 and A2 (read/write) */
472/* Common to both TDA9855 and TDA9850: */
473/* lower 5 bites are wideband and spectral expander alignment
474 * from 0x00 to 0x1f - nominal at 0x0f and 0x10 (read/write) */
475#define TDA985x_STP 1<<5 /* Stereo Pilot/detect (read-only) */
476#define TDA985x_SAPP 1<<6 /* SAP Pilot/detect (read-only) */
477#define TDA985x_STS 1<<7 /* Stereo trigger 1= <35mV 0= <30mV (write-only)*/
478
479/* 0x0a - A3 */
480/* Common to both TDA9855 and TDA9850: */
481/* lower 3 bits control timing current for alignment: -30% (0x0), -20% (0x1),
482 * -10% (0x2), nominal (0x3), +10% (0x6), +20% (0x5), +30% (0x4) */
483#define TDA985x_ADJ 1<<7 /* Stereo adjust on/off (wideband and spectral */
484
485static int tda9855_volume(int val) { return val/0x2e8+0x27; }
486static int tda9855_bass(int val) { return val/0xccc+0x06; }
487static int tda9855_treble(int val) { return (val/0x1c71+0x3)<<1; }
488
489static int tda985x_getmode(struct CHIPSTATE *chip)
490{
491 int mode;
492
493 mode = ((TDA985x_STP | TDA985x_SAPP) &
494 chip_read(chip)) >> 4;
495 /* Add mono mode regardless of SAP and stereo */
496 /* Allows forced mono */
dc3d75da 497 return mode | V4L2_TUNER_MODE_MONO;
1da177e4
LT		 498}
499
500static void tda985x_setmode(struct CHIPSTATE *chip, int mode)
501{
502 int update = 1;
503 int c6 = chip->shadow.bytes[TDA985x_C6+1] & 0x3f;
504
505 switch (mode) {
dc3d75da 506 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 507 c6 |= TDA985x_MONO;
508 break;
dc3d75da 509 case V4L2_TUNER_MODE_STEREO:
1da177e4
LT		 510 c6 |= TDA985x_STEREO;
511 break;
dc3d75da 512 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 513 c6 |= TDA985x_SAP;
514 break;
515 default:
516 update = 0;
517 }
518 if (update)
519 chip_write(chip,TDA985x_C6,c6);
520}
521
522
523/* ---------------------------------------------------------------------- */
524/* audio chip descriptions - defines+functions for tda9873h */
525
526/* Subaddresses for TDA9873H */
527
528#define TDA9873_SW 0x00 /* Switching */
529#define TDA9873_AD 0x01 /* Adjust */
530#define TDA9873_PT 0x02 /* Port */
531
532/* Subaddress 0x00: Switching Data
533 * B7..B0:
534 *
535 * B1, B0: Input source selection
536 * 0, 0 internal
537 * 1, 0 external stereo
538 * 0, 1 external mono
539 */
540#define TDA9873_INP_MASK 3
541#define TDA9873_INTERNAL 0
542#define TDA9873_EXT_STEREO 2
543#define TDA9873_EXT_MONO 1
544
545/* B3, B2: output signal select
546 * B4 : transmission mode
547 * 0, 0, 1 Mono
548 * 1, 0, 0 Stereo
549 * 1, 1, 1 Stereo (reversed channel)
550 * 0, 0, 0 Dual AB
551 * 0, 0, 1 Dual AA
552 * 0, 1, 0 Dual BB
553 * 0, 1, 1 Dual BA
554 */
555
556#define TDA9873_TR_MASK (7 << 2)
557#define TDA9873_TR_MONO 4
558#define TDA9873_TR_STEREO 1 << 4
559#define TDA9873_TR_REVERSE (1 << 3) & (1 << 2)
560#define TDA9873_TR_DUALA 1 << 2
561#define TDA9873_TR_DUALB 1 << 3
562
563/* output level controls
564 * B5: output level switch (0 = reduced gain, 1 = normal gain)
565 * B6: mute (1 = muted)
566 * B7: auto-mute (1 = auto-mute enabled)
567 */
568
569#define TDA9873_GAIN_NORMAL 1 << 5
570#define TDA9873_MUTE 1 << 6
571#define TDA9873_AUTOMUTE 1 << 7
572
573/* Subaddress 0x01: Adjust/standard */
574
575/* Lower 4 bits (C3..C0) control stereo adjustment on R channel (-0.6 - +0.7 dB)
576 * Recommended value is +0 dB
577 */
578
579#define TDA9873_STEREO_ADJ 0x06 /* 0dB gain */
580
581/* Bits C6..C4 control FM stantard
582 * C6, C5, C4
583 * 0, 0, 0 B/G (PAL FM)
584 * 0, 0, 1 M
585 * 0, 1, 0 D/K(1)
586 * 0, 1, 1 D/K(2)
587 * 1, 0, 0 D/K(3)
588 * 1, 0, 1 I
589 */
590#define TDA9873_BG 0
591#define TDA9873_M 1
592#define TDA9873_DK1 2
593#define TDA9873_DK2 3
594#define TDA9873_DK3 4
595#define TDA9873_I 5
596
597/* C7 controls identification response time (1=fast/0=normal)
598 */
599#define TDA9873_IDR_NORM 0
600#define TDA9873_IDR_FAST 1 << 7
601
602
603/* Subaddress 0x02: Port data */
604
605/* E1, E0 free programmable ports P1/P2
606 0, 0 both ports low
607 0, 1 P1 high
608 1, 0 P2 high
609 1, 1 both ports high
610*/
611
612#define TDA9873_PORTS 3
613
614/* E2: test port */
615#define TDA9873_TST_PORT 1 << 2
616
617/* E5..E3 control mono output channel (together with transmission mode bit B4)
618 *
619 * E5 E4 E3 B4 OUTM
620 * 0 0 0 0 mono
621 * 0 0 1 0 DUAL B
622 * 0 1 0 1 mono (from stereo decoder)
623 */
624#define TDA9873_MOUT_MONO 0
625#define TDA9873_MOUT_FMONO 0
626#define TDA9873_MOUT_DUALA 0
627#define TDA9873_MOUT_DUALB 1 << 3
628#define TDA9873_MOUT_ST 1 << 4
629#define TDA9873_MOUT_EXTM (1 << 4 ) & (1 << 3)
630#define TDA9873_MOUT_EXTL 1 << 5
631#define TDA9873_MOUT_EXTR (1 << 5 ) & (1 << 3)
632#define TDA9873_MOUT_EXTLR (1 << 5 ) & (1 << 4)
633#define TDA9873_MOUT_MUTE (1 << 5 ) & (1 << 4) & (1 << 3)
634
635/* Status bits: (chip read) */
636#define TDA9873_PONR 0 /* Power-on reset detected if = 1 */
637#define TDA9873_STEREO 2 /* Stereo sound is identified */
638#define TDA9873_DUAL 4 /* Dual sound is identified */
639
640static int tda9873_getmode(struct CHIPSTATE *chip)
641{
642 int val,mode;
643
644 val = chip_read(chip);
dc3d75da 645 mode = V4L2_TUNER_MODE_MONO;
1da177e4 646 if (val & TDA9873_STEREO)
dc3d75da 647 mode |= V4L2_TUNER_MODE_STEREO;
1da177e4 648 if (val & TDA9873_DUAL)
dc3d75da 649 mode |= V4L2_TUNER_MODE_LANG1 | V4L2_TUNER_MODE_LANG2;
08e14054 650 v4l_dbg(1, debug, chip->c, "tda9873_getmode(): raw chip read: %d, return: %d\n",
18fc59e2 651 val, mode);
1da177e4
LT		 652 return mode;
653}
654
655static void tda9873_setmode(struct CHIPSTATE *chip, int mode)
656{
657 int sw_data = chip->shadow.bytes[TDA9873_SW+1] & ~ TDA9873_TR_MASK;
658 /* int adj_data = chip->shadow.bytes[TDA9873_AD+1] ; */
659
660 if ((sw_data & TDA9873_INP_MASK) != TDA9873_INTERNAL) {
08e14054 661 v4l_dbg(1, debug, chip->c, "tda9873_setmode(): external input\n");
1da177e4
LT		 662 return;
663 }
664
08e14054
HV		 665 v4l_dbg(1, debug, chip->c, "tda9873_setmode(): chip->shadow.bytes[%d] = %d\n", TDA9873_SW+1, chip->shadow.bytes[TDA9873_SW+1]);
666 v4l_dbg(1, debug, chip->c, "tda9873_setmode(): sw_data = %d\n", sw_data);
1da177e4
LT		 667
668 switch (mode) {
dc3d75da 669 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 670 sw_data |= TDA9873_TR_MONO;
671 break;
dc3d75da 672 case V4L2_TUNER_MODE_STEREO:
1da177e4
LT		 673 sw_data |= TDA9873_TR_STEREO;
674 break;
dc3d75da 675 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 676 sw_data |= TDA9873_TR_DUALA;
677 break;
dc3d75da 678 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 679 sw_data |= TDA9873_TR_DUALB;
680 break;
681 default:
682 chip->mode = 0;
683 return;
684 }
685
686 chip_write(chip, TDA9873_SW, sw_data);
08e14054 687 v4l_dbg(1, debug, chip->c, "tda9873_setmode(): req. mode %d; chip_write: %d\n",
1da177e4
LT		 688 mode, sw_data);
689}
690
691static int tda9873_checkit(struct CHIPSTATE *chip)
692{
693 int rc;
694
695 if (-1 == (rc = chip_read2(chip,254)))
696 return 0;
697 return (rc & ~0x1f) == 0x80;
698}
699
700
701/* ---------------------------------------------------------------------- */
702/* audio chip description - defines+functions for tda9874h and tda9874a */
703/* Dariusz Kowalewski <darekk@automex.pl> */
704
705/* Subaddresses for TDA9874H and TDA9874A (slave rx) */
706#define TDA9874A_AGCGR 0x00 /* AGC gain */
707#define TDA9874A_GCONR 0x01 /* general config */
708#define TDA9874A_MSR 0x02 /* monitor select */
709#define TDA9874A_C1FRA 0x03 /* carrier 1 freq. */
710#define TDA9874A_C1FRB 0x04 /* carrier 1 freq. */
711#define TDA9874A_C1FRC 0x05 /* carrier 1 freq. */
712#define TDA9874A_C2FRA 0x06 /* carrier 2 freq. */
713#define TDA9874A_C2FRB 0x07 /* carrier 2 freq. */
714#define TDA9874A_C2FRC 0x08 /* carrier 2 freq. */
715#define TDA9874A_DCR 0x09 /* demodulator config */
716#define TDA9874A_FMER 0x0a /* FM de-emphasis */
717#define TDA9874A_FMMR 0x0b /* FM dematrix */
718#define TDA9874A_C1OLAR 0x0c /* ch.1 output level adj. */
719#define TDA9874A_C2OLAR 0x0d /* ch.2 output level adj. */
720#define TDA9874A_NCONR 0x0e /* NICAM config */
721#define TDA9874A_NOLAR 0x0f /* NICAM output level adj. */
722#define TDA9874A_NLELR 0x10 /* NICAM lower error limit */
723#define TDA9874A_NUELR 0x11 /* NICAM upper error limit */
724#define TDA9874A_AMCONR 0x12 /* audio mute control */
725#define TDA9874A_SDACOSR 0x13 /* stereo DAC output select */
726#define TDA9874A_AOSR 0x14 /* analog output select */
727#define TDA9874A_DAICONR 0x15 /* digital audio interface config */
728#define TDA9874A_I2SOSR 0x16 /* I2S-bus output select */
729#define TDA9874A_I2SOLAR 0x17 /* I2S-bus output level adj. */
730#define TDA9874A_MDACOSR 0x18 /* mono DAC output select (tda9874a) */
731#define TDA9874A_ESP 0xFF /* easy standard progr. (tda9874a) */
732
733/* Subaddresses for TDA9874H and TDA9874A (slave tx) */
734#define TDA9874A_DSR 0x00 /* device status */
735#define TDA9874A_NSR 0x01 /* NICAM status */
736#define TDA9874A_NECR 0x02 /* NICAM error count */
737#define TDA9874A_DR1 0x03 /* add. data LSB */
738#define TDA9874A_DR2 0x04 /* add. data MSB */
739#define TDA9874A_LLRA 0x05 /* monitor level read-out LSB */
740#define TDA9874A_LLRB 0x06 /* monitor level read-out MSB */
741#define TDA9874A_SIFLR 0x07 /* SIF level */
742#define TDA9874A_TR2 252 /* test reg. 2 */
743#define TDA9874A_TR1 253 /* test reg. 1 */
744#define TDA9874A_DIC 254 /* device id. code */
745#define TDA9874A_SIC 255 /* software id. code */
746
747
748static int tda9874a_mode = 1; /* 0: A2, 1: NICAM */
749static int tda9874a_GCONR = 0xc0; /* default config. input pin: SIFSEL=0 */
750static int tda9874a_NCONR = 0x01; /* default NICAM config.: AMSEL=0,AMUTE=1 */
751static int tda9874a_ESP = 0x07; /* default standard: NICAM D/K */
752static int tda9874a_dic = -1; /* device id. code */
753
754/* insmod options for tda9874a */
755static unsigned int tda9874a_SIF = UNSET;
756static unsigned int tda9874a_AMSEL = UNSET;
757static unsigned int tda9874a_STD = UNSET;
758module_param(tda9874a_SIF, int, 0444);
759module_param(tda9874a_AMSEL, int, 0444);
760module_param(tda9874a_STD, int, 0444);
761
762/*
763 * initialization table for tda9874 decoder:
764 * - carrier 1 freq. registers (3 bytes)
765 * - carrier 2 freq. registers (3 bytes)
766 * - demudulator config register
767 * - FM de-emphasis register (slow identification mode)
768 * Note: frequency registers must be written in single i2c transfer.
769 */
770static struct tda9874a_MODES {
771 char *name;
772 audiocmd cmd;
773} tda9874a_modelist[9] = {
04e6f990 774 { "A2, B/G", /* default */
1da177e4
LT		 775 { 9, { TDA9874A_C1FRA, 0x72,0x95,0x55, 0x77,0xA0,0x00, 0x00,0x00 }} },
776 { "A2, M (Korea)",
777 { 9, { TDA9874A_C1FRA, 0x5D,0xC0,0x00, 0x62,0x6A,0xAA, 0x20,0x22 }} },
778 { "A2, D/K (1)",
779 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x82,0x60,0x00, 0x00,0x00 }} },
780 { "A2, D/K (2)",
781 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x8C,0x75,0x55, 0x00,0x00 }} },
782 { "A2, D/K (3)",
783 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x77,0xA0,0x00, 0x00,0x00 }} },
784 { "NICAM, I",
785 { 9, { TDA9874A_C1FRA, 0x7D,0x00,0x00, 0x88,0x8A,0xAA, 0x08,0x33 }} },
786 { "NICAM, B/G",
787 { 9, { TDA9874A_C1FRA, 0x72,0x95,0x55, 0x79,0xEA,0xAA, 0x08,0x33 }} },
04e6f990 788 { "NICAM, D/K",
1da177e4
LT		 789 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x79,0xEA,0xAA, 0x08,0x33 }} },
790 { "NICAM, L",
791 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x79,0xEA,0xAA, 0x09,0x33 }} }
792};
793
794static int tda9874a_setup(struct CHIPSTATE *chip)
795{
796 chip_write(chip, TDA9874A_AGCGR, 0x00); /* 0 dB */
797 chip_write(chip, TDA9874A_GCONR, tda9874a_GCONR);
798 chip_write(chip, TDA9874A_MSR, (tda9874a_mode) ? 0x03:0x02);
799 if(tda9874a_dic == 0x11) {
800 chip_write(chip, TDA9874A_FMMR, 0x80);
801 } else { /* dic == 0x07 */
802 chip_cmd(chip,"tda9874_modelist",&tda9874a_modelist[tda9874a_STD].cmd);
803 chip_write(chip, TDA9874A_FMMR, 0x00);
804 }
805 chip_write(chip, TDA9874A_C1OLAR, 0x00); /* 0 dB */
806 chip_write(chip, TDA9874A_C2OLAR, 0x00); /* 0 dB */
807 chip_write(chip, TDA9874A_NCONR, tda9874a_NCONR);
808 chip_write(chip, TDA9874A_NOLAR, 0x00); /* 0 dB */
809 /* Note: If signal quality is poor you may want to change NICAM */
810 /* error limit registers (NLELR and NUELR) to some greater values. */
811 /* Then the sound would remain stereo, but won't be so clear. */
812 chip_write(chip, TDA9874A_NLELR, 0x14); /* default */
813 chip_write(chip, TDA9874A_NUELR, 0x50); /* default */
814
815 if(tda9874a_dic == 0x11) {
816 chip_write(chip, TDA9874A_AMCONR, 0xf9);
817 chip_write(chip, TDA9874A_SDACOSR, (tda9874a_mode) ? 0x81:0x80);
818 chip_write(chip, TDA9874A_AOSR, 0x80);
819 chip_write(chip, TDA9874A_MDACOSR, (tda9874a_mode) ? 0x82:0x80);
820 chip_write(chip, TDA9874A_ESP, tda9874a_ESP);
821 } else { /* dic == 0x07 */
822 chip_write(chip, TDA9874A_AMCONR, 0xfb);
823 chip_write(chip, TDA9874A_SDACOSR, (tda9874a_mode) ? 0x81:0x80);
18fc59e2 824 chip_write(chip, TDA9874A_AOSR, 0x00); /* or 0x10 */
1da177e4 825 }
08e14054 826 v4l_dbg(1, debug, chip->c, "tda9874a_setup(): %s [0x%02X].\n",
1da177e4
LT		 827 tda9874a_modelist[tda9874a_STD].name,tda9874a_STD);
828 return 1;
829}
830
831static int tda9874a_getmode(struct CHIPSTATE *chip)
832{
833 int dsr,nsr,mode;
834 int necr; /* just for debugging */
835
dc3d75da 836 mode = V4L2_TUNER_MODE_MONO;
1da177e4
LT		 837
838 if(-1 == (dsr = chip_read2(chip,TDA9874A_DSR)))
839 return mode;
840 if(-1 == (nsr = chip_read2(chip,TDA9874A_NSR)))
841 return mode;
842 if(-1 == (necr = chip_read2(chip,TDA9874A_NECR)))
843 return mode;
844
845 /* need to store dsr/nsr somewhere */
846 chip->shadow.bytes[MAXREGS-2] = dsr;
847 chip->shadow.bytes[MAXREGS-1] = nsr;
848
849 if(tda9874a_mode) {
850 /* Note: DSR.RSSF and DSR.AMSTAT bits are also checked.
851 * If NICAM auto-muting is enabled, DSR.AMSTAT=1 indicates
852 * that sound has (temporarily) switched from NICAM to
853 * mono FM (or AM) on 1st sound carrier due to high NICAM bit
854 * error count. So in fact there is no stereo in this case :-(
dc3d75da 855 * But changing the mode to V4L2_TUNER_MODE_MONO would switch
1da177e4
LT		 856 * external 4052 multiplexer in audio_hook().
857 */
1da177e4 858 if(nsr & 0x02) /* NSR.S/MB=1 */
dc3d75da 859 mode |= V4L2_TUNER_MODE_STEREO;
1da177e4 860 if(nsr & 0x01) /* NSR.D/SB=1 */
dc3d75da 861 mode |= V4L2_TUNER_MODE_LANG1 | V4L2_TUNER_MODE_LANG2;
1da177e4
LT		 862 } else {
863 if(dsr & 0x02) /* DSR.IDSTE=1 */
dc3d75da 864 mode |= V4L2_TUNER_MODE_STEREO;
1da177e4 865 if(dsr & 0x04) /* DSR.IDDUA=1 */
dc3d75da 866 mode |= V4L2_TUNER_MODE_LANG1 | V4L2_TUNER_MODE_LANG2;
1da177e4
LT		 867 }
868
08e14054 869 v4l_dbg(1, debug, chip->c, "tda9874a_getmode(): DSR=0x%X, NSR=0x%X, NECR=0x%X, return: %d.\n",
1da177e4
LT		 870 dsr, nsr, necr, mode);
871 return mode;
872}
873
874static void tda9874a_setmode(struct CHIPSTATE *chip, int mode)
875{
876 /* Disable/enable NICAM auto-muting (based on DSR.RSSF status bit). */
877 /* If auto-muting is disabled, we can hear a signal of degrading quality. */
878 if(tda9874a_mode) {
879 if(chip->shadow.bytes[MAXREGS-2] & 0x20) /* DSR.RSSF=1 */
880 tda9874a_NCONR &= 0xfe; /* enable */
881 else
882 tda9874a_NCONR |= 0x01; /* disable */
883 chip_write(chip, TDA9874A_NCONR, tda9874a_NCONR);
884 }
885
886 /* Note: TDA9874A supports automatic FM dematrixing (FMMR register)
887 * and has auto-select function for audio output (AOSR register).
888 * Old TDA9874H doesn't support these features.
889 * TDA9874A also has additional mono output pin (OUTM), which
890 * on same (all?) tv-cards is not used, anyway (as well as MONOIN).
891 */
892 if(tda9874a_dic == 0x11) {
893 int aosr = 0x80;
894 int mdacosr = (tda9874a_mode) ? 0x82:0x80;
895
896 switch(mode) {
dc3d75da
MCC		 897 case V4L2_TUNER_MODE_MONO:
898 case V4L2_TUNER_MODE_STEREO:
1da177e4 899 break;
dc3d75da 900 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 901 aosr = 0x80; /* auto-select, dual A/A */
902 mdacosr = (tda9874a_mode) ? 0x82:0x80;
903 break;
dc3d75da 904 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 905 aosr = 0xa0; /* auto-select, dual B/B */
906 mdacosr = (tda9874a_mode) ? 0x83:0x81;
907 break;
908 default:
909 chip->mode = 0;
910 return;
911 }
912 chip_write(chip, TDA9874A_AOSR, aosr);
913 chip_write(chip, TDA9874A_MDACOSR, mdacosr);
914
08e14054 915 v4l_dbg(1, debug, chip->c, "tda9874a_setmode(): req. mode %d; AOSR=0x%X, MDACOSR=0x%X.\n",
1da177e4
LT		 916 mode, aosr, mdacosr);
917
918 } else { /* dic == 0x07 */
919 int fmmr,aosr;
920
921 switch(mode) {
dc3d75da 922 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 923 fmmr = 0x00; /* mono */
924 aosr = 0x10; /* A/A */
925 break;
dc3d75da 926 case V4L2_TUNER_MODE_STEREO:
1da177e4
LT		 927 if(tda9874a_mode) {
928 fmmr = 0x00;
929 aosr = 0x00; /* handled by NICAM auto-mute */
930 } else {
931 fmmr = (tda9874a_ESP == 1) ? 0x05 : 0x04; /* stereo */
932 aosr = 0x00;
933 }
934 break;
dc3d75da 935 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 936 fmmr = 0x02; /* dual */
937 aosr = 0x10; /* dual A/A */
938 break;
dc3d75da 939 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 940 fmmr = 0x02; /* dual */
941 aosr = 0x20; /* dual B/B */
942 break;
943 default:
944 chip->mode = 0;
945 return;
946 }
947 chip_write(chip, TDA9874A_FMMR, fmmr);
948 chip_write(chip, TDA9874A_AOSR, aosr);
949
08e14054 950 v4l_dbg(1, debug, chip->c, "tda9874a_setmode(): req. mode %d; FMMR=0x%X, AOSR=0x%X.\n",
1da177e4
LT		 951 mode, fmmr, aosr);
952 }
953}
954
955static int tda9874a_checkit(struct CHIPSTATE *chip)
956{
957 int dic,sic; /* device id. and software id. codes */
958
959 if(-1 == (dic = chip_read2(chip,TDA9874A_DIC)))
960 return 0;
961 if(-1 == (sic = chip_read2(chip,TDA9874A_SIC)))
962 return 0;
963
08e14054 964 v4l_dbg(1, debug, chip->c, "tda9874a_checkit(): DIC=0x%X, SIC=0x%X.\n", dic, sic);
1da177e4
LT		 965
966 if((dic == 0x11)||(dic == 0x07)) {
08e14054 967 v4l_info(chip->c, "found tda9874%s.\n", (dic == 0x11) ? "a":"h");
1da177e4
LT		 968 tda9874a_dic = dic; /* remember device id. */
969 return 1;
970 }
971 return 0; /* not found */
972}
973
974static int tda9874a_initialize(struct CHIPSTATE *chip)
975{
976 if (tda9874a_SIF > 2)
977 tda9874a_SIF = 1;
04e6f990 978 if (tda9874a_STD >= ARRAY_SIZE(tda9874a_modelist))
1da177e4
LT		 979 tda9874a_STD = 0;
980 if(tda9874a_AMSEL > 1)
981 tda9874a_AMSEL = 0;
982
983 if(tda9874a_SIF == 1)
984 tda9874a_GCONR = 0xc0; /* sound IF input 1 */
985 else
986 tda9874a_GCONR = 0xc1; /* sound IF input 2 */
987
988 tda9874a_ESP = tda9874a_STD;
989 tda9874a_mode = (tda9874a_STD < 5) ? 0 : 1;
990
991 if(tda9874a_AMSEL == 0)
992 tda9874a_NCONR = 0x01; /* auto-mute: analog mono input */
993 else
994 tda9874a_NCONR = 0x05; /* auto-mute: 1st carrier FM or AM */
995
996 tda9874a_setup(chip);
997 return 0;
998}
999
1000
1001/* ---------------------------------------------------------------------- */
1002/* audio chip descriptions - defines+functions for tea6420 */
1003
1004#define TEA6300_VL 0x00 /* volume left */
1005#define TEA6300_VR 0x01 /* volume right */
1006#define TEA6300_BA 0x02 /* bass */
1007#define TEA6300_TR 0x03 /* treble */
1008#define TEA6300_FA 0x04 /* fader control */
1009#define TEA6300_S 0x05 /* switch register */
f2421ca3 1010 /* values for those registers: */
1da177e4
LT		 1011#define TEA6300_S_SA 0x01 /* stereo A input */
1012#define TEA6300_S_SB 0x02 /* stereo B */
1013#define TEA6300_S_SC 0x04 /* stereo C */
1014#define TEA6300_S_GMU 0x80 /* general mute */
1015
1016#define TEA6320_V 0x00 /* volume (0-5)/loudness off (6)/zero crossing mute(7) */
1017#define TEA6320_FFR 0x01 /* fader front right (0-5) */
1018#define TEA6320_FFL 0x02 /* fader front left (0-5) */
1019#define TEA6320_FRR 0x03 /* fader rear right (0-5) */
1020#define TEA6320_FRL 0x04 /* fader rear left (0-5) */
1021#define TEA6320_BA 0x05 /* bass (0-4) */
1022#define TEA6320_TR 0x06 /* treble (0-4) */
1023#define TEA6320_S 0x07 /* switch register */
f2421ca3 1024 /* values for those registers: */
1da177e4
LT		 1025#define TEA6320_S_SA 0x07 /* stereo A input */
1026#define TEA6320_S_SB 0x06 /* stereo B */
1027#define TEA6320_S_SC 0x05 /* stereo C */
1028#define TEA6320_S_SD 0x04 /* stereo D */
1029#define TEA6320_S_GMU 0x80 /* general mute */
1030
1031#define TEA6420_S_SA 0x00 /* stereo A input */
1032#define TEA6420_S_SB 0x01 /* stereo B */
1033#define TEA6420_S_SC 0x02 /* stereo C */
1034#define TEA6420_S_SD 0x03 /* stereo D */
1035#define TEA6420_S_SE 0x04 /* stereo E */
1036#define TEA6420_S_GMU 0x05 /* general mute */
1037
1038static int tea6300_shift10(int val) { return val >> 10; }
1039static int tea6300_shift12(int val) { return val >> 12; }
1040
1041/* Assumes 16bit input (values 0x3f to 0x0c are unique, values less than */
1042/* 0x0c mirror those immediately higher) */
1043static int tea6320_volume(int val) { return (val / (65535/(63-12)) + 12) & 0x3f; }
1044static int tea6320_shift11(int val) { return val >> 11; }
1045static int tea6320_initialize(struct CHIPSTATE * chip)
1046{
1047 chip_write(chip, TEA6320_FFR, 0x3f);
1048 chip_write(chip, TEA6320_FFL, 0x3f);
1049 chip_write(chip, TEA6320_FRR, 0x3f);
1050 chip_write(chip, TEA6320_FRL, 0x3f);
1051
1052 return 0;
1053}
1054
1055
1056/* ---------------------------------------------------------------------- */
1057/* audio chip descriptions - defines+functions for tda8425 */
1058
1059#define TDA8425_VL 0x00 /* volume left */
1060#define TDA8425_VR 0x01 /* volume right */
1061#define TDA8425_BA 0x02 /* bass */
1062#define TDA8425_TR 0x03 /* treble */
1063#define TDA8425_S1 0x08 /* switch functions */
f2421ca3 1064 /* values for those registers: */
1da177e4
LT		 1065#define TDA8425_S1_OFF 0xEE /* audio off (mute on) */
1066#define TDA8425_S1_CH1 0xCE /* audio channel 1 (mute off) - "linear stereo" mode */
1067#define TDA8425_S1_CH2 0xCF /* audio channel 2 (mute off) - "linear stereo" mode */
1068#define TDA8425_S1_MU 0x20 /* mute bit */
1069#define TDA8425_S1_STEREO 0x18 /* stereo bits */
1070#define TDA8425_S1_STEREO_SPATIAL 0x18 /* spatial stereo */
1071#define TDA8425_S1_STEREO_LINEAR 0x08 /* linear stereo */
1072#define TDA8425_S1_STEREO_PSEUDO 0x10 /* pseudo stereo */
1073#define TDA8425_S1_STEREO_MONO 0x00 /* forced mono */
1074#define TDA8425_S1_ML 0x06 /* language selector */
1075#define TDA8425_S1_ML_SOUND_A 0x02 /* sound a */
1076#define TDA8425_S1_ML_SOUND_B 0x04 /* sound b */
1077#define TDA8425_S1_ML_STEREO 0x06 /* stereo */
1078#define TDA8425_S1_IS 0x01 /* channel selector */
1079
1080
1081static int tda8425_shift10(int val) { return (val >> 10) | 0xc0; }
1082static int tda8425_shift12(int val) { return (val >> 12) | 0xf0; }
1083
1084static int tda8425_initialize(struct CHIPSTATE *chip)
1085{
1086 struct CHIPDESC *desc = chiplist + chip->type;
8bf2f8e7
HV		 1087 int inputmap[4] = { /* tuner */ TDA8425_S1_CH2, /* radio */ TDA8425_S1_CH1,
1088 /* extern */ TDA8425_S1_CH1, /* intern */ TDA8425_S1_OFF};
1da177e4 1089
08e14054 1090 if (chip->c->adapter->id == I2C_HW_B_RIVA) {
1da177e4
LT		 1091 memcpy (desc->inputmap, inputmap, sizeof (inputmap));
1092 }
1093 return 0;
1094}
1095
1096static void tda8425_setmode(struct CHIPSTATE *chip, int mode)
1097{
1098 int s1 = chip->shadow.bytes[TDA8425_S1+1] & 0xe1;
1099
dc3d75da 1100 if (mode & V4L2_TUNER_MODE_LANG1) {
1da177e4
LT		 1101 s1 |= TDA8425_S1_ML_SOUND_A;
1102 s1 |= TDA8425_S1_STEREO_PSEUDO;
1103
dc3d75da 1104 } else if (mode & V4L2_TUNER_MODE_LANG2) {
1da177e4
LT		 1105 s1 |= TDA8425_S1_ML_SOUND_B;
1106 s1 |= TDA8425_S1_STEREO_PSEUDO;
1107
1108 } else {
1109 s1 |= TDA8425_S1_ML_STEREO;
1110
dc3d75da 1111 if (mode & V4L2_TUNER_MODE_MONO)
1da177e4 1112 s1 |= TDA8425_S1_STEREO_MONO;
dc3d75da 1113 if (mode & V4L2_TUNER_MODE_STEREO)
1da177e4
LT		 1114 s1 |= TDA8425_S1_STEREO_SPATIAL;
1115 }
1116 chip_write(chip,TDA8425_S1,s1);
1117}
1118
1119
1120/* ---------------------------------------------------------------------- */
1121/* audio chip descriptions - defines+functions for pic16c54 (PV951) */
1122
1123/* the registers of 16C54, I2C sub address. */
1124#define PIC16C54_REG_KEY_CODE 0x01 /* Not use. */
1125#define PIC16C54_REG_MISC 0x02
1126
1127/* bit definition of the RESET register, I2C data. */
1128#define PIC16C54_MISC_RESET_REMOTE_CTL 0x01 /* bit 0, Reset to receive the key */
f2421ca3 1129 /* code of remote controller */
1da177e4
LT		 1130#define PIC16C54_MISC_MTS_MAIN 0x02 /* bit 1 */
1131#define PIC16C54_MISC_MTS_SAP 0x04 /* bit 2 */
1132#define PIC16C54_MISC_MTS_BOTH 0x08 /* bit 3 */
1133#define PIC16C54_MISC_SND_MUTE 0x10 /* bit 4, Mute Audio(Line-in and Tuner) */
1134#define PIC16C54_MISC_SND_NOTMUTE 0x20 /* bit 5 */
1135#define PIC16C54_MISC_SWITCH_TUNER 0x40 /* bit 6 , Switch to Line-in */
1136#define PIC16C54_MISC_SWITCH_LINE 0x80 /* bit 7 , Switch to Tuner */
1137
1138/* ---------------------------------------------------------------------- */
1139/* audio chip descriptions - defines+functions for TA8874Z */
1140
18fc59e2 1141/* write 1st byte */
1da177e4
LT		 1142#define TA8874Z_LED_STE 0x80
1143#define TA8874Z_LED_BIL 0x40
1144#define TA8874Z_LED_EXT 0x20
1145#define TA8874Z_MONO_SET 0x10
1146#define TA8874Z_MUTE 0x08
1147#define TA8874Z_F_MONO 0x04
1148#define TA8874Z_MODE_SUB 0x02
1149#define TA8874Z_MODE_MAIN 0x01
1150
18fc59e2
MCC		 1151/* write 2nd byte */
1152/*#define TA8874Z_TI 0x80 */ /* test mode */
1da177e4
LT		 1153#define TA8874Z_SEPARATION 0x3f
1154#define TA8874Z_SEPARATION_DEFAULT 0x10
1155
18fc59e2 1156/* read */
1da177e4
LT		 1157#define TA8874Z_B1 0x80
1158#define TA8874Z_B0 0x40
1159#define TA8874Z_CHAG_FLAG 0x20
1160
18fc59e2
MCC		 1161/*
1162 * B1 B0
1163 * mono L H
1164 * stereo L L
1165 * BIL H L
1166 */
1da177e4
LT		 1167static int ta8874z_getmode(struct CHIPSTATE *chip)
1168{
1169 int val, mode;
1170
1171 val = chip_read(chip);
dc3d75da 1172 mode = V4L2_TUNER_MODE_MONO;
1da177e4 1173 if (val & TA8874Z_B1){
dc3d75da 1174 mode |= V4L2_TUNER_MODE_LANG1 | V4L2_TUNER_MODE_LANG2;
1da177e4 1175 }else if (!(val & TA8874Z_B0)){
dc3d75da 1176 mode |= V4L2_TUNER_MODE_STEREO;
1da177e4 1177 }
08e14054 1178 /* v4l_dbg(1, debug, chip->c, "ta8874z_getmode(): raw chip read: 0x%02x, return: 0x%02x\n", val, mode); */
1da177e4
LT		 1179 return mode;
1180}
1181
1182static audiocmd ta8874z_stereo = { 2, {0, TA8874Z_SEPARATION_DEFAULT}};
1183static audiocmd ta8874z_mono = {2, { TA8874Z_MONO_SET, TA8874Z_SEPARATION_DEFAULT}};
1184static audiocmd ta8874z_main = {2, { 0, TA8874Z_SEPARATION_DEFAULT}};
1185static audiocmd ta8874z_sub = {2, { TA8874Z_MODE_SUB, TA8874Z_SEPARATION_DEFAULT}};
1186
1187static void ta8874z_setmode(struct CHIPSTATE *chip, int mode)
1188{
1189 int update = 1;
1190 audiocmd *t = NULL;
08e14054 1191 v4l_dbg(1, debug, chip->c, "ta8874z_setmode(): mode: 0x%02x\n", mode);
1da177e4
LT		 1192
1193 switch(mode){
dc3d75da 1194 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 1195 t = &ta8874z_mono;
1196 break;
dc3d75da 1197 case V4L2_TUNER_MODE_STEREO:
1da177e4
LT		 1198 t = &ta8874z_stereo;
1199 break;
dc3d75da 1200 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 1201 t = &ta8874z_main;
1202 break;
dc3d75da 1203 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 1204 t = &ta8874z_sub;
1205 break;
1206 default:
1207 update = 0;
1208 }
1209
1210 if(update)
1211 chip_cmd(chip, "TA8874Z", t);
1212}
1213
1214static int ta8874z_checkit(struct CHIPSTATE *chip)
1215{
1216 int rc;
1217 rc = chip_read(chip);
1218 return ((rc & 0x1f) == 0x1f) ? 1 : 0;
1219}
1220
1221/* ---------------------------------------------------------------------- */
1222/* audio chip descriptions - struct CHIPDESC */
1223
1224/* insmod options to enable/disable individual audio chips */
52c1da39
AB		 1225static int tda8425 = 1;
1226static int tda9840 = 1;
1227static int tda9850 = 1;
1228static int tda9855 = 1;
1229static int tda9873 = 1;
1230static int tda9874a = 1;
ff699e6b
DSL		 1231static int tea6300; /* default 0 - address clash with msp34xx */
1232static int tea6320; /* default 0 - address clash with msp34xx */
52c1da39
AB		 1233static int tea6420 = 1;
1234static int pic16c54 = 1;
ff699e6b 1235static int ta8874z; /* default 0 - address clash with tda9840 */
1da177e4
LT		 1236
1237module_param(tda8425, int, 0444);
1238module_param(tda9840, int, 0444);
1239module_param(tda9850, int, 0444);
1240module_param(tda9855, int, 0444);
1241module_param(tda9873, int, 0444);
1242module_param(tda9874a, int, 0444);
1243module_param(tea6300, int, 0444);
1244module_param(tea6320, int, 0444);
1245module_param(tea6420, int, 0444);
1246module_param(pic16c54, int, 0444);
1247module_param(ta8874z, int, 0444);
1248
1249static struct CHIPDESC chiplist[] = {
1250 {
1251 .name = "tda9840",
1da177e4 1252 .insmodopt = &tda9840,
09df1c16
MCC		 1253 .addr_lo = I2C_ADDR_TDA9840 >> 1,
1254 .addr_hi = I2C_ADDR_TDA9840 >> 1,
1da177e4 1255 .registers = 5,
dd03e970 1256 .flags = CHIP_NEED_CHECKMODE,
1da177e4 1257
af1a9951 1258 /* callbacks */
94f9e56e 1259 .checkit = tda9840_checkit,
1da177e4
LT		 1260 .getmode = tda9840_getmode,
1261 .setmode = tda9840_setmode,
1da177e4 1262
4ac97914 1263 .init = { 2, { TDA9840_TEST, TDA9840_TEST_INT1SN
1da177e4
LT		 1264 /* ,TDA9840_SW, TDA9840_MONO */} }
1265 },
1266 {
1267 .name = "tda9873h",
1da177e4 1268 .insmodopt = &tda9873,
09df1c16
MCC		 1269 .addr_lo = I2C_ADDR_TDA985x_L >> 1,
1270 .addr_hi = I2C_ADDR_TDA985x_H >> 1,
1da177e4 1271 .registers = 3,
dd03e970 1272 .flags = CHIP_HAS_INPUTSEL | CHIP_NEED_CHECKMODE,
1da177e4 1273
af1a9951
MCC		 1274 /* callbacks */
1275 .checkit = tda9873_checkit,
1da177e4
LT		 1276 .getmode = tda9873_getmode,
1277 .setmode = tda9873_setmode,
1da177e4
LT		 1278
1279 .init = { 4, { TDA9873_SW, 0xa4, 0x06, 0x03 } },
1280 .inputreg = TDA9873_SW,
1281 .inputmute = TDA9873_MUTE | TDA9873_AUTOMUTE,
8bf2f8e7 1282 .inputmap = {0xa0, 0xa2, 0xa0, 0xa0},
1da177e4
LT		 1283 .inputmask = TDA9873_INP_MASK|TDA9873_MUTE|TDA9873_AUTOMUTE,
1284
1285 },
1286 {
1287 .name = "tda9874h/a",
1da177e4 1288 .insmodopt = &tda9874a,
09df1c16
MCC		 1289 .addr_lo = I2C_ADDR_TDA9874 >> 1,
1290 .addr_hi = I2C_ADDR_TDA9874 >> 1,
dd03e970 1291 .flags = CHIP_NEED_CHECKMODE,
1da177e4 1292
af1a9951
MCC		 1293 /* callbacks */
1294 .initialize = tda9874a_initialize,
1295 .checkit = tda9874a_checkit,
1da177e4
LT		 1296 .getmode = tda9874a_getmode,
1297 .setmode = tda9874a_setmode,
1da177e4
LT		 1298 },
1299 {
1300 .name = "tda9850",
1da177e4 1301 .insmodopt = &tda9850,
09df1c16
MCC		 1302 .addr_lo = I2C_ADDR_TDA985x_L >> 1,
1303 .addr_hi = I2C_ADDR_TDA985x_H >> 1,
1da177e4
LT		 1304 .registers = 11,
1305
1306 .getmode = tda985x_getmode,
1307 .setmode = tda985x_setmode,
1308
1309 .init = { 8, { TDA9850_C4, 0x08, 0x08, TDA985x_STEREO, 0x07, 0x10, 0x10, 0x03 } }
1310 },
1311 {
1312 .name = "tda9855",
1da177e4 1313 .insmodopt = &tda9855,
09df1c16
MCC		 1314 .addr_lo = I2C_ADDR_TDA985x_L >> 1,
1315 .addr_hi = I2C_ADDR_TDA985x_H >> 1,
1da177e4
LT		 1316 .registers = 11,
1317 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE,
1318
1319 .leftreg = TDA9855_VL,
1320 .rightreg = TDA9855_VR,
1321 .bassreg = TDA9855_BA,
1322 .treblereg = TDA9855_TR,
af1a9951
MCC		 1323
1324 /* callbacks */
1da177e4
LT		 1325 .volfunc = tda9855_volume,
1326 .bassfunc = tda9855_bass,
1327 .treblefunc = tda9855_treble,
1da177e4
LT		 1328 .getmode = tda985x_getmode,
1329 .setmode = tda985x_setmode,
1330
1331 .init = { 12, { 0, 0x6f, 0x6f, 0x0e, 0x07<<1, 0x8<<2,
1332 TDA9855_MUTE | TDA9855_AVL | TDA9855_LOUD | TDA9855_INT,
1333 TDA985x_STEREO | TDA9855_LINEAR | TDA9855_TZCM | TDA9855_VZCM,
1334 0x07, 0x10, 0x10, 0x03 }}
1335 },
1336 {
1337 .name = "tea6300",
1da177e4 1338 .insmodopt = &tea6300,
09df1c16
MCC		 1339 .addr_lo = I2C_ADDR_TEA6300 >> 1,
1340 .addr_hi = I2C_ADDR_TEA6300 >> 1,
1da177e4
LT		 1341 .registers = 6,
1342 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE | CHIP_HAS_INPUTSEL,
1343
1344 .leftreg = TEA6300_VR,
1345 .rightreg = TEA6300_VL,
1346 .bassreg = TEA6300_BA,
1347 .treblereg = TEA6300_TR,
af1a9951
MCC		 1348
1349 /* callbacks */
1da177e4
LT		 1350 .volfunc = tea6300_shift10,
1351 .bassfunc = tea6300_shift12,
1352 .treblefunc = tea6300_shift12,
1353
1354 .inputreg = TEA6300_S,
1355 .inputmap = { TEA6300_S_SA, TEA6300_S_SB, TEA6300_S_SC },
1356 .inputmute = TEA6300_S_GMU,
1357 },
1358 {
1359 .name = "tea6320",
1da177e4 1360 .insmodopt = &tea6320,
09df1c16
MCC		 1361 .addr_lo = I2C_ADDR_TEA6300 >> 1,
1362 .addr_hi = I2C_ADDR_TEA6300 >> 1,
1da177e4
LT		 1363 .registers = 8,
1364 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE | CHIP_HAS_INPUTSEL,
1365
1366 .leftreg = TEA6320_V,
1367 .rightreg = TEA6320_V,
1368 .bassreg = TEA6320_BA,
1369 .treblereg = TEA6320_TR,
af1a9951
MCC		 1370
1371 /* callbacks */
1372 .initialize = tea6320_initialize,
1da177e4
LT		 1373 .volfunc = tea6320_volume,
1374 .bassfunc = tea6320_shift11,
1375 .treblefunc = tea6320_shift11,
1376
1377 .inputreg = TEA6320_S,
1378 .inputmap = { TEA6320_S_SA, TEA6420_S_SB, TEA6300_S_SC, TEA6320_S_SD },
1379 .inputmute = TEA6300_S_GMU,
1380 },
1381 {
1382 .name = "tea6420",
1da177e4 1383 .insmodopt = &tea6420,
09df1c16
MCC		 1384 .addr_lo = I2C_ADDR_TEA6420 >> 1,
1385 .addr_hi = I2C_ADDR_TEA6420 >> 1,
1da177e4
LT		 1386 .registers = 1,
1387 .flags = CHIP_HAS_INPUTSEL,
1388
1389 .inputreg = -1,
1390 .inputmap = { TEA6420_S_SA, TEA6420_S_SB, TEA6420_S_SC },
1391 .inputmute = TEA6300_S_GMU,
1392 },
1393 {
1394 .name = "tda8425",
1da177e4 1395 .insmodopt = &tda8425,
09df1c16
MCC		 1396 .addr_lo = I2C_ADDR_TDA8425 >> 1,
1397 .addr_hi = I2C_ADDR_TDA8425 >> 1,
1da177e4
LT		 1398 .registers = 9,
1399 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE | CHIP_HAS_INPUTSEL,
1400
1401 .leftreg = TDA8425_VL,
1402 .rightreg = TDA8425_VR,
1403 .bassreg = TDA8425_BA,
1404 .treblereg = TDA8425_TR,
af1a9951
MCC		 1405
1406 /* callbacks */
1407 .initialize = tda8425_initialize,
1da177e4
LT		 1408 .volfunc = tda8425_shift10,
1409 .bassfunc = tda8425_shift12,
1410 .treblefunc = tda8425_shift12,
af1a9951 1411 .setmode = tda8425_setmode,
1da177e4
LT		 1412
1413 .inputreg = TDA8425_S1,
1414 .inputmap = { TDA8425_S1_CH1, TDA8425_S1_CH1, TDA8425_S1_CH1 },
1415 .inputmute = TDA8425_S1_OFF,
1416
1da177e4
LT		 1417 },
1418 {
1419 .name = "pic16c54 (PV951)",
1da177e4 1420 .insmodopt = &pic16c54,
09df1c16
MCC		 1421 .addr_lo = I2C_ADDR_PIC16C54 >> 1,
1422 .addr_hi = I2C_ADDR_PIC16C54>> 1,
1da177e4
LT		 1423 .registers = 2,
1424 .flags = CHIP_HAS_INPUTSEL,
1425
1426 .inputreg = PIC16C54_REG_MISC,
1427 .inputmap = {PIC16C54_MISC_SND_NOTMUTE|PIC16C54_MISC_SWITCH_TUNER,
1428 PIC16C54_MISC_SND_NOTMUTE|PIC16C54_MISC_SWITCH_LINE,
1429 PIC16C54_MISC_SND_NOTMUTE|PIC16C54_MISC_SWITCH_LINE,
8bf2f8e7 1430 PIC16C54_MISC_SND_MUTE},
1da177e4
LT		 1431 .inputmute = PIC16C54_MISC_SND_MUTE,
1432 },
1433 {
1434 .name = "ta8874z",
1da177e4
LT		 1435 .checkit = ta8874z_checkit,
1436 .insmodopt = &ta8874z,
09df1c16
MCC		 1437 .addr_lo = I2C_ADDR_TDA9840 >> 1,
1438 .addr_hi = I2C_ADDR_TDA9840 >> 1,
1da177e4 1439 .registers = 2,
dd03e970 1440 .flags = CHIP_NEED_CHECKMODE,
1da177e4 1441
af1a9951 1442 /* callbacks */
1da177e4
LT		 1443 .getmode = ta8874z_getmode,
1444 .setmode = ta8874z_setmode,
1da177e4 1445
4ac97914 1446 .init = {2, { TA8874Z_MONO_SET, TA8874Z_SEPARATION_DEFAULT}},
1da177e4
LT		 1447 },
1448 { .name = NULL } /* EOF */
1449};
1450
1451
1452/* ---------------------------------------------------------------------- */
1453/* i2c registration */
1454
d2653e92 1455static int chip_probe(struct i2c_client *client, const struct i2c_device_id *id)
1da177e4
LT		 1456{
1457 struct CHIPSTATE *chip;
1458 struct CHIPDESC *desc;
1459
08e14054
HV		 1460 if (debug) {
1461 printk(KERN_INFO "tvaudio: TV audio decoder + audio/video mux driver\n");
1462 printk(KERN_INFO "tvaudio: known chips: ");
1463 for (desc = chiplist; desc->name != NULL; desc++)
1464 printk("%s%s", (desc == chiplist) ? "" : ", ", desc->name);
1465 printk("\n");
1466 }
1467
7408187d 1468 chip = kzalloc(sizeof(*chip),GFP_KERNEL);
1da177e4
LT		 1469 if (!chip)
1470 return -ENOMEM;
08e14054
HV		 1471 chip->c = client;
1472 i2c_set_clientdata(client, chip);
1da177e4
LT		 1473
1474 /* find description for the chip */
08e14054 1475 v4l_dbg(1, debug, client, "chip found @ 0x%x\n", client->addr<<1);
1da177e4
LT		 1476 for (desc = chiplist; desc->name != NULL; desc++) {
1477 if (0 == *(desc->insmodopt))
1478 continue;
08e14054
HV		 1479 if (client->addr < desc->addr_lo ||
1480 client->addr > desc->addr_hi)
1da177e4
LT		 1481 continue;
1482 if (desc->checkit && !desc->checkit(chip))
1483 continue;
1484 break;
1485 }
1486 if (desc->name == NULL) {
08e14054 1487 v4l_dbg(1, debug, client, "no matching chip description found\n");
5c653351 1488 kfree(chip);
1da177e4
LT		 1489 return -EIO;
1490 }
08e14054 1491 v4l_info(client, "%s found @ 0x%x (%s)\n", desc->name, client->addr<<1, client->adapter->name);
afd1a0c9 1492 if (desc->flags) {
08e14054 1493 v4l_dbg(1, debug, client, "matches:%s%s%s.\n",
674434c6
MCC		 1494 (desc->flags & CHIP_HAS_VOLUME) ? " volume" : "",
1495 (desc->flags & CHIP_HAS_BASSTREBLE) ? " bass/treble" : "",
1496 (desc->flags & CHIP_HAS_INPUTSEL) ? " audiomux" : "");
afd1a0c9 1497 }
1da177e4
LT		 1498
1499 /* fill required data structures */
ae429083
JD		 1500 if (!id)
1501 strlcpy(client->name, desc->name, I2C_NAME_SIZE);
1da177e4
LT		 1502 chip->type = desc-chiplist;
1503 chip->shadow.count = desc->registers+1;
afd1a0c9 1504 chip->prevmode = -1;
8a4b275f 1505 chip->audmode = V4L2_TUNER_MODE_LANG1;
1da177e4
LT		 1506
1507 /* initialization */
1508 if (desc->initialize != NULL)
1509 desc->initialize(chip);
1510 else
1511 chip_cmd(chip,"init",&desc->init);
1512
1513 if (desc->flags & CHIP_HAS_VOLUME) {
099b7fcc
MCC		 1514 if (!desc->volfunc) {
1515 /* This shouldn't be happen. Warn user, but keep working
1516 without volume controls
1517 */
1518 v4l_info(chip->c, "volume callback undefined!\n");
1519 desc->flags &= ~CHIP_HAS_VOLUME;
1520 } else {
1521 chip->left = desc->leftinit ? desc->leftinit : 65535;
1522 chip->right = desc->rightinit ? desc->rightinit : 65535;
1523 chip_write(chip, desc->leftreg,
1524 desc->volfunc(chip->left));
1525 chip_write(chip, desc->rightreg,
1526 desc->volfunc(chip->right));
1527 }
1da177e4
LT		 1528 }
1529 if (desc->flags & CHIP_HAS_BASSTREBLE) {
099b7fcc
MCC		 1530 if (!desc->bassfunc || !desc->treblefunc) {
1531 /* This shouldn't be happen. Warn user, but keep working
1532 without bass/treble controls
1533 */
1534 v4l_info(chip->c, "bass/treble callbacks undefined!\n");
1535 desc->flags &= ~CHIP_HAS_BASSTREBLE;
1536 } else {
1537 chip->treble = desc->trebleinit ?
1538 desc->trebleinit : 32768;
1539 chip->bass = desc->bassinit ?
1540 desc->bassinit : 32768;
1541 chip_write(chip, desc->bassreg,
1542 desc->bassfunc(chip->bass));
1543 chip_write(chip, desc->treblereg,
1544 desc->treblefunc(chip->treble));
1545 }
1da177e4
LT		 1546 }
1547
bc282879 1548 chip->thread = NULL;
dd03e970 1549 if (desc->flags & CHIP_NEED_CHECKMODE) {
099b7fcc
MCC		 1550 if (!desc->getmode || !desc->setmode) {
1551 /* This shouldn't be happen. Warn user, but keep working
1552 without kthread
1553 */
1554 v4l_info(chip->c, "set/get mode callbacks undefined!\n");
1555 return 0;
1556 }
1da177e4
LT		 1557 /* start async thread */
1558 init_timer(&chip->wt);
1559 chip->wt.function = chip_thread_wake;
1560 chip->wt.data = (unsigned long)chip;
08e14054 1561 chip->thread = kthread_run(chip_thread, chip, chip->c->name);
bc282879 1562 if (IS_ERR(chip->thread)) {
08e14054
HV		 1563 v4l_warn(chip->c, "%s: failed to create kthread\n",
1564 chip->c->name);
bc282879
CLG		 1565 chip->thread = NULL;
1566 }
1da177e4
LT		 1567 }
1568 return 0;
1569}
1570
08e14054 1571static int chip_remove(struct i2c_client *client)
1da177e4
LT		 1572{
1573 struct CHIPSTATE *chip = i2c_get_clientdata(client);
1574
1575 del_timer_sync(&chip->wt);
bc282879 1576 if (chip->thread) {
1da177e4 1577 /* shutdown async thread */
bc282879
CLG		 1578 kthread_stop(chip->thread);
1579 chip->thread = NULL;
1da177e4
LT		 1580 }
1581
1da177e4
LT		 1582 kfree(chip);
1583 return 0;
1584}
1585
dc3d75da
MCC		 1586static int tvaudio_get_ctrl(struct CHIPSTATE *chip,
1587 struct v4l2_control *ctrl)
1588{
1589 struct CHIPDESC *desc = chiplist + chip->type;
1590
1591 switch (ctrl->id) {
1592 case V4L2_CID_AUDIO_MUTE:
1593 ctrl->value=chip->muted;
1594 return 0;
1595 case V4L2_CID_AUDIO_VOLUME:
18c0ecf1 1596 if (!(desc->flags & CHIP_HAS_VOLUME))
dc3d75da
MCC		 1597 break;
1598 ctrl->value = max(chip->left,chip->right);
1599 return 0;
1600 case V4L2_CID_AUDIO_BALANCE:
1601 {
1602 int volume;
18c0ecf1 1603 if (!(desc->flags & CHIP_HAS_VOLUME))
dc3d75da
MCC		 1604 break;
1605 volume = max(chip->left,chip->right);
1606 if (volume)
1607 ctrl->value=(32768*min(chip->left,chip->right))/volume;
1608 else
1609 ctrl->value=32768;
1610 return 0;
1611 }
1612 case V4L2_CID_AUDIO_BASS:
1613 if (desc->flags & CHIP_HAS_BASSTREBLE)
1614 break;
1615 ctrl->value = chip->bass;
1616 return 0;
1617 case V4L2_CID_AUDIO_TREBLE:
1618 if (desc->flags & CHIP_HAS_BASSTREBLE)
1619 return -EINVAL;
1620 ctrl->value = chip->treble;
1621 return 0;
1622 }
1623 return -EINVAL;
1624}
1625
1626static int tvaudio_set_ctrl(struct CHIPSTATE *chip,
1627 struct v4l2_control *ctrl)
8bf2f8e7
HV		 1628{
1629 struct CHIPDESC *desc = chiplist + chip->type;
1630
1631 switch (ctrl->id) {
1632 case V4L2_CID_AUDIO_MUTE:
1633 if (ctrl->value < 0 || ctrl->value >= 2)
1634 return -ERANGE;
1635 chip->muted = ctrl->value;
1636 if (chip->muted)
1637 chip_write_masked(chip,desc->inputreg,desc->inputmute,desc->inputmask);
1638 else
1639 chip_write_masked(chip,desc->inputreg,
1640 desc->inputmap[chip->input],desc->inputmask);
dc3d75da
MCC		 1641 return 0;
1642 case V4L2_CID_AUDIO_VOLUME:
1643 {
1644 int volume,balance;
1645
18c0ecf1 1646 if (!(desc->flags & CHIP_HAS_VOLUME))
dc3d75da
MCC		 1647 break;
1648
1649 volume = max(chip->left,chip->right);
1650 if (volume)
1651 balance=(32768*min(chip->left,chip->right))/volume;
1652 else
1653 balance=32768;
1654
1655 volume=ctrl->value;
1656 chip->left = (min(65536 - balance,32768) * volume) / 32768;
1657 chip->right = (min(balance,volume *(__u16)32768)) / 32768;
1658
1659 chip_write(chip,desc->leftreg,desc->volfunc(chip->left));
1660 chip_write(chip,desc->rightreg,desc->volfunc(chip->right));
1661
1662 return 0;
8bf2f8e7 1663 }
dc3d75da
MCC		 1664 case V4L2_CID_AUDIO_BALANCE:
1665 {
1666 int volume, balance;
18c0ecf1 1667 if (!(desc->flags & CHIP_HAS_VOLUME))
dc3d75da
MCC		 1668 break;
1669
1670 volume = max(chip->left,chip->right);
1671 balance = ctrl->value;
1672
1673 chip_write(chip,desc->leftreg,desc->volfunc(chip->left));
1674 chip_write(chip,desc->rightreg,desc->volfunc(chip->right));
1675
1676 return 0;
1677 }
1678 case V4L2_CID_AUDIO_BASS:
1679 if (desc->flags & CHIP_HAS_BASSTREBLE)
1680 break;
1681 chip->bass = ctrl->value;
1682 chip_write(chip,desc->bassreg,desc->bassfunc(chip->bass));
1683
1684 return 0;
1685 case V4L2_CID_AUDIO_TREBLE:
1686 if (desc->flags & CHIP_HAS_BASSTREBLE)
1687 return -EINVAL;
1688
1689 chip->treble = ctrl->value;
1690 chip_write(chip,desc->treblereg,desc->treblefunc(chip->treble));
1691
1692 return 0;
1693 }
1694 return -EINVAL;
8bf2f8e7
HV		 1695}
1696
1697
1da177e4
LT		 1698/* ---------------------------------------------------------------------- */
1699/* video4linux interface */
1700
1701static int chip_command(struct i2c_client *client,
1702 unsigned int cmd, void *arg)
1703{
1da177e4
LT		 1704 struct CHIPSTATE *chip = i2c_get_clientdata(client);
1705 struct CHIPDESC *desc = chiplist + chip->type;
1706
08e14054 1707 v4l_dbg(1, debug, chip->c, "%s: chip_command 0x%x\n", chip->c->name, cmd);
1da177e4
LT		 1708
1709 switch (cmd) {
1da177e4 1710 case AUDC_SET_RADIO:
8a854284 1711 chip->radio = 1;
1da177e4
LT		 1712 chip->watch_stereo = 0;
1713 /* del_timer(&chip->wt); */
1714 break;
1da177e4
LT		 1715 /* --- v4l ioctls --- */
1716 /* take care: bttv does userspace copying, we'll get a
674434c6 1717 kernel pointer here... */
dc3d75da 1718 case VIDIOC_QUERYCTRL:
1da177e4 1719 {
dc3d75da
MCC		 1720 struct v4l2_queryctrl *qc = arg;
1721
1722 switch (qc->id) {
1723 case V4L2_CID_AUDIO_MUTE:
1724 break;
1725 case V4L2_CID_AUDIO_VOLUME:
1726 case V4L2_CID_AUDIO_BALANCE:
18c0ecf1 1727 if (!(desc->flags & CHIP_HAS_VOLUME))
dc3d75da
MCC		 1728 return -EINVAL;
1729 break;
1730 case V4L2_CID_AUDIO_BASS:
1731 case V4L2_CID_AUDIO_TREBLE:
1732 if (desc->flags & CHIP_HAS_BASSTREBLE)
1733 return -EINVAL;
1734 break;
1735 default:
1736 return -EINVAL;
1da177e4 1737 }
dc3d75da 1738 return v4l2_ctrl_query_fill_std(qc);
1da177e4 1739 }
8bf2f8e7
HV		 1740 case VIDIOC_S_CTRL:
1741 return tvaudio_set_ctrl(chip, arg);
1742
dc3d75da
MCC		 1743 case VIDIOC_G_CTRL:
1744 return tvaudio_get_ctrl(chip, arg);
2474ed44
HV		 1745 case VIDIOC_INT_G_AUDIO_ROUTING:
1746 {
1747 struct v4l2_routing *rt = arg;
1748
1749 rt->input = chip->input;
1750 rt->output = 0;
1751 break;
1752 }
2474ed44
HV		 1753 case VIDIOC_INT_S_AUDIO_ROUTING:
1754 {
1755 struct v4l2_routing *rt = arg;
1756
1757 if (!(desc->flags & CHIP_HAS_INPUTSEL) || rt->input >= 4)
1758 return -EINVAL;
1759 /* There are four inputs: tuner, radio, extern and intern. */
1760 chip->input = rt->input;
1761 if (chip->muted)
1762 break;
1763 chip_write_masked(chip, desc->inputreg,
1764 desc->inputmap[chip->input], desc->inputmask);
1765 break;
1766 }
8a854284 1767 case VIDIOC_S_TUNER:
1da177e4 1768 {
8a854284
HV		 1769 struct v4l2_tuner *vt = arg;
1770 int mode = 0;
1da177e4 1771
8a4b275f
HV		 1772 if (chip->radio)
1773 break;
8a854284
HV		 1774 switch (vt->audmode) {
1775 case V4L2_TUNER_MODE_MONO:
8a854284 1776 case V4L2_TUNER_MODE_STEREO:
8a854284 1777 case V4L2_TUNER_MODE_LANG1:
8a854284 1778 case V4L2_TUNER_MODE_LANG2:
dc3d75da
MCC		 1779 mode = vt->audmode;
1780 break;
1781 case V4L2_TUNER_MODE_LANG1_LANG2:
1782 mode = V4L2_TUNER_MODE_STEREO;
8a854284
HV		 1783 break;
1784 default:
8a4b275f 1785 return -EINVAL;
8a854284 1786 }
8a4b275f 1787 chip->audmode = vt->audmode;
8a854284
HV		 1788
1789 if (desc->setmode && mode) {
1790 chip->watch_stereo = 0;
1791 /* del_timer(&chip->wt); */
1792 chip->mode = mode;
1793 desc->setmode(chip, mode);
1794 }
1da177e4
LT		 1795 break;
1796 }
8a854284 1797 case VIDIOC_G_TUNER:
1da177e4 1798 {
8a854284 1799 struct v4l2_tuner *vt = arg;
dc3d75da 1800 int mode = V4L2_TUNER_MODE_MONO;
8a854284 1801
d3900bc4
HV		 1802 if (chip->radio)
1803 break;
8a4b275f 1804 vt->audmode = chip->audmode;
8a854284
HV		 1805 vt->rxsubchans = 0;
1806 vt->capability = V4L2_TUNER_CAP_STEREO |
1807 V4L2_TUNER_CAP_LANG1 | V4L2_TUNER_CAP_LANG2;
8a854284
HV		 1808
1809 if (desc->getmode)
1810 mode = desc->getmode(chip);
1811
dc3d75da 1812 if (mode & V4L2_TUNER_MODE_MONO)
8a854284 1813 vt->rxsubchans |= V4L2_TUNER_SUB_MONO;
dc3d75da 1814 if (mode & V4L2_TUNER_MODE_STEREO)
8a854284 1815 vt->rxsubchans |= V4L2_TUNER_SUB_STEREO;
8a4b275f
HV		 1816 /* Note: for SAP it should be mono/lang2 or stereo/lang2.
1817 When this module is converted fully to v4l2, then this
1818 should change for those chips that can detect SAP. */
dc3d75da 1819 if (mode & V4L2_TUNER_MODE_LANG1)
8a4b275f
HV		 1820 vt->rxsubchans = V4L2_TUNER_SUB_LANG1 |
1821 V4L2_TUNER_SUB_LANG2;
8a854284
HV		 1822 break;
1823 }
8a854284
HV		 1824 case VIDIOC_S_STD:
1825 chip->radio = 0;
1826 break;
8a854284 1827 case VIDIOC_S_FREQUENCY:
18fc59e2 1828 chip->mode = 0; /* automatic */
dd03e970
MCC		 1829
1830 /* For chips that provide getmode, setmode and checkmode,
1831 a kthread is created to automatically to set the audio
1832 standard. In this case, start with MONO and wait 2 seconds
1833 for the decoding to stablize. Then, run kthread to change
1834 to stereo, if carrier detected.
1835 */
1836 if (chip->thread) {
dc3d75da
MCC		 1837 desc->setmode(chip,V4L2_TUNER_MODE_MONO);
1838 if (chip->prevmode != V4L2_TUNER_MODE_MONO)
18fc59e2 1839 chip->prevmode = -1; /* reset previous mode */
09df5cbe 1840 mod_timer(&chip->wt, jiffies+msecs_to_jiffies(2000));
1da177e4 1841 }
8a854284 1842 break;
74cab31c
HV		 1843
1844 case VIDIOC_G_CHIP_IDENT:
1845 return v4l2_chip_ident_i2c_client(client, arg, V4L2_IDENT_TVAUDIO, 0);
1da177e4
LT		 1846 }
1847 return 0;
1848}
1849
08e14054 1850static int chip_legacy_probe(struct i2c_adapter *adap)
1da177e4 1851{
08e14054
HV		 1852 /* don't attach on saa7146 based cards,
1853 because dedicated drivers are used */
1854 if ((adap->id == I2C_HW_SAA7146))
1855 return 0;
1856 if (adap->class & I2C_CLASS_TV_ANALOG)
1857 return 1;
1858 return 0;
1da177e4
LT		 1859}
1860
ae429083
JD		 1861/* This driver supports many devices and the idea is to let the driver
1862 detect which device is present. So rather than listing all supported
1863 devices here, we pretend to support a single, fake device type. */
1864static const struct i2c_device_id chip_id[] = {
1865 { "tvaudio", 0 },
1866 { }
1867};
1868MODULE_DEVICE_TABLE(i2c, chip_id);
1869
08e14054
HV		 1870static struct v4l2_i2c_driver_data v4l2_i2c_data = {
1871 .name = "tvaudio",
1872 .driverid = I2C_DRIVERID_TVAUDIO,
1873 .command = chip_command,
1874 .probe = chip_probe,
1875 .remove = chip_remove,
1876 .legacy_probe = chip_legacy_probe,
ae429083 1877 .id_table = chip_id,
08e14054 1878};
1da177e4
LT		 1879
1880/*
1881 * Local variables:
1882 * c-basic-offset: 8
1883 * End:
1884 */
Linux kernel - Deliverables
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