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[media] tvaudio: obey V4L2 tuner audio matrix
[deliverable/linux.git] / drivers / media / video / tvaudio.c
CommitLineData
1da177e4 1/*
b4ab114c 2 * Driver for simple i2c audio chips.
1da177e4
LT		 3 *
4 * Copyright (c) 2000 Gerd Knorr
5 * based on code by:
6 * Eric Sandeen (eric_sandeen@bigfoot.com)
7 * Steve VanDeBogart (vandebo@uclink.berkeley.edu)
8 * Greg Alexander (galexand@acm.org)
9 *
b4ab114c
MCC		 10 * Copyright(c) 2005-2008 Mauro Carvalho Chehab
11 * - Some cleanups, code fixes, etc
12 * - Convert it to V4L2 API
13 *
1da177e4
LT		 14 * This code is placed under the terms of the GNU General Public License
15 *
16 * OPTIONS:
17 * debug - set to 1 if you'd like to see debug messages
18 *
19 */
20
1da177e4 21#include <linux/module.h>
1da177e4
LT		 22#include <linux/kernel.h>
23#include <linux/sched.h>
24#include <linux/string.h>
25#include <linux/timer.h>
26#include <linux/delay.h>
27#include <linux/errno.h>
28#include <linux/slab.h>
7f6adeaf 29#include <linux/videodev2.h>
1da177e4 30#include <linux/i2c.h>
1da177e4 31#include <linux/init.h>
bc282879 32#include <linux/kthread.h>
7dfb7103 33#include <linux/freezer.h>
1da177e4 34
8bf2f8e7 35#include <media/tvaudio.h>
64f70e7e 36#include <media/v4l2-device.h>
74cab31c 37#include <media/v4l2-chip-ident.h>
1da177e4 38
7c9b5048 39#include <media/i2c-addr.h>
1da177e4
LT		 40
41/* ---------------------------------------------------------------------- */
42/* insmod args */
43
ff699e6b 44static int debug; /* insmod parameter */
1da177e4
LT		 45module_param(debug, int, 0644);
46
47MODULE_DESCRIPTION("device driver for various i2c TV sound decoder / audiomux chips");
48MODULE_AUTHOR("Eric Sandeen, Steve VanDeBogart, Greg Alexander, Gerd Knorr");
49MODULE_LICENSE("GPL");
50
51#define UNSET (-1U)
18fc59e2 52
1da177e4
LT		 53/* ---------------------------------------------------------------------- */
54/* our structs */
55
4c6c390e 56#define MAXREGS 256
1da177e4
LT		 57
58struct CHIPSTATE;
59typedef int (*getvalue)(int);
60typedef int (*checkit)(struct CHIPSTATE*);
61typedef int (*initialize)(struct CHIPSTATE*);
62typedef int (*getmode)(struct CHIPSTATE*);
63typedef void (*setmode)(struct CHIPSTATE*, int mode);
1da177e4
LT		 64
65/* i2c command */
66typedef struct AUDIOCMD {
67 int count; /* # of bytes to send */
68 unsigned char bytes[MAXREGS+1]; /* addr, data, data, ... */
69} audiocmd;
70
71/* chip description */
72struct CHIPDESC {
73 char *name; /* chip name */
1da177e4
LT		 74 int addr_lo, addr_hi; /* i2c address range */
75 int registers; /* # of registers */
76
77 int *insmodopt;
78 checkit checkit;
79 initialize initialize;
80 int flags;
81#define CHIP_HAS_VOLUME 1
82#define CHIP_HAS_BASSTREBLE 2
83#define CHIP_HAS_INPUTSEL 4
dd03e970 84#define CHIP_NEED_CHECKMODE 8
1da177e4
LT		 85
86 /* various i2c command sequences */
87 audiocmd init;
88
89 /* which register has which value */
90 int leftreg,rightreg,treblereg,bassreg;
91
92 /* initialize with (defaults to 65535/65535/32768/32768 */
93 int leftinit,rightinit,trebleinit,bassinit;
94
95 /* functions to convert the values (v4l -> chip) */
96 getvalue volfunc,treblefunc,bassfunc;
97
98 /* get/set mode */
99 getmode getmode;
100 setmode setmode;
101
1da177e4
LT		 102 /* input switch register + values for v4l inputs */
103 int inputreg;
8bf2f8e7 104 int inputmap[4];
1da177e4
LT		 105 int inputmute;
106 int inputmask;
107};
1da177e4
LT		 108
109/* current state of the chip */
110struct CHIPSTATE {
64f70e7e 111 struct v4l2_subdev sd;
1da177e4 112
81cb5c4f
MCC		 113 /* chip-specific description - should point to
114 an entry at CHIPDESC table */
115 struct CHIPDESC *desc;
1da177e4
LT		 116
117 /* shadow register set */
118 audiocmd shadow;
119
120 /* current settings */
e21adca8 121 __u16 left, right, treble, bass, muted;
1da177e4 122 int prevmode;
8a854284 123 int radio;
8bf2f8e7 124 int input;
1da177e4
LT		 125
126 /* thread */
bc282879 127 struct task_struct *thread;
1da177e4 128 struct timer_list wt;
8a4b275f 129 int audmode;
1da177e4
LT		 130};
131
64f70e7e
HV		 132static inline struct CHIPSTATE *to_state(struct v4l2_subdev *sd)
133{
134 return container_of(sd, struct CHIPSTATE, sd);
135}
136
1da177e4 137
1da177e4
LT		 138/* ---------------------------------------------------------------------- */
139/* i2c I/O functions */
140
141static int chip_write(struct CHIPSTATE *chip, int subaddr, int val)
142{
64f70e7e
HV		 143 struct v4l2_subdev *sd = &chip->sd;
144 struct i2c_client *c = v4l2_get_subdevdata(sd);
1da177e4
LT		 145 unsigned char buffer[2];
146
49426437 147 if (subaddr < 0) {
64f70e7e 148 v4l2_dbg(1, debug, sd, "chip_write: 0x%x\n", val);
1da177e4
LT		 149 chip->shadow.bytes[1] = val;
150 buffer[0] = val;
64f70e7e
HV		 151 if (1 != i2c_master_send(c, buffer, 1)) {
152 v4l2_warn(sd, "I/O error (write 0x%x)\n", val);
1da177e4
LT		 153 return -1;
154 }
155 } else {
49426437 156 if (subaddr + 1 >= ARRAY_SIZE(chip->shadow.bytes)) {
64f70e7e 157 v4l2_info(sd,
49426437
MCC		 158 "Tried to access a non-existent register: %d\n",
159 subaddr);
160 return -EINVAL;
161 }
162
64f70e7e
HV		 163 v4l2_dbg(1, debug, sd, "chip_write: reg%d=0x%x\n",
164 subaddr, val);
1da177e4
LT		 165 chip->shadow.bytes[subaddr+1] = val;
166 buffer[0] = subaddr;
167 buffer[1] = val;
64f70e7e
HV		 168 if (2 != i2c_master_send(c, buffer, 2)) {
169 v4l2_warn(sd, "I/O error (write reg%d=0x%x)\n",
170 subaddr, val);
1da177e4
LT		 171 return -1;
172 }
173 }
174 return 0;
175}
176
49426437
MCC		 177static int chip_write_masked(struct CHIPSTATE *chip,
178 int subaddr, int val, int mask)
1da177e4 179{
64f70e7e
HV		 180 struct v4l2_subdev *sd = &chip->sd;
181
1da177e4 182 if (mask != 0) {
49426437 183 if (subaddr < 0) {
1da177e4
LT		 184 val = (chip->shadow.bytes[1] & ~mask) | (val & mask);
185 } else {
49426437 186 if (subaddr + 1 >= ARRAY_SIZE(chip->shadow.bytes)) {
64f70e7e 187 v4l2_info(sd,
49426437
MCC		 188 "Tried to access a non-existent register: %d\n",
189 subaddr);
190 return -EINVAL;
191 }
192
1da177e4
LT		 193 val = (chip->shadow.bytes[subaddr+1] & ~mask) | (val & mask);
194 }
195 }
196 return chip_write(chip, subaddr, val);
197}
198
199static int chip_read(struct CHIPSTATE *chip)
200{
64f70e7e
HV		 201 struct v4l2_subdev *sd = &chip->sd;
202 struct i2c_client *c = v4l2_get_subdevdata(sd);
1da177e4
LT		 203 unsigned char buffer;
204
64f70e7e
HV		 205 if (1 != i2c_master_recv(c, &buffer, 1)) {
206 v4l2_warn(sd, "I/O error (read)\n");
1da177e4
LT		 207 return -1;
208 }
64f70e7e 209 v4l2_dbg(1, debug, sd, "chip_read: 0x%x\n", buffer);
1da177e4
LT		 210 return buffer;
211}
212
213static int chip_read2(struct CHIPSTATE *chip, int subaddr)
214{
64f70e7e
HV		 215 struct v4l2_subdev *sd = &chip->sd;
216 struct i2c_client *c = v4l2_get_subdevdata(sd);
18fc59e2
MCC		 217 unsigned char write[1];
218 unsigned char read[1];
219 struct i2c_msg msgs[2] = {
64f70e7e
HV		 220 { c->addr, 0, 1, write },
221 { c->addr, I2C_M_RD, 1, read }
18fc59e2 222 };
64f70e7e 223
18fc59e2 224 write[0] = subaddr;
1da177e4 225
64f70e7e
HV		 226 if (2 != i2c_transfer(c->adapter, msgs, 2)) {
227 v4l2_warn(sd, "I/O error (read2)\n");
1da177e4
LT		 228 return -1;
229 }
64f70e7e
HV		 230 v4l2_dbg(1, debug, sd, "chip_read2: reg%d=0x%x\n",
231 subaddr, read[0]);
1da177e4
LT		 232 return read[0];
233}
234
235static int chip_cmd(struct CHIPSTATE *chip, char *name, audiocmd *cmd)
236{
64f70e7e
HV		 237 struct v4l2_subdev *sd = &chip->sd;
238 struct i2c_client *c = v4l2_get_subdevdata(sd);
1da177e4
LT		 239 int i;
240
241 if (0 == cmd->count)
242 return 0;
243
49426437 244 if (cmd->count + cmd->bytes[0] - 1 >= ARRAY_SIZE(chip->shadow.bytes)) {
64f70e7e 245 v4l2_info(sd,
49426437
MCC		 246 "Tried to access a non-existent register range: %d to %d\n",
247 cmd->bytes[0] + 1, cmd->bytes[0] + cmd->count - 1);
248 return -EINVAL;
249 }
250
251 /* FIXME: it seems that the shadow bytes are wrong bellow !*/
252
1da177e4 253 /* update our shadow register set; print bytes if (debug > 0) */
64f70e7e
HV		 254 v4l2_dbg(1, debug, sd, "chip_cmd(%s): reg=%d, data:",
255 name, cmd->bytes[0]);
1da177e4 256 for (i = 1; i < cmd->count; i++) {
18fc59e2 257 if (debug)
64f70e7e 258 printk(KERN_CONT " 0x%x", cmd->bytes[i]);
1da177e4
LT		 259 chip->shadow.bytes[i+cmd->bytes[0]] = cmd->bytes[i];
260 }
18fc59e2 261 if (debug)
64f70e7e 262 printk(KERN_CONT "\n");
1da177e4
LT		 263
264 /* send data to the chip */
64f70e7e
HV		 265 if (cmd->count != i2c_master_send(c, cmd->bytes, cmd->count)) {
266 v4l2_warn(sd, "I/O error (%s)\n", name);
1da177e4
LT		 267 return -1;
268 }
269 return 0;
270}
271
272/* ---------------------------------------------------------------------- */
273/* kernel thread for doing i2c stuff asyncronly
274 * right now it is used only to check the audio mode (mono/stereo/whatever)
275 * some time after switching to another TV channel, then turn on stereo
276 * if available, ...
277 */
278
279static void chip_thread_wake(unsigned long data)
280{
18fc59e2 281 struct CHIPSTATE *chip = (struct CHIPSTATE*)data;
bc282879 282 wake_up_process(chip->thread);
1da177e4
LT		 283}
284
285static int chip_thread(void *data)
286{
18fc59e2 287 struct CHIPSTATE *chip = data;
81cb5c4f 288 struct CHIPDESC *desc = chip->desc;
64f70e7e 289 struct v4l2_subdev *sd = &chip->sd;
e21adca8 290 int mode, selected;
1da177e4 291
64f70e7e 292 v4l2_dbg(1, debug, sd, "thread started\n");
83144186 293 set_freezable();
1da177e4 294 for (;;) {
bc282879
CLG		 295 set_current_state(TASK_INTERRUPTIBLE);
296 if (!kthread_should_stop())
1da177e4 297 schedule();
bc282879 298 set_current_state(TASK_RUNNING);
5e50e7a9 299 try_to_freeze();
bc282879 300 if (kthread_should_stop())
1da177e4 301 break;
64f70e7e 302 v4l2_dbg(1, debug, sd, "thread wakeup\n");
1da177e4 303
e21adca8
DG		 304 /* don't do anything for radio */
305 if (chip->radio)
1da177e4
LT		 306 continue;
307
308 /* have a look what's going on */
dd03e970
MCC		 309 mode = desc->getmode(chip);
310 if (mode == chip->prevmode)
311 continue;
312
313 /* chip detected a new audio mode - set it */
64f70e7e 314 v4l2_dbg(1, debug, sd, "thread checkmode\n");
dd03e970
MCC		 315
316 chip->prevmode = mode;
317
e21adca8
DG		 318 selected = V4L2_TUNER_MODE_MONO;
319 switch (chip->audmode) {
320 case V4L2_TUNER_MODE_MONO:
321 if (mode & V4L2_TUNER_SUB_LANG1)
322 selected = V4L2_TUNER_MODE_LANG1;
323 break;
324 case V4L2_TUNER_MODE_STEREO:
325 case V4L2_TUNER_MODE_LANG1:
326 if (mode & V4L2_TUNER_SUB_LANG1)
327 selected = V4L2_TUNER_MODE_LANG1;
328 else if (mode & V4L2_TUNER_SUB_STEREO)
329 selected = V4L2_TUNER_MODE_STEREO;
330 break;
331 case V4L2_TUNER_MODE_LANG2:
332 if (mode & V4L2_TUNER_SUB_LANG2)
333 selected = V4L2_TUNER_MODE_LANG2;
334 else if (mode & V4L2_TUNER_SUB_STEREO)
335 selected = V4L2_TUNER_MODE_STEREO;
336 break;
337 }
338 desc->setmode(chip, selected);
1da177e4
LT		 339
340 /* schedule next check */
09df5cbe 341 mod_timer(&chip->wt, jiffies+msecs_to_jiffies(2000));
1da177e4
LT		 342 }
343
64f70e7e 344 v4l2_dbg(1, debug, sd, "thread exiting\n");
1da177e4
LT		 345 return 0;
346}
347
1da177e4
LT		 348/* ---------------------------------------------------------------------- */
349/* audio chip descriptions - defines+functions for tda9840 */
350
351#define TDA9840_SW 0x00
352#define TDA9840_LVADJ 0x02
353#define TDA9840_STADJ 0x03
354#define TDA9840_TEST 0x04
355
356#define TDA9840_MONO 0x10
357#define TDA9840_STEREO 0x2a
358#define TDA9840_DUALA 0x12
359#define TDA9840_DUALB 0x1e
360#define TDA9840_DUALAB 0x1a
361#define TDA9840_DUALBA 0x16
362#define TDA9840_EXTERNAL 0x7a
363
364#define TDA9840_DS_DUAL 0x20 /* Dual sound identified */
365#define TDA9840_ST_STEREO 0x40 /* Stereo sound identified */
366#define TDA9840_PONRES 0x80 /* Power-on reset detected if = 1 */
367
368#define TDA9840_TEST_INT1SN 0x1 /* Integration time 0.5s when set */
369#define TDA9840_TEST_INTFU 0x02 /* Disables integrator function */
370
371static int tda9840_getmode(struct CHIPSTATE *chip)
372{
64f70e7e 373 struct v4l2_subdev *sd = &chip->sd;
1da177e4
LT		 374 int val, mode;
375
376 val = chip_read(chip);
3322a59e 377 mode = V4L2_TUNER_SUB_MONO;
1da177e4 378 if (val & TDA9840_DS_DUAL)
3322a59e 379 mode |= V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
1da177e4 380 if (val & TDA9840_ST_STEREO)
3322a59e 381 mode |= V4L2_TUNER_SUB_STEREO;
1da177e4 382
64f70e7e 383 v4l2_dbg(1, debug, sd, "tda9840_getmode(): raw chip read: %d, return: %d\n",
18fc59e2 384 val, mode);
1da177e4
LT		 385 return mode;
386}
387
388static void tda9840_setmode(struct CHIPSTATE *chip, int mode)
389{
390 int update = 1;
391 int t = chip->shadow.bytes[TDA9840_SW + 1] & ~0x7e;
392
393 switch (mode) {
dc3d75da 394 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 395 t |= TDA9840_MONO;
396 break;
dc3d75da 397 case V4L2_TUNER_MODE_STEREO:
1da177e4
LT		 398 t |= TDA9840_STEREO;
399 break;
dc3d75da 400 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 401 t |= TDA9840_DUALA;
402 break;
dc3d75da 403 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 404 t |= TDA9840_DUALB;
405 break;
406 default:
407 update = 0;
408 }
409
410 if (update)
411 chip_write(chip, TDA9840_SW, t);
412}
413
94f9e56e
HV		 414static int tda9840_checkit(struct CHIPSTATE *chip)
415{
416 int rc;
417 rc = chip_read(chip);
418 /* lower 5 bits should be 0 */
419 return ((rc & 0x1f) == 0) ? 1 : 0;
420}
421
1da177e4
LT		 422/* ---------------------------------------------------------------------- */
423/* audio chip descriptions - defines+functions for tda985x */
424
425/* subaddresses for TDA9855 */
426#define TDA9855_VR 0x00 /* Volume, right */
427#define TDA9855_VL 0x01 /* Volume, left */
428#define TDA9855_BA 0x02 /* Bass */
429#define TDA9855_TR 0x03 /* Treble */
430#define TDA9855_SW 0x04 /* Subwoofer - not connected on DTV2000 */
431
432/* subaddresses for TDA9850 */
433#define TDA9850_C4 0x04 /* Control 1 for TDA9850 */
434
435/* subaddesses for both chips */
436#define TDA985x_C5 0x05 /* Control 2 for TDA9850, Control 1 for TDA9855 */
437#define TDA985x_C6 0x06 /* Control 3 for TDA9850, Control 2 for TDA9855 */
438#define TDA985x_C7 0x07 /* Control 4 for TDA9850, Control 3 for TDA9855 */
439#define TDA985x_A1 0x08 /* Alignment 1 for both chips */
440#define TDA985x_A2 0x09 /* Alignment 2 for both chips */
441#define TDA985x_A3 0x0a /* Alignment 3 for both chips */
442
443/* Masks for bits in TDA9855 subaddresses */
444/* 0x00 - VR in TDA9855 */
445/* 0x01 - VL in TDA9855 */
446/* lower 7 bits control gain from -71dB (0x28) to 16dB (0x7f)
447 * in 1dB steps - mute is 0x27 */
448
449
450/* 0x02 - BA in TDA9855 */
451/* lower 5 bits control bass gain from -12dB (0x06) to 16.5dB (0x19)
452 * in .5dB steps - 0 is 0x0E */
453
454
455/* 0x03 - TR in TDA9855 */
456/* 4 bits << 1 control treble gain from -12dB (0x3) to 12dB (0xb)
457 * in 3dB steps - 0 is 0x7 */
458
459/* Masks for bits in both chips' subaddresses */
460/* 0x04 - SW in TDA9855, C4/Control 1 in TDA9850 */
461/* Unique to TDA9855: */
462/* 4 bits << 2 control subwoofer/surround gain from -14db (0x1) to 14db (0xf)
463 * in 3dB steps - mute is 0x0 */
464
465/* Unique to TDA9850: */
466/* lower 4 bits control stereo noise threshold, over which stereo turns off
467 * set to values of 0x00 through 0x0f for Ster1 through Ster16 */
468
469
470/* 0x05 - C5 - Control 1 in TDA9855 , Control 2 in TDA9850*/
471/* Unique to TDA9855: */
472#define TDA9855_MUTE 1<<7 /* GMU, Mute at outputs */
473#define TDA9855_AVL 1<<6 /* AVL, Automatic Volume Level */
474#define TDA9855_LOUD 1<<5 /* Loudness, 1==off */
475#define TDA9855_SUR 1<<3 /* Surround / Subwoofer 1==.5(L-R) 0==.5(L+R) */
476 /* Bits 0 to 3 select various combinations
4ac97914
MCC		 477 * of line in and line out, only the
478 * interesting ones are defined */
1da177e4
LT		 479#define TDA9855_EXT 1<<2 /* Selects inputs LIR and LIL. Pins 41 & 12 */
480#define TDA9855_INT 0 /* Selects inputs LOR and LOL. (internal) */
481
482/* Unique to TDA9850: */
483/* lower 4 bits contol SAP noise threshold, over which SAP turns off
484 * set to values of 0x00 through 0x0f for SAP1 through SAP16 */
485
486
487/* 0x06 - C6 - Control 2 in TDA9855, Control 3 in TDA9850 */
488/* Common to TDA9855 and TDA9850: */
489#define TDA985x_SAP 3<<6 /* Selects SAP output, mute if not received */
490#define TDA985x_STEREO 1<<6 /* Selects Stereo ouput, mono if not received */
491#define TDA985x_MONO 0 /* Forces Mono output */
492#define TDA985x_LMU 1<<3 /* Mute (LOR/LOL for 9855, OUTL/OUTR for 9850) */
493
494/* Unique to TDA9855: */
495#define TDA9855_TZCM 1<<5 /* If set, don't mute till zero crossing */
496#define TDA9855_VZCM 1<<4 /* If set, don't change volume till zero crossing*/
497#define TDA9855_LINEAR 0 /* Linear Stereo */
498#define TDA9855_PSEUDO 1 /* Pseudo Stereo */
499#define TDA9855_SPAT_30 2 /* Spatial Stereo, 30% anti-phase crosstalk */
500#define TDA9855_SPAT_50 3 /* Spatial Stereo, 52% anti-phase crosstalk */
501#define TDA9855_E_MONO 7 /* Forced mono - mono select elseware, so useless*/
502
503/* 0x07 - C7 - Control 3 in TDA9855, Control 4 in TDA9850 */
504/* Common to both TDA9855 and TDA9850: */
505/* lower 4 bits control input gain from -3.5dB (0x0) to 4dB (0xF)
506 * in .5dB steps - 0dB is 0x7 */
507
508/* 0x08, 0x09 - A1 and A2 (read/write) */
509/* Common to both TDA9855 and TDA9850: */
510/* lower 5 bites are wideband and spectral expander alignment
511 * from 0x00 to 0x1f - nominal at 0x0f and 0x10 (read/write) */
512#define TDA985x_STP 1<<5 /* Stereo Pilot/detect (read-only) */
513#define TDA985x_SAPP 1<<6 /* SAP Pilot/detect (read-only) */
514#define TDA985x_STS 1<<7 /* Stereo trigger 1= <35mV 0= <30mV (write-only)*/
515
516/* 0x0a - A3 */
517/* Common to both TDA9855 and TDA9850: */
518/* lower 3 bits control timing current for alignment: -30% (0x0), -20% (0x1),
519 * -10% (0x2), nominal (0x3), +10% (0x6), +20% (0x5), +30% (0x4) */
520#define TDA985x_ADJ 1<<7 /* Stereo adjust on/off (wideband and spectral */
521
522static int tda9855_volume(int val) { return val/0x2e8+0x27; }
523static int tda9855_bass(int val) { return val/0xccc+0x06; }
524static int tda9855_treble(int val) { return (val/0x1c71+0x3)<<1; }
525
526static int tda985x_getmode(struct CHIPSTATE *chip)
527{
3322a59e 528 int mode, val;
1da177e4 529
1da177e4
LT		 530 /* Add mono mode regardless of SAP and stereo */
531 /* Allows forced mono */
3322a59e
DG		 532 mode = V4L2_TUNER_SUB_MONO;
533 val = chip_read(chip);
534 if (val & TDA985x_STP)
535 mode |= V4L2_TUNER_SUB_STEREO;
536 if (val & TDA985x_SAPP)
537 mode |= V4L2_TUNER_SUB_SAP;
538 return mode;
1da177e4
LT		 539}
540
541static void tda985x_setmode(struct CHIPSTATE *chip, int mode)
542{
543 int update = 1;
544 int c6 = chip->shadow.bytes[TDA985x_C6+1] & 0x3f;
545
546 switch (mode) {
dc3d75da 547 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 548 c6 |= TDA985x_MONO;
549 break;
dc3d75da 550 case V4L2_TUNER_MODE_STEREO:
00fb1850 551 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 552 c6 |= TDA985x_STEREO;
553 break;
00fb1850 554 case V4L2_TUNER_MODE_SAP:
1da177e4
LT		 555 c6 |= TDA985x_SAP;
556 break;
557 default:
558 update = 0;
559 }
560 if (update)
561 chip_write(chip,TDA985x_C6,c6);
562}
563
564
565/* ---------------------------------------------------------------------- */
566/* audio chip descriptions - defines+functions for tda9873h */
567
568/* Subaddresses for TDA9873H */
569
570#define TDA9873_SW 0x00 /* Switching */
571#define TDA9873_AD 0x01 /* Adjust */
572#define TDA9873_PT 0x02 /* Port */
573
574/* Subaddress 0x00: Switching Data
575 * B7..B0:
576 *
577 * B1, B0: Input source selection
578 * 0, 0 internal
579 * 1, 0 external stereo
580 * 0, 1 external mono
581 */
582#define TDA9873_INP_MASK 3
583#define TDA9873_INTERNAL 0
584#define TDA9873_EXT_STEREO 2
585#define TDA9873_EXT_MONO 1
586
587/* B3, B2: output signal select
588 * B4 : transmission mode
589 * 0, 0, 1 Mono
590 * 1, 0, 0 Stereo
591 * 1, 1, 1 Stereo (reversed channel)
592 * 0, 0, 0 Dual AB
593 * 0, 0, 1 Dual AA
594 * 0, 1, 0 Dual BB
595 * 0, 1, 1 Dual BA
596 */
597
598#define TDA9873_TR_MASK (7 << 2)
599#define TDA9873_TR_MONO 4
600#define TDA9873_TR_STEREO 1 << 4
d59a14e2 601#define TDA9873_TR_REVERSE ((1 << 3) | (1 << 2))
1da177e4
LT		 602#define TDA9873_TR_DUALA 1 << 2
603#define TDA9873_TR_DUALB 1 << 3
604
605/* output level controls
606 * B5: output level switch (0 = reduced gain, 1 = normal gain)
607 * B6: mute (1 = muted)
608 * B7: auto-mute (1 = auto-mute enabled)
609 */
610
611#define TDA9873_GAIN_NORMAL 1 << 5
612#define TDA9873_MUTE 1 << 6
613#define TDA9873_AUTOMUTE 1 << 7
614
615/* Subaddress 0x01: Adjust/standard */
616
617/* Lower 4 bits (C3..C0) control stereo adjustment on R channel (-0.6 - +0.7 dB)
618 * Recommended value is +0 dB
619 */
620
621#define TDA9873_STEREO_ADJ 0x06 /* 0dB gain */
622
623/* Bits C6..C4 control FM stantard
624 * C6, C5, C4
625 * 0, 0, 0 B/G (PAL FM)
626 * 0, 0, 1 M
627 * 0, 1, 0 D/K(1)
628 * 0, 1, 1 D/K(2)
629 * 1, 0, 0 D/K(3)
630 * 1, 0, 1 I
631 */
632#define TDA9873_BG 0
633#define TDA9873_M 1
634#define TDA9873_DK1 2
635#define TDA9873_DK2 3
636#define TDA9873_DK3 4
637#define TDA9873_I 5
638
639/* C7 controls identification response time (1=fast/0=normal)
640 */
641#define TDA9873_IDR_NORM 0
642#define TDA9873_IDR_FAST 1 << 7
643
644
645/* Subaddress 0x02: Port data */
646
647/* E1, E0 free programmable ports P1/P2
648 0, 0 both ports low
649 0, 1 P1 high
650 1, 0 P2 high
651 1, 1 both ports high
652*/
653
654#define TDA9873_PORTS 3
655
656/* E2: test port */
657#define TDA9873_TST_PORT 1 << 2
658
659/* E5..E3 control mono output channel (together with transmission mode bit B4)
660 *
661 * E5 E4 E3 B4 OUTM
662 * 0 0 0 0 mono
663 * 0 0 1 0 DUAL B
664 * 0 1 0 1 mono (from stereo decoder)
665 */
666#define TDA9873_MOUT_MONO 0
667#define TDA9873_MOUT_FMONO 0
668#define TDA9873_MOUT_DUALA 0
669#define TDA9873_MOUT_DUALB 1 << 3
670#define TDA9873_MOUT_ST 1 << 4
d59a14e2 671#define TDA9873_MOUT_EXTM ((1 << 4) | (1 << 3))
1da177e4 672#define TDA9873_MOUT_EXTL 1 << 5
d59a14e2
DG		 673#define TDA9873_MOUT_EXTR ((1 << 5) | (1 << 3))
674#define TDA9873_MOUT_EXTLR ((1 << 5) | (1 << 4))
675#define TDA9873_MOUT_MUTE ((1 << 5) | (1 << 4) | (1 << 3))
1da177e4
LT		 676
677/* Status bits: (chip read) */
678#define TDA9873_PONR 0 /* Power-on reset detected if = 1 */
679#define TDA9873_STEREO 2 /* Stereo sound is identified */
680#define TDA9873_DUAL 4 /* Dual sound is identified */
681
682static int tda9873_getmode(struct CHIPSTATE *chip)
683{
64f70e7e 684 struct v4l2_subdev *sd = &chip->sd;
1da177e4
LT		 685 int val,mode;
686
687 val = chip_read(chip);
3322a59e 688 mode = V4L2_TUNER_SUB_MONO;
1da177e4 689 if (val & TDA9873_STEREO)
3322a59e 690 mode |= V4L2_TUNER_SUB_STEREO;
1da177e4 691 if (val & TDA9873_DUAL)
3322a59e 692 mode |= V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
64f70e7e 693 v4l2_dbg(1, debug, sd, "tda9873_getmode(): raw chip read: %d, return: %d\n",
18fc59e2 694 val, mode);
1da177e4
LT		 695 return mode;
696}
697
698static void tda9873_setmode(struct CHIPSTATE *chip, int mode)
699{
64f70e7e 700 struct v4l2_subdev *sd = &chip->sd;
1da177e4
LT		 701 int sw_data = chip->shadow.bytes[TDA9873_SW+1] & ~ TDA9873_TR_MASK;
702 /* int adj_data = chip->shadow.bytes[TDA9873_AD+1] ; */
703
704 if ((sw_data & TDA9873_INP_MASK) != TDA9873_INTERNAL) {
64f70e7e 705 v4l2_dbg(1, debug, sd, "tda9873_setmode(): external input\n");
1da177e4
LT		 706 return;
707 }
708
64f70e7e
HV		 709 v4l2_dbg(1, debug, sd, "tda9873_setmode(): chip->shadow.bytes[%d] = %d\n", TDA9873_SW+1, chip->shadow.bytes[TDA9873_SW+1]);
710 v4l2_dbg(1, debug, sd, "tda9873_setmode(): sw_data = %d\n", sw_data);
1da177e4
LT		 711
712 switch (mode) {
dc3d75da 713 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 714 sw_data |= TDA9873_TR_MONO;
715 break;
dc3d75da 716 case V4L2_TUNER_MODE_STEREO:
1da177e4
LT		 717 sw_data |= TDA9873_TR_STEREO;
718 break;
dc3d75da 719 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 720 sw_data |= TDA9873_TR_DUALA;
721 break;
dc3d75da 722 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 723 sw_data |= TDA9873_TR_DUALB;
724 break;
725 default:
1da177e4
LT		 726 return;
727 }
728
729 chip_write(chip, TDA9873_SW, sw_data);
64f70e7e 730 v4l2_dbg(1, debug, sd, "tda9873_setmode(): req. mode %d; chip_write: %d\n",
1da177e4
LT		 731 mode, sw_data);
732}
733
734static int tda9873_checkit(struct CHIPSTATE *chip)
735{
736 int rc;
737
738 if (-1 == (rc = chip_read2(chip,254)))
739 return 0;
740 return (rc & ~0x1f) == 0x80;
741}
742
743
744/* ---------------------------------------------------------------------- */
745/* audio chip description - defines+functions for tda9874h and tda9874a */
746/* Dariusz Kowalewski <darekk@automex.pl> */
747
748/* Subaddresses for TDA9874H and TDA9874A (slave rx) */
749#define TDA9874A_AGCGR 0x00 /* AGC gain */
750#define TDA9874A_GCONR 0x01 /* general config */
751#define TDA9874A_MSR 0x02 /* monitor select */
752#define TDA9874A_C1FRA 0x03 /* carrier 1 freq. */
753#define TDA9874A_C1FRB 0x04 /* carrier 1 freq. */
754#define TDA9874A_C1FRC 0x05 /* carrier 1 freq. */
755#define TDA9874A_C2FRA 0x06 /* carrier 2 freq. */
756#define TDA9874A_C2FRB 0x07 /* carrier 2 freq. */
757#define TDA9874A_C2FRC 0x08 /* carrier 2 freq. */
758#define TDA9874A_DCR 0x09 /* demodulator config */
759#define TDA9874A_FMER 0x0a /* FM de-emphasis */
760#define TDA9874A_FMMR 0x0b /* FM dematrix */
761#define TDA9874A_C1OLAR 0x0c /* ch.1 output level adj. */
762#define TDA9874A_C2OLAR 0x0d /* ch.2 output level adj. */
763#define TDA9874A_NCONR 0x0e /* NICAM config */
764#define TDA9874A_NOLAR 0x0f /* NICAM output level adj. */
765#define TDA9874A_NLELR 0x10 /* NICAM lower error limit */
766#define TDA9874A_NUELR 0x11 /* NICAM upper error limit */
767#define TDA9874A_AMCONR 0x12 /* audio mute control */
768#define TDA9874A_SDACOSR 0x13 /* stereo DAC output select */
769#define TDA9874A_AOSR 0x14 /* analog output select */
770#define TDA9874A_DAICONR 0x15 /* digital audio interface config */
771#define TDA9874A_I2SOSR 0x16 /* I2S-bus output select */
772#define TDA9874A_I2SOLAR 0x17 /* I2S-bus output level adj. */
773#define TDA9874A_MDACOSR 0x18 /* mono DAC output select (tda9874a) */
774#define TDA9874A_ESP 0xFF /* easy standard progr. (tda9874a) */
775
776/* Subaddresses for TDA9874H and TDA9874A (slave tx) */
777#define TDA9874A_DSR 0x00 /* device status */
778#define TDA9874A_NSR 0x01 /* NICAM status */
779#define TDA9874A_NECR 0x02 /* NICAM error count */
780#define TDA9874A_DR1 0x03 /* add. data LSB */
781#define TDA9874A_DR2 0x04 /* add. data MSB */
782#define TDA9874A_LLRA 0x05 /* monitor level read-out LSB */
783#define TDA9874A_LLRB 0x06 /* monitor level read-out MSB */
784#define TDA9874A_SIFLR 0x07 /* SIF level */
785#define TDA9874A_TR2 252 /* test reg. 2 */
786#define TDA9874A_TR1 253 /* test reg. 1 */
787#define TDA9874A_DIC 254 /* device id. code */
788#define TDA9874A_SIC 255 /* software id. code */
789
790
791static int tda9874a_mode = 1; /* 0: A2, 1: NICAM */
792static int tda9874a_GCONR = 0xc0; /* default config. input pin: SIFSEL=0 */
793static int tda9874a_NCONR = 0x01; /* default NICAM config.: AMSEL=0,AMUTE=1 */
794static int tda9874a_ESP = 0x07; /* default standard: NICAM D/K */
795static int tda9874a_dic = -1; /* device id. code */
796
797/* insmod options for tda9874a */
798static unsigned int tda9874a_SIF = UNSET;
799static unsigned int tda9874a_AMSEL = UNSET;
800static unsigned int tda9874a_STD = UNSET;
801module_param(tda9874a_SIF, int, 0444);
802module_param(tda9874a_AMSEL, int, 0444);
803module_param(tda9874a_STD, int, 0444);
804
805/*
806 * initialization table for tda9874 decoder:
807 * - carrier 1 freq. registers (3 bytes)
808 * - carrier 2 freq. registers (3 bytes)
809 * - demudulator config register
810 * - FM de-emphasis register (slow identification mode)
811 * Note: frequency registers must be written in single i2c transfer.
812 */
813static struct tda9874a_MODES {
814 char *name;
815 audiocmd cmd;
816} tda9874a_modelist[9] = {
04e6f990 817 { "A2, B/G", /* default */
1da177e4
LT		 818 { 9, { TDA9874A_C1FRA, 0x72,0x95,0x55, 0x77,0xA0,0x00, 0x00,0x00 }} },
819 { "A2, M (Korea)",
820 { 9, { TDA9874A_C1FRA, 0x5D,0xC0,0x00, 0x62,0x6A,0xAA, 0x20,0x22 }} },
821 { "A2, D/K (1)",
822 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x82,0x60,0x00, 0x00,0x00 }} },
823 { "A2, D/K (2)",
824 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x8C,0x75,0x55, 0x00,0x00 }} },
825 { "A2, D/K (3)",
826 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x77,0xA0,0x00, 0x00,0x00 }} },
827 { "NICAM, I",
828 { 9, { TDA9874A_C1FRA, 0x7D,0x00,0x00, 0x88,0x8A,0xAA, 0x08,0x33 }} },
829 { "NICAM, B/G",
830 { 9, { TDA9874A_C1FRA, 0x72,0x95,0x55, 0x79,0xEA,0xAA, 0x08,0x33 }} },
04e6f990 831 { "NICAM, D/K",
1da177e4
LT		 832 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x79,0xEA,0xAA, 0x08,0x33 }} },
833 { "NICAM, L",
834 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x79,0xEA,0xAA, 0x09,0x33 }} }
835};
836
837static int tda9874a_setup(struct CHIPSTATE *chip)
838{
64f70e7e
HV		 839 struct v4l2_subdev *sd = &chip->sd;
840
1da177e4
LT		 841 chip_write(chip, TDA9874A_AGCGR, 0x00); /* 0 dB */
842 chip_write(chip, TDA9874A_GCONR, tda9874a_GCONR);
843 chip_write(chip, TDA9874A_MSR, (tda9874a_mode) ? 0x03:0x02);
844 if(tda9874a_dic == 0x11) {
845 chip_write(chip, TDA9874A_FMMR, 0x80);
846 } else { /* dic == 0x07 */
847 chip_cmd(chip,"tda9874_modelist",&tda9874a_modelist[tda9874a_STD].cmd);
848 chip_write(chip, TDA9874A_FMMR, 0x00);
849 }
850 chip_write(chip, TDA9874A_C1OLAR, 0x00); /* 0 dB */
851 chip_write(chip, TDA9874A_C2OLAR, 0x00); /* 0 dB */
852 chip_write(chip, TDA9874A_NCONR, tda9874a_NCONR);
853 chip_write(chip, TDA9874A_NOLAR, 0x00); /* 0 dB */
854 /* Note: If signal quality is poor you may want to change NICAM */
855 /* error limit registers (NLELR and NUELR) to some greater values. */
856 /* Then the sound would remain stereo, but won't be so clear. */
857 chip_write(chip, TDA9874A_NLELR, 0x14); /* default */
858 chip_write(chip, TDA9874A_NUELR, 0x50); /* default */
859
860 if(tda9874a_dic == 0x11) {
861 chip_write(chip, TDA9874A_AMCONR, 0xf9);
862 chip_write(chip, TDA9874A_SDACOSR, (tda9874a_mode) ? 0x81:0x80);
863 chip_write(chip, TDA9874A_AOSR, 0x80);
864 chip_write(chip, TDA9874A_MDACOSR, (tda9874a_mode) ? 0x82:0x80);
865 chip_write(chip, TDA9874A_ESP, tda9874a_ESP);
866 } else { /* dic == 0x07 */
867 chip_write(chip, TDA9874A_AMCONR, 0xfb);
868 chip_write(chip, TDA9874A_SDACOSR, (tda9874a_mode) ? 0x81:0x80);
18fc59e2 869 chip_write(chip, TDA9874A_AOSR, 0x00); /* or 0x10 */
1da177e4 870 }
64f70e7e 871 v4l2_dbg(1, debug, sd, "tda9874a_setup(): %s [0x%02X].\n",
1da177e4
LT		 872 tda9874a_modelist[tda9874a_STD].name,tda9874a_STD);
873 return 1;
874}
875
876static int tda9874a_getmode(struct CHIPSTATE *chip)
877{
64f70e7e 878 struct v4l2_subdev *sd = &chip->sd;
1da177e4
LT		 879 int dsr,nsr,mode;
880 int necr; /* just for debugging */
881
3322a59e 882 mode = V4L2_TUNER_SUB_MONO;
1da177e4
LT		 883
884 if(-1 == (dsr = chip_read2(chip,TDA9874A_DSR)))
885 return mode;
886 if(-1 == (nsr = chip_read2(chip,TDA9874A_NSR)))
887 return mode;
888 if(-1 == (necr = chip_read2(chip,TDA9874A_NECR)))
889 return mode;
890
891 /* need to store dsr/nsr somewhere */
892 chip->shadow.bytes[MAXREGS-2] = dsr;
893 chip->shadow.bytes[MAXREGS-1] = nsr;
894
895 if(tda9874a_mode) {
896 /* Note: DSR.RSSF and DSR.AMSTAT bits are also checked.
897 * If NICAM auto-muting is enabled, DSR.AMSTAT=1 indicates
898 * that sound has (temporarily) switched from NICAM to
899 * mono FM (or AM) on 1st sound carrier due to high NICAM bit
900 * error count. So in fact there is no stereo in this case :-(
dc3d75da 901 * But changing the mode to V4L2_TUNER_MODE_MONO would switch
1da177e4
LT		 902 * external 4052 multiplexer in audio_hook().
903 */
1da177e4 904 if(nsr & 0x02) /* NSR.S/MB=1 */
3322a59e 905 mode |= V4L2_TUNER_SUB_STEREO;
1da177e4 906 if(nsr & 0x01) /* NSR.D/SB=1 */
3322a59e 907 mode |= V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
1da177e4
LT		 908 } else {
909 if(dsr & 0x02) /* DSR.IDSTE=1 */
3322a59e 910 mode |= V4L2_TUNER_SUB_STEREO;
1da177e4 911 if(dsr & 0x04) /* DSR.IDDUA=1 */
3322a59e 912 mode |= V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
1da177e4
LT		 913 }
914
64f70e7e 915 v4l2_dbg(1, debug, sd, "tda9874a_getmode(): DSR=0x%X, NSR=0x%X, NECR=0x%X, return: %d.\n",
1da177e4
LT		 916 dsr, nsr, necr, mode);
917 return mode;
918}
919
920static void tda9874a_setmode(struct CHIPSTATE *chip, int mode)
921{
64f70e7e
HV		 922 struct v4l2_subdev *sd = &chip->sd;
923
1da177e4
LT		 924 /* Disable/enable NICAM auto-muting (based on DSR.RSSF status bit). */
925 /* If auto-muting is disabled, we can hear a signal of degrading quality. */
64f70e7e 926 if (tda9874a_mode) {
1da177e4
LT		 927 if(chip->shadow.bytes[MAXREGS-2] & 0x20) /* DSR.RSSF=1 */
928 tda9874a_NCONR &= 0xfe; /* enable */
929 else
930 tda9874a_NCONR |= 0x01; /* disable */
931 chip_write(chip, TDA9874A_NCONR, tda9874a_NCONR);
932 }
933
934 /* Note: TDA9874A supports automatic FM dematrixing (FMMR register)
935 * and has auto-select function for audio output (AOSR register).
936 * Old TDA9874H doesn't support these features.
937 * TDA9874A also has additional mono output pin (OUTM), which
938 * on same (all?) tv-cards is not used, anyway (as well as MONOIN).
939 */
940 if(tda9874a_dic == 0x11) {
941 int aosr = 0x80;
942 int mdacosr = (tda9874a_mode) ? 0x82:0x80;
943
944 switch(mode) {
dc3d75da
MCC		 945 case V4L2_TUNER_MODE_MONO:
946 case V4L2_TUNER_MODE_STEREO:
1da177e4 947 break;
dc3d75da 948 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 949 aosr = 0x80; /* auto-select, dual A/A */
950 mdacosr = (tda9874a_mode) ? 0x82:0x80;
951 break;
dc3d75da 952 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 953 aosr = 0xa0; /* auto-select, dual B/B */
954 mdacosr = (tda9874a_mode) ? 0x83:0x81;
955 break;
956 default:
1da177e4
LT		 957 return;
958 }
959 chip_write(chip, TDA9874A_AOSR, aosr);
960 chip_write(chip, TDA9874A_MDACOSR, mdacosr);
961
64f70e7e 962 v4l2_dbg(1, debug, sd, "tda9874a_setmode(): req. mode %d; AOSR=0x%X, MDACOSR=0x%X.\n",
1da177e4
LT		 963 mode, aosr, mdacosr);
964
965 } else { /* dic == 0x07 */
966 int fmmr,aosr;
967
968 switch(mode) {
dc3d75da 969 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 970 fmmr = 0x00; /* mono */
971 aosr = 0x10; /* A/A */
972 break;
dc3d75da 973 case V4L2_TUNER_MODE_STEREO:
1da177e4
LT		 974 if(tda9874a_mode) {
975 fmmr = 0x00;
976 aosr = 0x00; /* handled by NICAM auto-mute */
977 } else {
978 fmmr = (tda9874a_ESP == 1) ? 0x05 : 0x04; /* stereo */
979 aosr = 0x00;
980 }
981 break;
dc3d75da 982 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 983 fmmr = 0x02; /* dual */
984 aosr = 0x10; /* dual A/A */
985 break;
dc3d75da 986 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 987 fmmr = 0x02; /* dual */
988 aosr = 0x20; /* dual B/B */
989 break;
990 default:
1da177e4
LT		 991 return;
992 }
993 chip_write(chip, TDA9874A_FMMR, fmmr);
994 chip_write(chip, TDA9874A_AOSR, aosr);
995
64f70e7e 996 v4l2_dbg(1, debug, sd, "tda9874a_setmode(): req. mode %d; FMMR=0x%X, AOSR=0x%X.\n",
1da177e4
LT		 997 mode, fmmr, aosr);
998 }
999}
1000
1001static int tda9874a_checkit(struct CHIPSTATE *chip)
1002{
64f70e7e 1003 struct v4l2_subdev *sd = &chip->sd;
1da177e4
LT		 1004 int dic,sic; /* device id. and software id. codes */
1005
1006 if(-1 == (dic = chip_read2(chip,TDA9874A_DIC)))
1007 return 0;
1008 if(-1 == (sic = chip_read2(chip,TDA9874A_SIC)))
1009 return 0;
1010
64f70e7e 1011 v4l2_dbg(1, debug, sd, "tda9874a_checkit(): DIC=0x%X, SIC=0x%X.\n", dic, sic);
1da177e4
LT		 1012
1013 if((dic == 0x11)||(dic == 0x07)) {
64f70e7e 1014 v4l2_info(sd, "found tda9874%s.\n", (dic == 0x11) ? "a" : "h");
1da177e4
LT		 1015 tda9874a_dic = dic; /* remember device id. */
1016 return 1;
1017 }
1018 return 0; /* not found */
1019}
1020
1021static int tda9874a_initialize(struct CHIPSTATE *chip)
1022{
1023 if (tda9874a_SIF > 2)
1024 tda9874a_SIF = 1;
04e6f990 1025 if (tda9874a_STD >= ARRAY_SIZE(tda9874a_modelist))
1da177e4
LT		 1026 tda9874a_STD = 0;
1027 if(tda9874a_AMSEL > 1)
1028 tda9874a_AMSEL = 0;
1029
1030 if(tda9874a_SIF == 1)
1031 tda9874a_GCONR = 0xc0; /* sound IF input 1 */
1032 else
1033 tda9874a_GCONR = 0xc1; /* sound IF input 2 */
1034
1035 tda9874a_ESP = tda9874a_STD;
1036 tda9874a_mode = (tda9874a_STD < 5) ? 0 : 1;
1037
1038 if(tda9874a_AMSEL == 0)
1039 tda9874a_NCONR = 0x01; /* auto-mute: analog mono input */
1040 else
1041 tda9874a_NCONR = 0x05; /* auto-mute: 1st carrier FM or AM */
1042
1043 tda9874a_setup(chip);
1044 return 0;
1045}
1046
411674fd
HV		 1047/* ---------------------------------------------------------------------- */
1048/* audio chip description - defines+functions for tda9875 */
1049/* The TDA9875 is made by Philips Semiconductor
1050 * http://www.semiconductors.philips.com
1051 * TDA9875: I2C-bus controlled DSP audio processor, FM demodulator
1052 *
1053 */
1054
1055/* subaddresses for TDA9875 */
1056#define TDA9875_MUT 0x12 /*General mute (value --> 0b11001100*/
1057#define TDA9875_CFG 0x01 /* Config register (value --> 0b00000000 */
1058#define TDA9875_DACOS 0x13 /*DAC i/o select (ADC) 0b0000100*/
1059#define TDA9875_LOSR 0x16 /*Line output select regirter 0b0100 0001*/
1060
1061#define TDA9875_CH1V 0x0c /*Channel 1 volume (mute)*/
1062#define TDA9875_CH2V 0x0d /*Channel 2 volume (mute)*/
1063#define TDA9875_SC1 0x14 /*SCART 1 in (mono)*/
1064#define TDA9875_SC2 0x15 /*SCART 2 in (mono)*/
1065
1066#define TDA9875_ADCIS 0x17 /*ADC input select (mono) 0b0110 000*/
1067#define TDA9875_AER 0x19 /*Audio effect (AVL+Pseudo) 0b0000 0110*/
1068#define TDA9875_MCS 0x18 /*Main channel select (DAC) 0b0000100*/
1069#define TDA9875_MVL 0x1a /* Main volume gauche */
1070#define TDA9875_MVR 0x1b /* Main volume droite */
1071#define TDA9875_MBA 0x1d /* Main Basse */
1072#define TDA9875_MTR 0x1e /* Main treble */
25985edc
LDM		 1073#define TDA9875_ACS 0x1f /* Auxiliary channel select (FM) 0b0000000*/
1074#define TDA9875_AVL 0x20 /* Auxiliary volume gauche */
1075#define TDA9875_AVR 0x21 /* Auxiliary volume droite */
1076#define TDA9875_ABA 0x22 /* Auxiliary Basse */
1077#define TDA9875_ATR 0x23 /* Auxiliary treble */
411674fd
HV		 1078
1079#define TDA9875_MSR 0x02 /* Monitor select register */
1080#define TDA9875_C1MSB 0x03 /* Carrier 1 (FM) frequency register MSB */
1081#define TDA9875_C1MIB 0x04 /* Carrier 1 (FM) frequency register (16-8]b */
1082#define TDA9875_C1LSB 0x05 /* Carrier 1 (FM) frequency register LSB */
1083#define TDA9875_C2MSB 0x06 /* Carrier 2 (nicam) frequency register MSB */
1084#define TDA9875_C2MIB 0x07 /* Carrier 2 (nicam) frequency register (16-8]b */
1085#define TDA9875_C2LSB 0x08 /* Carrier 2 (nicam) frequency register LSB */
1086#define TDA9875_DCR 0x09 /* Demodulateur configuration regirter*/
1087#define TDA9875_DEEM 0x0a /* FM de-emphasis regirter*/
1088#define TDA9875_FMAT 0x0b /* FM Matrix regirter*/
1089
1090/* values */
1091#define TDA9875_MUTE_ON 0xff /* general mute */
1092#define TDA9875_MUTE_OFF 0xcc /* general no mute */
1093
1094static int tda9875_initialize(struct CHIPSTATE *chip)
1095{
1096 chip_write(chip, TDA9875_CFG, 0xd0); /*reg de config 0 (reset)*/
1097 chip_write(chip, TDA9875_MSR, 0x03); /* Monitor 0b00000XXX*/
1098 chip_write(chip, TDA9875_C1MSB, 0x00); /*Car1(FM) MSB XMHz*/
1099 chip_write(chip, TDA9875_C1MIB, 0x00); /*Car1(FM) MIB XMHz*/
1100 chip_write(chip, TDA9875_C1LSB, 0x00); /*Car1(FM) LSB XMHz*/
1101 chip_write(chip, TDA9875_C2MSB, 0x00); /*Car2(NICAM) MSB XMHz*/
1102 chip_write(chip, TDA9875_C2MIB, 0x00); /*Car2(NICAM) MIB XMHz*/
1103 chip_write(chip, TDA9875_C2LSB, 0x00); /*Car2(NICAM) LSB XMHz*/
1104 chip_write(chip, TDA9875_DCR, 0x00); /*Demod config 0x00*/
1105 chip_write(chip, TDA9875_DEEM, 0x44); /*DE-Emph 0b0100 0100*/
1106 chip_write(chip, TDA9875_FMAT, 0x00); /*FM Matrix reg 0x00*/
1107 chip_write(chip, TDA9875_SC1, 0x00); /* SCART 1 (SC1)*/
1108 chip_write(chip, TDA9875_SC2, 0x01); /* SCART 2 (sc2)*/
1109
1110 chip_write(chip, TDA9875_CH1V, 0x10); /* Channel volume 1 mute*/
1111 chip_write(chip, TDA9875_CH2V, 0x10); /* Channel volume 2 mute */
1112 chip_write(chip, TDA9875_DACOS, 0x02); /* sig DAC i/o(in:nicam)*/
1113 chip_write(chip, TDA9875_ADCIS, 0x6f); /* sig ADC input(in:mono)*/
1114 chip_write(chip, TDA9875_LOSR, 0x00); /* line out (in:mono)*/
1115 chip_write(chip, TDA9875_AER, 0x00); /*06 Effect (AVL+PSEUDO) */
1116 chip_write(chip, TDA9875_MCS, 0x44); /* Main ch select (DAC) */
1117 chip_write(chip, TDA9875_MVL, 0x03); /* Vol Main left 10dB */
1118 chip_write(chip, TDA9875_MVR, 0x03); /* Vol Main right 10dB*/
1119 chip_write(chip, TDA9875_MBA, 0x00); /* Main Bass Main 0dB*/
1120 chip_write(chip, TDA9875_MTR, 0x00); /* Main Treble Main 0dB*/
1121 chip_write(chip, TDA9875_ACS, 0x44); /* Aux chan select (dac)*/
1122 chip_write(chip, TDA9875_AVL, 0x00); /* Vol Aux left 0dB*/
1123 chip_write(chip, TDA9875_AVR, 0x00); /* Vol Aux right 0dB*/
1124 chip_write(chip, TDA9875_ABA, 0x00); /* Aux Bass Main 0dB*/
1125 chip_write(chip, TDA9875_ATR, 0x00); /* Aux Aigus Main 0dB*/
1126
1127 chip_write(chip, TDA9875_MUT, 0xcc); /* General mute */
1128 return 0;
1129}
1130
1131static int tda9875_volume(int val) { return (unsigned char)(val / 602 - 84); }
1132static int tda9875_bass(int val) { return (unsigned char)(max(-12, val / 2115 - 15)); }
1133static int tda9875_treble(int val) { return (unsigned char)(val / 2622 - 12); }
1134
1135/* ----------------------------------------------------------------------- */
1136
1137
1138/* *********************** *
1139 * i2c interface functions *
1140 * *********************** */
1141
1142static int tda9875_checkit(struct CHIPSTATE *chip)
1143{
1144 struct v4l2_subdev *sd = &chip->sd;
1145 int dic, rev;
1146
1147 dic = chip_read2(chip, 254);
1148 rev = chip_read2(chip, 255);
1149
1150 if (dic == 0 || dic == 2) { /* tda9875 and tda9875A */
1151 v4l2_info(sd, "found tda9875%s rev. %d.\n",
1152 dic == 0 ? "" : "A", rev);
1153 return 1;
1154 }
1155 return 0;
1156}
1da177e4
LT		 1157
1158/* ---------------------------------------------------------------------- */
1159/* audio chip descriptions - defines+functions for tea6420 */
1160
1161#define TEA6300_VL 0x00 /* volume left */
1162#define TEA6300_VR 0x01 /* volume right */
1163#define TEA6300_BA 0x02 /* bass */
1164#define TEA6300_TR 0x03 /* treble */
1165#define TEA6300_FA 0x04 /* fader control */
1166#define TEA6300_S 0x05 /* switch register */
f2421ca3 1167 /* values for those registers: */
1da177e4
LT		 1168#define TEA6300_S_SA 0x01 /* stereo A input */
1169#define TEA6300_S_SB 0x02 /* stereo B */
1170#define TEA6300_S_SC 0x04 /* stereo C */
1171#define TEA6300_S_GMU 0x80 /* general mute */
1172
1173#define TEA6320_V 0x00 /* volume (0-5)/loudness off (6)/zero crossing mute(7) */
1174#define TEA6320_FFR 0x01 /* fader front right (0-5) */
1175#define TEA6320_FFL 0x02 /* fader front left (0-5) */
1176#define TEA6320_FRR 0x03 /* fader rear right (0-5) */
1177#define TEA6320_FRL 0x04 /* fader rear left (0-5) */
1178#define TEA6320_BA 0x05 /* bass (0-4) */
1179#define TEA6320_TR 0x06 /* treble (0-4) */
1180#define TEA6320_S 0x07 /* switch register */
f2421ca3 1181 /* values for those registers: */
1da177e4
LT		 1182#define TEA6320_S_SA 0x07 /* stereo A input */
1183#define TEA6320_S_SB 0x06 /* stereo B */
1184#define TEA6320_S_SC 0x05 /* stereo C */
1185#define TEA6320_S_SD 0x04 /* stereo D */
1186#define TEA6320_S_GMU 0x80 /* general mute */
1187
1188#define TEA6420_S_SA 0x00 /* stereo A input */
1189#define TEA6420_S_SB 0x01 /* stereo B */
1190#define TEA6420_S_SC 0x02 /* stereo C */
1191#define TEA6420_S_SD 0x03 /* stereo D */
1192#define TEA6420_S_SE 0x04 /* stereo E */
1193#define TEA6420_S_GMU 0x05 /* general mute */
1194
1195static int tea6300_shift10(int val) { return val >> 10; }
1196static int tea6300_shift12(int val) { return val >> 12; }
1197
1198/* Assumes 16bit input (values 0x3f to 0x0c are unique, values less than */
1199/* 0x0c mirror those immediately higher) */
1200static int tea6320_volume(int val) { return (val / (65535/(63-12)) + 12) & 0x3f; }
1201static int tea6320_shift11(int val) { return val >> 11; }
1202static int tea6320_initialize(struct CHIPSTATE * chip)
1203{
1204 chip_write(chip, TEA6320_FFR, 0x3f);
1205 chip_write(chip, TEA6320_FFL, 0x3f);
1206 chip_write(chip, TEA6320_FRR, 0x3f);
1207 chip_write(chip, TEA6320_FRL, 0x3f);
1208
1209 return 0;
1210}
1211
1212
1213/* ---------------------------------------------------------------------- */
1214/* audio chip descriptions - defines+functions for tda8425 */
1215
1216#define TDA8425_VL 0x00 /* volume left */
1217#define TDA8425_VR 0x01 /* volume right */
1218#define TDA8425_BA 0x02 /* bass */
1219#define TDA8425_TR 0x03 /* treble */
1220#define TDA8425_S1 0x08 /* switch functions */
f2421ca3 1221 /* values for those registers: */
1da177e4
LT		 1222#define TDA8425_S1_OFF 0xEE /* audio off (mute on) */
1223#define TDA8425_S1_CH1 0xCE /* audio channel 1 (mute off) - "linear stereo" mode */
1224#define TDA8425_S1_CH2 0xCF /* audio channel 2 (mute off) - "linear stereo" mode */
1225#define TDA8425_S1_MU 0x20 /* mute bit */
1226#define TDA8425_S1_STEREO 0x18 /* stereo bits */
1227#define TDA8425_S1_STEREO_SPATIAL 0x18 /* spatial stereo */
1228#define TDA8425_S1_STEREO_LINEAR 0x08 /* linear stereo */
1229#define TDA8425_S1_STEREO_PSEUDO 0x10 /* pseudo stereo */
1230#define TDA8425_S1_STEREO_MONO 0x00 /* forced mono */
1231#define TDA8425_S1_ML 0x06 /* language selector */
1232#define TDA8425_S1_ML_SOUND_A 0x02 /* sound a */
1233#define TDA8425_S1_ML_SOUND_B 0x04 /* sound b */
1234#define TDA8425_S1_ML_STEREO 0x06 /* stereo */
1235#define TDA8425_S1_IS 0x01 /* channel selector */
1236
1237
1238static int tda8425_shift10(int val) { return (val >> 10) | 0xc0; }
1239static int tda8425_shift12(int val) { return (val >> 12) | 0xf0; }
1240
1da177e4
LT		 1241static void tda8425_setmode(struct CHIPSTATE *chip, int mode)
1242{
1243 int s1 = chip->shadow.bytes[TDA8425_S1+1] & 0xe1;
1244
f952848d
DG		 1245 switch (mode) {
1246 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 1247 s1 |= TDA8425_S1_ML_SOUND_A;
1248 s1 |= TDA8425_S1_STEREO_PSEUDO;
f952848d
DG		 1249 break;
1250 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 1251 s1 |= TDA8425_S1_ML_SOUND_B;
1252 s1 |= TDA8425_S1_STEREO_PSEUDO;
f952848d
DG		 1253 break;
1254 case V4L2_TUNER_MODE_MONO:
1da177e4 1255 s1 |= TDA8425_S1_ML_STEREO;
f952848d
DG		 1256 s1 |= TDA8425_S1_STEREO_MONO;
1257 break;
1258 case V4L2_TUNER_MODE_STEREO:
1259 s1 |= TDA8425_S1_ML_STEREO;
1260 s1 |= TDA8425_S1_STEREO_SPATIAL;
1261 break;
1262 default:
1263 return;
1da177e4
LT		 1264 }
1265 chip_write(chip,TDA8425_S1,s1);
1266}
1267
1268
1269/* ---------------------------------------------------------------------- */
1270/* audio chip descriptions - defines+functions for pic16c54 (PV951) */
1271
1272/* the registers of 16C54, I2C sub address. */
1273#define PIC16C54_REG_KEY_CODE 0x01 /* Not use. */
1274#define PIC16C54_REG_MISC 0x02
1275
1276/* bit definition of the RESET register, I2C data. */
1277#define PIC16C54_MISC_RESET_REMOTE_CTL 0x01 /* bit 0, Reset to receive the key */
f2421ca3 1278 /* code of remote controller */
1da177e4
LT		 1279#define PIC16C54_MISC_MTS_MAIN 0x02 /* bit 1 */
1280#define PIC16C54_MISC_MTS_SAP 0x04 /* bit 2 */
1281#define PIC16C54_MISC_MTS_BOTH 0x08 /* bit 3 */
1282#define PIC16C54_MISC_SND_MUTE 0x10 /* bit 4, Mute Audio(Line-in and Tuner) */
1283#define PIC16C54_MISC_SND_NOTMUTE 0x20 /* bit 5 */
1284#define PIC16C54_MISC_SWITCH_TUNER 0x40 /* bit 6 , Switch to Line-in */
1285#define PIC16C54_MISC_SWITCH_LINE 0x80 /* bit 7 , Switch to Tuner */
1286
1287/* ---------------------------------------------------------------------- */
1288/* audio chip descriptions - defines+functions for TA8874Z */
1289
18fc59e2 1290/* write 1st byte */
1da177e4
LT		 1291#define TA8874Z_LED_STE 0x80
1292#define TA8874Z_LED_BIL 0x40
1293#define TA8874Z_LED_EXT 0x20
1294#define TA8874Z_MONO_SET 0x10
1295#define TA8874Z_MUTE 0x08
1296#define TA8874Z_F_MONO 0x04
1297#define TA8874Z_MODE_SUB 0x02
1298#define TA8874Z_MODE_MAIN 0x01
1299
18fc59e2
MCC		 1300/* write 2nd byte */
1301/*#define TA8874Z_TI 0x80 */ /* test mode */
1da177e4
LT		 1302#define TA8874Z_SEPARATION 0x3f
1303#define TA8874Z_SEPARATION_DEFAULT 0x10
1304
18fc59e2 1305/* read */
1da177e4
LT		 1306#define TA8874Z_B1 0x80
1307#define TA8874Z_B0 0x40
1308#define TA8874Z_CHAG_FLAG 0x20
1309
18fc59e2
MCC		 1310/*
1311 * B1 B0
1312 * mono L H
1313 * stereo L L
1314 * BIL H L
1315 */
1da177e4
LT		 1316static int ta8874z_getmode(struct CHIPSTATE *chip)
1317{
1318 int val, mode;
1319
1320 val = chip_read(chip);
3322a59e 1321 mode = V4L2_TUNER_SUB_MONO;
1da177e4 1322 if (val & TA8874Z_B1){
3322a59e 1323 mode |= V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
1da177e4 1324 }else if (!(val & TA8874Z_B0)){
3322a59e 1325 mode |= V4L2_TUNER_SUB_STEREO;
1da177e4 1326 }
08e14054 1327 /* v4l_dbg(1, debug, chip->c, "ta8874z_getmode(): raw chip read: 0x%02x, return: 0x%02x\n", val, mode); */
1da177e4
LT		 1328 return mode;
1329}
1330
1331static audiocmd ta8874z_stereo = { 2, {0, TA8874Z_SEPARATION_DEFAULT}};
1332static audiocmd ta8874z_mono = {2, { TA8874Z_MONO_SET, TA8874Z_SEPARATION_DEFAULT}};
1333static audiocmd ta8874z_main = {2, { 0, TA8874Z_SEPARATION_DEFAULT}};
1334static audiocmd ta8874z_sub = {2, { TA8874Z_MODE_SUB, TA8874Z_SEPARATION_DEFAULT}};
1335
1336static void ta8874z_setmode(struct CHIPSTATE *chip, int mode)
1337{
64f70e7e 1338 struct v4l2_subdev *sd = &chip->sd;
1da177e4
LT		 1339 int update = 1;
1340 audiocmd *t = NULL;
64f70e7e
HV		 1341
1342 v4l2_dbg(1, debug, sd, "ta8874z_setmode(): mode: 0x%02x\n", mode);
1da177e4
LT		 1343
1344 switch(mode){
dc3d75da 1345 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 1346 t = &ta8874z_mono;
1347 break;
dc3d75da 1348 case V4L2_TUNER_MODE_STEREO:
1da177e4
LT		 1349 t = &ta8874z_stereo;
1350 break;
dc3d75da 1351 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 1352 t = &ta8874z_main;
1353 break;
dc3d75da 1354 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 1355 t = &ta8874z_sub;
1356 break;
1357 default:
1358 update = 0;
1359 }
1360
1361 if(update)
1362 chip_cmd(chip, "TA8874Z", t);
1363}
1364
1365static int ta8874z_checkit(struct CHIPSTATE *chip)
1366{
1367 int rc;
1368 rc = chip_read(chip);
1369 return ((rc & 0x1f) == 0x1f) ? 1 : 0;
1370}
1371
1372/* ---------------------------------------------------------------------- */
1373/* audio chip descriptions - struct CHIPDESC */
1374
1375/* insmod options to enable/disable individual audio chips */
52c1da39
AB		 1376static int tda8425 = 1;
1377static int tda9840 = 1;
1378static int tda9850 = 1;
1379static int tda9855 = 1;
1380static int tda9873 = 1;
1381static int tda9874a = 1;
411674fd 1382static int tda9875 = 1;
ff699e6b
DSL		 1383static int tea6300; /* default 0 - address clash with msp34xx */
1384static int tea6320; /* default 0 - address clash with msp34xx */
52c1da39
AB		 1385static int tea6420 = 1;
1386static int pic16c54 = 1;
ff699e6b 1387static int ta8874z; /* default 0 - address clash with tda9840 */
1da177e4
LT		 1388
1389module_param(tda8425, int, 0444);
1390module_param(tda9840, int, 0444);
1391module_param(tda9850, int, 0444);
1392module_param(tda9855, int, 0444);
1393module_param(tda9873, int, 0444);
1394module_param(tda9874a, int, 0444);
411674fd 1395module_param(tda9875, int, 0444);
1da177e4
LT		 1396module_param(tea6300, int, 0444);
1397module_param(tea6320, int, 0444);
1398module_param(tea6420, int, 0444);
1399module_param(pic16c54, int, 0444);
1400module_param(ta8874z, int, 0444);
1401
1402static struct CHIPDESC chiplist[] = {
1403 {
1404 .name = "tda9840",
1da177e4 1405 .insmodopt = &tda9840,
09df1c16
MCC		 1406 .addr_lo = I2C_ADDR_TDA9840 >> 1,
1407 .addr_hi = I2C_ADDR_TDA9840 >> 1,
1da177e4 1408 .registers = 5,
dd03e970 1409 .flags = CHIP_NEED_CHECKMODE,
1da177e4 1410
af1a9951 1411 /* callbacks */
94f9e56e 1412 .checkit = tda9840_checkit,
1da177e4
LT		 1413 .getmode = tda9840_getmode,
1414 .setmode = tda9840_setmode,
1da177e4 1415
4ac97914 1416 .init = { 2, { TDA9840_TEST, TDA9840_TEST_INT1SN
1da177e4
LT		 1417 /* ,TDA9840_SW, TDA9840_MONO */} }
1418 },
1419 {
1420 .name = "tda9873h",
1da177e4 1421 .insmodopt = &tda9873,
09df1c16
MCC		 1422 .addr_lo = I2C_ADDR_TDA985x_L >> 1,
1423 .addr_hi = I2C_ADDR_TDA985x_H >> 1,
1da177e4 1424 .registers = 3,
dd03e970 1425 .flags = CHIP_HAS_INPUTSEL | CHIP_NEED_CHECKMODE,
1da177e4 1426
af1a9951
MCC		 1427 /* callbacks */
1428 .checkit = tda9873_checkit,
1da177e4
LT		 1429 .getmode = tda9873_getmode,
1430 .setmode = tda9873_setmode,
1da177e4
LT		 1431
1432 .init = { 4, { TDA9873_SW, 0xa4, 0x06, 0x03 } },
1433 .inputreg = TDA9873_SW,
1434 .inputmute = TDA9873_MUTE | TDA9873_AUTOMUTE,
8bf2f8e7 1435 .inputmap = {0xa0, 0xa2, 0xa0, 0xa0},
1da177e4
LT		 1436 .inputmask = TDA9873_INP_MASK|TDA9873_MUTE|TDA9873_AUTOMUTE,
1437
1438 },
1439 {
1440 .name = "tda9874h/a",
1da177e4 1441 .insmodopt = &tda9874a,
09df1c16
MCC		 1442 .addr_lo = I2C_ADDR_TDA9874 >> 1,
1443 .addr_hi = I2C_ADDR_TDA9874 >> 1,
dd03e970 1444 .flags = CHIP_NEED_CHECKMODE,
1da177e4 1445
af1a9951
MCC		 1446 /* callbacks */
1447 .initialize = tda9874a_initialize,
1448 .checkit = tda9874a_checkit,
1da177e4
LT		 1449 .getmode = tda9874a_getmode,
1450 .setmode = tda9874a_setmode,
1da177e4 1451 },
411674fd
HV		 1452 {
1453 .name = "tda9875",
1454 .insmodopt = &tda9875,
1455 .addr_lo = I2C_ADDR_TDA9875 >> 1,
1456 .addr_hi = I2C_ADDR_TDA9875 >> 1,
1457 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE,
1458
1459 /* callbacks */
1460 .initialize = tda9875_initialize,
1461 .checkit = tda9875_checkit,
1462 .volfunc = tda9875_volume,
1463 .bassfunc = tda9875_bass,
1464 .treblefunc = tda9875_treble,
1465 .leftreg = TDA9875_MVL,
1466 .rightreg = TDA9875_MVR,
1467 .bassreg = TDA9875_MBA,
1468 .treblereg = TDA9875_MTR,
1469 .leftinit = 58880,
1470 .rightinit = 58880,
1471 },
1da177e4
LT		 1472 {
1473 .name = "tda9850",
1da177e4 1474 .insmodopt = &tda9850,
09df1c16
MCC		 1475 .addr_lo = I2C_ADDR_TDA985x_L >> 1,
1476 .addr_hi = I2C_ADDR_TDA985x_H >> 1,
1da177e4
LT		 1477 .registers = 11,
1478
1479 .getmode = tda985x_getmode,
1480 .setmode = tda985x_setmode,
1481
1482 .init = { 8, { TDA9850_C4, 0x08, 0x08, TDA985x_STEREO, 0x07, 0x10, 0x10, 0x03 } }
1483 },
1484 {
1485 .name = "tda9855",
1da177e4 1486 .insmodopt = &tda9855,
09df1c16
MCC		 1487 .addr_lo = I2C_ADDR_TDA985x_L >> 1,
1488 .addr_hi = I2C_ADDR_TDA985x_H >> 1,
1da177e4
LT		 1489 .registers = 11,
1490 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE,
1491
1492 .leftreg = TDA9855_VL,
1493 .rightreg = TDA9855_VR,
1494 .bassreg = TDA9855_BA,
1495 .treblereg = TDA9855_TR,
af1a9951
MCC		 1496
1497 /* callbacks */
1da177e4
LT		 1498 .volfunc = tda9855_volume,
1499 .bassfunc = tda9855_bass,
1500 .treblefunc = tda9855_treble,
1da177e4
LT		 1501 .getmode = tda985x_getmode,
1502 .setmode = tda985x_setmode,
1503
1504 .init = { 12, { 0, 0x6f, 0x6f, 0x0e, 0x07<<1, 0x8<<2,
1505 TDA9855_MUTE | TDA9855_AVL | TDA9855_LOUD | TDA9855_INT,
1506 TDA985x_STEREO | TDA9855_LINEAR | TDA9855_TZCM | TDA9855_VZCM,
1507 0x07, 0x10, 0x10, 0x03 }}
1508 },
1509 {
1510 .name = "tea6300",
1da177e4 1511 .insmodopt = &tea6300,
09df1c16
MCC		 1512 .addr_lo = I2C_ADDR_TEA6300 >> 1,
1513 .addr_hi = I2C_ADDR_TEA6300 >> 1,
1da177e4
LT		 1514 .registers = 6,
1515 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE | CHIP_HAS_INPUTSEL,
1516
1517 .leftreg = TEA6300_VR,
1518 .rightreg = TEA6300_VL,
1519 .bassreg = TEA6300_BA,
1520 .treblereg = TEA6300_TR,
af1a9951
MCC		 1521
1522 /* callbacks */
1da177e4
LT		 1523 .volfunc = tea6300_shift10,
1524 .bassfunc = tea6300_shift12,
1525 .treblefunc = tea6300_shift12,
1526
1527 .inputreg = TEA6300_S,
1528 .inputmap = { TEA6300_S_SA, TEA6300_S_SB, TEA6300_S_SC },
1529 .inputmute = TEA6300_S_GMU,
1530 },
1531 {
1532 .name = "tea6320",
1da177e4 1533 .insmodopt = &tea6320,
09df1c16
MCC		 1534 .addr_lo = I2C_ADDR_TEA6300 >> 1,
1535 .addr_hi = I2C_ADDR_TEA6300 >> 1,
1da177e4
LT		 1536 .registers = 8,
1537 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE | CHIP_HAS_INPUTSEL,
1538
1539 .leftreg = TEA6320_V,
1540 .rightreg = TEA6320_V,
1541 .bassreg = TEA6320_BA,
1542 .treblereg = TEA6320_TR,
af1a9951
MCC		 1543
1544 /* callbacks */
1545 .initialize = tea6320_initialize,
1da177e4
LT		 1546 .volfunc = tea6320_volume,
1547 .bassfunc = tea6320_shift11,
1548 .treblefunc = tea6320_shift11,
1549
1550 .inputreg = TEA6320_S,
1551 .inputmap = { TEA6320_S_SA, TEA6420_S_SB, TEA6300_S_SC, TEA6320_S_SD },
1552 .inputmute = TEA6300_S_GMU,
1553 },
1554 {
1555 .name = "tea6420",
1da177e4 1556 .insmodopt = &tea6420,
09df1c16
MCC		 1557 .addr_lo = I2C_ADDR_TEA6420 >> 1,
1558 .addr_hi = I2C_ADDR_TEA6420 >> 1,
1da177e4
LT		 1559 .registers = 1,
1560 .flags = CHIP_HAS_INPUTSEL,
1561
1562 .inputreg = -1,
1563 .inputmap = { TEA6420_S_SA, TEA6420_S_SB, TEA6420_S_SC },
1564 .inputmute = TEA6300_S_GMU,
1565 },
1566 {
1567 .name = "tda8425",
1da177e4 1568 .insmodopt = &tda8425,
09df1c16
MCC		 1569 .addr_lo = I2C_ADDR_TDA8425 >> 1,
1570 .addr_hi = I2C_ADDR_TDA8425 >> 1,
1da177e4
LT		 1571 .registers = 9,
1572 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE | CHIP_HAS_INPUTSEL,
1573
1574 .leftreg = TDA8425_VL,
1575 .rightreg = TDA8425_VR,
1576 .bassreg = TDA8425_BA,
1577 .treblereg = TDA8425_TR,
af1a9951
MCC		 1578
1579 /* callbacks */
1da177e4
LT		 1580 .volfunc = tda8425_shift10,
1581 .bassfunc = tda8425_shift12,
1582 .treblefunc = tda8425_shift12,
af1a9951 1583 .setmode = tda8425_setmode,
1da177e4
LT		 1584
1585 .inputreg = TDA8425_S1,
1586 .inputmap = { TDA8425_S1_CH1, TDA8425_S1_CH1, TDA8425_S1_CH1 },
1587 .inputmute = TDA8425_S1_OFF,
1588
1da177e4
LT		 1589 },
1590 {
1591 .name = "pic16c54 (PV951)",
1da177e4 1592 .insmodopt = &pic16c54,
09df1c16
MCC		 1593 .addr_lo = I2C_ADDR_PIC16C54 >> 1,
1594 .addr_hi = I2C_ADDR_PIC16C54>> 1,
1da177e4
LT		 1595 .registers = 2,
1596 .flags = CHIP_HAS_INPUTSEL,
1597
1598 .inputreg = PIC16C54_REG_MISC,
1599 .inputmap = {PIC16C54_MISC_SND_NOTMUTE|PIC16C54_MISC_SWITCH_TUNER,
1600 PIC16C54_MISC_SND_NOTMUTE|PIC16C54_MISC_SWITCH_LINE,
1601 PIC16C54_MISC_SND_NOTMUTE|PIC16C54_MISC_SWITCH_LINE,
8bf2f8e7 1602 PIC16C54_MISC_SND_MUTE},
1da177e4
LT		 1603 .inputmute = PIC16C54_MISC_SND_MUTE,
1604 },
1605 {
1606 .name = "ta8874z",
1da177e4
LT		 1607 .checkit = ta8874z_checkit,
1608 .insmodopt = &ta8874z,
09df1c16
MCC		 1609 .addr_lo = I2C_ADDR_TDA9840 >> 1,
1610 .addr_hi = I2C_ADDR_TDA9840 >> 1,
1da177e4
LT		 1611 .registers = 2,
1612
af1a9951 1613 /* callbacks */
1da177e4
LT		 1614 .getmode = ta8874z_getmode,
1615 .setmode = ta8874z_setmode,
1da177e4 1616
4ac97914 1617 .init = {2, { TA8874Z_MONO_SET, TA8874Z_SEPARATION_DEFAULT}},
1da177e4
LT		 1618 },
1619 { .name = NULL } /* EOF */
1620};
1621
1622
1623/* ---------------------------------------------------------------------- */
1da177e4 1624
64f70e7e 1625static int tvaudio_g_ctrl(struct v4l2_subdev *sd,
dc3d75da
MCC		 1626 struct v4l2_control *ctrl)
1627{
64f70e7e 1628 struct CHIPSTATE *chip = to_state(sd);
81cb5c4f 1629 struct CHIPDESC *desc = chip->desc;
dc3d75da
MCC		 1630
1631 switch (ctrl->id) {
1632 case V4L2_CID_AUDIO_MUTE:
5fa7b9f3
HV		 1633 if (!(desc->flags & CHIP_HAS_INPUTSEL))
1634 break;
dc3d75da
MCC		 1635 ctrl->value=chip->muted;
1636 return 0;
1637 case V4L2_CID_AUDIO_VOLUME:
18c0ecf1 1638 if (!(desc->flags & CHIP_HAS_VOLUME))
dc3d75da
MCC		 1639 break;
1640 ctrl->value = max(chip->left,chip->right);
1641 return 0;
1642 case V4L2_CID_AUDIO_BALANCE:
1643 {
1644 int volume;
18c0ecf1 1645 if (!(desc->flags & CHIP_HAS_VOLUME))
dc3d75da
MCC		 1646 break;
1647 volume = max(chip->left,chip->right);
1648 if (volume)
1649 ctrl->value=(32768*min(chip->left,chip->right))/volume;
1650 else
1651 ctrl->value=32768;
1652 return 0;
1653 }
1654 case V4L2_CID_AUDIO_BASS:
01a1a3cc 1655 if (!(desc->flags & CHIP_HAS_BASSTREBLE))
dc3d75da
MCC		 1656 break;
1657 ctrl->value = chip->bass;
1658 return 0;
1659 case V4L2_CID_AUDIO_TREBLE:
01a1a3cc
MCC		 1660 if (!(desc->flags & CHIP_HAS_BASSTREBLE))
1661 break;
dc3d75da
MCC		 1662 ctrl->value = chip->treble;
1663 return 0;
1664 }
1665 return -EINVAL;
1666}
1667
64f70e7e 1668static int tvaudio_s_ctrl(struct v4l2_subdev *sd,
dc3d75da 1669 struct v4l2_control *ctrl)
8bf2f8e7 1670{
64f70e7e 1671 struct CHIPSTATE *chip = to_state(sd);
81cb5c4f 1672 struct CHIPDESC *desc = chip->desc;
8bf2f8e7
HV		 1673
1674 switch (ctrl->id) {
1675 case V4L2_CID_AUDIO_MUTE:
5fa7b9f3
HV		 1676 if (!(desc->flags & CHIP_HAS_INPUTSEL))
1677 break;
1678
8bf2f8e7
HV		 1679 if (ctrl->value < 0 || ctrl->value >= 2)
1680 return -ERANGE;
1681 chip->muted = ctrl->value;
1682 if (chip->muted)
1683 chip_write_masked(chip,desc->inputreg,desc->inputmute,desc->inputmask);
1684 else
1685 chip_write_masked(chip,desc->inputreg,
1686 desc->inputmap[chip->input],desc->inputmask);
dc3d75da
MCC		 1687 return 0;
1688 case V4L2_CID_AUDIO_VOLUME:
1689 {
1690 int volume,balance;
1691
18c0ecf1 1692 if (!(desc->flags & CHIP_HAS_VOLUME))
dc3d75da
MCC		 1693 break;
1694
1695 volume = max(chip->left,chip->right);
1696 if (volume)
1697 balance=(32768*min(chip->left,chip->right))/volume;
1698 else
1699 balance=32768;
1700
1701 volume=ctrl->value;
1702 chip->left = (min(65536 - balance,32768) * volume) / 32768;
1703 chip->right = (min(balance,volume *(__u16)32768)) / 32768;
1704
1705 chip_write(chip,desc->leftreg,desc->volfunc(chip->left));
1706 chip_write(chip,desc->rightreg,desc->volfunc(chip->right));
1707
1708 return 0;
8bf2f8e7 1709 }
dc3d75da
MCC		 1710 case V4L2_CID_AUDIO_BALANCE:
1711 {
1712 int volume, balance;
88af8304 1713
18c0ecf1 1714 if (!(desc->flags & CHIP_HAS_VOLUME))
dc3d75da
MCC		 1715 break;
1716
88af8304 1717 volume = max(chip->left, chip->right);
dc3d75da 1718 balance = ctrl->value;
88af8304
HV		 1719 chip->left = (min(65536 - balance, 32768) * volume) / 32768;
1720 chip->right = (min(balance, volume * (__u16)32768)) / 32768;
dc3d75da 1721
88af8304
HV		 1722 chip_write(chip, desc->leftreg, desc->volfunc(chip->left));
1723 chip_write(chip, desc->rightreg, desc->volfunc(chip->right));
dc3d75da
MCC		 1724
1725 return 0;
1726 }
1727 case V4L2_CID_AUDIO_BASS:
01a1a3cc 1728 if (!(desc->flags & CHIP_HAS_BASSTREBLE))
dc3d75da
MCC		 1729 break;
1730 chip->bass = ctrl->value;
1731 chip_write(chip,desc->bassreg,desc->bassfunc(chip->bass));
1732
1733 return 0;
1734 case V4L2_CID_AUDIO_TREBLE:
01a1a3cc
MCC		 1735 if (!(desc->flags & CHIP_HAS_BASSTREBLE))
1736 break;
dc3d75da
MCC		 1737 chip->treble = ctrl->value;
1738 chip_write(chip,desc->treblereg,desc->treblefunc(chip->treble));
1739
1740 return 0;
1741 }
1742 return -EINVAL;
8bf2f8e7
HV		 1743}
1744
1745
1da177e4
LT		 1746/* ---------------------------------------------------------------------- */
1747/* video4linux interface */
1748
64f70e7e 1749static int tvaudio_s_radio(struct v4l2_subdev *sd)
1da177e4 1750{
64f70e7e 1751 struct CHIPSTATE *chip = to_state(sd);
1da177e4 1752
64f70e7e 1753 chip->radio = 1;
64f70e7e
HV		 1754 /* del_timer(&chip->wt); */
1755 return 0;
1756}
1757
1758static int tvaudio_queryctrl(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc)
1759{
1760 struct CHIPSTATE *chip = to_state(sd);
1761 struct CHIPDESC *desc = chip->desc;
1762
1763 switch (qc->id) {
1764 case V4L2_CID_AUDIO_MUTE:
5fa7b9f3
HV		 1765 if (desc->flags & CHIP_HAS_INPUTSEL)
1766 return v4l2_ctrl_query_fill(qc, 0, 1, 1, 0);
1767 break;
64f70e7e 1768 case V4L2_CID_AUDIO_VOLUME:
10afbef1
HV		 1769 if (desc->flags & CHIP_HAS_VOLUME)
1770 return v4l2_ctrl_query_fill(qc, 0, 65535, 65535 / 100, 58880);
1771 break;
64f70e7e 1772 case V4L2_CID_AUDIO_BALANCE:
10afbef1
HV		 1773 if (desc->flags & CHIP_HAS_VOLUME)
1774 return v4l2_ctrl_query_fill(qc, 0, 65535, 65535 / 100, 32768);
64f70e7e
HV		 1775 break;
1776 case V4L2_CID_AUDIO_BASS:
1777 case V4L2_CID_AUDIO_TREBLE:
10afbef1
HV		 1778 if (desc->flags & CHIP_HAS_BASSTREBLE)
1779 return v4l2_ctrl_query_fill(qc, 0, 65535, 65535 / 100, 32768);
64f70e7e
HV		 1780 break;
1781 default:
10afbef1 1782 break;
c6241b6c 1783 }
10afbef1 1784 return -EINVAL;
64f70e7e
HV		 1785}
1786
5325b427
HV		 1787static int tvaudio_s_routing(struct v4l2_subdev *sd,
1788 u32 input, u32 output, u32 config)
64f70e7e
HV		 1789{
1790 struct CHIPSTATE *chip = to_state(sd);
1791 struct CHIPDESC *desc = chip->desc;
1da177e4 1792
5fa7b9f3
HV		 1793 if (!(desc->flags & CHIP_HAS_INPUTSEL))
1794 return 0;
5325b427 1795 if (input >= 4)
64f70e7e
HV		 1796 return -EINVAL;
1797 /* There are four inputs: tuner, radio, extern and intern. */
5325b427 1798 chip->input = input;
64f70e7e
HV		 1799 if (chip->muted)
1800 return 0;
1801 chip_write_masked(chip, desc->inputreg,
1802 desc->inputmap[chip->input], desc->inputmask);
1803 return 0;
1804}
1805
1806static int tvaudio_s_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1807{
1808 struct CHIPSTATE *chip = to_state(sd);
1809 struct CHIPDESC *desc = chip->desc;
64f70e7e 1810
5fa7b9f3
HV		 1811 if (!desc->setmode)
1812 return 0;
64f70e7e
HV		 1813 if (chip->radio)
1814 return 0;
5fa7b9f3 1815
64f70e7e
HV		 1816 switch (vt->audmode) {
1817 case V4L2_TUNER_MODE_MONO:
1818 case V4L2_TUNER_MODE_STEREO:
1819 case V4L2_TUNER_MODE_LANG1:
1820 case V4L2_TUNER_MODE_LANG2:
64f70e7e
HV		 1821 break;
1822 case V4L2_TUNER_MODE_LANG1_LANG2:
e21adca8 1823 vt->audmode = V4L2_TUNER_MODE_STEREO;
64f70e7e
HV		 1824 break;
1825 default:
1826 return -EINVAL;
1827 }
1828 chip->audmode = vt->audmode;
1829
e21adca8
DG		 1830 if (chip->thread)
1831 wake_up_process(chip->thread);
1832 else
1833 desc->setmode(chip, vt->audmode);
1834
64f70e7e
HV		 1835 return 0;
1836}
8bf2f8e7 1837
64f70e7e
HV		 1838static int tvaudio_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1839{
1840 struct CHIPSTATE *chip = to_state(sd);
1841 struct CHIPDESC *desc = chip->desc;
2474ed44 1842
5fa7b9f3
HV		 1843 if (!desc->getmode)
1844 return 0;
64f70e7e
HV		 1845 if (chip->radio)
1846 return 0;
5fa7b9f3 1847
64f70e7e 1848 vt->audmode = chip->audmode;
3322a59e 1849 vt->rxsubchans = desc->getmode(chip);
64f70e7e
HV		 1850 vt->capability = V4L2_TUNER_CAP_STEREO |
1851 V4L2_TUNER_CAP_LANG1 | V4L2_TUNER_CAP_LANG2;
1852
64f70e7e
HV		 1853 return 0;
1854}
1855
1856static int tvaudio_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
1857{
1858 struct CHIPSTATE *chip = to_state(sd);
1859
1860 chip->radio = 0;
1861 return 0;
1862}
1863
1864static int tvaudio_s_frequency(struct v4l2_subdev *sd, struct v4l2_frequency *freq)
1865{
1866 struct CHIPSTATE *chip = to_state(sd);
1867 struct CHIPDESC *desc = chip->desc;
1868
64f70e7e
HV		 1869 /* For chips that provide getmode and setmode, and doesn't
1870 automatically follows the stereo carrier, a kthread is
1871 created to set the audio standard. In this case, when then
1872 the video channel is changed, tvaudio starts on MONO mode.
1873 After waiting for 2 seconds, the kernel thread is called,
1874 to follow whatever audio standard is pointed by the
1875 audio carrier.
1876 */
1877 if (chip->thread) {
1878 desc->setmode(chip, V4L2_TUNER_MODE_MONO);
e21adca8 1879 chip->prevmode = -1; /* reset previous mode */
64f70e7e 1880 mod_timer(&chip->wt, jiffies+msecs_to_jiffies(2000));
2474ed44 1881 }
64f70e7e
HV		 1882 return 0;
1883}
2474ed44 1884
aecde8b5 1885static int tvaudio_g_chip_ident(struct v4l2_subdev *sd, struct v4l2_dbg_chip_ident *chip)
64f70e7e
HV		 1886{
1887 struct i2c_client *client = v4l2_get_subdevdata(sd);
1888
1889 return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_TVAUDIO, 0);
1890}
1891
64f70e7e
HV		 1892/* ----------------------------------------------------------------------- */
1893
1894static const struct v4l2_subdev_core_ops tvaudio_core_ops = {
1895 .g_chip_ident = tvaudio_g_chip_ident,
1896 .queryctrl = tvaudio_queryctrl,
1897 .g_ctrl = tvaudio_g_ctrl,
1898 .s_ctrl = tvaudio_s_ctrl,
f41737ec 1899 .s_std = tvaudio_s_std,
64f70e7e
HV		 1900};
1901
1902static const struct v4l2_subdev_tuner_ops tvaudio_tuner_ops = {
1903 .s_radio = tvaudio_s_radio,
1904 .s_frequency = tvaudio_s_frequency,
64f70e7e 1905 .s_tuner = tvaudio_s_tuner,
e6a1a08f 1906 .g_tuner = tvaudio_g_tuner,
64f70e7e
HV		 1907};
1908
1909static const struct v4l2_subdev_audio_ops tvaudio_audio_ops = {
1910 .s_routing = tvaudio_s_routing,
1911};
1912
1913static const struct v4l2_subdev_ops tvaudio_ops = {
1914 .core = &tvaudio_core_ops,
1915 .tuner = &tvaudio_tuner_ops,
1916 .audio = &tvaudio_audio_ops,
1917};
1918
1919/* ----------------------------------------------------------------------- */
1920
1921
1922/* i2c registration */
1923
1924static int tvaudio_probe(struct i2c_client *client, const struct i2c_device_id *id)
1925{
1926 struct CHIPSTATE *chip;
1927 struct CHIPDESC *desc;
1928 struct v4l2_subdev *sd;
1929
1930 if (debug) {
1931 printk(KERN_INFO "tvaudio: TV audio decoder + audio/video mux driver\n");
1932 printk(KERN_INFO "tvaudio: known chips: ");
1933 for (desc = chiplist; desc->name != NULL; desc++)
1934 printk("%s%s", (desc == chiplist) ? "" : ", ", desc->name);
1935 printk("\n");
2474ed44 1936 }
1da177e4 1937
64f70e7e
HV		 1938 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1939 if (!chip)
1940 return -ENOMEM;
1941 sd = &chip->sd;
1942 v4l2_i2c_subdev_init(sd, client, &tvaudio_ops);
8a854284 1943
64f70e7e
HV		 1944 /* find description for the chip */
1945 v4l2_dbg(1, debug, sd, "chip found @ 0x%x\n", client->addr<<1);
1946 for (desc = chiplist; desc->name != NULL; desc++) {
1947 if (0 == *(desc->insmodopt))
1948 continue;
1949 if (client->addr < desc->addr_lo ||
1950 client->addr > desc->addr_hi)
1951 continue;
1952 if (desc->checkit && !desc->checkit(chip))
1953 continue;
1da177e4
LT		 1954 break;
1955 }
64f70e7e
HV		 1956 if (desc->name == NULL) {
1957 v4l2_dbg(1, debug, sd, "no matching chip description found\n");
1958 kfree(chip);
1959 return -EIO;
1960 }
1961 v4l2_info(sd, "%s found @ 0x%x (%s)\n", desc->name, client->addr<<1, client->adapter->name);
1962 if (desc->flags) {
1963 v4l2_dbg(1, debug, sd, "matches:%s%s%s.\n",
1964 (desc->flags & CHIP_HAS_VOLUME) ? " volume" : "",
1965 (desc->flags & CHIP_HAS_BASSTREBLE) ? " bass/treble" : "",
1966 (desc->flags & CHIP_HAS_INPUTSEL) ? " audiomux" : "");
1967 }
8a854284 1968
64f70e7e
HV		 1969 /* fill required data structures */
1970 if (!id)
1971 strlcpy(client->name, desc->name, I2C_NAME_SIZE);
1972 chip->desc = desc;
1973 chip->shadow.count = desc->registers+1;
1974 chip->prevmode = -1;
1975 chip->audmode = V4L2_TUNER_MODE_LANG1;
8a854284 1976
64f70e7e
HV		 1977 /* initialization */
1978 if (desc->initialize != NULL)
1979 desc->initialize(chip);
1980 else
1981 chip_cmd(chip, "init", &desc->init);
8a854284 1982
64f70e7e
HV		 1983 if (desc->flags & CHIP_HAS_VOLUME) {
1984 if (!desc->volfunc) {
1985 /* This shouldn't be happen. Warn user, but keep working
1986 without volume controls
1987 */
1988 v4l2_info(sd, "volume callback undefined!\n");
1989 desc->flags &= ~CHIP_HAS_VOLUME;
1990 } else {
1991 chip->left = desc->leftinit ? desc->leftinit : 65535;
1992 chip->right = desc->rightinit ? desc->rightinit : 65535;
1993 chip_write(chip, desc->leftreg,
1994 desc->volfunc(chip->left));
1995 chip_write(chip, desc->rightreg,
1996 desc->volfunc(chip->right));
1997 }
8a854284 1998 }
64f70e7e
HV		 1999 if (desc->flags & CHIP_HAS_BASSTREBLE) {
2000 if (!desc->bassfunc || !desc->treblefunc) {
2001 /* This shouldn't be happen. Warn user, but keep working
2002 without bass/treble controls
2003 */
2004 v4l2_info(sd, "bass/treble callbacks undefined!\n");
2005 desc->flags &= ~CHIP_HAS_BASSTREBLE;
2006 } else {
2007 chip->treble = desc->trebleinit ?
2008 desc->trebleinit : 32768;
2009 chip->bass = desc->bassinit ?
2010 desc->bassinit : 32768;
2011 chip_write(chip, desc->bassreg,
2012 desc->bassfunc(chip->bass));
2013 chip_write(chip, desc->treblereg,
2014 desc->treblefunc(chip->treble));
1da177e4 2015 }
64f70e7e 2016 }
74cab31c 2017
64f70e7e 2018 chip->thread = NULL;
e4129a9c 2019 init_timer(&chip->wt);
64f70e7e
HV		 2020 if (desc->flags & CHIP_NEED_CHECKMODE) {
2021 if (!desc->getmode || !desc->setmode) {
2022 /* This shouldn't be happen. Warn user, but keep working
2023 without kthread
2024 */
2025 v4l2_info(sd, "set/get mode callbacks undefined!\n");
2026 return 0;
2027 }
2028 /* start async thread */
64f70e7e
HV		 2029 chip->wt.function = chip_thread_wake;
2030 chip->wt.data = (unsigned long)chip;
2031 chip->thread = kthread_run(chip_thread, chip, client->name);
2032 if (IS_ERR(chip->thread)) {
2033 v4l2_warn(sd, "failed to create kthread\n");
2034 chip->thread = NULL;
2035 }
1da177e4
LT		 2036 }
2037 return 0;
2038}
2039
64f70e7e
HV		 2040static int tvaudio_remove(struct i2c_client *client)
2041{
2042 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2043 struct CHIPSTATE *chip = to_state(sd);
2044
2045 del_timer_sync(&chip->wt);
2046 if (chip->thread) {
2047 /* shutdown async thread */
2048 kthread_stop(chip->thread);
2049 chip->thread = NULL;
2050 }
2051
2052 v4l2_device_unregister_subdev(sd);
2053 kfree(chip);
2054 return 0;
2055}
2056
ae429083
JD		 2057/* This driver supports many devices and the idea is to let the driver
2058 detect which device is present. So rather than listing all supported
2059 devices here, we pretend to support a single, fake device type. */
64f70e7e 2060static const struct i2c_device_id tvaudio_id[] = {
ae429083
JD		 2061 { "tvaudio", 0 },
2062 { }
2063};
64f70e7e 2064MODULE_DEVICE_TABLE(i2c, tvaudio_id);
ae429083 2065
7a004d13
HV		 2066static struct i2c_driver tvaudio_driver = {
2067 .driver = {
2068 .owner = THIS_MODULE,
2069 .name = "tvaudio",
2070 },
2071 .probe = tvaudio_probe,
2072 .remove = tvaudio_remove,
2073 .id_table = tvaudio_id,
08e14054 2074};
7a004d13 2075
c6e8d86f 2076module_i2c_driver(tvaudio_driver);
Linux kernel - Deliverables
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