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07b1747c VH |
1 | /* |
2 | * drivers/media/video/tvp514x_regs.h | |
3 | * | |
4 | * Copyright (C) 2008 Texas Instruments Inc | |
5 | * Author: Vaibhav Hiremath <hvaibhav@ti.com> | |
6 | * | |
7 | * Contributors: | |
8 | * Sivaraj R <sivaraj@ti.com> | |
9 | * Brijesh R Jadav <brijesh.j@ti.com> | |
10 | * Hardik Shah <hardik.shah@ti.com> | |
11 | * Manjunath Hadli <mrh@ti.com> | |
12 | * Karicheri Muralidharan <m-karicheri2@ti.com> | |
13 | * | |
14 | * This package is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License version 2 as | |
16 | * published by the Free Software Foundation. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
26 | * | |
27 | */ | |
28 | ||
29 | #ifndef _TVP514X_REGS_H | |
30 | #define _TVP514X_REGS_H | |
31 | ||
32 | /* | |
33 | * TVP5146/47 registers | |
34 | */ | |
35 | #define REG_INPUT_SEL (0x00) | |
36 | #define REG_AFE_GAIN_CTRL (0x01) | |
37 | #define REG_VIDEO_STD (0x02) | |
38 | #define REG_OPERATION_MODE (0x03) | |
39 | #define REG_AUTOSWITCH_MASK (0x04) | |
40 | ||
41 | #define REG_COLOR_KILLER (0x05) | |
42 | #define REG_LUMA_CONTROL1 (0x06) | |
43 | #define REG_LUMA_CONTROL2 (0x07) | |
44 | #define REG_LUMA_CONTROL3 (0x08) | |
45 | ||
46 | #define REG_BRIGHTNESS (0x09) | |
47 | #define REG_CONTRAST (0x0A) | |
48 | #define REG_SATURATION (0x0B) | |
49 | #define REG_HUE (0x0C) | |
50 | ||
51 | #define REG_CHROMA_CONTROL1 (0x0D) | |
52 | #define REG_CHROMA_CONTROL2 (0x0E) | |
53 | ||
54 | /* 0x0F Reserved */ | |
55 | ||
56 | #define REG_COMP_PR_SATURATION (0x10) | |
57 | #define REG_COMP_Y_CONTRAST (0x11) | |
58 | #define REG_COMP_PB_SATURATION (0x12) | |
59 | ||
60 | /* 0x13 Reserved */ | |
61 | ||
62 | #define REG_COMP_Y_BRIGHTNESS (0x14) | |
63 | ||
64 | /* 0x15 Reserved */ | |
65 | ||
66 | #define REG_AVID_START_PIXEL_LSB (0x16) | |
67 | #define REG_AVID_START_PIXEL_MSB (0x17) | |
68 | #define REG_AVID_STOP_PIXEL_LSB (0x18) | |
69 | #define REG_AVID_STOP_PIXEL_MSB (0x19) | |
70 | ||
71 | #define REG_HSYNC_START_PIXEL_LSB (0x1A) | |
72 | #define REG_HSYNC_START_PIXEL_MSB (0x1B) | |
73 | #define REG_HSYNC_STOP_PIXEL_LSB (0x1C) | |
74 | #define REG_HSYNC_STOP_PIXEL_MSB (0x1D) | |
75 | ||
76 | #define REG_VSYNC_START_LINE_LSB (0x1E) | |
77 | #define REG_VSYNC_START_LINE_MSB (0x1F) | |
78 | #define REG_VSYNC_STOP_LINE_LSB (0x20) | |
79 | #define REG_VSYNC_STOP_LINE_MSB (0x21) | |
80 | ||
81 | #define REG_VBLK_START_LINE_LSB (0x22) | |
82 | #define REG_VBLK_START_LINE_MSB (0x23) | |
83 | #define REG_VBLK_STOP_LINE_LSB (0x24) | |
84 | #define REG_VBLK_STOP_LINE_MSB (0x25) | |
85 | ||
86 | /* 0x26 - 0x27 Reserved */ | |
87 | ||
88 | #define REG_FAST_SWTICH_CONTROL (0x28) | |
89 | ||
90 | /* 0x29 Reserved */ | |
91 | ||
92 | #define REG_FAST_SWTICH_SCART_DELAY (0x2A) | |
93 | ||
94 | /* 0x2B Reserved */ | |
95 | ||
96 | #define REG_SCART_DELAY (0x2C) | |
97 | #define REG_CTI_DELAY (0x2D) | |
98 | #define REG_CTI_CONTROL (0x2E) | |
99 | ||
100 | /* 0x2F - 0x31 Reserved */ | |
101 | ||
102 | #define REG_SYNC_CONTROL (0x32) | |
103 | #define REG_OUTPUT_FORMATTER1 (0x33) | |
104 | #define REG_OUTPUT_FORMATTER2 (0x34) | |
105 | #define REG_OUTPUT_FORMATTER3 (0x35) | |
106 | #define REG_OUTPUT_FORMATTER4 (0x36) | |
107 | #define REG_OUTPUT_FORMATTER5 (0x37) | |
108 | #define REG_OUTPUT_FORMATTER6 (0x38) | |
109 | #define REG_CLEAR_LOST_LOCK (0x39) | |
110 | ||
111 | #define REG_STATUS1 (0x3A) | |
112 | #define REG_STATUS2 (0x3B) | |
113 | ||
114 | #define REG_AGC_GAIN_STATUS_LSB (0x3C) | |
115 | #define REG_AGC_GAIN_STATUS_MSB (0x3D) | |
116 | ||
117 | /* 0x3E Reserved */ | |
118 | ||
119 | #define REG_VIDEO_STD_STATUS (0x3F) | |
120 | #define REG_GPIO_INPUT1 (0x40) | |
121 | #define REG_GPIO_INPUT2 (0x41) | |
122 | ||
123 | /* 0x42 - 0x45 Reserved */ | |
124 | ||
125 | #define REG_AFE_COARSE_GAIN_CH1 (0x46) | |
126 | #define REG_AFE_COARSE_GAIN_CH2 (0x47) | |
127 | #define REG_AFE_COARSE_GAIN_CH3 (0x48) | |
128 | #define REG_AFE_COARSE_GAIN_CH4 (0x49) | |
129 | ||
130 | #define REG_AFE_FINE_GAIN_PB_B_LSB (0x4A) | |
131 | #define REG_AFE_FINE_GAIN_PB_B_MSB (0x4B) | |
132 | #define REG_AFE_FINE_GAIN_Y_G_CHROMA_LSB (0x4C) | |
133 | #define REG_AFE_FINE_GAIN_Y_G_CHROMA_MSB (0x4D) | |
134 | #define REG_AFE_FINE_GAIN_PR_R_LSB (0x4E) | |
135 | #define REG_AFE_FINE_GAIN_PR_R_MSB (0x4F) | |
136 | #define REG_AFE_FINE_GAIN_CVBS_LUMA_LSB (0x50) | |
137 | #define REG_AFE_FINE_GAIN_CVBS_LUMA_MSB (0x51) | |
138 | ||
139 | /* 0x52 - 0x68 Reserved */ | |
140 | ||
141 | #define REG_FBIT_VBIT_CONTROL1 (0x69) | |
142 | ||
143 | /* 0x6A - 0x6B Reserved */ | |
144 | ||
145 | #define REG_BACKEND_AGC_CONTROL (0x6C) | |
146 | ||
147 | /* 0x6D - 0x6E Reserved */ | |
148 | ||
149 | #define REG_AGC_DECREMENT_SPEED_CONTROL (0x6F) | |
150 | #define REG_ROM_VERSION (0x70) | |
151 | ||
152 | /* 0x71 - 0x73 Reserved */ | |
153 | ||
154 | #define REG_AGC_WHITE_PEAK_PROCESSING (0x74) | |
155 | #define REG_FBIT_VBIT_CONTROL2 (0x75) | |
156 | #define REG_VCR_TRICK_MODE_CONTROL (0x76) | |
157 | #define REG_HORIZONTAL_SHAKE_INCREMENT (0x77) | |
158 | #define REG_AGC_INCREMENT_SPEED (0x78) | |
159 | #define REG_AGC_INCREMENT_DELAY (0x79) | |
160 | ||
161 | /* 0x7A - 0x7F Reserved */ | |
162 | ||
163 | #define REG_CHIP_ID_MSB (0x80) | |
164 | #define REG_CHIP_ID_LSB (0x81) | |
165 | ||
166 | /* 0x82 Reserved */ | |
167 | ||
168 | #define REG_CPLL_SPEED_CONTROL (0x83) | |
169 | ||
170 | /* 0x84 - 0x96 Reserved */ | |
171 | ||
172 | #define REG_STATUS_REQUEST (0x97) | |
173 | ||
174 | /* 0x98 - 0x99 Reserved */ | |
175 | ||
176 | #define REG_VERTICAL_LINE_COUNT_LSB (0x9A) | |
177 | #define REG_VERTICAL_LINE_COUNT_MSB (0x9B) | |
178 | ||
179 | /* 0x9C - 0x9D Reserved */ | |
180 | ||
181 | #define REG_AGC_DECREMENT_DELAY (0x9E) | |
182 | ||
183 | /* 0x9F - 0xB0 Reserved */ | |
184 | ||
185 | #define REG_VDP_TTX_FILTER_1_MASK1 (0xB1) | |
186 | #define REG_VDP_TTX_FILTER_1_MASK2 (0xB2) | |
187 | #define REG_VDP_TTX_FILTER_1_MASK3 (0xB3) | |
188 | #define REG_VDP_TTX_FILTER_1_MASK4 (0xB4) | |
189 | #define REG_VDP_TTX_FILTER_1_MASK5 (0xB5) | |
190 | #define REG_VDP_TTX_FILTER_2_MASK1 (0xB6) | |
191 | #define REG_VDP_TTX_FILTER_2_MASK2 (0xB7) | |
192 | #define REG_VDP_TTX_FILTER_2_MASK3 (0xB8) | |
193 | #define REG_VDP_TTX_FILTER_2_MASK4 (0xB9) | |
194 | #define REG_VDP_TTX_FILTER_2_MASK5 (0xBA) | |
195 | #define REG_VDP_TTX_FILTER_CONTROL (0xBB) | |
196 | #define REG_VDP_FIFO_WORD_COUNT (0xBC) | |
197 | #define REG_VDP_FIFO_INTERRUPT_THRLD (0xBD) | |
198 | ||
199 | /* 0xBE Reserved */ | |
200 | ||
201 | #define REG_VDP_FIFO_RESET (0xBF) | |
202 | #define REG_VDP_FIFO_OUTPUT_CONTROL (0xC0) | |
203 | #define REG_VDP_LINE_NUMBER_INTERRUPT (0xC1) | |
204 | #define REG_VDP_PIXEL_ALIGNMENT_LSB (0xC2) | |
205 | #define REG_VDP_PIXEL_ALIGNMENT_MSB (0xC3) | |
206 | ||
207 | /* 0xC4 - 0xD5 Reserved */ | |
208 | ||
209 | #define REG_VDP_LINE_START (0xD6) | |
210 | #define REG_VDP_LINE_STOP (0xD7) | |
211 | #define REG_VDP_GLOBAL_LINE_MODE (0xD8) | |
212 | #define REG_VDP_FULL_FIELD_ENABLE (0xD9) | |
213 | #define REG_VDP_FULL_FIELD_MODE (0xDA) | |
214 | ||
215 | /* 0xDB - 0xDF Reserved */ | |
216 | ||
217 | #define REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR (0xE0) | |
218 | #define REG_VBUS_DATA_ACCESS_VBUS_ADDR_INCR (0xE1) | |
219 | #define REG_FIFO_READ_DATA (0xE2) | |
220 | ||
221 | /* 0xE3 - 0xE7 Reserved */ | |
222 | ||
223 | #define REG_VBUS_ADDRESS_ACCESS1 (0xE8) | |
224 | #define REG_VBUS_ADDRESS_ACCESS2 (0xE9) | |
225 | #define REG_VBUS_ADDRESS_ACCESS3 (0xEA) | |
226 | ||
227 | /* 0xEB - 0xEF Reserved */ | |
228 | ||
229 | #define REG_INTERRUPT_RAW_STATUS0 (0xF0) | |
230 | #define REG_INTERRUPT_RAW_STATUS1 (0xF1) | |
231 | #define REG_INTERRUPT_STATUS0 (0xF2) | |
232 | #define REG_INTERRUPT_STATUS1 (0xF3) | |
233 | #define REG_INTERRUPT_MASK0 (0xF4) | |
234 | #define REG_INTERRUPT_MASK1 (0xF5) | |
235 | #define REG_INTERRUPT_CLEAR0 (0xF6) | |
236 | #define REG_INTERRUPT_CLEAR1 (0xF7) | |
237 | ||
238 | /* 0xF8 - 0xFF Reserved */ | |
239 | ||
240 | /* | |
241 | * Mask and bit definitions of TVP5146/47 registers | |
242 | */ | |
243 | /* The ID values we are looking for */ | |
244 | #define TVP514X_CHIP_ID_MSB (0x51) | |
245 | #define TVP5146_CHIP_ID_LSB (0x46) | |
246 | #define TVP5147_CHIP_ID_LSB (0x47) | |
247 | ||
248 | #define VIDEO_STD_MASK (0x07) | |
249 | #define VIDEO_STD_AUTO_SWITCH_BIT (0x00) | |
250 | #define VIDEO_STD_NTSC_MJ_BIT (0x01) | |
251 | #define VIDEO_STD_PAL_BDGHIN_BIT (0x02) | |
252 | #define VIDEO_STD_PAL_M_BIT (0x03) | |
253 | #define VIDEO_STD_PAL_COMBINATION_N_BIT (0x04) | |
254 | #define VIDEO_STD_NTSC_4_43_BIT (0x05) | |
255 | #define VIDEO_STD_SECAM_BIT (0x06) | |
256 | #define VIDEO_STD_PAL_60_BIT (0x07) | |
257 | ||
258 | /* | |
259 | * Status bit | |
260 | */ | |
261 | #define STATUS_TV_VCR_BIT (1<<0) | |
262 | #define STATUS_HORZ_SYNC_LOCK_BIT (1<<1) | |
263 | #define STATUS_VIRT_SYNC_LOCK_BIT (1<<2) | |
264 | #define STATUS_CLR_SUBCAR_LOCK_BIT (1<<3) | |
265 | #define STATUS_LOST_LOCK_DETECT_BIT (1<<4) | |
266 | #define STATUS_FEILD_RATE_BIT (1<<5) | |
267 | #define STATUS_LINE_ALTERNATING_BIT (1<<6) | |
268 | #define STATUS_PEAK_WHITE_DETECT_BIT (1<<7) | |
269 | ||
270 | /* Tokens for register write */ | |
271 | #define TOK_WRITE (0) /* token for write operation */ | |
272 | #define TOK_TERM (1) /* terminating token */ | |
273 | #define TOK_DELAY (2) /* delay token for reg list */ | |
274 | #define TOK_SKIP (3) /* token to skip a register */ | |
275 | /** | |
276 | * struct tvp514x_reg - Structure for TVP5146/47 register initialization values | |
277 | * @token - Token: TOK_WRITE, TOK_TERM etc.. | |
278 | * @reg - Register offset | |
279 | * @val - Register Value for TOK_WRITE or delay in ms for TOK_DELAY | |
280 | */ | |
281 | struct tvp514x_reg { | |
282 | u8 token; | |
283 | u8 reg; | |
284 | u32 val; | |
285 | }; | |
286 | ||
07b1747c | 287 | #endif /* ifndef _TVP514X_REGS_H */ |