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[media] staging: easycap: Fix incorrect comment
[deliverable/linux.git] / drivers / media / video / tvp5150.c
CommitLineData
cd4665c5 1/*
6ac48b45 2 * tvp5150 - Texas Instruments TVP5150A/AM1 video decoder driver
cd4665c5 3 *
6ac48b45
MCC		 4 * Copyright (c) 2005,2006 Mauro Carvalho Chehab (mchehab@infradead.org)
5 * This code is placed under the terms of the GNU General Public License v2
cd4665c5
MCC		 6 */
7
cd4665c5 8#include <linux/i2c.h>
5a0e3ad6 9#include <linux/slab.h>
33b687cf 10#include <linux/videodev2.h>
cd4665c5 11#include <linux/delay.h>
7a707b89 12#include <linux/module.h>
6b8fe025 13#include <media/v4l2-device.h>
c7c0b34c 14#include <media/tvp5150.h>
bc974305 15#include <media/v4l2-chip-ident.h>
6c45ec71 16#include <media/v4l2-ctrls.h>
cd4665c5
MCC		 17
18#include "tvp5150_reg.h"
19
6ac48b45 20MODULE_DESCRIPTION("Texas Instruments TVP5150A video decoder driver");
cd4665c5
MCC		 21MODULE_AUTHOR("Mauro Carvalho Chehab");
22MODULE_LICENSE("GPL");
23
cd4665c5 24
ff699e6b 25static int debug;
cd4665c5 26module_param(debug, int, 0);
6b8fe025 27MODULE_PARM_DESC(debug, "Debug level (0-2)");
cd4665c5
MCC		 28
29struct tvp5150 {
6b8fe025 30 struct v4l2_subdev sd;
6c45ec71 31 struct v4l2_ctrl_handler hdl;
84486d53 32
3ad96835 33 v4l2_std_id norm; /* Current set standard */
5325b427
HV		 34 u32 input;
35 u32 output;
84486d53 36 int enable;
cd4665c5
MCC		 37};
38
6b8fe025 39static inline struct tvp5150 *to_tvp5150(struct v4l2_subdev *sd)
cd4665c5 40{
6b8fe025
HV		 41 return container_of(sd, struct tvp5150, sd);
42}
43
6c45ec71
HV		 44static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
45{
46 return &container_of(ctrl->handler, struct tvp5150, hdl)->sd;
47}
48
6b8fe025
HV		 49static int tvp5150_read(struct v4l2_subdev *sd, unsigned char addr)
50{
51 struct i2c_client *c = v4l2_get_subdevdata(sd);
cd4665c5
MCC		 52 unsigned char buffer[1];
53 int rc;
cd4665c5
MCC		 54
55 buffer[0] = addr;
56 if (1 != (rc = i2c_master_send(c, buffer, 1)))
6b8fe025 57 v4l2_dbg(0, debug, sd, "i2c i/o error: rc == %d (should be 1)\n", rc);
cd4665c5
MCC		 58
59 msleep(10);
60
61 if (1 != (rc = i2c_master_recv(c, buffer, 1)))
6b8fe025 62 v4l2_dbg(0, debug, sd, "i2c i/o error: rc == %d (should be 1)\n", rc);
e1bc80ad 63
6b8fe025 64 v4l2_dbg(2, debug, sd, "tvp5150: read 0x%02x = 0x%02x\n", addr, buffer[0]);
cd4665c5
MCC		 65
66 return (buffer[0]);
67}
68
6b8fe025 69static inline void tvp5150_write(struct v4l2_subdev *sd, unsigned char addr,
84486d53 70 unsigned char value)
cd4665c5 71{
6b8fe025 72 struct i2c_client *c = v4l2_get_subdevdata(sd);
cd4665c5
MCC		 73 unsigned char buffer[2];
74 int rc;
cd4665c5
MCC		 75
76 buffer[0] = addr;
84486d53 77 buffer[1] = value;
6b8fe025 78 v4l2_dbg(2, debug, sd, "tvp5150: writing 0x%02x 0x%02x\n", buffer[0], buffer[1]);
cd4665c5 79 if (2 != (rc = i2c_master_send(c, buffer, 2)))
6b8fe025 80 v4l2_dbg(0, debug, sd, "i2c i/o error: rc == %d (should be 2)\n", rc);
cd4665c5
MCC		 81}
82
6b8fe025
HV		 83static void dump_reg_range(struct v4l2_subdev *sd, char *s, u8 init,
84 const u8 end, int max_line)
3ad96835 85{
6b8fe025 86 int i = 0;
3ad96835 87
6b8fe025
HV		 88 while (init != (u8)(end + 1)) {
89 if ((i % max_line) == 0) {
90 if (i > 0)
3ad96835 91 printk("\n");
6b8fe025 92 printk("tvp5150: %s reg 0x%02x = ", s, init);
3ad96835 93 }
6b8fe025 94 printk("%02x ", tvp5150_read(sd, init));
3ad96835
MCC		 95
96 init++;
97 i++;
98 }
99 printk("\n");
100}
101
6b8fe025 102static int tvp5150_log_status(struct v4l2_subdev *sd)
cd4665c5 103{
84486d53 104 printk("tvp5150: Video input source selection #1 = 0x%02x\n",
6b8fe025 105 tvp5150_read(sd, TVP5150_VD_IN_SRC_SEL_1));
84486d53 106 printk("tvp5150: Analog channel controls = 0x%02x\n",
6b8fe025 107 tvp5150_read(sd, TVP5150_ANAL_CHL_CTL));
84486d53 108 printk("tvp5150: Operation mode controls = 0x%02x\n",
6b8fe025 109 tvp5150_read(sd, TVP5150_OP_MODE_CTL));
84486d53 110 printk("tvp5150: Miscellaneous controls = 0x%02x\n",
6b8fe025 111 tvp5150_read(sd, TVP5150_MISC_CTL));
3ad96835 112 printk("tvp5150: Autoswitch mask= 0x%02x\n",
6b8fe025 113 tvp5150_read(sd, TVP5150_AUTOSW_MSK));
84486d53 114 printk("tvp5150: Color killer threshold control = 0x%02x\n",
6b8fe025 115 tvp5150_read(sd, TVP5150_COLOR_KIL_THSH_CTL));
3ad96835 116 printk("tvp5150: Luminance processing controls #1 #2 and #3 = %02x %02x %02x\n",
6b8fe025
HV		 117 tvp5150_read(sd, TVP5150_LUMA_PROC_CTL_1),
118 tvp5150_read(sd, TVP5150_LUMA_PROC_CTL_2),
119 tvp5150_read(sd, TVP5150_LUMA_PROC_CTL_3));
84486d53 120 printk("tvp5150: Brightness control = 0x%02x\n",
6b8fe025 121 tvp5150_read(sd, TVP5150_BRIGHT_CTL));
84486d53 122 printk("tvp5150: Color saturation control = 0x%02x\n",
6b8fe025 123 tvp5150_read(sd, TVP5150_SATURATION_CTL));
84486d53 124 printk("tvp5150: Hue control = 0x%02x\n",
6b8fe025 125 tvp5150_read(sd, TVP5150_HUE_CTL));
84486d53 126 printk("tvp5150: Contrast control = 0x%02x\n",
6b8fe025 127 tvp5150_read(sd, TVP5150_CONTRAST_CTL));
84486d53 128 printk("tvp5150: Outputs and data rates select = 0x%02x\n",
6b8fe025 129 tvp5150_read(sd, TVP5150_DATA_RATE_SEL));
84486d53 130 printk("tvp5150: Configuration shared pins = 0x%02x\n",
6b8fe025 131 tvp5150_read(sd, TVP5150_CONF_SHARED_PIN));
3ad96835 132 printk("tvp5150: Active video cropping start = 0x%02x%02x\n",
6b8fe025
HV		 133 tvp5150_read(sd, TVP5150_ACT_VD_CROP_ST_MSB),
134 tvp5150_read(sd, TVP5150_ACT_VD_CROP_ST_LSB));
3ad96835 135 printk("tvp5150: Active video cropping stop = 0x%02x%02x\n",
6b8fe025
HV		 136 tvp5150_read(sd, TVP5150_ACT_VD_CROP_STP_MSB),
137 tvp5150_read(sd, TVP5150_ACT_VD_CROP_STP_LSB));
84486d53 138 printk("tvp5150: Genlock/RTC = 0x%02x\n",
6b8fe025 139 tvp5150_read(sd, TVP5150_GENLOCK));
84486d53 140 printk("tvp5150: Horizontal sync start = 0x%02x\n",
6b8fe025 141 tvp5150_read(sd, TVP5150_HORIZ_SYNC_START));
84486d53 142 printk("tvp5150: Vertical blanking start = 0x%02x\n",
6b8fe025 143 tvp5150_read(sd, TVP5150_VERT_BLANKING_START));
84486d53 144 printk("tvp5150: Vertical blanking stop = 0x%02x\n",
6b8fe025 145 tvp5150_read(sd, TVP5150_VERT_BLANKING_STOP));
3ad96835 146 printk("tvp5150: Chrominance processing control #1 and #2 = %02x %02x\n",
6b8fe025
HV		 147 tvp5150_read(sd, TVP5150_CHROMA_PROC_CTL_1),
148 tvp5150_read(sd, TVP5150_CHROMA_PROC_CTL_2));
84486d53 149 printk("tvp5150: Interrupt reset register B = 0x%02x\n",
6b8fe025 150 tvp5150_read(sd, TVP5150_INT_RESET_REG_B));
84486d53 151 printk("tvp5150: Interrupt enable register B = 0x%02x\n",
6b8fe025 152 tvp5150_read(sd, TVP5150_INT_ENABLE_REG_B));
84486d53 153 printk("tvp5150: Interrupt configuration register B = 0x%02x\n",
6b8fe025 154 tvp5150_read(sd, TVP5150_INTT_CONFIG_REG_B));
84486d53 155 printk("tvp5150: Video standard = 0x%02x\n",
6b8fe025 156 tvp5150_read(sd, TVP5150_VIDEO_STD));
3ad96835 157 printk("tvp5150: Chroma gain factor: Cb=0x%02x Cr=0x%02x\n",
6b8fe025
HV		 158 tvp5150_read(sd, TVP5150_CB_GAIN_FACT),
159 tvp5150_read(sd, TVP5150_CR_GAIN_FACTOR));
84486d53 160 printk("tvp5150: Macrovision on counter = 0x%02x\n",
6b8fe025 161 tvp5150_read(sd, TVP5150_MACROVISION_ON_CTR));
84486d53 162 printk("tvp5150: Macrovision off counter = 0x%02x\n",
6b8fe025 163 tvp5150_read(sd, TVP5150_MACROVISION_OFF_CTR));
3ad96835 164 printk("tvp5150: ITU-R BT.656.%d timing(TVP5150AM1 only)\n",
6b8fe025 165 (tvp5150_read(sd, TVP5150_REV_SELECT) & 1) ? 3 : 4);
3ad96835 166 printk("tvp5150: Device ID = %02x%02x\n",
6b8fe025
HV		 167 tvp5150_read(sd, TVP5150_MSB_DEV_ID),
168 tvp5150_read(sd, TVP5150_LSB_DEV_ID));
3ad96835 169 printk("tvp5150: ROM version = (hex) %02x.%02x\n",
6b8fe025
HV		 170 tvp5150_read(sd, TVP5150_ROM_MAJOR_VER),
171 tvp5150_read(sd, TVP5150_ROM_MINOR_VER));
3ad96835 172 printk("tvp5150: Vertical line count = 0x%02x%02x\n",
6b8fe025
HV		 173 tvp5150_read(sd, TVP5150_VERT_LN_COUNT_MSB),
174 tvp5150_read(sd, TVP5150_VERT_LN_COUNT_LSB));
84486d53 175 printk("tvp5150: Interrupt status register B = 0x%02x\n",
6b8fe025 176 tvp5150_read(sd, TVP5150_INT_STATUS_REG_B));
84486d53 177 printk("tvp5150: Interrupt active register B = 0x%02x\n",
6b8fe025 178 tvp5150_read(sd, TVP5150_INT_ACTIVE_REG_B));
3ad96835 179 printk("tvp5150: Status regs #1 to #5 = %02x %02x %02x %02x %02x\n",
6b8fe025
HV		 180 tvp5150_read(sd, TVP5150_STATUS_REG_1),
181 tvp5150_read(sd, TVP5150_STATUS_REG_2),
182 tvp5150_read(sd, TVP5150_STATUS_REG_3),
183 tvp5150_read(sd, TVP5150_STATUS_REG_4),
184 tvp5150_read(sd, TVP5150_STATUS_REG_5));
3ad96835 185
6b8fe025
HV		 186 dump_reg_range(sd, "Teletext filter 1", TVP5150_TELETEXT_FIL1_INI,
187 TVP5150_TELETEXT_FIL1_END, 8);
188 dump_reg_range(sd, "Teletext filter 2", TVP5150_TELETEXT_FIL2_INI,
189 TVP5150_TELETEXT_FIL2_END, 8);
3ad96835 190
84486d53 191 printk("tvp5150: Teletext filter enable = 0x%02x\n",
6b8fe025 192 tvp5150_read(sd, TVP5150_TELETEXT_FIL_ENA));
84486d53 193 printk("tvp5150: Interrupt status register A = 0x%02x\n",
6b8fe025 194 tvp5150_read(sd, TVP5150_INT_STATUS_REG_A));
84486d53 195 printk("tvp5150: Interrupt enable register A = 0x%02x\n",
6b8fe025 196 tvp5150_read(sd, TVP5150_INT_ENABLE_REG_A));
84486d53 197 printk("tvp5150: Interrupt configuration = 0x%02x\n",
6b8fe025 198 tvp5150_read(sd, TVP5150_INT_CONF));
84486d53 199 printk("tvp5150: VDP status register = 0x%02x\n",
6b8fe025 200 tvp5150_read(sd, TVP5150_VDP_STATUS_REG));
84486d53 201 printk("tvp5150: FIFO word count = 0x%02x\n",
6b8fe025 202 tvp5150_read(sd, TVP5150_FIFO_WORD_COUNT));
84486d53 203 printk("tvp5150: FIFO interrupt threshold = 0x%02x\n",
6b8fe025 204 tvp5150_read(sd, TVP5150_FIFO_INT_THRESHOLD));
84486d53 205 printk("tvp5150: FIFO reset = 0x%02x\n",
6b8fe025 206 tvp5150_read(sd, TVP5150_FIFO_RESET));
84486d53 207 printk("tvp5150: Line number interrupt = 0x%02x\n",
6b8fe025 208 tvp5150_read(sd, TVP5150_LINE_NUMBER_INT));
3ad96835 209 printk("tvp5150: Pixel alignment register = 0x%02x%02x\n",
6b8fe025
HV		 210 tvp5150_read(sd, TVP5150_PIX_ALIGN_REG_HIGH),
211 tvp5150_read(sd, TVP5150_PIX_ALIGN_REG_LOW));
84486d53 212 printk("tvp5150: FIFO output control = 0x%02x\n",
6b8fe025 213 tvp5150_read(sd, TVP5150_FIFO_OUT_CTRL));
3ad96835 214 printk("tvp5150: Full field enable = 0x%02x\n",
6b8fe025 215 tvp5150_read(sd, TVP5150_FULL_FIELD_ENA));
84486d53 216 printk("tvp5150: Full field mode register = 0x%02x\n",
6b8fe025 217 tvp5150_read(sd, TVP5150_FULL_FIELD_MODE_REG));
3ad96835 218
6b8fe025
HV		 219 dump_reg_range(sd, "CC data", TVP5150_CC_DATA_INI,
220 TVP5150_CC_DATA_END, 8);
3ad96835 221
6b8fe025
HV		 222 dump_reg_range(sd, "WSS data", TVP5150_WSS_DATA_INI,
223 TVP5150_WSS_DATA_END, 8);
3ad96835 224
6b8fe025
HV		 225 dump_reg_range(sd, "VPS data", TVP5150_VPS_DATA_INI,
226 TVP5150_VPS_DATA_END, 8);
3ad96835 227
6b8fe025
HV		 228 dump_reg_range(sd, "VITC data", TVP5150_VITC_DATA_INI,
229 TVP5150_VITC_DATA_END, 10);
3ad96835 230
6b8fe025
HV		 231 dump_reg_range(sd, "Line mode", TVP5150_LINE_MODE_INI,
232 TVP5150_LINE_MODE_END, 8);
233 return 0;
cd4665c5
MCC		 234}
235
236/****************************************************************************
237 Basic functions
238 ****************************************************************************/
cd4665c5 239
6b8fe025 240static inline void tvp5150_selmux(struct v4l2_subdev *sd)
cd4665c5 241{
2962fc01 242 int opmode = 0;
6b8fe025 243 struct tvp5150 *decoder = to_tvp5150(sd);
c7c0b34c 244 int input = 0;
f4b8b3ae 245 unsigned char val;
84486d53 246
5325b427 247 if ((decoder->output & TVP5150_BLACK_SCREEN) || !decoder->enable)
c7c0b34c 248 input = 8;
4c86f973 249
5325b427 250 switch (decoder->input) {
c7c0b34c
HV		 251 case TVP5150_COMPOSITE1:
252 input |= 2;
253 /* fall through */
254 case TVP5150_COMPOSITE0:
c0477ad9 255 break;
c7c0b34c 256 case TVP5150_SVIDEO:
c0477ad9 257 default:
c7c0b34c 258 input |= 1;
c0477ad9
MCC		 259 break;
260 }
261
6b8fe025 262 v4l2_dbg(1, debug, sd, "Selecting video route: route input=%i, output=%i "
12500f07 263 "=> tvp5150 input=%i, opmode=%i\n",
5325b427
HV		 264 decoder->input, decoder->output,
265 input, opmode);
12500f07 266
6b8fe025
HV		 267 tvp5150_write(sd, TVP5150_OP_MODE_CTL, opmode);
268 tvp5150_write(sd, TVP5150_VD_IN_SRC_SEL_1, input);
f4b8b3ae
MCC		 269
270 /* Svideo should enable YCrCb output and disable GPCL output
271 * For Composite and TV, it should be the reverse
272 */
6b8fe025 273 val = tvp5150_read(sd, TVP5150_MISC_CTL);
5325b427 274 if (decoder->input == TVP5150_SVIDEO)
f4b8b3ae
MCC		 275 val = (val & ~0x40) | 0x10;
276 else
277 val = (val & ~0x10) | 0x40;
6b8fe025 278 tvp5150_write(sd, TVP5150_MISC_CTL, val);
cd4665c5
MCC		 279};
280
e1bc80ad
MCC		 281struct i2c_reg_value {
282 unsigned char reg;
283 unsigned char value;
284};
285
286/* Default values as sugested at TVP5150AM1 datasheet */
287static const struct i2c_reg_value tvp5150_init_default[] = {
288 { /* 0x00 */
289 TVP5150_VD_IN_SRC_SEL_1,0x00
290 },
291 { /* 0x01 */
292 TVP5150_ANAL_CHL_CTL,0x15
293 },
294 { /* 0x02 */
295 TVP5150_OP_MODE_CTL,0x00
296 },
297 { /* 0x03 */
298 TVP5150_MISC_CTL,0x01
299 },
300 { /* 0x06 */
301 TVP5150_COLOR_KIL_THSH_CTL,0x10
302 },
303 { /* 0x07 */
304 TVP5150_LUMA_PROC_CTL_1,0x60
305 },
306 { /* 0x08 */
307 TVP5150_LUMA_PROC_CTL_2,0x00
308 },
309 { /* 0x09 */
310 TVP5150_BRIGHT_CTL,0x80
311 },
312 { /* 0x0a */
313 TVP5150_SATURATION_CTL,0x80
314 },
315 { /* 0x0b */
316 TVP5150_HUE_CTL,0x00
317 },
318 { /* 0x0c */
319 TVP5150_CONTRAST_CTL,0x80
320 },
321 { /* 0x0d */
322 TVP5150_DATA_RATE_SEL,0x47
323 },
324 { /* 0x0e */
325 TVP5150_LUMA_PROC_CTL_3,0x00
326 },
327 { /* 0x0f */
328 TVP5150_CONF_SHARED_PIN,0x08
329 },
330 { /* 0x11 */
331 TVP5150_ACT_VD_CROP_ST_MSB,0x00
332 },
333 { /* 0x12 */
334 TVP5150_ACT_VD_CROP_ST_LSB,0x00
335 },
336 { /* 0x13 */
337 TVP5150_ACT_VD_CROP_STP_MSB,0x00
338 },
339 { /* 0x14 */
340 TVP5150_ACT_VD_CROP_STP_LSB,0x00
341 },
342 { /* 0x15 */
343 TVP5150_GENLOCK,0x01
344 },
345 { /* 0x16 */
346 TVP5150_HORIZ_SYNC_START,0x80
347 },
348 { /* 0x18 */
349 TVP5150_VERT_BLANKING_START,0x00
350 },
351 { /* 0x19 */
352 TVP5150_VERT_BLANKING_STOP,0x00
353 },
354 { /* 0x1a */
355 TVP5150_CHROMA_PROC_CTL_1,0x0c
356 },
357 { /* 0x1b */
358 TVP5150_CHROMA_PROC_CTL_2,0x14
359 },
360 { /* 0x1c */
361 TVP5150_INT_RESET_REG_B,0x00
362 },
363 { /* 0x1d */
364 TVP5150_INT_ENABLE_REG_B,0x00
365 },
366 { /* 0x1e */
367 TVP5150_INTT_CONFIG_REG_B,0x00
368 },
369 { /* 0x28 */
370 TVP5150_VIDEO_STD,0x00
371 },
372 { /* 0x2e */
373 TVP5150_MACROVISION_ON_CTR,0x0f
374 },
375 { /* 0x2f */
376 TVP5150_MACROVISION_OFF_CTR,0x01
377 },
378 { /* 0xbb */
379 TVP5150_TELETEXT_FIL_ENA,0x00
380 },
381 { /* 0xc0 */
382 TVP5150_INT_STATUS_REG_A,0x00
383 },
384 { /* 0xc1 */
385 TVP5150_INT_ENABLE_REG_A,0x00
386 },
387 { /* 0xc2 */
388 TVP5150_INT_CONF,0x04
389 },
390 { /* 0xc8 */
391 TVP5150_FIFO_INT_THRESHOLD,0x80
392 },
393 { /* 0xc9 */
394 TVP5150_FIFO_RESET,0x00
395 },
396 { /* 0xca */
397 TVP5150_LINE_NUMBER_INT,0x00
398 },
399 { /* 0xcb */
400 TVP5150_PIX_ALIGN_REG_LOW,0x4e
401 },
402 { /* 0xcc */
403 TVP5150_PIX_ALIGN_REG_HIGH,0x00
404 },
405 { /* 0xcd */
406 TVP5150_FIFO_OUT_CTRL,0x01
407 },
408 { /* 0xcf */
3ad96835 409 TVP5150_FULL_FIELD_ENA,0x00
e1bc80ad
MCC		 410 },
411 { /* 0xd0 */
3ad96835 412 TVP5150_LINE_MODE_INI,0x00
e1bc80ad
MCC		 413 },
414 { /* 0xfc */
415 TVP5150_FULL_FIELD_MODE_REG,0x7f
416 },
417 { /* end of data */
418 0xff,0xff
419 }
420};
421
422/* Default values as sugested at TVP5150AM1 datasheet */
423static const struct i2c_reg_value tvp5150_init_enable[] = {
424 {
425 TVP5150_CONF_SHARED_PIN, 2
426 },{ /* Automatic offset and AGC enabled */
427 TVP5150_ANAL_CHL_CTL, 0x15
428 },{ /* Activate YCrCb output 0x9 or 0xd ? */
429 TVP5150_MISC_CTL, 0x6f
430 },{ /* Activates video std autodetection for all standards */
431 TVP5150_AUTOSW_MSK, 0x0
432 },{ /* Default format: 0x47. For 4:2:2: 0x40 */
433 TVP5150_DATA_RATE_SEL, 0x47
434 },{
435 TVP5150_CHROMA_PROC_CTL_1, 0x0c
436 },{
437 TVP5150_CHROMA_PROC_CTL_2, 0x54
438 },{ /* Non documented, but initialized on WinTV USB2 */
439 0x27, 0x20
440 },{
441 0xff,0xff
442 }
443};
444
6ac48b45
MCC		 445struct tvp5150_vbi_type {
446 unsigned int vbi_type;
447 unsigned int ini_line;
448 unsigned int end_line;
449 unsigned int by_field :1;
450};
451
e1bc80ad
MCC		 452struct i2c_vbi_ram_value {
453 u16 reg;
6ac48b45
MCC		 454 struct tvp5150_vbi_type type;
455 unsigned char values[16];
e1bc80ad
MCC		 456};
457
6ac48b45
MCC		 458/* This struct have the values for each supported VBI Standard
459 * by
460 tvp5150_vbi_types should follow the same order as vbi_ram_default
3ad96835
MCC		 461 * value 0 means rom position 0x10, value 1 means rom position 0x30
462 * and so on. There are 16 possible locations from 0 to 15.
463 */
3ad96835 464
a9cff90e 465static struct i2c_vbi_ram_value vbi_ram_default[] =
cd4665c5 466{
9bc7400a
HV		 467 /* FIXME: Current api doesn't handle all VBI types, those not
468 yet supported are placed under #if 0 */
469#if 0
6ac48b45
MCC		 470 {0x010, /* Teletext, SECAM, WST System A */
471 {V4L2_SLICED_TELETEXT_SECAM,6,23,1},
472 { 0xaa, 0xaa, 0xff, 0xff, 0xe7, 0x2e, 0x20, 0x26,
473 0xe6, 0xb4, 0x0e, 0x00, 0x00, 0x00, 0x10, 0x00 }
e1bc80ad 474 },
9bc7400a 475#endif
6ac48b45 476 {0x030, /* Teletext, PAL, WST System B */
9bc7400a 477 {V4L2_SLICED_TELETEXT_B,6,22,1},
6ac48b45
MCC		 478 { 0xaa, 0xaa, 0xff, 0xff, 0x27, 0x2e, 0x20, 0x2b,
479 0xa6, 0x72, 0x10, 0x00, 0x00, 0x00, 0x10, 0x00 }
e1bc80ad 480 },
9bc7400a 481#if 0
6ac48b45
MCC		 482 {0x050, /* Teletext, PAL, WST System C */
483 {V4L2_SLICED_TELETEXT_PAL_C,6,22,1},
484 { 0xaa, 0xaa, 0xff, 0xff, 0xe7, 0x2e, 0x20, 0x22,
485 0xa6, 0x98, 0x0d, 0x00, 0x00, 0x00, 0x10, 0x00 }
e1bc80ad 486 },
6ac48b45
MCC		 487 {0x070, /* Teletext, NTSC, WST System B */
488 {V4L2_SLICED_TELETEXT_NTSC_B,10,21,1},
489 { 0xaa, 0xaa, 0xff, 0xff, 0x27, 0x2e, 0x20, 0x23,
490 0x69, 0x93, 0x0d, 0x00, 0x00, 0x00, 0x10, 0x00 }
e1bc80ad 491 },
6ac48b45
MCC		 492 {0x090, /* Tetetext, NTSC NABTS System C */
493 {V4L2_SLICED_TELETEXT_NTSC_C,10,21,1},
494 { 0xaa, 0xaa, 0xff, 0xff, 0xe7, 0x2e, 0x20, 0x22,
495 0x69, 0x93, 0x0d, 0x00, 0x00, 0x00, 0x15, 0x00 }
e1bc80ad 496 },
6ac48b45
MCC		 497 {0x0b0, /* Teletext, NTSC-J, NABTS System D */
498 {V4L2_SLICED_TELETEXT_NTSC_D,10,21,1},
499 { 0xaa, 0xaa, 0xff, 0xff, 0xa7, 0x2e, 0x20, 0x23,
500 0x69, 0x93, 0x0d, 0x00, 0x00, 0x00, 0x10, 0x00 }
e1bc80ad 501 },
6ac48b45
MCC		 502 {0x0d0, /* Closed Caption, PAL/SECAM */
503 {V4L2_SLICED_CAPTION_625,22,22,1},
504 { 0xaa, 0x2a, 0xff, 0x3f, 0x04, 0x51, 0x6e, 0x02,
505 0xa6, 0x7b, 0x09, 0x00, 0x00, 0x00, 0x27, 0x00 }
e1bc80ad 506 },
9bc7400a 507#endif
6ac48b45
MCC		 508 {0x0f0, /* Closed Caption, NTSC */
509 {V4L2_SLICED_CAPTION_525,21,21,1},
510 { 0xaa, 0x2a, 0xff, 0x3f, 0x04, 0x51, 0x6e, 0x02,
511 0x69, 0x8c, 0x09, 0x00, 0x00, 0x00, 0x27, 0x00 }
e1bc80ad 512 },
6ac48b45 513 {0x110, /* Wide Screen Signal, PAL/SECAM */
12db5607 514 {V4L2_SLICED_WSS_625,23,23,1},
6ac48b45
MCC		 515 { 0x5b, 0x55, 0xc5, 0xff, 0x00, 0x71, 0x6e, 0x42,
516 0xa6, 0xcd, 0x0f, 0x00, 0x00, 0x00, 0x3a, 0x00 }
e1bc80ad 517 },
9bc7400a 518#if 0
6ac48b45
MCC		 519 {0x130, /* Wide Screen Signal, NTSC C */
520 {V4L2_SLICED_WSS_525,20,20,1},
521 { 0x38, 0x00, 0x3f, 0x00, 0x00, 0x71, 0x6e, 0x43,
522 0x69, 0x7c, 0x08, 0x00, 0x00, 0x00, 0x39, 0x00 }
e1bc80ad 523 },
6ac48b45
MCC		 524 {0x150, /* Vertical Interval Timecode (VITC), PAL/SECAM */
525 {V4l2_SLICED_VITC_625,6,22,0},
526 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x8f, 0x6d, 0x49,
527 0xa6, 0x85, 0x08, 0x00, 0x00, 0x00, 0x4c, 0x00 }
e1bc80ad 528 },
6ac48b45
MCC		 529 {0x170, /* Vertical Interval Timecode (VITC), NTSC */
530 {V4l2_SLICED_VITC_525,10,20,0},
531 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x8f, 0x6d, 0x49,
532 0x69, 0x94, 0x08, 0x00, 0x00, 0x00, 0x4c, 0x00 }
e1bc80ad 533 },
9bc7400a 534#endif
6ac48b45
MCC		 535 {0x190, /* Video Program System (VPS), PAL */
536 {V4L2_SLICED_VPS,16,16,0},
537 { 0xaa, 0xaa, 0xff, 0xff, 0xba, 0xce, 0x2b, 0x0d,
538 0xa6, 0xda, 0x0b, 0x00, 0x00, 0x00, 0x60, 0x00 }
3ad96835 539 },
6ac48b45
MCC		 540 /* 0x1d0 User programmable */
541
542 /* End of struct */
543 { (u16)-1 }
e1bc80ad 544};
4c86f973 545
6b8fe025 546static int tvp5150_write_inittab(struct v4l2_subdev *sd,
6ac48b45 547 const struct i2c_reg_value *regs)
e1bc80ad
MCC		 548{
549 while (regs->reg != 0xff) {
6b8fe025 550 tvp5150_write(sd, regs->reg, regs->value);
e1bc80ad
MCC		 551 regs++;
552 }
553 return 0;
554}
84486d53 555
6b8fe025 556static int tvp5150_vdp_init(struct v4l2_subdev *sd,
6ac48b45 557 const struct i2c_vbi_ram_value *regs)
e1bc80ad
MCC		 558{
559 unsigned int i;
cd4665c5 560
e1bc80ad 561 /* Disable Full Field */
6b8fe025 562 tvp5150_write(sd, TVP5150_FULL_FIELD_ENA, 0);
cd4665c5 563
e1bc80ad 564 /* Before programming, Line mode should be at 0xff */
6b8fe025
HV		 565 for (i = TVP5150_LINE_MODE_INI; i <= TVP5150_LINE_MODE_END; i++)
566 tvp5150_write(sd, i, 0xff);
cd4665c5 567
e1bc80ad 568 /* Load Ram Table */
6b8fe025
HV		 569 while (regs->reg != (u16)-1) {
570 tvp5150_write(sd, TVP5150_CONF_RAM_ADDR_HIGH, regs->reg >> 8);
571 tvp5150_write(sd, TVP5150_CONF_RAM_ADDR_LOW, regs->reg);
cd4665c5 572
6b8fe025
HV		 573 for (i = 0; i < 16; i++)
574 tvp5150_write(sd, TVP5150_VDP_CONF_RAM_DATA, regs->values[i]);
84486d53 575
e1bc80ad
MCC		 576 regs++;
577 }
578 return 0;
579}
cd4665c5 580
6ac48b45 581/* Fills VBI capabilities based on i2c_vbi_ram_value struct */
6b8fe025 582static int tvp5150_g_sliced_vbi_cap(struct v4l2_subdev *sd,
6ac48b45
MCC		 583 struct v4l2_sliced_vbi_cap *cap)
584{
6b8fe025 585 const struct i2c_vbi_ram_value *regs = vbi_ram_default;
6ac48b45
MCC		 586 int line;
587
bccfa449 588 v4l2_dbg(1, debug, sd, "g_sliced_vbi_cap\n");
6ac48b45
MCC		 589 memset(cap, 0, sizeof *cap);
590
591 while (regs->reg != (u16)-1 ) {
592 for (line=regs->type.ini_line;line<=regs->type.end_line;line++) {
593 cap->service_lines[0][line] |= regs->type.vbi_type;
594 }
595 cap->service_set |= regs->type.vbi_type;
596
597 regs++;
598 }
6b8fe025 599 return 0;
6ac48b45
MCC		 600}
601
3ad96835
MCC		 602/* Set vbi processing
603 * type - one of tvp5150_vbi_types
604 * line - line to gather data
605 * fields: bit 0 field1, bit 1, field2
606 * flags (default=0xf0) is a bitmask, were set means:
607 * bit 7: enable filtering null bytes on CC
608 * bit 6: send data also to FIFO
609 * bit 5: don't allow data with errors on FIFO
610 * bit 4: enable ECC when possible
611 * pix_align = pix alignment:
612 * LSB = field1
613 * MSB = field2
614 */
6b8fe025 615static int tvp5150_set_vbi(struct v4l2_subdev *sd,
2701dacb
MCC		 616 const struct i2c_vbi_ram_value *regs,
617 unsigned int type,u8 flags, int line,
618 const int fields)
3ad96835 619{
6b8fe025
HV		 620 struct tvp5150 *decoder = to_tvp5150(sd);
621 v4l2_std_id std = decoder->norm;
3ad96835 622 u8 reg;
2701dacb 623 int pos=0;
3ad96835
MCC		 624
625 if (std == V4L2_STD_ALL) {
6b8fe025 626 v4l2_err(sd, "VBI can't be configured without knowing number of lines\n");
12db5607 627 return 0;
7d5b7b98 628 } else if (std & V4L2_STD_625_50) {
3ad96835
MCC		 629 /* Don't follow NTSC Line number convension */
630 line += 3;
631 }
632
633 if (line<6||line>27)
2701dacb
MCC		 634 return 0;
635
636 while (regs->reg != (u16)-1 ) {
637 if ((type & regs->type.vbi_type) &&
638 (line>=regs->type.ini_line) &&
639 (line<=regs->type.end_line)) {
640 type=regs->type.vbi_type;
641 break;
642 }
643
644 regs++;
645 pos++;
646 }
647 if (regs->reg == (u16)-1)
648 return 0;
3ad96835 649
2701dacb 650 type=pos | (flags & 0xf0);
3ad96835
MCC		 651 reg=((line-6)<<1)+TVP5150_LINE_MODE_INI;
652
653 if (fields&1) {
6b8fe025 654 tvp5150_write(sd, reg, type);
3ad96835
MCC		 655 }
656
657 if (fields&2) {
6b8fe025 658 tvp5150_write(sd, reg+1, type);
3ad96835
MCC		 659 }
660
2701dacb 661 return type;
3ad96835
MCC		 662}
663
6b8fe025 664static int tvp5150_get_vbi(struct v4l2_subdev *sd,
12db5607
MCC		 665 const struct i2c_vbi_ram_value *regs, int line)
666{
6b8fe025
HV		 667 struct tvp5150 *decoder = to_tvp5150(sd);
668 v4l2_std_id std = decoder->norm;
12db5607 669 u8 reg;
6b8fe025 670 int pos, type = 0;
12db5607
MCC		 671
672 if (std == V4L2_STD_ALL) {
6b8fe025 673 v4l2_err(sd, "VBI can't be configured without knowing number of lines\n");
12db5607 674 return 0;
7d5b7b98 675 } else if (std & V4L2_STD_625_50) {
12db5607
MCC		 676 /* Don't follow NTSC Line number convension */
677 line += 3;
678 }
679
6b8fe025 680 if (line < 6 || line > 27)
12db5607
MCC		 681 return 0;
682
6b8fe025 683 reg = ((line - 6) << 1) + TVP5150_LINE_MODE_INI;
12db5607 684
6b8fe025
HV		 685 pos = tvp5150_read(sd, reg) & 0x0f;
686 if (pos < 0x0f)
687 type = regs[pos].type.vbi_type;
12db5607 688
6b8fe025
HV		 689 pos = tvp5150_read(sd, reg + 1) & 0x0f;
690 if (pos < 0x0f)
691 type |= regs[pos].type.vbi_type;
12db5607
MCC		 692
693 return type;
694}
6b8fe025
HV		 695
696static int tvp5150_set_std(struct v4l2_subdev *sd, v4l2_std_id std)
e1bc80ad 697{
6b8fe025
HV		 698 struct tvp5150 *decoder = to_tvp5150(sd);
699 int fmt = 0;
e1bc80ad 700
6b8fe025 701 decoder->norm = std;
e1bc80ad
MCC		 702
703 /* First tests should be against specific std */
704
705 if (std == V4L2_STD_ALL) {
2da12fcb 706 fmt = VIDEO_STD_AUTO_SWITCH_BIT; /* Autodetect mode */
e1bc80ad 707 } else if (std & V4L2_STD_NTSC_443) {
2da12fcb 708 fmt = VIDEO_STD_NTSC_4_43_BIT;
e1bc80ad 709 } else if (std & V4L2_STD_PAL_M) {
2da12fcb 710 fmt = VIDEO_STD_PAL_M_BIT;
6b8fe025 711 } else if (std & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) {
2da12fcb 712 fmt = VIDEO_STD_PAL_COMBINATION_N_BIT;
e1bc80ad
MCC		 713 } else {
714 /* Then, test against generic ones */
6b8fe025 715 if (std & V4L2_STD_NTSC)
2da12fcb 716 fmt = VIDEO_STD_NTSC_MJ_BIT;
6b8fe025 717 else if (std & V4L2_STD_PAL)
2da12fcb 718 fmt = VIDEO_STD_PAL_BDGHIN_BIT;
6b8fe025 719 else if (std & V4L2_STD_SECAM)
2da12fcb 720 fmt = VIDEO_STD_SECAM_BIT;
e1bc80ad 721 }
84486d53 722
6b8fe025
HV		 723 v4l2_dbg(1, debug, sd, "Set video std register to %d.\n", fmt);
724 tvp5150_write(sd, TVP5150_VIDEO_STD, fmt);
e1bc80ad
MCC		 725 return 0;
726}
727
6b8fe025
HV		 728static int tvp5150_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
729{
730 struct tvp5150 *decoder = to_tvp5150(sd);
731
732 if (decoder->norm == std)
733 return 0;
734
735 return tvp5150_set_std(sd, std);
736}
737
738static int tvp5150_reset(struct v4l2_subdev *sd, u32 val)
e1bc80ad 739{
6b8fe025 740 struct tvp5150 *decoder = to_tvp5150(sd);
84486d53 741
e1bc80ad 742 /* Initializes TVP5150 to its default values */
6b8fe025 743 tvp5150_write_inittab(sd, tvp5150_init_default);
e1bc80ad
MCC		 744
745 /* Initializes VDP registers */
6b8fe025 746 tvp5150_vdp_init(sd, vbi_ram_default);
e1bc80ad
MCC		 747
748 /* Selects decoder input */
6b8fe025 749 tvp5150_selmux(sd);
e1bc80ad
MCC		 750
751 /* Initializes TVP5150 to stream enabled values */
6b8fe025 752 tvp5150_write_inittab(sd, tvp5150_init_enable);
e1bc80ad
MCC		 753
754 /* Initialize image preferences */
6c45ec71 755 v4l2_ctrl_handler_setup(&decoder->hdl);
e1bc80ad 756
6b8fe025
HV		 757 tvp5150_set_std(sd, decoder->norm);
758 return 0;
cd4665c5
MCC		 759};
760
6c45ec71 761static int tvp5150_s_ctrl(struct v4l2_ctrl *ctrl)
a6c2ba28 762{
6c45ec71 763 struct v4l2_subdev *sd = to_sd(ctrl);
a6c2ba28 764
765 switch (ctrl->id) {
766 case V4L2_CID_BRIGHTNESS:
6c45ec71 767 tvp5150_write(sd, TVP5150_BRIGHT_CTL, ctrl->val);
a6c2ba28 768 return 0;
769 case V4L2_CID_CONTRAST:
6c45ec71 770 tvp5150_write(sd, TVP5150_CONTRAST_CTL, ctrl->val);
a6c2ba28 771 return 0;
772 case V4L2_CID_SATURATION:
6c45ec71 773 tvp5150_write(sd, TVP5150_SATURATION_CTL, ctrl->val);
a6c2ba28 774 return 0;
775 case V4L2_CID_HUE:
6c45ec71 776 tvp5150_write(sd, TVP5150_HUE_CTL, ctrl->val);
a6c2ba28 777 return 0;
a6c2ba28 778 }
c0477ad9 779 return -EINVAL;
a6c2ba28 780}
781
ec2c4f3f
JM		 782static v4l2_std_id tvp5150_read_std(struct v4l2_subdev *sd)
783{
784 int val = tvp5150_read(sd, TVP5150_STATUS_REG_5);
785
786 switch (val & 0x0F) {
787 case 0x01:
788 return V4L2_STD_NTSC;
789 case 0x03:
790 return V4L2_STD_PAL;
791 case 0x05:
792 return V4L2_STD_PAL_M;
793 case 0x07:
794 return V4L2_STD_PAL_N | V4L2_STD_PAL_Nc;
795 case 0x09:
796 return V4L2_STD_NTSC_443;
797 case 0xb:
798 return V4L2_STD_SECAM;
799 default:
800 return V4L2_STD_UNKNOWN;
801 }
802}
803
804static int tvp5150_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned index,
805 enum v4l2_mbus_pixelcode *code)
806{
807 if (index)
808 return -EINVAL;
809
810 *code = V4L2_MBUS_FMT_YUYV8_2X8;
811 return 0;
812}
813
814static int tvp5150_mbus_fmt(struct v4l2_subdev *sd,
815 struct v4l2_mbus_framefmt *f)
816{
817 struct tvp5150 *decoder = to_tvp5150(sd);
818 v4l2_std_id std;
819
820 if (f == NULL)
821 return -EINVAL;
822
823 tvp5150_reset(sd, 0);
824
825 /* Calculate height and width based on current standard */
826 if (decoder->norm == V4L2_STD_ALL)
827 std = tvp5150_read_std(sd);
828 else
829 std = decoder->norm;
830
831 f->width = 720;
832 if (std & V4L2_STD_525_60)
833 f->height = 480;
834 else
835 f->height = 576;
836
837 f->code = V4L2_MBUS_FMT_YUYV8_2X8;
838 f->field = V4L2_FIELD_SEQ_TB;
839 f->colorspace = V4L2_COLORSPACE_SMPTE170M;
840
841 v4l2_dbg(1, debug, sd, "width = %d, height = %d\n", f->width,
842 f->height);
843 return 0;
844}
845
84486d53
MCC		 846/****************************************************************************
847 I2C Command
848 ****************************************************************************/
c7c0b34c 849
5325b427
HV		 850static int tvp5150_s_routing(struct v4l2_subdev *sd,
851 u32 input, u32 output, u32 config)
6b8fe025
HV		 852{
853 struct tvp5150 *decoder = to_tvp5150(sd);
84486d53 854
5325b427
HV		 855 decoder->input = input;
856 decoder->output = output;
6b8fe025
HV		 857 tvp5150_selmux(sd);
858 return 0;
859}
6ac48b45 860
d37dad49
HV		 861static int tvp5150_s_raw_fmt(struct v4l2_subdev *sd, struct v4l2_vbi_format *fmt)
862{
863 /* this is for capturing 36 raw vbi lines
864 if there's a way to cut off the beginning 2 vbi lines
865 with the tvp5150 then the vbi line count could be lowered
866 to 17 lines/field again, although I couldn't find a register
867 which could do that cropping */
868 if (fmt->sample_format == V4L2_PIX_FMT_GREY)
869 tvp5150_write(sd, TVP5150_LUMA_PROC_CTL_1, 0x70);
870 if (fmt->count[0] == 18 && fmt->count[1] == 18) {
871 tvp5150_write(sd, TVP5150_VERT_BLANKING_START, 0x00);
872 tvp5150_write(sd, TVP5150_VERT_BLANKING_STOP, 0x01);
873 }
874 return 0;
875}
876
877static int tvp5150_s_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *svbi)
6b8fe025 878{
6b8fe025
HV		 879 int i;
880
6b8fe025
HV		 881 if (svbi->service_set != 0) {
882 for (i = 0; i <= 23; i++) {
883 svbi->service_lines[1][i] = 0;
884 svbi->service_lines[0][i] =
885 tvp5150_set_vbi(sd, vbi_ram_default,
886 svbi->service_lines[0][i], 0xf0, i, 3);
2c5aacc6 887 }
6b8fe025
HV		 888 /* Enables FIFO */
889 tvp5150_write(sd, TVP5150_FIFO_OUT_CTRL, 1);
890 } else {
891 /* Disables FIFO*/
892 tvp5150_write(sd, TVP5150_FIFO_OUT_CTRL, 0);
12db5607 893
6b8fe025
HV		 894 /* Disable Full Field */
895 tvp5150_write(sd, TVP5150_FULL_FIELD_ENA, 0);
12db5607 896
6b8fe025
HV		 897 /* Disable Line modes */
898 for (i = TVP5150_LINE_MODE_INI; i <= TVP5150_LINE_MODE_END; i++)
899 tvp5150_write(sd, i, 0xff);
12db5607 900 }
6b8fe025
HV		 901 return 0;
902}
12db5607 903
d37dad49
HV		 904static int tvp5150_g_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *svbi)
905{
906 int i, mask = 0;
907
6b8fe025 908 memset(svbi, 0, sizeof(*svbi));
12db5607 909
6b8fe025
HV		 910 for (i = 0; i <= 23; i++) {
911 svbi->service_lines[0][i] =
912 tvp5150_get_vbi(sd, vbi_ram_default, i);
913 mask |= svbi->service_lines[0][i];
2701dacb 914 }
6b8fe025
HV		 915 svbi->service_set = mask;
916 return 0;
917}
918
bc974305 919static int tvp5150_g_chip_ident(struct v4l2_subdev *sd,
aecde8b5 920 struct v4l2_dbg_chip_ident *chip)
bc974305
MCC		 921{
922 int rev;
923 struct i2c_client *client = v4l2_get_subdevdata(sd);
924
925 rev = tvp5150_read(sd, TVP5150_ROM_MAJOR_VER) << 8 |
926 tvp5150_read(sd, TVP5150_ROM_MINOR_VER);
927
928 return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_TVP5150,
929 rev);
930}
931
932
21dcd8cc 933#ifdef CONFIG_VIDEO_ADV_DEBUG
aecde8b5 934static int tvp5150_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
6b8fe025
HV		 935{
936 struct i2c_client *client = v4l2_get_subdevdata(sd);
21dcd8cc 937
aecde8b5 938 if (!v4l2_chip_match_i2c_client(client, &reg->match))
6b8fe025
HV		 939 return -EINVAL;
940 if (!capable(CAP_SYS_ADMIN))
941 return -EPERM;
942 reg->val = tvp5150_read(sd, reg->reg & 0xff);
aecde8b5 943 reg->size = 1;
6b8fe025
HV		 944 return 0;
945}
84486d53 946
aecde8b5 947static int tvp5150_s_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
6b8fe025
HV		 948{
949 struct i2c_client *client = v4l2_get_subdevdata(sd);
84486d53 950
aecde8b5 951 if (!v4l2_chip_match_i2c_client(client, &reg->match))
6b8fe025
HV		 952 return -EINVAL;
953 if (!capable(CAP_SYS_ADMIN))
954 return -EPERM;
955 tvp5150_write(sd, reg->reg & 0xff, reg->val & 0xff);
956 return 0;
957}
958#endif
a6c2ba28 959
6b8fe025
HV		 960static int tvp5150_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
961{
962 int status = tvp5150_read(sd, 0x88);
a6c2ba28 963
6b8fe025
HV		 964 vt->signal = ((status & 0x04) && (status & 0x02)) ? 0xffff : 0x0;
965 return 0;
966}
a6c2ba28 967
6b8fe025
HV		 968/* ----------------------------------------------------------------------- */
969
6c45ec71
HV		 970static const struct v4l2_ctrl_ops tvp5150_ctrl_ops = {
971 .s_ctrl = tvp5150_s_ctrl,
972};
973
6b8fe025
HV		 974static const struct v4l2_subdev_core_ops tvp5150_core_ops = {
975 .log_status = tvp5150_log_status,
6c45ec71
HV		 976 .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
977 .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
978 .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
979 .g_ctrl = v4l2_subdev_g_ctrl,
980 .s_ctrl = v4l2_subdev_s_ctrl,
981 .queryctrl = v4l2_subdev_queryctrl,
982 .querymenu = v4l2_subdev_querymenu,
f41737ec 983 .s_std = tvp5150_s_std,
6b8fe025 984 .reset = tvp5150_reset,
bc974305 985 .g_chip_ident = tvp5150_g_chip_ident,
6b8fe025
HV		 986#ifdef CONFIG_VIDEO_ADV_DEBUG
987 .g_register = tvp5150_g_register,
988 .s_register = tvp5150_s_register,
989#endif
990};
991
992static const struct v4l2_subdev_tuner_ops tvp5150_tuner_ops = {
6b8fe025
HV		 993 .g_tuner = tvp5150_g_tuner,
994};
995
996static const struct v4l2_subdev_video_ops tvp5150_video_ops = {
997 .s_routing = tvp5150_s_routing,
ec2c4f3f
JM		 998 .enum_mbus_fmt = tvp5150_enum_mbus_fmt,
999 .s_mbus_fmt = tvp5150_mbus_fmt,
1000 .try_mbus_fmt = tvp5150_mbus_fmt,
32cd527f
HV		 1001};
1002
1003static const struct v4l2_subdev_vbi_ops tvp5150_vbi_ops = {
6b8fe025 1004 .g_sliced_vbi_cap = tvp5150_g_sliced_vbi_cap,
d37dad49
HV		 1005 .g_sliced_fmt = tvp5150_g_sliced_fmt,
1006 .s_sliced_fmt = tvp5150_s_sliced_fmt,
1007 .s_raw_fmt = tvp5150_s_raw_fmt,
6b8fe025
HV		 1008};
1009
1010static const struct v4l2_subdev_ops tvp5150_ops = {
1011 .core = &tvp5150_core_ops,
1012 .tuner = &tvp5150_tuner_ops,
1013 .video = &tvp5150_video_ops,
32cd527f 1014 .vbi = &tvp5150_vbi_ops,
6b8fe025
HV		 1015};
1016
1017
cd4665c5
MCC		 1018/****************************************************************************
1019 I2C Client & Driver
1020 ****************************************************************************/
cd4665c5 1021
6b8fe025
HV		 1022static int tvp5150_probe(struct i2c_client *c,
1023 const struct i2c_device_id *id)
cd4665c5 1024{
cd4665c5 1025 struct tvp5150 *core;
6b8fe025 1026 struct v4l2_subdev *sd;
0e09a3c9 1027 u8 msb_id, lsb_id, msb_rom, lsb_rom;
cd4665c5
MCC		 1028
1029 /* Check if the adapter supports the needed features */
6b8fe025 1030 if (!i2c_check_functionality(c->adapter,
cd4665c5 1031 I2C_FUNC_SMBUS_READ_BYTE | I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
6b8fe025 1032 return -EIO;
cd4665c5 1033
7408187d 1034 core = kzalloc(sizeof(struct tvp5150), GFP_KERNEL);
5fa1247a 1035 if (!core) {
cd4665c5
MCC		 1036 return -ENOMEM;
1037 }
6b8fe025
HV		 1038 sd = &core->sd;
1039 v4l2_i2c_subdev_init(sd, c, &tvp5150_ops);
1040 v4l_info(c, "chip found @ 0x%02x (%s)\n",
1041 c->addr << 1, c->adapter->name);
cd4665c5 1042
0e09a3c9
MCC		 1043 msb_id = tvp5150_read(sd, TVP5150_MSB_DEV_ID);
1044 lsb_id = tvp5150_read(sd, TVP5150_LSB_DEV_ID);
1045 msb_rom = tvp5150_read(sd, TVP5150_ROM_MAJOR_VER);
1046 lsb_rom = tvp5150_read(sd, TVP5150_ROM_MINOR_VER);
1047
1048 if (msb_rom == 4 && lsb_rom == 0) { /* Is TVP5150AM1 */
1049 v4l2_info(sd, "tvp%02x%02xam1 detected.\n", msb_id, lsb_id);
1050
1051 /* ITU-T BT.656.4 timing */
1052 tvp5150_write(sd, TVP5150_REV_SELECT, 0);
1053 } else {
1054 if (msb_rom == 3 || lsb_rom == 0x21) { /* Is TVP5150A */
1055 v4l2_info(sd, "tvp%02x%02xa detected.\n", msb_id, lsb_id);
1056 } else {
1057 v4l2_info(sd, "*** unknown tvp%02x%02x chip detected.\n",
1058 msb_id, lsb_id);
1059 v4l2_info(sd, "*** Rom ver is %d.%d\n", msb_rom, lsb_rom);
1060 }
1061 }
1062
3ad96835 1063 core->norm = V4L2_STD_ALL; /* Default is autodetect */
5325b427 1064 core->input = TVP5150_COMPOSITE1;
4c86f973 1065 core->enable = 1;
6c45ec71
HV		 1066
1067 v4l2_ctrl_handler_init(&core->hdl, 4);
1068 v4l2_ctrl_new_std(&core->hdl, &tvp5150_ctrl_ops,
1069 V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
1070 v4l2_ctrl_new_std(&core->hdl, &tvp5150_ctrl_ops,
1071 V4L2_CID_CONTRAST, 0, 255, 1, 128);
1072 v4l2_ctrl_new_std(&core->hdl, &tvp5150_ctrl_ops,
1073 V4L2_CID_SATURATION, 0, 255, 1, 128);
1074 v4l2_ctrl_new_std(&core->hdl, &tvp5150_ctrl_ops,
1075 V4L2_CID_HUE, -128, 127, 1, 0);
1076 sd->ctrl_handler = &core->hdl;
1077 if (core->hdl.error) {
1078 int err = core->hdl.error;
1079
1080 v4l2_ctrl_handler_free(&core->hdl);
1081 kfree(core);
1082 return err;
1083 }
1084 v4l2_ctrl_handler_setup(&core->hdl);
4c86f973 1085
f1e5ee45 1086 if (debug > 1)
6b8fe025 1087 tvp5150_log_status(sd);
cd4665c5
MCC		 1088 return 0;
1089}
1090
6b8fe025 1091static int tvp5150_remove(struct i2c_client *c)
cd4665c5 1092{
6b8fe025 1093 struct v4l2_subdev *sd = i2c_get_clientdata(c);
6c45ec71 1094 struct tvp5150 *decoder = to_tvp5150(sd);
cd4665c5 1095
6b8fe025 1096 v4l2_dbg(1, debug, sd,
e1bc80ad
MCC		 1097 "tvp5150.c: removing tvp5150 adapter on address 0x%x\n",
1098 c->addr << 1);
1099
6b8fe025 1100 v4l2_device_unregister_subdev(sd);
6c45ec71 1101 v4l2_ctrl_handler_free(&decoder->hdl);
6b8fe025 1102 kfree(to_tvp5150(sd));
cd4665c5
MCC		 1103 return 0;
1104}
1105
1106/* ----------------------------------------------------------------------- */
1107
6b8fe025
HV		 1108static const struct i2c_device_id tvp5150_id[] = {
1109 { "tvp5150", 0 },
1110 { }
1111};
1112MODULE_DEVICE_TABLE(i2c, tvp5150_id);
84486d53 1113
c771145b
HV		 1114static struct i2c_driver tvp5150_driver = {
1115 .driver = {
1116 .owner = THIS_MODULE,
1117 .name = "tvp5150",
1118 },
1119 .probe = tvp5150_probe,
1120 .remove = tvp5150_remove,
1121 .id_table = tvp5150_id,
cd4665c5 1122};
c771145b 1123
c6e8d86f 1124module_i2c_driver(tvp5150_driver);
Linux kernel - Deliverables
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