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[media] V4L: sh_mobile_csi2: support the new mbus-config subdev ops
[deliverable/linux.git] / drivers / media / video / tw9910.c
CommitLineData
ed922a89
KM		 1/*
2 * tw9910 Video Driver
3 *
4 * Copyright (C) 2008 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on ov772x driver,
8 *
9 * Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com>
10 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
11 * Copyright (C) 2008 Magnus Damm
12 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/init.h>
20#include <linux/module.h>
21#include <linux/i2c.h>
22#include <linux/slab.h>
23#include <linux/kernel.h>
24#include <linux/delay.h>
25#include <linux/videodev2.h>
26#include <media/v4l2-chip-ident.h>
979ea1dd 27#include <media/v4l2-subdev.h>
ed922a89
KM		 28#include <media/soc_camera.h>
29#include <media/tw9910.h>
30
31#define GET_ID(val) ((val & 0xF8) >> 3)
6d74e5f3 32#define GET_REV(val) (val & 0x07)
ed922a89
KM		 33
34/*
35 * register offset
36 */
37#define ID 0x00 /* Product ID Code Register */
38#define STATUS1 0x01 /* Chip Status Register I */
39#define INFORM 0x02 /* Input Format */
40#define OPFORM 0x03 /* Output Format Control Register */
41#define DLYCTR 0x04 /* Hysteresis and HSYNC Delay Control */
42#define OUTCTR1 0x05 /* Output Control I */
43#define ACNTL1 0x06 /* Analog Control Register 1 */
44#define CROP_HI 0x07 /* Cropping Register, High */
45#define VDELAY_LO 0x08 /* Vertical Delay Register, Low */
46#define VACTIVE_LO 0x09 /* Vertical Active Register, Low */
47#define HDELAY_LO 0x0A /* Horizontal Delay Register, Low */
48#define HACTIVE_LO 0x0B /* Horizontal Active Register, Low */
49#define CNTRL1 0x0C /* Control Register I */
50#define VSCALE_LO 0x0D /* Vertical Scaling Register, Low */
51#define SCALE_HI 0x0E /* Scaling Register, High */
52#define HSCALE_LO 0x0F /* Horizontal Scaling Register, Low */
53#define BRIGHT 0x10 /* BRIGHTNESS Control Register */
54#define CONTRAST 0x11 /* CONTRAST Control Register */
55#define SHARPNESS 0x12 /* SHARPNESS Control Register I */
56#define SAT_U 0x13 /* Chroma (U) Gain Register */
57#define SAT_V 0x14 /* Chroma (V) Gain Register */
58#define HUE 0x15 /* Hue Control Register */
59#define CORING1 0x17
60#define CORING2 0x18 /* Coring and IF compensation */
61#define VBICNTL 0x19 /* VBI Control Register */
62#define ACNTL2 0x1A /* Analog Control 2 */
63#define OUTCTR2 0x1B /* Output Control 2 */
64#define SDT 0x1C /* Standard Selection */
65#define SDTR 0x1D /* Standard Recognition */
66#define TEST 0x1F /* Test Control Register */
67#define CLMPG 0x20 /* Clamping Gain */
68#define IAGC 0x21 /* Individual AGC Gain */
69#define AGCGAIN 0x22 /* AGC Gain */
70#define PEAKWT 0x23 /* White Peak Threshold */
71#define CLMPL 0x24 /* Clamp level */
72#define SYNCT 0x25 /* Sync Amplitude */
73#define MISSCNT 0x26 /* Sync Miss Count Register */
74#define PCLAMP 0x27 /* Clamp Position Register */
75#define VCNTL1 0x28 /* Vertical Control I */
76#define VCNTL2 0x29 /* Vertical Control II */
77#define CKILL 0x2A /* Color Killer Level Control */
78#define COMB 0x2B /* Comb Filter Control */
79#define LDLY 0x2C /* Luma Delay and H Filter Control */
80#define MISC1 0x2D /* Miscellaneous Control I */
81#define LOOP 0x2E /* LOOP Control Register */
82#define MISC2 0x2F /* Miscellaneous Control II */
83#define MVSN 0x30 /* Macrovision Detection */
84#define STATUS2 0x31 /* Chip STATUS II */
85#define HFREF 0x32 /* H monitor */
86#define CLMD 0x33 /* CLAMP MODE */
87#define IDCNTL 0x34 /* ID Detection Control */
88#define CLCNTL1 0x35 /* Clamp Control I */
89#define ANAPLLCTL 0x4C
90#define VBIMIN 0x4D
91#define HSLOWCTL 0x4E
92#define WSS3 0x4F
93#define FILLDATA 0x50
94#define SDID 0x51
95#define DID 0x52
96#define WSS1 0x53
97#define WSS2 0x54
98#define VVBI 0x55
99#define LCTL6 0x56
100#define LCTL7 0x57
101#define LCTL8 0x58
102#define LCTL9 0x59
103#define LCTL10 0x5A
104#define LCTL11 0x5B
105#define LCTL12 0x5C
106#define LCTL13 0x5D
107#define LCTL14 0x5E
108#define LCTL15 0x5F
109#define LCTL16 0x60
110#define LCTL17 0x61
111#define LCTL18 0x62
112#define LCTL19 0x63
113#define LCTL20 0x64
114#define LCTL21 0x65
115#define LCTL22 0x66
116#define LCTL23 0x67
117#define LCTL24 0x68
118#define LCTL25 0x69
119#define LCTL26 0x6A
faa58261 120#define HSBEGIN 0x6B
ed922a89
KM		 121#define HSEND 0x6C
122#define OVSDLY 0x6D
123#define OVSEND 0x6E
124#define VBIDELAY 0x6F
125
126/*
127 * register detail
128 */
129
130/* INFORM */
131#define FC27_ON 0x40 /* 1 : Input crystal clock frequency is 27MHz */
132#define FC27_FF 0x00 /* 0 : Square pixel mode. */
133 /* Must use 24.54MHz for 60Hz field rate */
134 /* source or 29.5MHz for 50Hz field rate */
135#define IFSEL_S 0x10 /* 01 : S-video decoding */
136#define IFSEL_C 0x00 /* 00 : Composite video decoding */
137 /* Y input video selection */
138#define YSEL_M0 0x00 /* 00 : Mux0 selected */
139#define YSEL_M1 0x04 /* 01 : Mux1 selected */
140#define YSEL_M2 0x08 /* 10 : Mux2 selected */
141#define YSEL_M3 0x10 /* 11 : Mux3 selected */
142
143/* OPFORM */
144#define MODE 0x80 /* 0 : CCIR601 compatible YCrCb 4:2:2 format */
145 /* 1 : ITU-R-656 compatible data sequence format */
146#define LEN 0x40 /* 0 : 8-bit YCrCb 4:2:2 output format */
147 /* 1 : 16-bit YCrCb 4:2:2 output format.*/
148#define LLCMODE 0x20 /* 1 : LLC output mode. */
149 /* 0 : free-run output mode */
150#define AINC 0x10 /* Serial interface auto-indexing control */
151 /* 0 : auto-increment */
152 /* 1 : non-auto */
153#define VSCTL 0x08 /* 1 : Vertical out ctrl by DVALID */
154 /* 0 : Vertical out ctrl by HACTIVE and DVALID */
06f292e4
KM		 155#define OEN_TRI_SEL_MASK 0x07
156#define OEN_TRI_SEL_ALL_ON 0x00 /* Enable output for Rev0/Rev1 */
157#define OEN_TRI_SEL_ALL_OFF_r0 0x06 /* All tri-stated for Rev0 */
158#define OEN_TRI_SEL_ALL_OFF_r1 0x07 /* All tri-stated for Rev1 */
ed922a89
KM		 159
160/* OUTCTR1 */
161#define VSP_LO 0x00 /* 0 : VS pin output polarity is active low */
162#define VSP_HI 0x80 /* 1 : VS pin output polarity is active high. */
163 /* VS pin output control */
164#define VSSL_VSYNC 0x00 /* 0 : VSYNC */
165#define VSSL_VACT 0x10 /* 1 : VACT */
166#define VSSL_FIELD 0x20 /* 2 : FIELD */
167#define VSSL_VVALID 0x30 /* 3 : VVALID */
168#define VSSL_ZERO 0x70 /* 7 : 0 */
169#define HSP_LOW 0x00 /* 0 : HS pin output polarity is active low */
170#define HSP_HI 0x08 /* 1 : HS pin output polarity is active high.*/
171 /* HS pin output control */
172#define HSSL_HACT 0x00 /* 0 : HACT */
173#define HSSL_HSYNC 0x01 /* 1 : HSYNC */
174#define HSSL_DVALID 0x02 /* 2 : DVALID */
175#define HSSL_HLOCK 0x03 /* 3 : HLOCK */
176#define HSSL_ASYNCW 0x04 /* 4 : ASYNCW */
177#define HSSL_ZERO 0x07 /* 7 : 0 */
178
179/* ACNTL1 */
180#define SRESET 0x80 /* resets the device to its default state
181 * but all register content remain unchanged.
182 * This bit is self-resetting.
183 */
607e5ad8
KM		 184#define ACNTL1_PDN_MASK 0x0e
185#define CLK_PDN 0x08 /* system clock power down */
186#define Y_PDN 0x04 /* Luma ADC power down */
187#define C_PDN 0x02 /* Chroma ADC power down */
188
189/* ACNTL2 */
190#define ACNTL2_PDN_MASK 0x40
191#define PLL_PDN 0x40 /* PLL power down */
ed922a89
KM		 192
193/* VBICNTL */
5d28d525
GL		 194
195/* RTSEL : control the real time signal output from the MPOUT pin */
ed922a89
KM		 196#define RTSEL_MASK 0x07
197#define RTSEL_VLOSS 0x00 /* 0000 = Video loss */
198#define RTSEL_HLOCK 0x01 /* 0001 = H-lock */
199#define RTSEL_SLOCK 0x02 /* 0010 = S-lock */
200#define RTSEL_VLOCK 0x03 /* 0011 = V-lock */
201#define RTSEL_MONO 0x04 /* 0100 = MONO */
202#define RTSEL_DET50 0x05 /* 0101 = DET50 */
203#define RTSEL_FIELD 0x06 /* 0110 = FIELD */
204#define RTSEL_RTCO 0x07 /* 0111 = RTCO ( Real Time Control ) */
205
206/*
207 * structure
208 */
209
210struct regval_list {
211 unsigned char reg_num;
212 unsigned char value;
213};
214
215struct tw9910_scale_ctrl {
216 char *name;
217 unsigned short width;
218 unsigned short height;
219 u16 hscale;
220 u16 vscale;
221};
222
223struct tw9910_cropping_ctrl {
224 u16 vdelay;
225 u16 vactive;
226 u16 hdelay;
227 u16 hactive;
228};
229
230struct tw9910_hsync_ctrl {
231 u16 start;
232 u16 end;
233};
234
235struct tw9910_priv {
906b1018
GL		 236 struct v4l2_subdev subdev;
237 struct tw9910_video_info *info;
238 const struct tw9910_scale_ctrl *scale;
239 u32 revision;
ed922a89
KM		 240};
241
ed922a89
KM		 242static const struct tw9910_scale_ctrl tw9910_ntsc_scales[] = {
243 {
244 .name = "NTSC SQ",
245 .width = 640,
246 .height = 480,
247 .hscale = 0x0100,
248 .vscale = 0x0100,
249 },
250 {
251 .name = "NTSC CCIR601",
252 .width = 720,
253 .height = 480,
254 .hscale = 0x0100,
255 .vscale = 0x0100,
256 },
257 {
258 .name = "NTSC SQ (CIF)",
259 .width = 320,
260 .height = 240,
261 .hscale = 0x0200,
262 .vscale = 0x0200,
263 },
264 {
265 .name = "NTSC CCIR601 (CIF)",
266 .width = 360,
267 .height = 240,
268 .hscale = 0x0200,
269 .vscale = 0x0200,
270 },
271 {
272 .name = "NTSC SQ (QCIF)",
273 .width = 160,
274 .height = 120,
275 .hscale = 0x0400,
276 .vscale = 0x0400,
277 },
278 {
279 .name = "NTSC CCIR601 (QCIF)",
280 .width = 180,
281 .height = 120,
282 .hscale = 0x0400,
283 .vscale = 0x0400,
284 },
285};
286
287static const struct tw9910_scale_ctrl tw9910_pal_scales[] = {
288 {
289 .name = "PAL SQ",
290 .width = 768,
291 .height = 576,
292 .hscale = 0x0100,
293 .vscale = 0x0100,
294 },
295 {
296 .name = "PAL CCIR601",
297 .width = 720,
298 .height = 576,
299 .hscale = 0x0100,
300 .vscale = 0x0100,
301 },
302 {
303 .name = "PAL SQ (CIF)",
304 .width = 384,
305 .height = 288,
306 .hscale = 0x0200,
307 .vscale = 0x0200,
308 },
309 {
310 .name = "PAL CCIR601 (CIF)",
311 .width = 360,
312 .height = 288,
313 .hscale = 0x0200,
314 .vscale = 0x0200,
315 },
316 {
317 .name = "PAL SQ (QCIF)",
318 .width = 192,
319 .height = 144,
320 .hscale = 0x0400,
321 .vscale = 0x0400,
322 },
323 {
324 .name = "PAL CCIR601 (QCIF)",
325 .width = 180,
326 .height = 144,
327 .hscale = 0x0400,
328 .vscale = 0x0400,
329 },
330};
331
ed922a89
KM		 332static const struct tw9910_hsync_ctrl tw9910_hsync_ctrl = {
333 .start = 0x0260,
334 .end = 0x0300,
335};
336
337/*
338 * general function
339 */
979ea1dd
GL		 340static struct tw9910_priv *to_tw9910(const struct i2c_client *client)
341{
96c75399
GL		 342 return container_of(i2c_get_clientdata(client), struct tw9910_priv,
343 subdev);
979ea1dd
GL		 344}
345
20797083
KM		 346static int tw9910_mask_set(struct i2c_client *client, u8 command,
347 u8 mask, u8 set)
348{
349 s32 val = i2c_smbus_read_byte_data(client, command);
350 if (val < 0)
351 return val;
352
353 val &= ~mask;
354 val |= set & mask;
355
356 return i2c_smbus_write_byte_data(client, command, val);
357}
358
ed922a89
KM		 359static int tw9910_set_scale(struct i2c_client *client,
360 const struct tw9910_scale_ctrl *scale)
361{
362 int ret;
363
364 ret = i2c_smbus_write_byte_data(client, SCALE_HI,
365 (scale->vscale & 0x0F00) >> 4 |
366 (scale->hscale & 0x0F00) >> 8);
367 if (ret < 0)
368 return ret;
369
370 ret = i2c_smbus_write_byte_data(client, HSCALE_LO,
371 scale->hscale & 0x00FF);
372 if (ret < 0)
373 return ret;
374
375 ret = i2c_smbus_write_byte_data(client, VSCALE_LO,
376 scale->vscale & 0x00FF);
377
378 return ret;
379}
380
ed922a89
KM		 381static int tw9910_set_hsync(struct i2c_client *client,
382 const struct tw9910_hsync_ctrl *hsync)
383{
faa58261 384 struct tw9910_priv *priv = to_tw9910(client);
ed922a89
KM		 385 int ret;
386
387 /* bit 10 - 3 */
faa58261 388 ret = i2c_smbus_write_byte_data(client, HSBEGIN,
ed922a89
KM		 389 (hsync->start & 0x07F8) >> 3);
390 if (ret < 0)
391 return ret;
392
393 /* bit 10 - 3 */
394 ret = i2c_smbus_write_byte_data(client, HSEND,
395 (hsync->end & 0x07F8) >> 3);
396 if (ret < 0)
397 return ret;
398
faa58261 399 /* So far only revisions 0 and 1 have been seen */
ed922a89 400 /* bit 2 - 0 */
faa58261
KM		 401 if (1 == priv->revision)
402 ret = tw9910_mask_set(client, HSLOWCTL, 0x77,
403 (hsync->start & 0x0007) << 4 |
404 (hsync->end & 0x0007));
ed922a89
KM		 405
406 return ret;
407}
408
ed922a89
KM		 409static void tw9910_reset(struct i2c_client *client)
410{
607e5ad8 411 tw9910_mask_set(client, ACNTL1, SRESET, SRESET);
ed922a89
KM		 412 msleep(1);
413}
414
607e5ad8
KM		 415static int tw9910_power(struct i2c_client *client, int enable)
416{
417 int ret;
418 u8 acntl1;
419 u8 acntl2;
420
421 if (enable) {
422 acntl1 = 0;
423 acntl2 = 0;
424 } else {
425 acntl1 = CLK_PDN | Y_PDN | C_PDN;
426 acntl2 = PLL_PDN;
427 }
428
429 ret = tw9910_mask_set(client, ACNTL1, ACNTL1_PDN_MASK, acntl1);
430 if (ret < 0)
431 return ret;
432
433 return tw9910_mask_set(client, ACNTL2, ACNTL2_PDN_MASK, acntl2);
434}
435
ed922a89
KM		 436static const struct tw9910_scale_ctrl*
437tw9910_select_norm(struct soc_camera_device *icd, u32 width, u32 height)
438{
439 const struct tw9910_scale_ctrl *scale;
440 const struct tw9910_scale_ctrl *ret = NULL;
441 v4l2_std_id norm = icd->vdev->current_norm;
442 __u32 diff = 0xffffffff, tmp;
443 int size, i;
444
445 if (norm & V4L2_STD_NTSC) {
446 scale = tw9910_ntsc_scales;
447 size = ARRAY_SIZE(tw9910_ntsc_scales);
448 } else if (norm & V4L2_STD_PAL) {
449 scale = tw9910_pal_scales;
450 size = ARRAY_SIZE(tw9910_pal_scales);
451 } else {
452 return NULL;
453 }
454
455 for (i = 0; i < size; i++) {
456 tmp = abs(width - scale[i].width) +
457 abs(height - scale[i].height);
458 if (tmp < diff) {
459 diff = tmp;
460 ret = scale + i;
461 }
462 }
463
464 return ret;
465}
466
467/*
468 * soc_camera_ops function
469 */
979ea1dd 470static int tw9910_s_stream(struct v4l2_subdev *sd, int enable)
ed922a89 471{
c4ce6d14 472 struct i2c_client *client = v4l2_get_subdevdata(sd);
979ea1dd 473 struct tw9910_priv *priv = to_tw9910(client);
06f292e4 474 u8 val;
607e5ad8 475 int ret;
06f292e4
KM		 476
477 if (!enable) {
478 switch (priv->revision) {
479 case 0:
480 val = OEN_TRI_SEL_ALL_OFF_r0;
481 break;
482 case 1:
483 val = OEN_TRI_SEL_ALL_OFF_r1;
484 break;
485 default:
486 dev_err(&client->dev, "un-supported revision\n");
487 return -EINVAL;
488 }
489 } else {
490 val = OEN_TRI_SEL_ALL_ON;
ed922a89 491
06f292e4
KM		 492 if (!priv->scale) {
493 dev_err(&client->dev, "norm select error\n");
494 return -EPERM;
495 }
ed922a89 496
06f292e4
KM		 497 dev_dbg(&client->dev, "%s %dx%d\n",
498 priv->scale->name,
499 priv->scale->width,
500 priv->scale->height);
501 }
ed922a89 502
607e5ad8
KM		 503 ret = tw9910_mask_set(client, OPFORM, OEN_TRI_SEL_MASK, val);
504 if (ret < 0)
505 return ret;
506
507 return tw9910_power(client, enable);
ed922a89
KM		 508}
509
ed922a89
KM		 510static int tw9910_set_bus_param(struct soc_camera_device *icd,
511 unsigned long flags)
512{
398994c1 513 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
c4ce6d14 514 struct i2c_client *client = v4l2_get_subdevdata(sd);
70da92e5 515 u8 val = VSSL_VVALID | HSSL_DVALID;
398994c1
KM		 516
517 /*
518 * set OUTCTR1
70da92e5
KM		 519 *
520 * We use VVALID and DVALID signals to control VSYNC and HSYNC
521 * outputs, in this mode their polarity is inverted.
398994c1 522 */
70da92e5
KM		 523 if (flags & SOCAM_HSYNC_ACTIVE_LOW)
524 val |= HSP_HI;
525
526 if (flags & SOCAM_VSYNC_ACTIVE_LOW)
527 val |= VSP_HI;
528
529 return i2c_smbus_write_byte_data(client, OUTCTR1, val);
ed922a89
KM		 530}
531
532static unsigned long tw9910_query_bus_param(struct soc_camera_device *icd)
533{
40e2e092 534 struct i2c_client *client = to_i2c_client(to_soc_camera_control(icd));
979ea1dd 535 struct tw9910_priv *priv = to_tw9910(client);
40e2e092 536 struct soc_camera_link *icl = to_soc_camera_link(icd);
ed922a89
KM		 537 unsigned long flags = SOCAM_PCLK_SAMPLE_RISING | SOCAM_MASTER |
538 SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_HSYNC_ACTIVE_HIGH |
70da92e5 539 SOCAM_VSYNC_ACTIVE_LOW | SOCAM_HSYNC_ACTIVE_LOW |
ed922a89
KM		 540 SOCAM_DATA_ACTIVE_HIGH | priv->info->buswidth;
541
542 return soc_camera_apply_sensor_flags(icl, flags);
543}
544
979ea1dd 545static int tw9910_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
ed922a89
KM		 546{
547 int ret = -EINVAL;
548
979ea1dd 549 if (norm & (V4L2_STD_NTSC | V4L2_STD_PAL))
ed922a89
KM		 550 ret = 0;
551
552 return ret;
553}
554
979ea1dd
GL		 555static int tw9910_g_chip_ident(struct v4l2_subdev *sd,
556 struct v4l2_dbg_chip_ident *id)
557{
c4ce6d14 558 struct i2c_client *client = v4l2_get_subdevdata(sd);
6d74e5f3
KM		 559 struct tw9910_priv *priv = to_tw9910(client);
560
979ea1dd 561 id->ident = V4L2_IDENT_TW9910;
6d74e5f3 562 id->revision = priv->revision;
979ea1dd
GL		 563
564 return 0;
565}
566
ed922a89 567#ifdef CONFIG_VIDEO_ADV_DEBUG
979ea1dd
GL		 568static int tw9910_g_register(struct v4l2_subdev *sd,
569 struct v4l2_dbg_register *reg)
ed922a89 570{
c4ce6d14 571 struct i2c_client *client = v4l2_get_subdevdata(sd);
ed922a89
KM		 572 int ret;
573
574 if (reg->reg > 0xff)
575 return -EINVAL;
576
40e2e092 577 ret = i2c_smbus_read_byte_data(client, reg->reg);
ed922a89
KM		 578 if (ret < 0)
579 return ret;
580
5d28d525
GL		 581 /*
582 * ret = int
ed922a89
KM		 583 * reg->val = __u64
584 */
585 reg->val = (__u64)ret;
586
587 return 0;
588}
589
979ea1dd
GL		 590static int tw9910_s_register(struct v4l2_subdev *sd,
591 struct v4l2_dbg_register *reg)
ed922a89 592{
c4ce6d14 593 struct i2c_client *client = v4l2_get_subdevdata(sd);
ed922a89
KM		 594
595 if (reg->reg > 0xff ||
596 reg->val > 0xff)
597 return -EINVAL;
598
40e2e092 599 return i2c_smbus_write_byte_data(client, reg->reg, reg->val);
ed922a89
KM		 600}
601#endif
602
08590b96 603static int tw9910_s_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
ed922a89 604{
08590b96 605 struct v4l2_rect *rect = &a->c;
c4ce6d14 606 struct i2c_client *client = v4l2_get_subdevdata(sd);
979ea1dd 607 struct tw9910_priv *priv = to_tw9910(client);
08590b96 608 struct soc_camera_device *icd = client->dev.platform_data;
ed922a89
KM		 609 int ret = -EINVAL;
610 u8 val;
611
612 /*
613 * select suitable norm
614 */
615 priv->scale = tw9910_select_norm(icd, rect->width, rect->height);
616 if (!priv->scale)
6d756112 617 goto tw9910_set_fmt_error;
ed922a89
KM		 618
619 /*
620 * reset hardware
621 */
40e2e092 622 tw9910_reset(client);
6d756112 623
ed922a89
KM		 624 /*
625 * set bus width
626 */
627 val = 0x00;
628 if (SOCAM_DATAWIDTH_16 == priv->info->buswidth)
629 val = LEN;
630
40e2e092 631 ret = tw9910_mask_set(client, OPFORM, LEN, val);
ed922a89 632 if (ret < 0)
6d756112 633 goto tw9910_set_fmt_error;
ed922a89
KM		 634
635 /*
636 * select MPOUT behavior
637 */
638 switch (priv->info->mpout) {
639 case TW9910_MPO_VLOSS:
640 val = RTSEL_VLOSS; break;
641 case TW9910_MPO_HLOCK:
642 val = RTSEL_HLOCK; break;
643 case TW9910_MPO_SLOCK:
644 val = RTSEL_SLOCK; break;
645 case TW9910_MPO_VLOCK:
646 val = RTSEL_VLOCK; break;
647 case TW9910_MPO_MONO:
648 val = RTSEL_MONO; break;
649 case TW9910_MPO_DET50:
650 val = RTSEL_DET50; break;
651 case TW9910_MPO_FIELD:
652 val = RTSEL_FIELD; break;
653 case TW9910_MPO_RTCO:
654 val = RTSEL_RTCO; break;
655 default:
656 val = 0;
657 }
658
40e2e092 659 ret = tw9910_mask_set(client, VBICNTL, RTSEL_MASK, val);
ed922a89 660 if (ret < 0)
6d756112 661 goto tw9910_set_fmt_error;
ed922a89
KM		 662
663 /*
664 * set scale
665 */
40e2e092 666 ret = tw9910_set_scale(client, priv->scale);
ed922a89 667 if (ret < 0)
6d756112 668 goto tw9910_set_fmt_error;
ed922a89 669
ed922a89
KM		 670 /*
671 * set hsync
672 */
40e2e092 673 ret = tw9910_set_hsync(client, &tw9910_hsync_ctrl);
6d756112
KM		 674 if (ret < 0)
675 goto tw9910_set_fmt_error;
676
123ab622
GL		 677 rect->width = priv->scale->width;
678 rect->height = priv->scale->height;
679 rect->left = 0;
680 rect->top = 0;
681
6d756112
KM		 682 return ret;
683
684tw9910_set_fmt_error:
685
40e2e092 686 tw9910_reset(client);
6d756112 687 priv->scale = NULL;
ed922a89
KM		 688
689 return ret;
690}
691
6a6c8786
GL		 692static int tw9910_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
693{
c4ce6d14 694 struct i2c_client *client = v4l2_get_subdevdata(sd);
6a6c8786
GL		 695 struct tw9910_priv *priv = to_tw9910(client);
696
697 if (!priv->scale) {
698 int ret;
699 struct v4l2_crop crop = {
700 .c = {
701 .left = 0,
702 .top = 0,
703 .width = 640,
704 .height = 480,
705 },
706 };
707 ret = tw9910_s_crop(sd, &crop);
708 if (ret < 0)
709 return ret;
710 }
711
712 a->c.left = 0;
713 a->c.top = 0;
714 a->c.width = priv->scale->width;
715 a->c.height = priv->scale->height;
716 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
717
718 return 0;
719}
720
721static int tw9910_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
722{
723 a->bounds.left = 0;
724 a->bounds.top = 0;
725 a->bounds.width = 768;
726 a->bounds.height = 576;
727 a->defrect.left = 0;
728 a->defrect.top = 0;
729 a->defrect.width = 640;
730 a->defrect.height = 480;
731 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
732 a->pixelaspect.numerator = 1;
733 a->pixelaspect.denominator = 1;
734
735 return 0;
736}
737
760697be
GL		 738static int tw9910_g_fmt(struct v4l2_subdev *sd,
739 struct v4l2_mbus_framefmt *mf)
6a6c8786 740{
c4ce6d14 741 struct i2c_client *client = v4l2_get_subdevdata(sd);
6a6c8786 742 struct tw9910_priv *priv = to_tw9910(client);
6a6c8786
GL		 743
744 if (!priv->scale) {
745 int ret;
746 struct v4l2_crop crop = {
747 .c = {
748 .left = 0,
749 .top = 0,
750 .width = 640,
751 .height = 480,
752 },
753 };
754 ret = tw9910_s_crop(sd, &crop);
755 if (ret < 0)
756 return ret;
757 }
758
760697be
GL		 759 mf->width = priv->scale->width;
760 mf->height = priv->scale->height;
ace6e979 761 mf->code = V4L2_MBUS_FMT_UYVY8_2X8;
760697be 762 mf->colorspace = V4L2_COLORSPACE_JPEG;
34cae30b 763 mf->field = V4L2_FIELD_INTERLACED_BT;
6a6c8786
GL		 764
765 return 0;
766}
767
760697be
GL		 768static int tw9910_s_fmt(struct v4l2_subdev *sd,
769 struct v4l2_mbus_framefmt *mf)
09e231b3 770{
c4ce6d14 771 struct i2c_client *client = v4l2_get_subdevdata(sd);
6a6c8786 772 struct tw9910_priv *priv = to_tw9910(client);
08590b96
GL		 773 /* See tw9910_s_crop() - no proper cropping support */
774 struct v4l2_crop a = {
775 .c = {
776 .left = 0,
777 .top = 0,
760697be
GL		 778 .width = mf->width,
779 .height = mf->height,
08590b96 780 },
09e231b3 781 };
760697be
GL		 782 int ret;
783
784 WARN_ON(mf->field != V4L2_FIELD_ANY &&
34cae30b 785 mf->field != V4L2_FIELD_INTERLACED_BT);
09e231b3
GL		 786
787 /*
788 * check color format
789 */
ace6e979 790 if (mf->code != V4L2_MBUS_FMT_UYVY8_2X8)
09e231b3
GL		 791 return -EINVAL;
792
760697be
GL		 793 mf->colorspace = V4L2_COLORSPACE_JPEG;
794
08590b96 795 ret = tw9910_s_crop(sd, &a);
123ab622 796 if (!ret) {
760697be
GL		 797 mf->width = priv->scale->width;
798 mf->height = priv->scale->height;
123ab622
GL		 799 }
800 return ret;
09e231b3
GL		 801}
802
760697be
GL		 803static int tw9910_try_fmt(struct v4l2_subdev *sd,
804 struct v4l2_mbus_framefmt *mf)
ed922a89 805{
c4ce6d14 806 struct i2c_client *client = v4l2_get_subdevdata(sd);
979ea1dd 807 struct soc_camera_device *icd = client->dev.platform_data;
ed922a89
KM		 808 const struct tw9910_scale_ctrl *scale;
809
760697be 810 if (V4L2_FIELD_ANY == mf->field) {
34cae30b
KM		 811 mf->field = V4L2_FIELD_INTERLACED_BT;
812 } else if (V4L2_FIELD_INTERLACED_BT != mf->field) {
760697be 813 dev_err(&client->dev, "Field type %d invalid.\n", mf->field);
ed922a89
KM		 814 return -EINVAL;
815 }
816
ace6e979 817 mf->code = V4L2_MBUS_FMT_UYVY8_2X8;
760697be
GL		 818 mf->colorspace = V4L2_COLORSPACE_JPEG;
819
ed922a89
KM		 820 /*
821 * select suitable norm
822 */
760697be 823 scale = tw9910_select_norm(icd, mf->width, mf->height);
ed922a89
KM		 824 if (!scale)
825 return -EINVAL;
826
760697be
GL		 827 mf->width = scale->width;
828 mf->height = scale->height;
ed922a89
KM		 829
830 return 0;
831}
832
40e2e092
GL		 833static int tw9910_video_probe(struct soc_camera_device *icd,
834 struct i2c_client *client)
ed922a89 835{
979ea1dd 836 struct tw9910_priv *priv = to_tw9910(client);
88a67c51 837 s32 id;
ed922a89 838
7dfff953
GL		 839 /* We must have a parent by now. And it cannot be a wrong one. */
840 BUG_ON(!icd->parent ||
841 to_soc_camera_host(icd->parent)->nr != icd->iface);
ed922a89
KM		 842
843 /*
844 * tw9910 only use 8 or 16 bit bus width
845 */
846 if (SOCAM_DATAWIDTH_16 != priv->info->buswidth &&
847 SOCAM_DATAWIDTH_8 != priv->info->buswidth) {
85f8be68 848 dev_err(&client->dev, "bus width error\n");
ed922a89
KM		 849 return -ENODEV;
850 }
851
ed922a89
KM		 852 /*
853 * check and show Product ID
4a4bc5e4 854 * So far only revisions 0 and 1 have been seen
ed922a89 855 */
88a67c51
KM		 856 id = i2c_smbus_read_byte_data(client, ID);
857 priv->revision = GET_REV(id);
858 id = GET_ID(id);
40e2e092 859
88a67c51 860 if (0x0B != id ||
6d74e5f3 861 0x01 < priv->revision) {
85f8be68 862 dev_err(&client->dev,
6d74e5f3 863 "Product ID error %x:%x\n",
88a67c51 864 id, priv->revision);
ed922a89
KM		 865 return -ENODEV;
866 }
867
85f8be68 868 dev_info(&client->dev,
88a67c51 869 "tw9910 Product ID %0x:%0x\n", id, priv->revision);
ed922a89 870
ed922a89
KM		 871 icd->vdev->tvnorms = V4L2_STD_NTSC | V4L2_STD_PAL;
872 icd->vdev->current_norm = V4L2_STD_NTSC;
873
979ea1dd 874 return 0;
ed922a89
KM		 875}
876
ed922a89 877static struct soc_camera_ops tw9910_ops = {
ed922a89
KM		 878 .set_bus_param = tw9910_set_bus_param,
879 .query_bus_param = tw9910_query_bus_param,
979ea1dd
GL		 880};
881
882static struct v4l2_subdev_core_ops tw9910_subdev_core_ops = {
883 .g_chip_ident = tw9910_g_chip_ident,
884 .s_std = tw9910_s_std,
ed922a89 885#ifdef CONFIG_VIDEO_ADV_DEBUG
979ea1dd
GL		 886 .g_register = tw9910_g_register,
887 .s_register = tw9910_s_register,
ed922a89
KM		 888#endif
889};
890
3805f201 891static int tw9910_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
760697be
GL		 892 enum v4l2_mbus_pixelcode *code)
893{
894 if (index)
895 return -EINVAL;
896
ace6e979 897 *code = V4L2_MBUS_FMT_UYVY8_2X8;
760697be
GL		 898 return 0;
899}
900
979ea1dd
GL		 901static struct v4l2_subdev_video_ops tw9910_subdev_video_ops = {
902 .s_stream = tw9910_s_stream,
760697be
GL		 903 .g_mbus_fmt = tw9910_g_fmt,
904 .s_mbus_fmt = tw9910_s_fmt,
905 .try_mbus_fmt = tw9910_try_fmt,
6a6c8786
GL		 906 .cropcap = tw9910_cropcap,
907 .g_crop = tw9910_g_crop,
08590b96 908 .s_crop = tw9910_s_crop,
760697be 909 .enum_mbus_fmt = tw9910_enum_fmt,
979ea1dd
GL		 910};
911
912static struct v4l2_subdev_ops tw9910_subdev_ops = {
913 .core = &tw9910_subdev_core_ops,
914 .video = &tw9910_subdev_video_ops,
915};
916
ed922a89
KM		 917/*
918 * i2c_driver function
919 */
920
921static int tw9910_probe(struct i2c_client *client,
922 const struct i2c_device_id *did)
923
924{
925 struct tw9910_priv *priv;
926 struct tw9910_video_info *info;
40e2e092
GL		 927 struct soc_camera_device *icd = client->dev.platform_data;
928 struct i2c_adapter *adapter =
929 to_i2c_adapter(client->dev.parent);
930 struct soc_camera_link *icl;
6a6c8786 931 int ret;
ed922a89 932
40e2e092
GL		 933 if (!icd) {
934 dev_err(&client->dev, "TW9910: missing soc-camera data!\n");
ed922a89 935 return -EINVAL;
40e2e092 936 }
ed922a89 937
40e2e092 938 icl = to_soc_camera_link(icd);
0f448294 939 if (!icl || !icl->priv)
40e2e092 940 return -EINVAL;
0a861e9e 941
0f448294 942 info = icl->priv;
40e2e092
GL		 943
944 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
ed922a89
KM		 945 dev_err(&client->dev,
946 "I2C-Adapter doesn't support "
947 "I2C_FUNC_SMBUS_BYTE_DATA\n");
948 return -EIO;
949 }
950
951 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
952 if (!priv)
953 return -ENOMEM;
954
955 priv->info = info;
979ea1dd
GL		 956
957 v4l2_i2c_subdev_init(&priv->subdev, client, &tw9910_subdev_ops);
ed922a89 958
ed922a89 959 icd->ops = &tw9910_ops;
0f448294 960 icd->iface = icl->bus_id;
ed922a89 961
40e2e092 962 ret = tw9910_video_probe(icd, client);
ed922a89 963 if (ret) {
40e2e092 964 icd->ops = NULL;
ed922a89
KM		 965 kfree(priv);
966 }
967
968 return ret;
969}
970
971static int tw9910_remove(struct i2c_client *client)
972{
979ea1dd 973 struct tw9910_priv *priv = to_tw9910(client);
40e2e092 974 struct soc_camera_device *icd = client->dev.platform_data;
ed922a89 975
40e2e092 976 icd->ops = NULL;
ed922a89
KM		 977 kfree(priv);
978 return 0;
979}
980
981static const struct i2c_device_id tw9910_id[] = {
982 { "tw9910", 0 },
983 { }
984};
985MODULE_DEVICE_TABLE(i2c, tw9910_id);
986
987static struct i2c_driver tw9910_i2c_driver = {
988 .driver = {
989 .name = "tw9910",
990 },
991 .probe = tw9910_probe,
992 .remove = tw9910_remove,
993 .id_table = tw9910_id,
994};
995
996/*
997 * module function
998 */
999static int __init tw9910_module_init(void)
1000{
1001 return i2c_add_driver(&tw9910_i2c_driver);
1002}
1003
1004static void __exit tw9910_module_exit(void)
1005{
1006 i2c_del_driver(&tw9910_i2c_driver);
1007}
1008
1009module_init(tw9910_module_init);
1010module_exit(tw9910_module_exit);
1011
1012MODULE_DESCRIPTION("SoC Camera driver for tw9910");
1013MODULE_AUTHOR("Kuninori Morimoto");
1014MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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