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a8aabb91 PD |
1 | /* |
2 | * Copyright (c) 2015 Samsung Electronics Co., Ltd. | |
3 | * http://www.samsung.com/ | |
4 | * | |
5 | * EXYNOS - SROM Controller support | |
6 | * Author: Pankaj Dubey <pankaj.dubey@samsung.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/io.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/of.h> | |
16 | #include <linux/of_address.h> | |
8ac2266d | 17 | #include <linux/of_platform.h> |
a8aabb91 PD |
18 | #include <linux/platform_device.h> |
19 | #include <linux/slab.h> | |
20 | ||
21 | #include "exynos-srom.h" | |
22 | ||
23 | static const unsigned long exynos_srom_offsets[] = { | |
24 | /* SROM side */ | |
25 | EXYNOS_SROM_BW, | |
26 | EXYNOS_SROM_BC0, | |
27 | EXYNOS_SROM_BC1, | |
28 | EXYNOS_SROM_BC2, | |
29 | EXYNOS_SROM_BC3, | |
30 | }; | |
31 | ||
32 | /** | |
33 | * struct exynos_srom_reg_dump: register dump of SROM Controller registers. | |
34 | * @offset: srom register offset from the controller base address. | |
35 | * @value: the value of register under the offset. | |
36 | */ | |
37 | struct exynos_srom_reg_dump { | |
38 | u32 offset; | |
39 | u32 value; | |
40 | }; | |
41 | ||
42 | /** | |
43 | * struct exynos_srom: platform data for exynos srom controller driver. | |
44 | * @dev: platform device pointer | |
45 | * @reg_base: srom base address | |
46 | * @reg_offset: exynos_srom_reg_dump pointer to hold offset and its value. | |
47 | */ | |
48 | struct exynos_srom { | |
49 | struct device *dev; | |
50 | void __iomem *reg_base; | |
51 | struct exynos_srom_reg_dump *reg_offset; | |
52 | }; | |
53 | ||
54 | static struct exynos_srom_reg_dump *exynos_srom_alloc_reg_dump( | |
55 | const unsigned long *rdump, | |
56 | unsigned long nr_rdump) | |
57 | { | |
58 | struct exynos_srom_reg_dump *rd; | |
59 | unsigned int i; | |
60 | ||
61 | rd = kcalloc(nr_rdump, sizeof(*rd), GFP_KERNEL); | |
62 | if (!rd) | |
63 | return NULL; | |
64 | ||
65 | for (i = 0; i < nr_rdump; ++i) | |
66 | rd[i].offset = rdump[i]; | |
67 | ||
68 | return rd; | |
69 | } | |
70 | ||
8ac2266d PF |
71 | static int exynos_srom_configure_bank(struct exynos_srom *srom, |
72 | struct device_node *np) | |
73 | { | |
74 | u32 bank, width, pmc = 0; | |
75 | u32 timing[6]; | |
76 | u32 cs, bw; | |
77 | ||
78 | if (of_property_read_u32(np, "reg", &bank)) | |
79 | return -EINVAL; | |
80 | if (of_property_read_u32(np, "reg-io-width", &width)) | |
81 | width = 1; | |
82 | if (of_property_read_bool(np, "samsung,srom-page-mode")) | |
83 | pmc = 1 << EXYNOS_SROM_BCX__PMC__SHIFT; | |
84 | if (of_property_read_u32_array(np, "samsung,srom-timing", timing, | |
85 | ARRAY_SIZE(timing))) | |
86 | return -EINVAL; | |
87 | ||
88 | bank *= 4; /* Convert bank into shift/offset */ | |
89 | ||
90 | cs = 1 << EXYNOS_SROM_BW__BYTEENABLE__SHIFT; | |
91 | if (width == 2) | |
92 | cs |= 1 << EXYNOS_SROM_BW__DATAWIDTH__SHIFT; | |
93 | ||
cbf73175 | 94 | bw = readl_relaxed(srom->reg_base + EXYNOS_SROM_BW); |
8ac2266d | 95 | bw = (bw & ~(EXYNOS_SROM_BW__CS_MASK << bank)) | (cs << bank); |
cbf73175 BD |
96 | writel_relaxed(bw, srom->reg_base + EXYNOS_SROM_BW); |
97 | ||
98 | writel_relaxed(pmc | (timing[0] << EXYNOS_SROM_BCX__TACP__SHIFT) | | |
99 | (timing[1] << EXYNOS_SROM_BCX__TCAH__SHIFT) | | |
100 | (timing[2] << EXYNOS_SROM_BCX__TCOH__SHIFT) | | |
101 | (timing[3] << EXYNOS_SROM_BCX__TACC__SHIFT) | | |
102 | (timing[4] << EXYNOS_SROM_BCX__TCOS__SHIFT) | | |
103 | (timing[5] << EXYNOS_SROM_BCX__TACS__SHIFT), | |
104 | srom->reg_base + EXYNOS_SROM_BC0 + bank); | |
8ac2266d PF |
105 | |
106 | return 0; | |
107 | } | |
108 | ||
a8aabb91 PD |
109 | static int exynos_srom_probe(struct platform_device *pdev) |
110 | { | |
8ac2266d | 111 | struct device_node *np, *child; |
a8aabb91 PD |
112 | struct exynos_srom *srom; |
113 | struct device *dev = &pdev->dev; | |
8ac2266d | 114 | bool bad_bank_config = false; |
a8aabb91 PD |
115 | |
116 | np = dev->of_node; | |
117 | if (!np) { | |
118 | dev_err(&pdev->dev, "could not find device info\n"); | |
119 | return -EINVAL; | |
120 | } | |
121 | ||
122 | srom = devm_kzalloc(&pdev->dev, | |
123 | sizeof(struct exynos_srom), GFP_KERNEL); | |
124 | if (!srom) | |
125 | return -ENOMEM; | |
126 | ||
127 | srom->dev = dev; | |
128 | srom->reg_base = of_iomap(np, 0); | |
129 | if (!srom->reg_base) { | |
130 | dev_err(&pdev->dev, "iomap of exynos srom controller failed\n"); | |
131 | return -ENOMEM; | |
132 | } | |
133 | ||
134 | platform_set_drvdata(pdev, srom); | |
135 | ||
136 | srom->reg_offset = exynos_srom_alloc_reg_dump(exynos_srom_offsets, | |
137 | sizeof(exynos_srom_offsets)); | |
138 | if (!srom->reg_offset) { | |
139 | iounmap(srom->reg_base); | |
140 | return -ENOMEM; | |
141 | } | |
142 | ||
8ac2266d PF |
143 | for_each_child_of_node(np, child) { |
144 | if (exynos_srom_configure_bank(srom, child)) { | |
145 | dev_err(dev, | |
146 | "Could not decode bank configuration for %s\n", | |
147 | child->name); | |
148 | bad_bank_config = true; | |
149 | } | |
150 | } | |
151 | ||
152 | /* | |
153 | * If any bank failed to configure, we still provide suspend/resume, | |
154 | * but do not probe child devices | |
155 | */ | |
156 | if (bad_bank_config) | |
157 | return 0; | |
158 | ||
159 | return of_platform_populate(np, NULL, NULL, dev); | |
a8aabb91 PD |
160 | } |
161 | ||
162 | static int exynos_srom_remove(struct platform_device *pdev) | |
163 | { | |
164 | struct exynos_srom *srom = platform_get_drvdata(pdev); | |
165 | ||
166 | kfree(srom->reg_offset); | |
167 | iounmap(srom->reg_base); | |
168 | ||
169 | return 0; | |
170 | } | |
171 | ||
172 | #ifdef CONFIG_PM_SLEEP | |
173 | static void exynos_srom_save(void __iomem *base, | |
174 | struct exynos_srom_reg_dump *rd, | |
175 | unsigned int num_regs) | |
176 | { | |
177 | for (; num_regs > 0; --num_regs, ++rd) | |
178 | rd->value = readl(base + rd->offset); | |
179 | } | |
180 | ||
181 | static void exynos_srom_restore(void __iomem *base, | |
182 | const struct exynos_srom_reg_dump *rd, | |
183 | unsigned int num_regs) | |
184 | { | |
185 | for (; num_regs > 0; --num_regs, ++rd) | |
186 | writel(rd->value, base + rd->offset); | |
187 | } | |
188 | ||
189 | static int exynos_srom_suspend(struct device *dev) | |
190 | { | |
191 | struct exynos_srom *srom = dev_get_drvdata(dev); | |
192 | ||
193 | exynos_srom_save(srom->reg_base, srom->reg_offset, | |
194 | ARRAY_SIZE(exynos_srom_offsets)); | |
195 | return 0; | |
196 | } | |
197 | ||
198 | static int exynos_srom_resume(struct device *dev) | |
199 | { | |
200 | struct exynos_srom *srom = dev_get_drvdata(dev); | |
201 | ||
202 | exynos_srom_restore(srom->reg_base, srom->reg_offset, | |
203 | ARRAY_SIZE(exynos_srom_offsets)); | |
204 | return 0; | |
205 | } | |
206 | #endif | |
207 | ||
208 | static const struct of_device_id of_exynos_srom_ids[] = { | |
209 | { | |
210 | .compatible = "samsung,exynos4210-srom", | |
211 | }, | |
212 | {}, | |
213 | }; | |
214 | MODULE_DEVICE_TABLE(of, of_exynos_srom_ids); | |
215 | ||
216 | static SIMPLE_DEV_PM_OPS(exynos_srom_pm_ops, exynos_srom_suspend, exynos_srom_resume); | |
217 | ||
218 | static struct platform_driver exynos_srom_driver = { | |
219 | .probe = exynos_srom_probe, | |
220 | .remove = exynos_srom_remove, | |
221 | .driver = { | |
222 | .name = "exynos-srom", | |
223 | .of_match_table = of_exynos_srom_ids, | |
224 | .pm = &exynos_srom_pm_ops, | |
225 | }, | |
226 | }; | |
227 | module_platform_driver(exynos_srom_driver); | |
228 | ||
229 | MODULE_AUTHOR("Pankaj Dubey <pankaj.dubey@samsung.com>"); | |
230 | MODULE_DESCRIPTION("Exynos SROM Controller Driver"); | |
231 | MODULE_LICENSE("GPL"); |