[deliverable/linux.git] / drivers / memory / tegra / tegra114.c

/*
 * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/of.h>
#include <linux/mm.h>

#include <asm/cacheflush.h>

#include <dt-bindings/memory/tegra114-mc.h>

#include "mc.h"

static const struct tegra_mc_client tegra114_mc_clients[] = {
	{
		.id = 0x00,
		.name = "ptcr",
		.swgroup = TEGRA_SWGROUP_PTC,
	}, {
		.id = 0x01,
		.name = "display0a",
		.swgroup = TEGRA_SWGROUP_DC,
		.smmu = {
			.reg = 0x228,
			.bit = 1,
		},
		.la = {
			.reg = 0x2e8,
			.shift = 0,
			.mask = 0xff,
			.def = 0x4e,
		},
	}, {
		.id = 0x02,
		.name = "display0ab",
		.swgroup = TEGRA_SWGROUP_DCB,
		.smmu = {
			.reg = 0x228,
			.bit = 2,
		},
		.la = {
			.reg = 0x2f4,
			.shift = 0,
			.mask = 0xff,
			.def = 0x4e,
		},
	}, {
		.id = 0x03,
		.name = "display0b",
		.swgroup = TEGRA_SWGROUP_DC,
		.smmu = {
			.reg = 0x228,
			.bit = 3,
		},
		.la = {
			.reg = 0x2e8,
			.shift = 16,
			.mask = 0xff,
			.def = 0x4e,
		},
	}, {
		.id = 0x04,
		.name = "display0bb",
		.swgroup = TEGRA_SWGROUP_DCB,
		.smmu = {
			.reg = 0x228,
			.bit = 4,
		},
		.la = {
			.reg = 0x2f4,
			.shift = 16,
			.mask = 0xff,
			.def = 0x4e,
		},
	}, {
		.id = 0x05,
		.name = "display0c",
		.swgroup = TEGRA_SWGROUP_DC,
		.smmu = {
			.reg = 0x228,
			.bit = 5,
		},
		.la = {
			.reg = 0x2ec,
			.shift = 0,
			.mask = 0xff,
			.def = 0x4e,
		},
	}, {
		.id = 0x06,
		.name = "display0cb",
		.swgroup = TEGRA_SWGROUP_DCB,
		.smmu = {
			.reg = 0x228,
			.bit = 6,
		},
		.la = {
			.reg = 0x2f8,
			.shift = 0,
			.mask = 0xff,
			.def = 0x4e,
		},
	}, {
		.id = 0x09,
		.name = "eppup",
		.swgroup = TEGRA_SWGROUP_EPP,
		.smmu = {
			.reg = 0x228,
			.bit = 9,
		},
		.la = {
			.reg = 0x300,
			.shift = 0,
			.mask = 0xff,
			.def = 0x33,
		},
	}, {
		.id = 0x0a,
		.name = "g2pr",
		.swgroup = TEGRA_SWGROUP_G2,
		.smmu = {
			.reg = 0x228,
			.bit = 10,
		},
		.la = {
			.reg = 0x308,
			.shift = 0,
			.mask = 0xff,
			.def = 0x09,
		},
	}, {
		.id = 0x0b,
		.name = "g2sr",
		.swgroup = TEGRA_SWGROUP_G2,
		.smmu = {
			.reg = 0x228,
			.bit = 11,
		},
		.la = {
			.reg = 0x308,
			.shift = 16,
			.mask = 0xff,
			.def = 0x09,
		},
	}, {
		.id = 0x0f,
		.name = "avpcarm7r",
		.swgroup = TEGRA_SWGROUP_AVPC,
		.smmu = {
			.reg = 0x228,
			.bit = 15,
		},
		.la = {
			.reg = 0x2e4,
			.shift = 0,
			.mask = 0xff,
			.def = 0x04,
		},
	}, {
		.id = 0x10,
		.name = "displayhc",
		.swgroup = TEGRA_SWGROUP_DC,
		.smmu = {
			.reg = 0x228,
			.bit = 16,
		},
		.la = {
			.reg = 0x2f0,
			.shift = 0,
			.mask = 0xff,
			.def = 0x68,
		},
	}, {
		.id = 0x11,
		.name = "displayhcb",
		.swgroup = TEGRA_SWGROUP_DCB,
		.smmu = {
			.reg = 0x228,
			.bit = 17,
		},
		.la = {
			.reg = 0x2fc,
			.shift = 0,
			.mask = 0xff,
			.def = 0x68,
		},
	}, {
		.id = 0x12,
		.name = "fdcdrd",
		.swgroup = TEGRA_SWGROUP_NV,
		.smmu = {
			.reg = 0x228,
			.bit = 18,
		},
		.la = {
			.reg = 0x334,
			.shift = 0,
			.mask = 0xff,
			.def = 0x0c,
		},
	}, {
		.id = 0x13,
		.name = "fdcdrd2",
		.swgroup = TEGRA_SWGROUP_NV,
		.smmu = {
			.reg = 0x228,
			.bit = 19,
		},
		.la = {
			.reg = 0x33c,
			.shift = 0,
			.mask = 0xff,
			.def = 0x0c,
		},
	}, {
		.id = 0x14,
		.name = "g2dr",
		.swgroup = TEGRA_SWGROUP_G2,
		.smmu = {
			.reg = 0x228,
			.bit = 20,
		},
		.la = {
			.reg = 0x30c,
			.shift = 0,
			.mask = 0xff,
			.def = 0x0a,
		},
	}, {
		.id = 0x15,
		.name = "hdar",
		.swgroup = TEGRA_SWGROUP_HDA,
		.smmu = {
			.reg = 0x228,
			.bit = 21,
		},
		.la = {
			.reg = 0x318,
			.shift = 0,
			.mask = 0xff,
			.def = 0xff,
		},
	}, {
		.id = 0x16,
		.name = "host1xdmar",
		.swgroup = TEGRA_SWGROUP_HC,
		.smmu = {
			.reg = 0x228,
			.bit = 22,
		},
		.la = {
			.reg = 0x310,
			.shift = 0,
			.mask = 0xff,
			.def = 0x10,
		},
	}, {
		.id = 0x17,
		.name = "host1xr",
		.swgroup = TEGRA_SWGROUP_HC,
		.smmu = {
			.reg = 0x228,
			.bit = 23,
		},
		.la = {
			.reg = 0x310,
			.shift = 16,
			.mask = 0xff,
			.def = 0xa5,
		},
	}, {
		.id = 0x18,
		.name = "idxsrd",
		.swgroup = TEGRA_SWGROUP_NV,
		.smmu = {
			.reg = 0x228,
			.bit = 24,
		},
		.la = {
			.reg = 0x334,
			.shift = 16,
			.mask = 0xff,
			.def = 0x0b,
		},
	}, {
		.id = 0x1c,
		.name = "msencsrd",
		.swgroup = TEGRA_SWGROUP_MSENC,
		.smmu = {
			.reg = 0x228,
			.bit = 28,
		},
		.la = {
			.reg = 0x328,
			.shift = 0,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x1d,
		.name = "ppcsahbdmar",
		.swgroup = TEGRA_SWGROUP_PPCS,
		.smmu = {
			.reg = 0x228,
			.bit = 29,
		},
		.la = {
			.reg = 0x344,
			.shift = 0,
			.mask = 0xff,
			.def = 0x50,
		},
	}, {
		.id = 0x1e,
		.name = "ppcsahbslvr",
		.swgroup = TEGRA_SWGROUP_PPCS,
		.smmu = {
			.reg = 0x228,
			.bit = 30,
		},
		.la = {
			.reg = 0x344,
			.shift = 16,
			.mask = 0xff,
			.def = 0xe8,
		},
	}, {
		.id = 0x20,
		.name = "texl2srd",
		.swgroup = TEGRA_SWGROUP_NV,
		.smmu = {
			.reg = 0x22c,
			.bit = 0,
		},
		.la = {
			.reg = 0x338,
			.shift = 0,
			.mask = 0xff,
			.def = 0x0c,
		},
	}, {
		.id = 0x22,
		.name = "vdebsevr",
		.swgroup = TEGRA_SWGROUP_VDE,
		.smmu = {
			.reg = 0x22c,
			.bit = 2,
		},
		.la = {
			.reg = 0x354,
			.shift = 0,
			.mask = 0xff,
			.def = 0xff,
		},
	}, {
		.id = 0x23,
		.name = "vdember",
		.swgroup = TEGRA_SWGROUP_VDE,
		.smmu = {
			.reg = 0x22c,
			.bit = 3,
		},
		.la = {
			.reg = 0x354,
			.shift = 16,
			.mask = 0xff,
			.def = 0xff,
		},
	}, {
		.id = 0x24,
		.name = "vdemcer",
		.swgroup = TEGRA_SWGROUP_VDE,
		.smmu = {
			.reg = 0x22c,
			.bit = 4,
		},
		.la = {
			.reg = 0x358,
			.shift = 0,
			.mask = 0xff,
			.def = 0xb8,
		},
	}, {
		.id = 0x25,
		.name = "vdetper",
		.swgroup = TEGRA_SWGROUP_VDE,
		.smmu = {
			.reg = 0x22c,
			.bit = 5,
		},
		.la = {
			.reg = 0x358,
			.shift = 16,
			.mask = 0xff,
			.def = 0xee,
		},
	}, {
		.id = 0x26,
		.name = "mpcorelpr",
		.swgroup = TEGRA_SWGROUP_MPCORELP,
		.la = {
			.reg = 0x324,
			.shift = 0,
			.mask = 0xff,
			.def = 0x04,
		},
	}, {
		.id = 0x27,
		.name = "mpcorer",
		.swgroup = TEGRA_SWGROUP_MPCORE,
		.la = {
			.reg = 0x320,
			.shift = 0,
			.mask = 0xff,
			.def = 0x04,
		},
	}, {
		.id = 0x28,
		.name = "eppu",
		.swgroup = TEGRA_SWGROUP_EPP,
		.smmu = {
			.reg = 0x22c,
			.bit = 8,
		},
		.la = {
			.reg = 0x300,
			.shift = 16,
			.mask = 0xff,
			.def = 0x33,
		},
	}, {
		.id = 0x29,
		.name = "eppv",
		.swgroup = TEGRA_SWGROUP_EPP,
		.smmu = {
			.reg = 0x22c,
			.bit = 9,
		},
		.la = {
			.reg = 0x304,
			.shift = 0,
			.mask = 0xff,
			.def = 0x6c,
		},
	}, {
		.id = 0x2a,
		.name = "eppy",
		.swgroup = TEGRA_SWGROUP_EPP,
		.smmu = {
			.reg = 0x22c,
			.bit = 10,
		},
		.la = {
			.reg = 0x304,
			.shift = 16,
			.mask = 0xff,
			.def = 0x6c,
		},
	}, {
		.id = 0x2b,
		.name = "msencswr",
		.swgroup = TEGRA_SWGROUP_MSENC,
		.smmu = {
			.reg = 0x22c,
			.bit = 11,
		},
		.la = {
			.reg = 0x328,
			.shift = 16,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x2c,
		.name = "viwsb",
		.swgroup = TEGRA_SWGROUP_VI,
		.smmu = {
			.reg = 0x22c,
			.bit = 12,
		},
		.la = {
			.reg = 0x364,
			.shift = 0,
			.mask = 0xff,
			.def = 0x47,
		},
	}, {
		.id = 0x2d,
		.name = "viwu",
		.swgroup = TEGRA_SWGROUP_VI,
		.smmu = {
			.reg = 0x22c,
			.bit = 13,
		},
		.la = {
			.reg = 0x368,
			.shift = 0,
			.mask = 0xff,
			.def = 0xff,
		},
	}, {
		.id = 0x2e,
		.name = "viwv",
		.swgroup = TEGRA_SWGROUP_VI,
		.smmu = {
			.reg = 0x22c,
			.bit = 14,
		},
		.la = {
			.reg = 0x368,
			.shift = 16,
			.mask = 0xff,
			.def = 0xff,
		},
	}, {
		.id = 0x2f,
		.name = "viwy",
		.swgroup = TEGRA_SWGROUP_VI,
		.smmu = {
			.reg = 0x22c,
			.bit = 15,
		},
		.la = {
			.reg = 0x36c,
			.shift = 0,
			.mask = 0xff,
			.def = 0x47,
		},
	}, {
		.id = 0x30,
		.name = "g2dw",
		.swgroup = TEGRA_SWGROUP_G2,
		.smmu = {
			.reg = 0x22c,
			.bit = 16,
		},
		.la = {
			.reg = 0x30c,
			.shift = 16,
			.mask = 0xff,
			.def = 0x9,
		},
	}, {
		.id = 0x32,
		.name = "avpcarm7w",
		.swgroup = TEGRA_SWGROUP_AVPC,
		.smmu = {
			.reg = 0x22c,
			.bit = 18,
		},
		.la = {
			.reg = 0x2e4,
			.shift = 16,
			.mask = 0xff,
			.def = 0x0e,
		},
	}, {
		.id = 0x33,
		.name = "fdcdwr",
		.swgroup = TEGRA_SWGROUP_NV,
		.smmu = {
			.reg = 0x22c,
			.bit = 19,
		},
		.la = {
			.reg = 0x338,
			.shift = 16,
			.mask = 0xff,
			.def = 0x10,
		},
	}, {
		.id = 0x34,
		.name = "fdcwr2",
		.swgroup = TEGRA_SWGROUP_NV,
		.smmu = {
			.reg = 0x22c,
			.bit = 20,
		},
		.la = {
			.reg = 0x340,
			.shift = 0,
			.mask = 0xff,
			.def = 0x10,
		},
	}, {
		.id = 0x35,
		.name = "hdaw",
		.swgroup = TEGRA_SWGROUP_HDA,
		.smmu = {
			.reg = 0x22c,
			.bit = 21,
		},
		.la = {
			.reg = 0x318,
			.shift = 16,
			.mask = 0xff,
			.def = 0xff,
		},
	}, {
		.id = 0x36,
		.name = "host1xw",
		.swgroup = TEGRA_SWGROUP_HC,
		.smmu = {
			.reg = 0x22c,
			.bit = 22,
		},
		.la = {
			.reg = 0x314,
			.shift = 0,
			.mask = 0xff,
			.def = 0x25,
		},
	}, {
		.id = 0x37,
		.name = "ispw",
		.swgroup = TEGRA_SWGROUP_ISP,
		.smmu = {
			.reg = 0x22c,
			.bit = 23,
		},
		.la = {
			.reg = 0x31c,
			.shift = 0,
			.mask = 0xff,
			.def = 0xff,
		},
	}, {
		.id = 0x38,
		.name = "mpcorelpw",
		.swgroup = TEGRA_SWGROUP_MPCORELP,
		.la = {
			.reg = 0x324,
			.shift = 16,
			.mask = 0xff,
			.def = 0x80,
		},
	}, {
		.id = 0x39,
		.name = "mpcorew",
		.swgroup = TEGRA_SWGROUP_MPCORE,
		.la = {
			.reg = 0x320,
			.shift = 16,
			.mask = 0xff,
			.def = 0x0e,
		},
	}, {
		.id = 0x3b,
		.name = "ppcsahbdmaw",
		.swgroup = TEGRA_SWGROUP_PPCS,
		.smmu = {
			.reg = 0x22c,
			.bit = 27,
		},
		.la = {
			.reg = 0x348,
			.shift = 0,
			.mask = 0xff,
			.def = 0xa5,
		},
	}, {
		.id = 0x3c,
		.name = "ppcsahbslvw",
		.swgroup = TEGRA_SWGROUP_PPCS,
		.smmu = {
			.reg = 0x22c,
			.bit = 28,
		},
		.la = {
			.reg = 0x348,
			.shift = 16,
			.mask = 0xff,
			.def = 0xe8,
		},
	}, {
		.id = 0x3e,
		.name = "vdebsevw",
		.swgroup = TEGRA_SWGROUP_VDE,
		.smmu = {
			.reg = 0x22c,
			.bit = 30,
		},
		.la = {
			.reg = 0x35c,
			.shift = 0,
			.mask = 0xff,
			.def = 0xff,
		},
	}, {
		.id = 0x3f,
		.name = "vdedbgw",
		.swgroup = TEGRA_SWGROUP_VDE,
		.smmu = {
			.reg = 0x22c,
			.bit = 31,
		},
		.la = {
			.reg = 0x35c,
			.shift = 16,
			.mask = 0xff,
			.def = 0xff,
		},
	}, {
		.id = 0x40,
		.name = "vdembew",
		.swgroup = TEGRA_SWGROUP_VDE,
		.smmu = {
			.reg = 0x230,
			.bit = 0,
		},
		.la = {
			.reg = 0x360,
			.shift = 0,
			.mask = 0xff,
			.def = 0x89,
		},
	}, {
		.id = 0x41,
		.name = "vdetpmw",
		.swgroup = TEGRA_SWGROUP_VDE,
		.smmu = {
			.reg = 0x230,
			.bit = 1,
		},
		.la = {
			.reg = 0x360,
			.shift = 16,
			.mask = 0xff,
			.def = 0x59,
		},
	}, {
		.id = 0x4a,
		.name = "xusb_hostr",
		.swgroup = TEGRA_SWGROUP_XUSB_HOST,
		.smmu = {
			.reg = 0x230,
			.bit = 10,
		},
		.la = {
			.reg = 0x37c,
			.shift = 0,
			.mask = 0xff,
			.def = 0xa5,
		},
	}, {
		.id = 0x4b,
		.name = "xusb_hostw",
		.swgroup = TEGRA_SWGROUP_XUSB_HOST,
		.smmu = {
			.reg = 0x230,
			.bit = 11,
		},
		.la = {
			.reg = 0x37c,
			.shift = 16,
			.mask = 0xff,
			.def = 0xa5,
		},
	}, {
		.id = 0x4c,
		.name = "xusb_devr",
		.swgroup = TEGRA_SWGROUP_XUSB_DEV,
		.smmu = {
			.reg = 0x230,
			.bit = 12,
		},
		.la = {
			.reg = 0x380,
			.shift = 0,
			.mask = 0xff,
			.def = 0xa5,
		},
	}, {
		.id = 0x4d,
		.name = "xusb_devw",
		.swgroup = TEGRA_SWGROUP_XUSB_DEV,
		.smmu = {
			.reg = 0x230,
			.bit = 13,
		},
		.la = {
			.reg = 0x380,
			.shift = 16,
			.mask = 0xff,
			.def = 0xa5,
		},
	}, {
		.id = 0x4e,
		.name = "fdcdwr3",
		.swgroup = TEGRA_SWGROUP_NV,
		.smmu = {
			.reg = 0x230,
			.bit = 14,
		},
		.la = {
			.reg = 0x388,
			.shift = 0,
			.mask = 0xff,
			.def = 0x10,
		},
	}, {
		.id = 0x4f,
		.name = "fdcdrd3",
		.swgroup = TEGRA_SWGROUP_NV,
		.smmu = {
			.reg = 0x230,
			.bit = 15,
		},
		.la = {
			.reg = 0x384,
			.shift = 0,
			.mask = 0xff,
			.def = 0x0c,
		},
	}, {
		.id = 0x50,
		.name = "fdcwr4",
		.swgroup = TEGRA_SWGROUP_NV,
		.smmu = {
			.reg = 0x230,
			.bit = 16,
		},
		.la = {
			.reg = 0x388,
			.shift = 16,
			.mask = 0xff,
			.def = 0x10,
		},
	}, {
		.id = 0x51,
		.name = "fdcrd4",
		.swgroup = TEGRA_SWGROUP_NV,
		.smmu = {
			.reg = 0x230,
			.bit = 17,
		},
		.la = {
			.reg = 0x384,
			.shift = 16,
			.mask = 0xff,
			.def = 0x0c,
		},
	}, {
		.id = 0x52,
		.name = "emucifr",
		.swgroup = TEGRA_SWGROUP_EMUCIF,
		.la = {
			.reg = 0x38c,
			.shift = 0,
			.mask = 0xff,
			.def = 0x04,
		},
	}, {
		.id = 0x53,
		.name = "emucifw",
		.swgroup = TEGRA_SWGROUP_EMUCIF,
		.la = {
			.reg = 0x38c,
			.shift = 16,
			.mask = 0xff,
			.def = 0x0e,
		},
	}, {
		.id = 0x54,
		.name = "tsecsrd",
		.swgroup = TEGRA_SWGROUP_TSEC,
		.smmu = {
			.reg = 0x230,
			.bit = 20,
		},
		.la = {
			.reg = 0x390,
			.shift = 0,
			.mask = 0xff,
			.def = 0x50,
		},
	}, {
		.id = 0x55,
		.name = "tsecswr",
		.swgroup = TEGRA_SWGROUP_TSEC,
		.smmu = {
			.reg = 0x230,
			.bit = 21,
		},
		.la = {
			.reg = 0x390,
			.shift = 16,
			.mask = 0xff,
			.def = 0x50,
		},
	},
};

static const struct tegra_smmu_swgroup tegra114_swgroups[] = {
	{ .swgroup = TEGRA_SWGROUP_DC,        .reg = 0x240 },
	{ .swgroup = TEGRA_SWGROUP_DCB,       .reg = 0x244 },
	{ .swgroup = TEGRA_SWGROUP_EPP,       .reg = 0x248 },
	{ .swgroup = TEGRA_SWGROUP_G2,        .reg = 0x24c },
	{ .swgroup = TEGRA_SWGROUP_AVPC,      .reg = 0x23c },
	{ .swgroup = TEGRA_SWGROUP_NV,        .reg = 0x268 },
	{ .swgroup = TEGRA_SWGROUP_HDA,       .reg = 0x254 },
	{ .swgroup = TEGRA_SWGROUP_HC,        .reg = 0x250 },
	{ .swgroup = TEGRA_SWGROUP_MSENC,     .reg = 0x264 },
	{ .swgroup = TEGRA_SWGROUP_PPCS,      .reg = 0x270 },
	{ .swgroup = TEGRA_SWGROUP_VDE,       .reg = 0x27c },
	{ .swgroup = TEGRA_SWGROUP_VI,        .reg = 0x280 },
	{ .swgroup = TEGRA_SWGROUP_ISP,       .reg = 0x258 },
	{ .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
	{ .swgroup = TEGRA_SWGROUP_XUSB_DEV,  .reg = 0x28c },
	{ .swgroup = TEGRA_SWGROUP_TSEC,      .reg = 0x294 },
};

static void tegra114_flush_dcache(struct page *page, unsigned long offset,
				  size_t size)
{
	phys_addr_t phys = page_to_phys(page) + offset;
	void *virt = page_address(page) + offset;

	__cpuc_flush_dcache_area(virt, size);
	outer_flush_range(phys, phys + size);
}

static const struct tegra_smmu_ops tegra114_smmu_ops = {
	.flush_dcache = tegra114_flush_dcache,
};

static const struct tegra_smmu_soc tegra114_smmu_soc = {
	.clients = tegra114_mc_clients,
	.num_clients = ARRAY_SIZE(tegra114_mc_clients),
	.swgroups = tegra114_swgroups,
	.num_swgroups = ARRAY_SIZE(tegra114_swgroups),
	.supports_round_robin_arbitration = false,
	.supports_request_limit = false,
	.num_asids = 4,
	.ops = &tegra114_smmu_ops,
};

const struct tegra_mc_soc tegra114_mc_soc = {
	.clients = tegra114_mc_clients,
	.num_clients = ARRAY_SIZE(tegra114_mc_clients),
	.num_address_bits = 32,
	.atom_size = 32,
	.smmu = &tegra114_smmu_soc,
};
Commit	Line	Data
89184651 TR	1	/*
	2	* Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8
	9	#include <linux/of.h>
	10	#include <linux/mm.h>
	11
	12	#include <asm/cacheflush.h>
	13
	14	#include <dt-bindings/memory/tegra114-mc.h>
	15
	16	#include "mc.h"
	17
	18	static const struct tegra_mc_client tegra114_mc_clients[] = {
	19	{
	20	.id = 0x00,
	21	.name = "ptcr",
	22	.swgroup = TEGRA_SWGROUP_PTC,
	23	}, {
	24	.id = 0x01,
	25	.name = "display0a",
	26	.swgroup = TEGRA_SWGROUP_DC,
	27	.smmu = {
	28	.reg = 0x228,
	29	.bit = 1,
	30	},
	31	.la = {
	32	.reg = 0x2e8,
	33	.shift = 0,
	34	.mask = 0xff,
	35	.def = 0x4e,
	36	},
	37	}, {
	38	.id = 0x02,
	39	.name = "display0ab",
	40	.swgroup = TEGRA_SWGROUP_DCB,
	41	.smmu = {
	42	.reg = 0x228,
	43	.bit = 2,
	44	},
	45	.la = {
	46	.reg = 0x2f4,
	47	.shift = 0,
	48	.mask = 0xff,
	49	.def = 0x4e,
	50	},
	51	}, {
	52	.id = 0x03,
	53	.name = "display0b",
	54	.swgroup = TEGRA_SWGROUP_DC,
	55	.smmu = {
	56	.reg = 0x228,
	57	.bit = 3,
	58	},
	59	.la = {
	60	.reg = 0x2e8,
	61	.shift = 16,
	62	.mask = 0xff,
	63	.def = 0x4e,
	64	},
65	}, {
66	.id = 0x04,
67	.name = "display0bb",
68	.swgroup = TEGRA_SWGROUP_DCB,
69	.smmu = {
70	.reg = 0x228,
71	.bit = 4,
72	},
73	.la = {
74	.reg = 0x2f4,
75	.shift = 16,
76	.mask = 0xff,
77	.def = 0x4e,
78	},
79	}, {
80	.id = 0x05,
81	.name = "display0c",
82	.swgroup = TEGRA_SWGROUP_DC,
83	.smmu = {
84	.reg = 0x228,
85	.bit = 5,
86	},
87	.la = {
88	.reg = 0x2ec,
89	.shift = 0,
90	.mask = 0xff,
91	.def = 0x4e,
92	},
93	}, {
94	.id = 0x06,
95	.name = "display0cb",
96	.swgroup = TEGRA_SWGROUP_DCB,
97	.smmu = {
98	.reg = 0x228,
99	.bit = 6,
100	},
101	.la = {
102	.reg = 0x2f8,
103	.shift = 0,
104	.mask = 0xff,
105	.def = 0x4e,
106	},
107	}, {
108	.id = 0x09,
109	.name = "eppup",
110	.swgroup = TEGRA_SWGROUP_EPP,
111	.smmu = {
112	.reg = 0x228,
113	.bit = 9,
114	},
115	.la = {
116	.reg = 0x300,
117	.shift = 0,
118	.mask = 0xff,
119	.def = 0x33,
120	},
121	}, {
122	.id = 0x0a,
123	.name = "g2pr",
124	.swgroup = TEGRA_SWGROUP_G2,
125	.smmu = {
126	.reg = 0x228,
127	.bit = 10,
128	},
129	.la = {
130	.reg = 0x308,
131	.shift = 0,
132	.mask = 0xff,
133	.def = 0x09,
134	},
135	}, {
136	.id = 0x0b,
137	.name = "g2sr",
138	.swgroup = TEGRA_SWGROUP_G2,
139	.smmu = {
140	.reg = 0x228,
141	.bit = 11,
142	},
143	.la = {
144	.reg = 0x308,
145	.shift = 16,
146	.mask = 0xff,
147	.def = 0x09,
148	},
149	}, {
150	.id = 0x0f,
151	.name = "avpcarm7r",
152	.swgroup = TEGRA_SWGROUP_AVPC,
153	.smmu = {
154	.reg = 0x228,
155	.bit = 15,
156	},
157	.la = {
158	.reg = 0x2e4,
159	.shift = 0,
160	.mask = 0xff,
161	.def = 0x04,
162	},
163	}, {
164	.id = 0x10,
165	.name = "displayhc",
166	.swgroup = TEGRA_SWGROUP_DC,
167	.smmu = {
168	.reg = 0x228,
169	.bit = 16,
170	},
171	.la = {
172	.reg = 0x2f0,
173	.shift = 0,
174	.mask = 0xff,
175	.def = 0x68,
176	},
177	}, {
178	.id = 0x11,
179	.name = "displayhcb",
180	.swgroup = TEGRA_SWGROUP_DCB,
181	.smmu = {
182	.reg = 0x228,
183	.bit = 17,
184	},
185	.la = {
186	.reg = 0x2fc,
187	.shift = 0,
188	.mask = 0xff,
189	.def = 0x68,
190	},
191	}, {
192	.id = 0x12,
193	.name = "fdcdrd",
194	.swgroup = TEGRA_SWGROUP_NV,
195	.smmu = {
196	.reg = 0x228,
197	.bit = 18,
198	},
199	.la = {
200	.reg = 0x334,
201	.shift = 0,
202	.mask = 0xff,
203	.def = 0x0c,
204	},
205	}, {
206	.id = 0x13,
207	.name = "fdcdrd2",
208	.swgroup = TEGRA_SWGROUP_NV,
209	.smmu = {
210	.reg = 0x228,
211	.bit = 19,
212	},
213	.la = {
214	.reg = 0x33c,
215	.shift = 0,
216	.mask = 0xff,
217	.def = 0x0c,
218	},
219	}, {
220	.id = 0x14,
221	.name = "g2dr",
222	.swgroup = TEGRA_SWGROUP_G2,
223	.smmu = {
224	.reg = 0x228,
225	.bit = 20,
226	},
227	.la = {
228	.reg = 0x30c,
229	.shift = 0,
230	.mask = 0xff,
231	.def = 0x0a,
232	},
233	}, {
234	.id = 0x15,
235	.name = "hdar",
236	.swgroup = TEGRA_SWGROUP_HDA,
237	.smmu = {
238	.reg = 0x228,
239	.bit = 21,
240	},
241	.la = {
242	.reg = 0x318,
243	.shift = 0,
244	.mask = 0xff,
245	.def = 0xff,
246	},
247	}, {
248	.id = 0x16,
249	.name = "host1xdmar",
250	.swgroup = TEGRA_SWGROUP_HC,
251	.smmu = {
252	.reg = 0x228,
253	.bit = 22,
254	},
255	.la = {
256	.reg = 0x310,
257	.shift = 0,
258	.mask = 0xff,
259	.def = 0x10,
260	},
261	}, {
262	.id = 0x17,
263	.name = "host1xr",
264	.swgroup = TEGRA_SWGROUP_HC,
265	.smmu = {
266	.reg = 0x228,
267	.bit = 23,
268	},
269	.la = {
270	.reg = 0x310,
271	.shift = 16,
272	.mask = 0xff,
273	.def = 0xa5,
274	},
275	}, {
276	.id = 0x18,
277	.name = "idxsrd",
278	.swgroup = TEGRA_SWGROUP_NV,
279	.smmu = {
280	.reg = 0x228,
281	.bit = 24,
282	},
283	.la = {
284	.reg = 0x334,
285	.shift = 16,
286	.mask = 0xff,
287	.def = 0x0b,
288	},
289	}, {
290	.id = 0x1c,
291	.name = "msencsrd",
292	.swgroup = TEGRA_SWGROUP_MSENC,
293	.smmu = {
294	.reg = 0x228,
295	.bit = 28,
296	},
297	.la = {
298	.reg = 0x328,
299	.shift = 0,
300	.mask = 0xff,
301	.def = 0x80,
302	},
303	}, {
304	.id = 0x1d,
305	.name = "ppcsahbdmar",
306	.swgroup = TEGRA_SWGROUP_PPCS,
307	.smmu = {
308	.reg = 0x228,
309	.bit = 29,
310	},
311	.la = {
312	.reg = 0x344,
313	.shift = 0,
314	.mask = 0xff,
315	.def = 0x50,
316	},
317	}, {
318	.id = 0x1e,
319	.name = "ppcsahbslvr",
320	.swgroup = TEGRA_SWGROUP_PPCS,
321	.smmu = {
322	.reg = 0x228,
323	.bit = 30,
324	},
325	.la = {
326	.reg = 0x344,
327	.shift = 16,
328	.mask = 0xff,
329	.def = 0xe8,
330	},
331	}, {
332	.id = 0x20,
333	.name = "texl2srd",
334	.swgroup = TEGRA_SWGROUP_NV,
335	.smmu = {
336	.reg = 0x22c,
337	.bit = 0,
338	},
339	.la = {
340	.reg = 0x338,
341	.shift = 0,
342	.mask = 0xff,
343	.def = 0x0c,
344	},
345	}, {
346	.id = 0x22,
347	.name = "vdebsevr",
348	.swgroup = TEGRA_SWGROUP_VDE,
349	.smmu = {
350	.reg = 0x22c,
351	.bit = 2,
352	},
353	.la = {
354	.reg = 0x354,
355	.shift = 0,
356	.mask = 0xff,
357	.def = 0xff,
358	},
359	}, {
360	.id = 0x23,
361	.name = "vdember",
362	.swgroup = TEGRA_SWGROUP_VDE,
363	.smmu = {
364	.reg = 0x22c,
365	.bit = 3,
366	},
367	.la = {
368	.reg = 0x354,
369	.shift = 16,
370	.mask = 0xff,
371	.def = 0xff,
372	},
373	}, {
374	.id = 0x24,
375	.name = "vdemcer",
376	.swgroup = TEGRA_SWGROUP_VDE,
377	.smmu = {
378	.reg = 0x22c,
379	.bit = 4,
380	},
381	.la = {
382	.reg = 0x358,
383	.shift = 0,
384	.mask = 0xff,
385	.def = 0xb8,
386	},
387	}, {
388	.id = 0x25,
389	.name = "vdetper",
390	.swgroup = TEGRA_SWGROUP_VDE,
391	.smmu = {
392	.reg = 0x22c,
393	.bit = 5,
394	},
395	.la = {
396	.reg = 0x358,
397	.shift = 16,
398	.mask = 0xff,
399	.def = 0xee,
400	},
401	}, {
402	.id = 0x26,
403	.name = "mpcorelpr",
404	.swgroup = TEGRA_SWGROUP_MPCORELP,
405	.la = {
406	.reg = 0x324,
407	.shift = 0,
408	.mask = 0xff,
409	.def = 0x04,
410	},
411	}, {
412	.id = 0x27,
413	.name = "mpcorer",
414	.swgroup = TEGRA_SWGROUP_MPCORE,
415	.la = {
416	.reg = 0x320,
417	.shift = 0,
418	.mask = 0xff,
419	.def = 0x04,
420	},
421	}, {
422	.id = 0x28,
423	.name = "eppu",
424	.swgroup = TEGRA_SWGROUP_EPP,
425	.smmu = {
426	.reg = 0x22c,
427	.bit = 8,
428	},
429	.la = {
430	.reg = 0x300,
431	.shift = 16,
432	.mask = 0xff,
433	.def = 0x33,
434	},
435	}, {
436	.id = 0x29,
437	.name = "eppv",
438	.swgroup = TEGRA_SWGROUP_EPP,
439	.smmu = {
440	.reg = 0x22c,
441	.bit = 9,
442	},
443	.la = {
444	.reg = 0x304,
445	.shift = 0,
446	.mask = 0xff,
447	.def = 0x6c,
448	},
449	}, {
450	.id = 0x2a,
451	.name = "eppy",
452	.swgroup = TEGRA_SWGROUP_EPP,
453	.smmu = {
454	.reg = 0x22c,
455	.bit = 10,
456	},
457	.la = {
458	.reg = 0x304,
459	.shift = 16,
460	.mask = 0xff,
461	.def = 0x6c,
462	},
463	}, {
464	.id = 0x2b,
465	.name = "msencswr",
466	.swgroup = TEGRA_SWGROUP_MSENC,
467	.smmu = {
468	.reg = 0x22c,
469	.bit = 11,
470	},
471	.la = {
472	.reg = 0x328,
473	.shift = 16,
474	.mask = 0xff,
475	.def = 0x80,
476	},
477	}, {
478	.id = 0x2c,
479	.name = "viwsb",
480	.swgroup = TEGRA_SWGROUP_VI,
481	.smmu = {
482	.reg = 0x22c,
483	.bit = 12,
484	},
485	.la = {
486	.reg = 0x364,
487	.shift = 0,
488	.mask = 0xff,
489	.def = 0x47,
490	},
491	}, {
492	.id = 0x2d,
493	.name = "viwu",
494	.swgroup = TEGRA_SWGROUP_VI,
495	.smmu = {
496	.reg = 0x22c,
497	.bit = 13,
498	},
499	.la = {
500	.reg = 0x368,
501	.shift = 0,
502	.mask = 0xff,
503	.def = 0xff,
504	},
505	}, {
506	.id = 0x2e,
507	.name = "viwv",
508	.swgroup = TEGRA_SWGROUP_VI,
509	.smmu = {
510	.reg = 0x22c,
511	.bit = 14,
512	},
513	.la = {
514	.reg = 0x368,
515	.shift = 16,
516	.mask = 0xff,
517	.def = 0xff,
518	},
519	}, {
520	.id = 0x2f,
521	.name = "viwy",
522	.swgroup = TEGRA_SWGROUP_VI,
523	.smmu = {
524	.reg = 0x22c,
525	.bit = 15,
526	},
527	.la = {
528	.reg = 0x36c,
529	.shift = 0,
530	.mask = 0xff,
531	.def = 0x47,
532	},
533	}, {
534	.id = 0x30,
535	.name = "g2dw",
536	.swgroup = TEGRA_SWGROUP_G2,
537	.smmu = {
538	.reg = 0x22c,
539	.bit = 16,
540	},
541	.la = {
542	.reg = 0x30c,
543	.shift = 16,
544	.mask = 0xff,
545	.def = 0x9,
546	},
547	}, {
548	.id = 0x32,
549	.name = "avpcarm7w",
550	.swgroup = TEGRA_SWGROUP_AVPC,
551	.smmu = {
552	.reg = 0x22c,
553	.bit = 18,
554	},
555	.la = {
556	.reg = 0x2e4,
557	.shift = 16,
558	.mask = 0xff,
559	.def = 0x0e,
560	},
561	}, {
562	.id = 0x33,
563	.name = "fdcdwr",
564	.swgroup = TEGRA_SWGROUP_NV,
565	.smmu = {
566	.reg = 0x22c,
567	.bit = 19,
568	},
569	.la = {
570	.reg = 0x338,
571	.shift = 16,
572	.mask = 0xff,
573	.def = 0x10,
574	},
575	}, {
576	.id = 0x34,
577	.name = "fdcwr2",
578	.swgroup = TEGRA_SWGROUP_NV,
579	.smmu = {
580	.reg = 0x22c,
581	.bit = 20,
582	},
583	.la = {
584	.reg = 0x340,
585	.shift = 0,
586	.mask = 0xff,
587	.def = 0x10,
588	},
589	}, {
590	.id = 0x35,
591	.name = "hdaw",
592	.swgroup = TEGRA_SWGROUP_HDA,
593	.smmu = {
594	.reg = 0x22c,
595	.bit = 21,
596	},
597	.la = {
598	.reg = 0x318,
599	.shift = 16,
600	.mask = 0xff,
601	.def = 0xff,
602	},
603	}, {
604	.id = 0x36,
605	.name = "host1xw",
606	.swgroup = TEGRA_SWGROUP_HC,
607	.smmu = {
608	.reg = 0x22c,
609	.bit = 22,
610	},
611	.la = {
612	.reg = 0x314,
613	.shift = 0,
614	.mask = 0xff,
615	.def = 0x25,
616	},
617	}, {
618	.id = 0x37,
619	.name = "ispw",
620	.swgroup = TEGRA_SWGROUP_ISP,
621	.smmu = {
622	.reg = 0x22c,
623	.bit = 23,
624	},
625	.la = {
626	.reg = 0x31c,
627	.shift = 0,
628	.mask = 0xff,
629	.def = 0xff,
630	},
631	}, {
632	.id = 0x38,
633	.name = "mpcorelpw",
634	.swgroup = TEGRA_SWGROUP_MPCORELP,
635	.la = {
636	.reg = 0x324,
637	.shift = 16,
638	.mask = 0xff,
639	.def = 0x80,
640	},
641	}, {
642	.id = 0x39,
643	.name = "mpcorew",
644	.swgroup = TEGRA_SWGROUP_MPCORE,
645	.la = {
646	.reg = 0x320,
647	.shift = 16,
648	.mask = 0xff,
649	.def = 0x0e,
650	},
651	}, {
652	.id = 0x3b,
653	.name = "ppcsahbdmaw",
654	.swgroup = TEGRA_SWGROUP_PPCS,
655	.smmu = {
656	.reg = 0x22c,
657	.bit = 27,
658	},
659	.la = {
660	.reg = 0x348,
661	.shift = 0,
662	.mask = 0xff,
663	.def = 0xa5,
664	},
665	}, {
666	.id = 0x3c,
667	.name = "ppcsahbslvw",
668	.swgroup = TEGRA_SWGROUP_PPCS,
669	.smmu = {
670	.reg = 0x22c,
671	.bit = 28,
672	},
673	.la = {
674	.reg = 0x348,
675	.shift = 16,
676	.mask = 0xff,
677	.def = 0xe8,
678	},
679	}, {
680	.id = 0x3e,
681	.name = "vdebsevw",
682	.swgroup = TEGRA_SWGROUP_VDE,
683	.smmu = {
684	.reg = 0x22c,
685	.bit = 30,
686	},
687	.la = {
688	.reg = 0x35c,
689	.shift = 0,
690	.mask = 0xff,
691	.def = 0xff,
692	},
693	}, {
694	.id = 0x3f,
695	.name = "vdedbgw",
696	.swgroup = TEGRA_SWGROUP_VDE,
697	.smmu = {
698	.reg = 0x22c,
699	.bit = 31,
700	},
701	.la = {
702	.reg = 0x35c,
703	.shift = 16,
704	.mask = 0xff,
705	.def = 0xff,
706	},
707	}, {
708	.id = 0x40,
709	.name = "vdembew",
710	.swgroup = TEGRA_SWGROUP_VDE,
711	.smmu = {
712	.reg = 0x230,
713	.bit = 0,
714	},
715	.la = {
716	.reg = 0x360,
717	.shift = 0,
718	.mask = 0xff,
719	.def = 0x89,
720	},
721	}, {
722	.id = 0x41,
723	.name = "vdetpmw",
724	.swgroup = TEGRA_SWGROUP_VDE,
725	.smmu = {
726	.reg = 0x230,
727	.bit = 1,
728	},
729	.la = {
730	.reg = 0x360,
731	.shift = 16,
732	.mask = 0xff,
733	.def = 0x59,
734	},
735	}, {
736	.id = 0x4a,
737	.name = "xusb_hostr",
738	.swgroup = TEGRA_SWGROUP_XUSB_HOST,
739	.smmu = {
740	.reg = 0x230,
741	.bit = 10,
742	},
743	.la = {
744	.reg = 0x37c,
745	.shift = 0,
746	.mask = 0xff,
747	.def = 0xa5,
748	},
749	}, {
750	.id = 0x4b,
751	.name = "xusb_hostw",
752	.swgroup = TEGRA_SWGROUP_XUSB_HOST,
753	.smmu = {
754	.reg = 0x230,
755	.bit = 11,
756	},
757	.la = {
758	.reg = 0x37c,
759	.shift = 16,
760	.mask = 0xff,
761	.def = 0xa5,
762	},
763	}, {
764	.id = 0x4c,
765	.name = "xusb_devr",
766	.swgroup = TEGRA_SWGROUP_XUSB_DEV,
767	.smmu = {
768	.reg = 0x230,
769	.bit = 12,
770	},
771	.la = {
772	.reg = 0x380,
773	.shift = 0,
774	.mask = 0xff,
775	.def = 0xa5,
776	},
777	}, {
778	.id = 0x4d,
779	.name = "xusb_devw",
780	.swgroup = TEGRA_SWGROUP_XUSB_DEV,
781	.smmu = {
782	.reg = 0x230,
783	.bit = 13,
784	},
785	.la = {
786	.reg = 0x380,
787	.shift = 16,
788	.mask = 0xff,
789	.def = 0xa5,
790	},
791	}, {
792	.id = 0x4e,
793	.name = "fdcdwr3",
794	.swgroup = TEGRA_SWGROUP_NV,
795	.smmu = {
796	.reg = 0x230,
797	.bit = 14,
798	},
799	.la = {
800	.reg = 0x388,
801	.shift = 0,
802	.mask = 0xff,
803	.def = 0x10,
804	},
805	}, {
806	.id = 0x4f,
807	.name = "fdcdrd3",
808	.swgroup = TEGRA_SWGROUP_NV,
809	.smmu = {
810	.reg = 0x230,
811	.bit = 15,
812	},
813	.la = {
814	.reg = 0x384,
815	.shift = 0,
816	.mask = 0xff,
817	.def = 0x0c,
818	},
819	}, {
820	.id = 0x50,
821	.name = "fdcwr4",
822	.swgroup = TEGRA_SWGROUP_NV,
823	.smmu = {
824	.reg = 0x230,
825	.bit = 16,
826	},
827	.la = {
828	.reg = 0x388,
829	.shift = 16,
830	.mask = 0xff,
831	.def = 0x10,
832	},
833	}, {
834	.id = 0x51,
835	.name = "fdcrd4",
836	.swgroup = TEGRA_SWGROUP_NV,
837	.smmu = {
838	.reg = 0x230,
839	.bit = 17,
840	},
841	.la = {
842	.reg = 0x384,
843	.shift = 16,
844	.mask = 0xff,
845	.def = 0x0c,
846	},
847	}, {
848	.id = 0x52,
849	.name = "emucifr",
850	.swgroup = TEGRA_SWGROUP_EMUCIF,
851	.la = {
852	.reg = 0x38c,
853	.shift = 0,
854	.mask = 0xff,
855	.def = 0x04,
856	},
857	}, {
858	.id = 0x53,
859	.name = "emucifw",
860	.swgroup = TEGRA_SWGROUP_EMUCIF,
861	.la = {
862	.reg = 0x38c,
863	.shift = 16,
864	.mask = 0xff,
865	.def = 0x0e,
866	},
867	}, {
868	.id = 0x54,
869	.name = "tsecsrd",
870	.swgroup = TEGRA_SWGROUP_TSEC,
871	.smmu = {
872	.reg = 0x230,
873	.bit = 20,
874	},
875	.la = {
876	.reg = 0x390,
877	.shift = 0,
878	.mask = 0xff,
879	.def = 0x50,
880	},
881	}, {
882	.id = 0x55,
883	.name = "tsecswr",
884	.swgroup = TEGRA_SWGROUP_TSEC,
885	.smmu = {
886	.reg = 0x230,
887	.bit = 21,
888	},
889	.la = {
890	.reg = 0x390,
891	.shift = 16,
892	.mask = 0xff,
893	.def = 0x50,
894	},
895	},
896	};
897
898	static const struct tegra_smmu_swgroup tegra114_swgroups[] = {
899	{ .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
900	{ .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
901	{ .swgroup = TEGRA_SWGROUP_EPP, .reg = 0x248 },
902	{ .swgroup = TEGRA_SWGROUP_G2, .reg = 0x24c },
903	{ .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
904	{ .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
905	{ .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
906	{ .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
907	{ .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
908	{ .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
909	{ .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
910	{ .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
911	{ .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
912	{ .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
913	{ .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
914	{ .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
915	};
916
917	static void tegra114_flush_dcache(struct page *page, unsigned long offset,
918	size_t size)
919	{
920	phys_addr_t phys = page_to_phys(page) + offset;
921	void *virt = page_address(page) + offset;
922
923	__cpuc_flush_dcache_area(virt, size);
924	outer_flush_range(phys, phys + size);
925	}
926
927	static const struct tegra_smmu_ops tegra114_smmu_ops = {
928	.flush_dcache = tegra114_flush_dcache,
929	};
930
931	static const struct tegra_smmu_soc tegra114_smmu_soc = {
932	.clients = tegra114_mc_clients,
933	.num_clients = ARRAY_SIZE(tegra114_mc_clients),
934	.swgroups = tegra114_swgroups,
935	.num_swgroups = ARRAY_SIZE(tegra114_swgroups),
936	.supports_round_robin_arbitration = false,
937	.supports_request_limit = false,
938	.num_asids = 4,
939	.ops = &tegra114_smmu_ops,
940	};
941
942	const struct tegra_mc_soc tegra114_mc_soc = {
943	.clients = tegra114_mc_clients,
944	.num_clients = ARRAY_SIZE(tegra114_mc_clients),
945	.num_address_bits = 32,
946	.atom_size = 32,
947	.smmu = &tegra114_smmu_soc,
948	};