[deliverable/linux.git] / drivers / memory / tegra30-mc.c

/*
 * Tegra30 Memory Controller
 *
 * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/ratelimit.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/io.h>

#define DRV_NAME "tegra30-mc"

#define MC_INTSTATUS			0x0
#define MC_INTMASK			0x4

#define MC_INT_ERR_SHIFT		6
#define MC_INT_ERR_MASK			(0x1f << MC_INT_ERR_SHIFT)
#define MC_INT_DECERR_EMEM		BIT(MC_INT_ERR_SHIFT)
#define MC_INT_SECURITY_VIOLATION	BIT(MC_INT_ERR_SHIFT + 2)
#define MC_INT_ARBITRATION_EMEM		BIT(MC_INT_ERR_SHIFT + 3)
#define MC_INT_INVALID_SMMU_PAGE	BIT(MC_INT_ERR_SHIFT + 4)

#define MC_ERR_STATUS			0x8
#define MC_ERR_ADR			0xc

#define MC_ERR_TYPE_SHIFT		28
#define MC_ERR_TYPE_MASK		(7 << MC_ERR_TYPE_SHIFT)
#define MC_ERR_TYPE_DECERR_EMEM		2
#define MC_ERR_TYPE_SECURITY_TRUSTZONE	3
#define MC_ERR_TYPE_SECURITY_CARVEOUT	4
#define MC_ERR_TYPE_INVALID_SMMU_PAGE	6

#define MC_ERR_INVALID_SMMU_PAGE_SHIFT	25
#define MC_ERR_INVALID_SMMU_PAGE_MASK	(7 << MC_ERR_INVALID_SMMU_PAGE_SHIFT)
#define MC_ERR_RW_SHIFT			16
#define MC_ERR_RW			BIT(MC_ERR_RW_SHIFT)
#define MC_ERR_SECURITY			BIT(MC_ERR_RW_SHIFT + 1)

#define SECURITY_VIOLATION_TYPE		BIT(30)	/* 0=TRUSTZONE, 1=CARVEOUT */

#define MC_EMEM_ARB_CFG			0x90
#define MC_EMEM_ARB_OUTSTANDING_REQ	0x94
#define MC_EMEM_ARB_TIMING_RCD		0x98
#define MC_EMEM_ARB_TIMING_RP		0x9c
#define MC_EMEM_ARB_TIMING_RC		0xa0
#define MC_EMEM_ARB_TIMING_RAS		0xa4
#define MC_EMEM_ARB_TIMING_FAW		0xa8
#define MC_EMEM_ARB_TIMING_RRD		0xac
#define MC_EMEM_ARB_TIMING_RAP2PRE	0xb0
#define MC_EMEM_ARB_TIMING_WAP2PRE	0xb4
#define MC_EMEM_ARB_TIMING_R2R		0xb8
#define MC_EMEM_ARB_TIMING_W2W		0xbc
#define MC_EMEM_ARB_TIMING_R2W		0xc0
#define MC_EMEM_ARB_TIMING_W2R		0xc4

#define MC_EMEM_ARB_DA_TURNS		0xd0
#define MC_EMEM_ARB_DA_COVERS		0xd4
#define MC_EMEM_ARB_MISC0		0xd8
#define MC_EMEM_ARB_MISC1		0xdc

#define MC_EMEM_ARB_RING3_THROTTLE	0xe4
#define MC_EMEM_ARB_OVERRIDE		0xe8

#define MC_TIMING_CONTROL		0xfc

#define MC_CLIENT_ID_MASK		0x7f

#define NUM_MC_REG_BANKS		4

struct tegra30_mc {
	void __iomem *regs[NUM_MC_REG_BANKS];
	struct device *dev;
	u32 ctx[0];
};

static inline u32 mc_readl(struct tegra30_mc *mc, u32 offs)
{
	u32 val = 0;

	if (offs < 0x10)
		val = readl(mc->regs[0] + offs);
	if (offs < 0x1f0)
		val = readl(mc->regs[1] + offs - 0x3c);
	if (offs < 0x228)
		val = readl(mc->regs[2] + offs - 0x200);
	if (offs < 0x400)
		val = readl(mc->regs[3] + offs - 0x284);

	return val;
}

static inline void mc_writel(struct tegra30_mc *mc, u32 val, u32 offs)
{
	if (offs < 0x10) {
		writel(val, mc->regs[0] + offs);
		return;
	}
	if (offs < 0x1f0) {
		writel(val, mc->regs[1] + offs - 0x3c);
		return;
	}
	if (offs < 0x228) {
		writel(val, mc->regs[2] + offs - 0x200);
		return;
	}
	if (offs < 0x400) {
		writel(val, mc->regs[3] + offs - 0x284);
		return;
	}
}

static const char * const tegra30_mc_client[] = {
	"csr_ptcr",
	"cbr_display0a",
	"cbr_display0ab",
	"cbr_display0b",
	"cbr_display0bb",
	"cbr_display0c",
	"cbr_display0cb",
	"cbr_display1b",
	"cbr_display1bb",
	"cbr_eppup",
	"cbr_g2pr",
	"cbr_g2sr",
	"cbr_mpeunifbr",
	"cbr_viruv",
	"csr_afir",
	"csr_avpcarm7r",
	"csr_displayhc",
	"csr_displayhcb",
	"csr_fdcdrd",
	"csr_fdcdrd2",
	"csr_g2dr",
	"csr_hdar",
	"csr_host1xdmar",
	"csr_host1xr",
	"csr_idxsrd",
	"csr_idxsrd2",
	"csr_mpe_ipred",
	"csr_mpeamemrd",
	"csr_mpecsrd",
	"csr_ppcsahbdmar",
	"csr_ppcsahbslvr",
	"csr_satar",
	"csr_texsrd",
	"csr_texsrd2",
	"csr_vdebsevr",
	"csr_vdember",
	"csr_vdemcer",
	"csr_vdetper",
	"csr_mpcorelpr",
	"csr_mpcorer",
	"cbw_eppu",
	"cbw_eppv",
	"cbw_eppy",
	"cbw_mpeunifbw",
	"cbw_viwsb",
	"cbw_viwu",
	"cbw_viwv",
	"cbw_viwy",
	"ccw_g2dw",
	"csw_afiw",
	"csw_avpcarm7w",
	"csw_fdcdwr",
	"csw_fdcdwr2",
	"csw_hdaw",
	"csw_host1xw",
	"csw_ispw",
	"csw_mpcorelpw",
	"csw_mpcorew",
	"csw_mpecswr",
	"csw_ppcsahbdmaw",
	"csw_ppcsahbslvw",
	"csw_sataw",
	"csw_vdebsevw",
	"csw_vdedbgw",
	"csw_vdembew",
	"csw_vdetpmw",
};

static void tegra30_mc_decode(struct tegra30_mc *mc, int n)
{
	u32 err, addr;
	const char * const mc_int_err[] = {
		"MC_DECERR",
		"Unknown",
		"MC_SECURITY_ERR",
		"MC_ARBITRATION_EMEM",
		"MC_SMMU_ERR",
	};
	const char * const err_type[] = {
		"Unknown",
		"Unknown",
		"DECERR_EMEM",
		"SECURITY_TRUSTZONE",
		"SECURITY_CARVEOUT",
		"Unknown",
		"INVALID_SMMU_PAGE",
		"Unknown",
	};
	char attr[6];
	int cid, perm, type, idx;
	const char *client = "Unknown";

	idx = n - MC_INT_ERR_SHIFT;
	if ((idx < 0) || (idx >= ARRAY_SIZE(mc_int_err)) || (idx == 1)) {
		dev_err_ratelimited(mc->dev, "Unknown interrupt status %08lx\n",
				    BIT(n));
		return;
	}

	err = readl(mc + MC_ERR_STATUS);

	type = (err & MC_ERR_TYPE_MASK) >> MC_ERR_TYPE_SHIFT;
	perm = (err & MC_ERR_INVALID_SMMU_PAGE_MASK) >>
		MC_ERR_INVALID_SMMU_PAGE_SHIFT;
	if (type == MC_ERR_TYPE_INVALID_SMMU_PAGE)
		sprintf(attr, "%c-%c-%c",
			(perm & BIT(2)) ? 'R' : '-',
			(perm & BIT(1)) ? 'W' : '-',
			(perm & BIT(0)) ? 'S' : '-');
	else
		attr[0] = '\0';

	cid = err & MC_CLIENT_ID_MASK;
	if (cid < ARRAY_SIZE(tegra30_mc_client))
		client = tegra30_mc_client[cid];

	addr = readl(mc + MC_ERR_ADR);

	dev_err_ratelimited(mc->dev, "%s (0x%08x): 0x%08x %s (%s %s %s %s)\n",
			   mc_int_err[idx], err, addr, client,
			   (err & MC_ERR_SECURITY) ? "secure" : "non-secure",
			   (err & MC_ERR_RW) ? "write" : "read",
			   err_type[type], attr);
}

static const u32 tegra30_mc_ctx[] = {
	MC_EMEM_ARB_CFG,
	MC_EMEM_ARB_OUTSTANDING_REQ,
	MC_EMEM_ARB_TIMING_RCD,
	MC_EMEM_ARB_TIMING_RP,
	MC_EMEM_ARB_TIMING_RC,
	MC_EMEM_ARB_TIMING_RAS,
	MC_EMEM_ARB_TIMING_FAW,
	MC_EMEM_ARB_TIMING_RRD,
	MC_EMEM_ARB_TIMING_RAP2PRE,
	MC_EMEM_ARB_TIMING_WAP2PRE,
	MC_EMEM_ARB_TIMING_R2R,
	MC_EMEM_ARB_TIMING_W2W,
	MC_EMEM_ARB_TIMING_R2W,
	MC_EMEM_ARB_TIMING_W2R,
	MC_EMEM_ARB_DA_TURNS,
	MC_EMEM_ARB_DA_COVERS,
	MC_EMEM_ARB_MISC0,
	MC_EMEM_ARB_MISC1,
	MC_EMEM_ARB_RING3_THROTTLE,
	MC_EMEM_ARB_OVERRIDE,
	MC_INTMASK,
};

static int tegra30_mc_suspend(struct device *dev)
{
	int i;
	struct tegra30_mc *mc = dev_get_drvdata(dev);

	for (i = 0; i < ARRAY_SIZE(tegra30_mc_ctx); i++)
		mc->ctx[i] = mc_readl(mc, tegra30_mc_ctx[i]);
	return 0;
}

static int tegra30_mc_resume(struct device *dev)
{
	int i;
	struct tegra30_mc *mc = dev_get_drvdata(dev);

	for (i = 0; i < ARRAY_SIZE(tegra30_mc_ctx); i++)
		mc_writel(mc, mc->ctx[i], tegra30_mc_ctx[i]);

	mc_writel(mc, 1, MC_TIMING_CONTROL);
	/* Read-back to ensure that write reached */
	mc_readl(mc, MC_TIMING_CONTROL);
	return 0;
}

static UNIVERSAL_DEV_PM_OPS(tegra30_mc_pm,
			    tegra30_mc_suspend,
			    tegra30_mc_resume, NULL);

static const struct of_device_id tegra30_mc_of_match[] __devinitconst = {
	{ .compatible = "nvidia,tegra30-mc", },
	{},
};

static irqreturn_t tegra30_mc_isr(int irq, void *data)
{
	u32 stat, mask, bit;
	struct tegra30_mc *mc = data;

	stat = mc_readl(mc, MC_INTSTATUS);
	mask = mc_readl(mc, MC_INTMASK);
	mask &= stat;
	if (!mask)
		return IRQ_NONE;
	while ((bit = ffs(mask)) != 0)
		tegra30_mc_decode(mc, bit - 1);
	mc_writel(mc, stat, MC_INTSTATUS);
	return IRQ_HANDLED;
}

static int __devinit tegra30_mc_probe(struct platform_device *pdev)
{
	struct resource *irq;
	struct tegra30_mc *mc;
	size_t bytes;
	int err, i;
	u32 intmask;

	bytes = sizeof(*mc) + sizeof(u32) * ARRAY_SIZE(tegra30_mc_ctx);
	mc = devm_kzalloc(&pdev->dev, bytes, GFP_KERNEL);
	if (!mc)
		return -ENOMEM;
	mc->dev = &pdev->dev;

	for (i = 0; i < ARRAY_SIZE(mc->regs); i++) {
		struct resource *res;

		res = platform_get_resource(pdev, IORESOURCE_MEM, i);
		if (!res)
			return -ENODEV;
		mc->regs[i] = devm_request_and_ioremap(&pdev->dev, res);
		if (!mc->regs[i])
			return -EBUSY;
	}

	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (!irq)
		return -ENODEV;
	err = devm_request_irq(&pdev->dev, irq->start, tegra30_mc_isr,
			       IRQF_SHARED, dev_name(&pdev->dev), mc);
	if (err)
		return -ENODEV;

	platform_set_drvdata(pdev, mc);

	intmask = MC_INT_INVALID_SMMU_PAGE |
		MC_INT_DECERR_EMEM | MC_INT_SECURITY_VIOLATION;
	mc_writel(mc, intmask, MC_INTMASK);
	return 0;
}

static struct platform_driver tegra30_mc_driver = {
	.probe = tegra30_mc_probe,
	.driver = {
		.name = DRV_NAME,
		.owner = THIS_MODULE,
		.of_match_table = tegra30_mc_of_match,
		.pm = &tegra30_mc_pm,
	},
};
module_platform_driver(tegra30_mc_driver);

MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
MODULE_DESCRIPTION("Tegra30 MC driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
Commit	Line	Data
af468109 HD	1	/*
	2	* Tegra30 Memory Controller
	3	*
	4	* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*
	15	* You should have received a copy of the GNU General Public License along with
	16	* this program; if not, write to the Free Software Foundation, Inc.,
	17	* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18	*/
	19
	20	#include <linux/kernel.h>
	21	#include <linux/module.h>
	22	#include <linux/ratelimit.h>
	23	#include <linux/platform_device.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/io.h>
	26
	27	#define DRV_NAME "tegra30-mc"
	28
	29	#define MC_INTSTATUS 0x0
	30	#define MC_INTMASK 0x4
	31
	32	#define MC_INT_ERR_SHIFT 6
	33	#define MC_INT_ERR_MASK (0x1f << MC_INT_ERR_SHIFT)
	34	#define MC_INT_DECERR_EMEM BIT(MC_INT_ERR_SHIFT)
	35	#define MC_INT_SECURITY_VIOLATION BIT(MC_INT_ERR_SHIFT + 2)
	36	#define MC_INT_ARBITRATION_EMEM BIT(MC_INT_ERR_SHIFT + 3)
	37	#define MC_INT_INVALID_SMMU_PAGE BIT(MC_INT_ERR_SHIFT + 4)
	38
	39	#define MC_ERR_STATUS 0x8
	40	#define MC_ERR_ADR 0xc
	41
	42	#define MC_ERR_TYPE_SHIFT 28
	43	#define MC_ERR_TYPE_MASK (7 << MC_ERR_TYPE_SHIFT)
	44	#define MC_ERR_TYPE_DECERR_EMEM 2
	45	#define MC_ERR_TYPE_SECURITY_TRUSTZONE 3
	46	#define MC_ERR_TYPE_SECURITY_CARVEOUT 4
	47	#define MC_ERR_TYPE_INVALID_SMMU_PAGE 6
	48
	49	#define MC_ERR_INVALID_SMMU_PAGE_SHIFT 25
	50	#define MC_ERR_INVALID_SMMU_PAGE_MASK (7 << MC_ERR_INVALID_SMMU_PAGE_SHIFT)
	51	#define MC_ERR_RW_SHIFT 16
	52	#define MC_ERR_RW BIT(MC_ERR_RW_SHIFT)
	53	#define MC_ERR_SECURITY BIT(MC_ERR_RW_SHIFT + 1)
	54
	55	#define SECURITY_VIOLATION_TYPE BIT(30) /* 0=TRUSTZONE, 1=CARVEOUT */
	56
	57	#define MC_EMEM_ARB_CFG 0x90
	58	#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
	59	#define MC_EMEM_ARB_TIMING_RCD 0x98
	60	#define MC_EMEM_ARB_TIMING_RP 0x9c
	61	#define MC_EMEM_ARB_TIMING_RC 0xa0
	62	#define MC_EMEM_ARB_TIMING_RAS 0xa4
	63	#define MC_EMEM_ARB_TIMING_FAW 0xa8
	64	#define MC_EMEM_ARB_TIMING_RRD 0xac
65	#define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0
66	#define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4
67	#define MC_EMEM_ARB_TIMING_R2R 0xb8
68	#define MC_EMEM_ARB_TIMING_W2W 0xbc
69	#define MC_EMEM_ARB_TIMING_R2W 0xc0
70	#define MC_EMEM_ARB_TIMING_W2R 0xc4
71
72	#define MC_EMEM_ARB_DA_TURNS 0xd0
73	#define MC_EMEM_ARB_DA_COVERS 0xd4
74	#define MC_EMEM_ARB_MISC0 0xd8
75	#define MC_EMEM_ARB_MISC1 0xdc
76
77	#define MC_EMEM_ARB_RING3_THROTTLE 0xe4
78	#define MC_EMEM_ARB_OVERRIDE 0xe8
79
80	#define MC_TIMING_CONTROL 0xfc
81
82	#define MC_CLIENT_ID_MASK 0x7f
83
84	#define NUM_MC_REG_BANKS 4
85
86	struct tegra30_mc {
87	void __iomem *regs[NUM_MC_REG_BANKS];
88	struct device *dev;
89	u32 ctx[0];
90	};
91
92	static inline u32 mc_readl(struct tegra30_mc *mc, u32 offs)
93	{
b37fd415 HD	94	u32 val = 0;
b37fd415 HD	95
af468109	96	if (offs < 0x10)
b37fd415	97	val = readl(mc->regs[0] + offs);
af468109	98	if (offs < 0x1f0)
b37fd415	99	val = readl(mc->regs[1] + offs - 0x3c);
af468109	100	if (offs < 0x228)
b37fd415	101	val = readl(mc->regs[2] + offs - 0x200);
af468109	102	if (offs < 0x400)
b37fd415 HD	103	val = readl(mc->regs[3] + offs - 0x284);
	104
	105	return val;
af468109 HD	106	}
	107
	108	static inline void mc_writel(struct tegra30_mc *mc, u32 val, u32 offs)
	109	{
	110	if (offs < 0x10) {
	111	writel(val, mc->regs[0] + offs);
	112	return;
	113	}
af468109 HD	114	if (offs < 0x1f0) {
	115	writel(val, mc->regs[1] + offs - 0x3c);
	116	return;
	117	}
af468109 HD	118	if (offs < 0x228) {
	119	writel(val, mc->regs[2] + offs - 0x200);
	120	return;
	121	}
af468109 HD	122	if (offs < 0x400) {
	123	writel(val, mc->regs[3] + offs - 0x284);
	124	return;
	125	}
af468109 HD	126	}
	127
	128	static const char * const tegra30_mc_client[] = {
	129	"csr_ptcr",
	130	"cbr_display0a",
	131	"cbr_display0ab",
	132	"cbr_display0b",
	133	"cbr_display0bb",
	134	"cbr_display0c",
	135	"cbr_display0cb",
	136	"cbr_display1b",
	137	"cbr_display1bb",
	138	"cbr_eppup",
	139	"cbr_g2pr",
	140	"cbr_g2sr",
	141	"cbr_mpeunifbr",
	142	"cbr_viruv",
	143	"csr_afir",
	144	"csr_avpcarm7r",
	145	"csr_displayhc",
	146	"csr_displayhcb",
	147	"csr_fdcdrd",
	148	"csr_fdcdrd2",
	149	"csr_g2dr",
	150	"csr_hdar",
	151	"csr_host1xdmar",
	152	"csr_host1xr",
	153	"csr_idxsrd",
	154	"csr_idxsrd2",
	155	"csr_mpe_ipred",
	156	"csr_mpeamemrd",
	157	"csr_mpecsrd",
	158	"csr_ppcsahbdmar",
	159	"csr_ppcsahbslvr",
	160	"csr_satar",
	161	"csr_texsrd",
	162	"csr_texsrd2",
	163	"csr_vdebsevr",
	164	"csr_vdember",
	165	"csr_vdemcer",
	166	"csr_vdetper",
	167	"csr_mpcorelpr",
	168	"csr_mpcorer",
	169	"cbw_eppu",
	170	"cbw_eppv",
	171	"cbw_eppy",
	172	"cbw_mpeunifbw",
	173	"cbw_viwsb",
	174	"cbw_viwu",
	175	"cbw_viwv",
	176	"cbw_viwy",
	177	"ccw_g2dw",
	178	"csw_afiw",
	179	"csw_avpcarm7w",
	180	"csw_fdcdwr",
	181	"csw_fdcdwr2",
	182	"csw_hdaw",
	183	"csw_host1xw",
	184	"csw_ispw",
	185	"csw_mpcorelpw",
	186	"csw_mpcorew",
	187	"csw_mpecswr",
	188	"csw_ppcsahbdmaw",
	189	"csw_ppcsahbslvw",
190	"csw_sataw",
191	"csw_vdebsevw",
192	"csw_vdedbgw",
193	"csw_vdembew",
194	"csw_vdetpmw",
195	};
196
197	static void tegra30_mc_decode(struct tegra30_mc *mc, int n)
198	{
199	u32 err, addr;
200	const char * const mc_int_err[] = {
201	"MC_DECERR",
202	"Unknown",
203	"MC_SECURITY_ERR",
204	"MC_ARBITRATION_EMEM",
205	"MC_SMMU_ERR",
206	};
207	const char * const err_type[] = {
208	"Unknown",
209	"Unknown",
210	"DECERR_EMEM",
211	"SECURITY_TRUSTZONE",
212	"SECURITY_CARVEOUT",
213	"Unknown",
214	"INVALID_SMMU_PAGE",
215	"Unknown",
216	};
217	char attr[6];
218	int cid, perm, type, idx;
219	const char *client = "Unknown";
220
221	idx = n - MC_INT_ERR_SHIFT;
222	if ((idx < 0) \|\| (idx >= ARRAY_SIZE(mc_int_err)) \|\| (idx == 1)) {
90394482 HD	223	dev_err_ratelimited(mc->dev, "Unknown interrupt status %08lx\n",
90394482 HD	224	BIT(n));
af468109 HD	225	return;
	226	}
	227
	228	err = readl(mc + MC_ERR_STATUS);
	229
	230	type = (err & MC_ERR_TYPE_MASK) >> MC_ERR_TYPE_SHIFT;
	231	perm = (err & MC_ERR_INVALID_SMMU_PAGE_MASK) >>
	232	MC_ERR_INVALID_SMMU_PAGE_SHIFT;
	233	if (type == MC_ERR_TYPE_INVALID_SMMU_PAGE)
	234	sprintf(attr, "%c-%c-%c",
	235	(perm & BIT(2)) ? 'R' : '-',
	236	(perm & BIT(1)) ? 'W' : '-',
	237	(perm & BIT(0)) ? 'S' : '-');
	238	else
	239	attr[0] = '\0';
	240
	241	cid = err & MC_CLIENT_ID_MASK;
	242	if (cid < ARRAY_SIZE(tegra30_mc_client))
	243	client = tegra30_mc_client[cid];
	244
	245	addr = readl(mc + MC_ERR_ADR);
	246
90394482	247	dev_err_ratelimited(mc->dev, "%s (0x%08x): 0x%08x %s (%s %s %s %s)\n",
af468109 HD	248	mc_int_err[idx], err, addr, client,
	249	(err & MC_ERR_SECURITY) ? "secure" : "non-secure",
	250	(err & MC_ERR_RW) ? "write" : "read",
	251	err_type[type], attr);
	252	}
	253
	254	static const u32 tegra30_mc_ctx[] = {
	255	MC_EMEM_ARB_CFG,
	256	MC_EMEM_ARB_OUTSTANDING_REQ,
	257	MC_EMEM_ARB_TIMING_RCD,
	258	MC_EMEM_ARB_TIMING_RP,
	259	MC_EMEM_ARB_TIMING_RC,
	260	MC_EMEM_ARB_TIMING_RAS,
	261	MC_EMEM_ARB_TIMING_FAW,
	262	MC_EMEM_ARB_TIMING_RRD,
	263	MC_EMEM_ARB_TIMING_RAP2PRE,
	264	MC_EMEM_ARB_TIMING_WAP2PRE,
	265	MC_EMEM_ARB_TIMING_R2R,
	266	MC_EMEM_ARB_TIMING_W2W,
	267	MC_EMEM_ARB_TIMING_R2W,
	268	MC_EMEM_ARB_TIMING_W2R,
	269	MC_EMEM_ARB_DA_TURNS,
	270	MC_EMEM_ARB_DA_COVERS,
	271	MC_EMEM_ARB_MISC0,
	272	MC_EMEM_ARB_MISC1,
	273	MC_EMEM_ARB_RING3_THROTTLE,
	274	MC_EMEM_ARB_OVERRIDE,
	275	MC_INTMASK,
	276	};
	277
	278	static int tegra30_mc_suspend(struct device *dev)
	279	{
	280	int i;
	281	struct tegra30_mc *mc = dev_get_drvdata(dev);
	282
	283	for (i = 0; i < ARRAY_SIZE(tegra30_mc_ctx); i++)
	284	mc->ctx[i] = mc_readl(mc, tegra30_mc_ctx[i]);
	285	return 0;
	286	}
	287
	288	static int tegra30_mc_resume(struct device *dev)
	289	{
	290	int i;
	291	struct tegra30_mc *mc = dev_get_drvdata(dev);
	292
	293	for (i = 0; i < ARRAY_SIZE(tegra30_mc_ctx); i++)
	294	mc_writel(mc, mc->ctx[i], tegra30_mc_ctx[i]);
	295
	296	mc_writel(mc, 1, MC_TIMING_CONTROL);
	297	/* Read-back to ensure that write reached */
	298	mc_readl(mc, MC_TIMING_CONTROL);
	299	return 0;
	300	}
	301
	302	static UNIVERSAL_DEV_PM_OPS(tegra30_mc_pm,
	303	tegra30_mc_suspend,
	304	tegra30_mc_resume, NULL);
	305
	306	static const struct of_device_id tegra30_mc_of_match[] __devinitconst = {
	307	{ .compatible = "nvidia,tegra30-mc", },
	308	{},
	309	};
	310
	311	static irqreturn_t tegra30_mc_isr(int irq, void *data)
312	{
313	u32 stat, mask, bit;
314	struct tegra30_mc *mc = data;
315
316	stat = mc_readl(mc, MC_INTSTATUS);
317	mask = mc_readl(mc, MC_INTMASK);
318	mask &= stat;
319	if (!mask)
320	return IRQ_NONE;
321	while ((bit = ffs(mask)) != 0)
322	tegra30_mc_decode(mc, bit - 1);
323	mc_writel(mc, stat, MC_INTSTATUS);
324	return IRQ_HANDLED;
325	}
326
327	static int __devinit tegra30_mc_probe(struct platform_device *pdev)
328	{
329	struct resource *irq;
330	struct tegra30_mc *mc;
331	size_t bytes;
332	int err, i;
333	u32 intmask;
334
335	bytes = sizeof(mc) + sizeof(u32) ARRAY_SIZE(tegra30_mc_ctx);
336	mc = devm_kzalloc(&pdev->dev, bytes, GFP_KERNEL);
337	if (!mc)
338	return -ENOMEM;
339	mc->dev = &pdev->dev;
340
341	for (i = 0; i < ARRAY_SIZE(mc->regs); i++) {
342	struct resource *res;
343
344	res = platform_get_resource(pdev, IORESOURCE_MEM, i);
345	if (!res)
346	return -ENODEV;
347	mc->regs[i] = devm_request_and_ioremap(&pdev->dev, res);
348	if (!mc->regs[i])
349	return -EBUSY;
350	}
351
352	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
353	if (!irq)
354	return -ENODEV;
355	err = devm_request_irq(&pdev->dev, irq->start, tegra30_mc_isr,
356	IRQF_SHARED, dev_name(&pdev->dev), mc);
357	if (err)
358	return -ENODEV;
359
360	platform_set_drvdata(pdev, mc);
361
362	intmask = MC_INT_INVALID_SMMU_PAGE \|
363	MC_INT_DECERR_EMEM \| MC_INT_SECURITY_VIOLATION;
364	mc_writel(mc, intmask, MC_INTMASK);
365	return 0;
366	}
367
af468109 HD	368	static struct platform_driver tegra30_mc_driver = {
af468109 HD	369	.probe = tegra30_mc_probe,
af468109 HD	370	.driver = {
	371	.name = DRV_NAME,
	372	.owner = THIS_MODULE,
	373	.of_match_table = tegra30_mc_of_match,
	374	.pm = &tegra30_mc_pm,
	375	},
	376	};
	377	module_platform_driver(tegra30_mc_driver);
	378
	379	MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
	380	MODULE_DESCRIPTION("Tegra30 MC driver");
	381	MODULE_LICENSE("GPL v2");
	382	MODULE_ALIAS("platform:" DRV_NAME);