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62579266 RV |
1 | /* |
2 | * Copyright (C) ST-Ericsson SA 2010 | |
3 | * | |
4 | * License Terms: GNU General Public License v2 | |
5 | * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> | |
6 | * Author: Rabin Vincent <rabin.vincent@stericsson.com> | |
adceed62 | 7 | * Author: Mattias Wallin <mattias.wallin@stericsson.com> |
62579266 RV |
8 | */ |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/slab.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/irq.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/mfd/core.h> | |
47c16975 | 19 | #include <linux/mfd/abx500.h> |
62579266 | 20 | #include <linux/mfd/ab8500.h> |
549931f9 | 21 | #include <linux/regulator/ab8500.h> |
62579266 RV |
22 | |
23 | /* | |
24 | * Interrupt register offsets | |
25 | * Bank : 0x0E | |
26 | */ | |
47c16975 MW |
27 | #define AB8500_IT_SOURCE1_REG 0x00 |
28 | #define AB8500_IT_SOURCE2_REG 0x01 | |
29 | #define AB8500_IT_SOURCE3_REG 0x02 | |
30 | #define AB8500_IT_SOURCE4_REG 0x03 | |
31 | #define AB8500_IT_SOURCE5_REG 0x04 | |
32 | #define AB8500_IT_SOURCE6_REG 0x05 | |
33 | #define AB8500_IT_SOURCE7_REG 0x06 | |
34 | #define AB8500_IT_SOURCE8_REG 0x07 | |
35 | #define AB8500_IT_SOURCE19_REG 0x12 | |
36 | #define AB8500_IT_SOURCE20_REG 0x13 | |
37 | #define AB8500_IT_SOURCE21_REG 0x14 | |
38 | #define AB8500_IT_SOURCE22_REG 0x15 | |
39 | #define AB8500_IT_SOURCE23_REG 0x16 | |
40 | #define AB8500_IT_SOURCE24_REG 0x17 | |
62579266 RV |
41 | |
42 | /* | |
43 | * latch registers | |
44 | */ | |
47c16975 MW |
45 | #define AB8500_IT_LATCH1_REG 0x20 |
46 | #define AB8500_IT_LATCH2_REG 0x21 | |
47 | #define AB8500_IT_LATCH3_REG 0x22 | |
48 | #define AB8500_IT_LATCH4_REG 0x23 | |
49 | #define AB8500_IT_LATCH5_REG 0x24 | |
50 | #define AB8500_IT_LATCH6_REG 0x25 | |
51 | #define AB8500_IT_LATCH7_REG 0x26 | |
52 | #define AB8500_IT_LATCH8_REG 0x27 | |
53 | #define AB8500_IT_LATCH9_REG 0x28 | |
54 | #define AB8500_IT_LATCH10_REG 0x29 | |
92d50a41 | 55 | #define AB8500_IT_LATCH12_REG 0x2B |
47c16975 MW |
56 | #define AB8500_IT_LATCH19_REG 0x32 |
57 | #define AB8500_IT_LATCH20_REG 0x33 | |
58 | #define AB8500_IT_LATCH21_REG 0x34 | |
59 | #define AB8500_IT_LATCH22_REG 0x35 | |
60 | #define AB8500_IT_LATCH23_REG 0x36 | |
61 | #define AB8500_IT_LATCH24_REG 0x37 | |
62579266 RV |
62 | |
63 | /* | |
64 | * mask registers | |
65 | */ | |
66 | ||
47c16975 MW |
67 | #define AB8500_IT_MASK1_REG 0x40 |
68 | #define AB8500_IT_MASK2_REG 0x41 | |
69 | #define AB8500_IT_MASK3_REG 0x42 | |
70 | #define AB8500_IT_MASK4_REG 0x43 | |
71 | #define AB8500_IT_MASK5_REG 0x44 | |
72 | #define AB8500_IT_MASK6_REG 0x45 | |
73 | #define AB8500_IT_MASK7_REG 0x46 | |
74 | #define AB8500_IT_MASK8_REG 0x47 | |
75 | #define AB8500_IT_MASK9_REG 0x48 | |
76 | #define AB8500_IT_MASK10_REG 0x49 | |
77 | #define AB8500_IT_MASK11_REG 0x4A | |
78 | #define AB8500_IT_MASK12_REG 0x4B | |
79 | #define AB8500_IT_MASK13_REG 0x4C | |
80 | #define AB8500_IT_MASK14_REG 0x4D | |
81 | #define AB8500_IT_MASK15_REG 0x4E | |
82 | #define AB8500_IT_MASK16_REG 0x4F | |
83 | #define AB8500_IT_MASK17_REG 0x50 | |
84 | #define AB8500_IT_MASK18_REG 0x51 | |
85 | #define AB8500_IT_MASK19_REG 0x52 | |
86 | #define AB8500_IT_MASK20_REG 0x53 | |
87 | #define AB8500_IT_MASK21_REG 0x54 | |
88 | #define AB8500_IT_MASK22_REG 0x55 | |
89 | #define AB8500_IT_MASK23_REG 0x56 | |
90 | #define AB8500_IT_MASK24_REG 0x57 | |
91 | ||
92 | #define AB8500_REV_REG 0x80 | |
e5c238c3 | 93 | #define AB8500_SWITCH_OFF_STATUS 0x00 |
62579266 RV |
94 | |
95 | /* | |
96 | * Map interrupt numbers to the LATCH and MASK register offsets, Interrupt | |
97 | * numbers are indexed into this array with (num / 8). | |
98 | * | |
99 | * This is one off from the register names, i.e. AB8500_IT_MASK1_REG is at | |
100 | * offset 0. | |
101 | */ | |
102 | static const int ab8500_irq_regoffset[AB8500_NUM_IRQ_REGS] = { | |
92d50a41 | 103 | 0, 1, 2, 3, 4, 6, 7, 8, 9, 11, 18, 19, 20, 21, |
62579266 RV |
104 | }; |
105 | ||
47c16975 MW |
106 | static int ab8500_get_chip_id(struct device *dev) |
107 | { | |
6bce7bf1 MW |
108 | struct ab8500 *ab8500; |
109 | ||
110 | if (!dev) | |
111 | return -EINVAL; | |
112 | ab8500 = dev_get_drvdata(dev->parent); | |
113 | return ab8500 ? (int)ab8500->chip_id : -EINVAL; | |
47c16975 MW |
114 | } |
115 | ||
116 | static int set_register_interruptible(struct ab8500 *ab8500, u8 bank, | |
117 | u8 reg, u8 data) | |
62579266 RV |
118 | { |
119 | int ret; | |
47c16975 MW |
120 | /* |
121 | * Put the u8 bank and u8 register together into a an u16. | |
122 | * The bank on higher 8 bits and register in lower 8 bits. | |
123 | * */ | |
124 | u16 addr = ((u16)bank) << 8 | reg; | |
62579266 RV |
125 | |
126 | dev_vdbg(ab8500->dev, "wr: addr %#x <= %#x\n", addr, data); | |
127 | ||
47c16975 MW |
128 | ret = mutex_lock_interruptible(&ab8500->lock); |
129 | if (ret) | |
130 | return ret; | |
131 | ||
62579266 RV |
132 | ret = ab8500->write(ab8500, addr, data); |
133 | if (ret < 0) | |
134 | dev_err(ab8500->dev, "failed to write reg %#x: %d\n", | |
135 | addr, ret); | |
47c16975 | 136 | mutex_unlock(&ab8500->lock); |
62579266 RV |
137 | |
138 | return ret; | |
139 | } | |
140 | ||
47c16975 MW |
141 | static int ab8500_set_register(struct device *dev, u8 bank, |
142 | u8 reg, u8 value) | |
62579266 | 143 | { |
47c16975 | 144 | struct ab8500 *ab8500 = dev_get_drvdata(dev->parent); |
62579266 | 145 | |
47c16975 | 146 | return set_register_interruptible(ab8500, bank, reg, value); |
62579266 | 147 | } |
62579266 | 148 | |
47c16975 MW |
149 | static int get_register_interruptible(struct ab8500 *ab8500, u8 bank, |
150 | u8 reg, u8 *value) | |
62579266 RV |
151 | { |
152 | int ret; | |
47c16975 MW |
153 | /* put the u8 bank and u8 reg together into a an u16. |
154 | * bank on higher 8 bits and reg in lower */ | |
155 | u16 addr = ((u16)bank) << 8 | reg; | |
156 | ||
157 | ret = mutex_lock_interruptible(&ab8500->lock); | |
158 | if (ret) | |
159 | return ret; | |
62579266 RV |
160 | |
161 | ret = ab8500->read(ab8500, addr); | |
162 | if (ret < 0) | |
163 | dev_err(ab8500->dev, "failed to read reg %#x: %d\n", | |
164 | addr, ret); | |
47c16975 MW |
165 | else |
166 | *value = ret; | |
62579266 | 167 | |
47c16975 | 168 | mutex_unlock(&ab8500->lock); |
62579266 RV |
169 | dev_vdbg(ab8500->dev, "rd: addr %#x => data %#x\n", addr, ret); |
170 | ||
171 | return ret; | |
172 | } | |
173 | ||
47c16975 MW |
174 | static int ab8500_get_register(struct device *dev, u8 bank, |
175 | u8 reg, u8 *value) | |
62579266 | 176 | { |
47c16975 | 177 | struct ab8500 *ab8500 = dev_get_drvdata(dev->parent); |
62579266 | 178 | |
47c16975 | 179 | return get_register_interruptible(ab8500, bank, reg, value); |
62579266 | 180 | } |
47c16975 MW |
181 | |
182 | static int mask_and_set_register_interruptible(struct ab8500 *ab8500, u8 bank, | |
183 | u8 reg, u8 bitmask, u8 bitvalues) | |
62579266 RV |
184 | { |
185 | int ret; | |
47c16975 MW |
186 | u8 data; |
187 | /* put the u8 bank and u8 reg together into a an u16. | |
188 | * bank on higher 8 bits and reg in lower */ | |
189 | u16 addr = ((u16)bank) << 8 | reg; | |
62579266 | 190 | |
47c16975 MW |
191 | ret = mutex_lock_interruptible(&ab8500->lock); |
192 | if (ret) | |
193 | return ret; | |
62579266 | 194 | |
47c16975 MW |
195 | ret = ab8500->read(ab8500, addr); |
196 | if (ret < 0) { | |
197 | dev_err(ab8500->dev, "failed to read reg %#x: %d\n", | |
198 | addr, ret); | |
62579266 | 199 | goto out; |
47c16975 | 200 | } |
62579266 | 201 | |
47c16975 MW |
202 | data = (u8)ret; |
203 | data = (~bitmask & data) | (bitmask & bitvalues); | |
62579266 | 204 | |
47c16975 MW |
205 | ret = ab8500->write(ab8500, addr, data); |
206 | if (ret < 0) | |
207 | dev_err(ab8500->dev, "failed to write reg %#x: %d\n", | |
208 | addr, ret); | |
62579266 | 209 | |
47c16975 | 210 | dev_vdbg(ab8500->dev, "mask: addr %#x => data %#x\n", addr, data); |
62579266 RV |
211 | out: |
212 | mutex_unlock(&ab8500->lock); | |
213 | return ret; | |
214 | } | |
47c16975 MW |
215 | |
216 | static int ab8500_mask_and_set_register(struct device *dev, | |
217 | u8 bank, u8 reg, u8 bitmask, u8 bitvalues) | |
218 | { | |
219 | struct ab8500 *ab8500 = dev_get_drvdata(dev->parent); | |
220 | ||
221 | return mask_and_set_register_interruptible(ab8500, bank, reg, | |
222 | bitmask, bitvalues); | |
223 | ||
224 | } | |
225 | ||
226 | static struct abx500_ops ab8500_ops = { | |
227 | .get_chip_id = ab8500_get_chip_id, | |
228 | .get_register = ab8500_get_register, | |
229 | .set_register = ab8500_set_register, | |
230 | .get_register_page = NULL, | |
231 | .set_register_page = NULL, | |
232 | .mask_and_set_register = ab8500_mask_and_set_register, | |
233 | .event_registers_startup_state_get = NULL, | |
234 | .startup_irq_enabled = NULL, | |
235 | }; | |
62579266 | 236 | |
9505a0a0 | 237 | static void ab8500_irq_lock(struct irq_data *data) |
62579266 | 238 | { |
9505a0a0 | 239 | struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data); |
62579266 RV |
240 | |
241 | mutex_lock(&ab8500->irq_lock); | |
242 | } | |
243 | ||
9505a0a0 | 244 | static void ab8500_irq_sync_unlock(struct irq_data *data) |
62579266 | 245 | { |
9505a0a0 | 246 | struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data); |
62579266 RV |
247 | int i; |
248 | ||
249 | for (i = 0; i < AB8500_NUM_IRQ_REGS; i++) { | |
250 | u8 old = ab8500->oldmask[i]; | |
251 | u8 new = ab8500->mask[i]; | |
252 | int reg; | |
253 | ||
254 | if (new == old) | |
255 | continue; | |
256 | ||
863dde5b LW |
257 | /* Interrupt register 12 doesn't exist prior to version 2.0 */ |
258 | if (ab8500_irq_regoffset[i] == 11 && | |
259 | ab8500->chip_id < AB8500_CUT2P0) | |
92d50a41 MW |
260 | continue; |
261 | ||
62579266 RV |
262 | ab8500->oldmask[i] = new; |
263 | ||
264 | reg = AB8500_IT_MASK1_REG + ab8500_irq_regoffset[i]; | |
47c16975 | 265 | set_register_interruptible(ab8500, AB8500_INTERRUPT, reg, new); |
62579266 RV |
266 | } |
267 | ||
268 | mutex_unlock(&ab8500->irq_lock); | |
269 | } | |
270 | ||
9505a0a0 | 271 | static void ab8500_irq_mask(struct irq_data *data) |
62579266 | 272 | { |
9505a0a0 MB |
273 | struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data); |
274 | int offset = data->irq - ab8500->irq_base; | |
62579266 RV |
275 | int index = offset / 8; |
276 | int mask = 1 << (offset % 8); | |
277 | ||
278 | ab8500->mask[index] |= mask; | |
279 | } | |
280 | ||
9505a0a0 | 281 | static void ab8500_irq_unmask(struct irq_data *data) |
62579266 | 282 | { |
9505a0a0 MB |
283 | struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data); |
284 | int offset = data->irq - ab8500->irq_base; | |
62579266 RV |
285 | int index = offset / 8; |
286 | int mask = 1 << (offset % 8); | |
287 | ||
288 | ab8500->mask[index] &= ~mask; | |
289 | } | |
290 | ||
291 | static struct irq_chip ab8500_irq_chip = { | |
292 | .name = "ab8500", | |
9505a0a0 MB |
293 | .irq_bus_lock = ab8500_irq_lock, |
294 | .irq_bus_sync_unlock = ab8500_irq_sync_unlock, | |
295 | .irq_mask = ab8500_irq_mask, | |
296 | .irq_unmask = ab8500_irq_unmask, | |
62579266 RV |
297 | }; |
298 | ||
299 | static irqreturn_t ab8500_irq(int irq, void *dev) | |
300 | { | |
301 | struct ab8500 *ab8500 = dev; | |
302 | int i; | |
303 | ||
304 | dev_vdbg(ab8500->dev, "interrupt\n"); | |
305 | ||
306 | for (i = 0; i < AB8500_NUM_IRQ_REGS; i++) { | |
307 | int regoffset = ab8500_irq_regoffset[i]; | |
308 | int status; | |
47c16975 | 309 | u8 value; |
62579266 | 310 | |
863dde5b LW |
311 | /* Interrupt register 12 doesn't exist prior to version 2.0 */ |
312 | if (regoffset == 11 && ab8500->chip_id < AB8500_CUT2P0) | |
92d50a41 MW |
313 | continue; |
314 | ||
47c16975 MW |
315 | status = get_register_interruptible(ab8500, AB8500_INTERRUPT, |
316 | AB8500_IT_LATCH1_REG + regoffset, &value); | |
317 | if (status < 0 || value == 0) | |
62579266 RV |
318 | continue; |
319 | ||
320 | do { | |
88aec4f7 | 321 | int bit = __ffs(value); |
62579266 RV |
322 | int line = i * 8 + bit; |
323 | ||
324 | handle_nested_irq(ab8500->irq_base + line); | |
47c16975 MW |
325 | value &= ~(1 << bit); |
326 | } while (value); | |
62579266 RV |
327 | } |
328 | ||
329 | return IRQ_HANDLED; | |
330 | } | |
331 | ||
332 | static int ab8500_irq_init(struct ab8500 *ab8500) | |
333 | { | |
334 | int base = ab8500->irq_base; | |
335 | int irq; | |
336 | ||
337 | for (irq = base; irq < base + AB8500_NR_IRQS; irq++) { | |
d5bb1221 TG |
338 | irq_set_chip_data(irq, ab8500); |
339 | irq_set_chip_and_handler(irq, &ab8500_irq_chip, | |
62579266 | 340 | handle_simple_irq); |
d5bb1221 | 341 | irq_set_nested_thread(irq, 1); |
62579266 RV |
342 | #ifdef CONFIG_ARM |
343 | set_irq_flags(irq, IRQF_VALID); | |
344 | #else | |
d5bb1221 | 345 | irq_set_noprobe(irq); |
62579266 RV |
346 | #endif |
347 | } | |
348 | ||
349 | return 0; | |
350 | } | |
351 | ||
352 | static void ab8500_irq_remove(struct ab8500 *ab8500) | |
353 | { | |
354 | int base = ab8500->irq_base; | |
355 | int irq; | |
356 | ||
357 | for (irq = base; irq < base + AB8500_NR_IRQS; irq++) { | |
358 | #ifdef CONFIG_ARM | |
359 | set_irq_flags(irq, 0); | |
360 | #endif | |
d5bb1221 TG |
361 | irq_set_chip_and_handler(irq, NULL, NULL); |
362 | irq_set_chip_data(irq, NULL); | |
62579266 RV |
363 | } |
364 | } | |
365 | ||
0cb3fcd7 BB |
366 | static struct resource ab8500_gpio_resources[] = { |
367 | { | |
368 | .name = "GPIO_INT6", | |
369 | .start = AB8500_INT_GPIO6R, | |
370 | .end = AB8500_INT_GPIO41F, | |
371 | .flags = IORESOURCE_IRQ, | |
372 | } | |
373 | }; | |
374 | ||
62579266 RV |
375 | static struct resource ab8500_gpadc_resources[] = { |
376 | { | |
377 | .name = "HW_CONV_END", | |
378 | .start = AB8500_INT_GP_HW_ADC_CONV_END, | |
379 | .end = AB8500_INT_GP_HW_ADC_CONV_END, | |
380 | .flags = IORESOURCE_IRQ, | |
381 | }, | |
382 | { | |
383 | .name = "SW_CONV_END", | |
384 | .start = AB8500_INT_GP_SW_ADC_CONV_END, | |
385 | .end = AB8500_INT_GP_SW_ADC_CONV_END, | |
386 | .flags = IORESOURCE_IRQ, | |
387 | }, | |
388 | }; | |
389 | ||
390 | static struct resource ab8500_rtc_resources[] = { | |
391 | { | |
392 | .name = "60S", | |
393 | .start = AB8500_INT_RTC_60S, | |
394 | .end = AB8500_INT_RTC_60S, | |
395 | .flags = IORESOURCE_IRQ, | |
396 | }, | |
397 | { | |
398 | .name = "ALARM", | |
399 | .start = AB8500_INT_RTC_ALARM, | |
400 | .end = AB8500_INT_RTC_ALARM, | |
401 | .flags = IORESOURCE_IRQ, | |
402 | }, | |
403 | }; | |
404 | ||
77686517 SI |
405 | static struct resource ab8500_poweronkey_db_resources[] = { |
406 | { | |
407 | .name = "ONKEY_DBF", | |
408 | .start = AB8500_INT_PON_KEY1DB_F, | |
409 | .end = AB8500_INT_PON_KEY1DB_F, | |
410 | .flags = IORESOURCE_IRQ, | |
411 | }, | |
412 | { | |
413 | .name = "ONKEY_DBR", | |
414 | .start = AB8500_INT_PON_KEY1DB_R, | |
415 | .end = AB8500_INT_PON_KEY1DB_R, | |
416 | .flags = IORESOURCE_IRQ, | |
417 | }, | |
418 | }; | |
419 | ||
e098aded MW |
420 | static struct resource ab8500_bm_resources[] = { |
421 | { | |
422 | .name = "MAIN_EXT_CH_NOT_OK", | |
423 | .start = AB8500_INT_MAIN_EXT_CH_NOT_OK, | |
424 | .end = AB8500_INT_MAIN_EXT_CH_NOT_OK, | |
425 | .flags = IORESOURCE_IRQ, | |
426 | }, | |
427 | { | |
428 | .name = "BATT_OVV", | |
429 | .start = AB8500_INT_BATT_OVV, | |
430 | .end = AB8500_INT_BATT_OVV, | |
431 | .flags = IORESOURCE_IRQ, | |
432 | }, | |
433 | { | |
434 | .name = "MAIN_CH_UNPLUG_DET", | |
435 | .start = AB8500_INT_MAIN_CH_UNPLUG_DET, | |
436 | .end = AB8500_INT_MAIN_CH_UNPLUG_DET, | |
437 | .flags = IORESOURCE_IRQ, | |
438 | }, | |
439 | { | |
440 | .name = "MAIN_CHARGE_PLUG_DET", | |
441 | .start = AB8500_INT_MAIN_CH_PLUG_DET, | |
442 | .end = AB8500_INT_MAIN_CH_PLUG_DET, | |
443 | .flags = IORESOURCE_IRQ, | |
444 | }, | |
445 | { | |
446 | .name = "VBUS_DET_F", | |
447 | .start = AB8500_INT_VBUS_DET_F, | |
448 | .end = AB8500_INT_VBUS_DET_F, | |
449 | .flags = IORESOURCE_IRQ, | |
450 | }, | |
451 | { | |
452 | .name = "VBUS_DET_R", | |
453 | .start = AB8500_INT_VBUS_DET_R, | |
454 | .end = AB8500_INT_VBUS_DET_R, | |
455 | .flags = IORESOURCE_IRQ, | |
456 | }, | |
457 | { | |
458 | .name = "BAT_CTRL_INDB", | |
459 | .start = AB8500_INT_BAT_CTRL_INDB, | |
460 | .end = AB8500_INT_BAT_CTRL_INDB, | |
461 | .flags = IORESOURCE_IRQ, | |
462 | }, | |
463 | { | |
464 | .name = "CH_WD_EXP", | |
465 | .start = AB8500_INT_CH_WD_EXP, | |
466 | .end = AB8500_INT_CH_WD_EXP, | |
467 | .flags = IORESOURCE_IRQ, | |
468 | }, | |
469 | { | |
470 | .name = "VBUS_OVV", | |
471 | .start = AB8500_INT_VBUS_OVV, | |
472 | .end = AB8500_INT_VBUS_OVV, | |
473 | .flags = IORESOURCE_IRQ, | |
474 | }, | |
475 | { | |
476 | .name = "NCONV_ACCU", | |
477 | .start = AB8500_INT_CCN_CONV_ACC, | |
478 | .end = AB8500_INT_CCN_CONV_ACC, | |
479 | .flags = IORESOURCE_IRQ, | |
480 | }, | |
481 | { | |
482 | .name = "LOW_BAT_F", | |
483 | .start = AB8500_INT_LOW_BAT_F, | |
484 | .end = AB8500_INT_LOW_BAT_F, | |
485 | .flags = IORESOURCE_IRQ, | |
486 | }, | |
487 | { | |
488 | .name = "LOW_BAT_R", | |
489 | .start = AB8500_INT_LOW_BAT_R, | |
490 | .end = AB8500_INT_LOW_BAT_R, | |
491 | .flags = IORESOURCE_IRQ, | |
492 | }, | |
493 | { | |
494 | .name = "BTEMP_LOW", | |
495 | .start = AB8500_INT_BTEMP_LOW, | |
496 | .end = AB8500_INT_BTEMP_LOW, | |
497 | .flags = IORESOURCE_IRQ, | |
498 | }, | |
499 | { | |
500 | .name = "BTEMP_HIGH", | |
501 | .start = AB8500_INT_BTEMP_HIGH, | |
502 | .end = AB8500_INT_BTEMP_HIGH, | |
503 | .flags = IORESOURCE_IRQ, | |
504 | }, | |
505 | { | |
506 | .name = "USB_CHARGER_NOT_OKR", | |
507 | .start = AB8500_INT_USB_CHARGER_NOT_OK, | |
508 | .end = AB8500_INT_USB_CHARGER_NOT_OK, | |
509 | .flags = IORESOURCE_IRQ, | |
510 | }, | |
511 | { | |
512 | .name = "USB_CHARGE_DET_DONE", | |
513 | .start = AB8500_INT_USB_CHG_DET_DONE, | |
514 | .end = AB8500_INT_USB_CHG_DET_DONE, | |
515 | .flags = IORESOURCE_IRQ, | |
516 | }, | |
517 | { | |
518 | .name = "USB_CH_TH_PROT_R", | |
519 | .start = AB8500_INT_USB_CH_TH_PROT_R, | |
520 | .end = AB8500_INT_USB_CH_TH_PROT_R, | |
521 | .flags = IORESOURCE_IRQ, | |
522 | }, | |
523 | { | |
524 | .name = "MAIN_CH_TH_PROT_R", | |
525 | .start = AB8500_INT_MAIN_CH_TH_PROT_R, | |
526 | .end = AB8500_INT_MAIN_CH_TH_PROT_R, | |
527 | .flags = IORESOURCE_IRQ, | |
528 | }, | |
529 | { | |
530 | .name = "USB_CHARGER_NOT_OKF", | |
531 | .start = AB8500_INT_USB_CHARGER_NOT_OKF, | |
532 | .end = AB8500_INT_USB_CHARGER_NOT_OKF, | |
533 | .flags = IORESOURCE_IRQ, | |
534 | }, | |
535 | }; | |
536 | ||
537 | static struct resource ab8500_debug_resources[] = { | |
538 | { | |
539 | .name = "IRQ_FIRST", | |
540 | .start = AB8500_INT_MAIN_EXT_CH_NOT_OK, | |
541 | .end = AB8500_INT_MAIN_EXT_CH_NOT_OK, | |
542 | .flags = IORESOURCE_IRQ, | |
543 | }, | |
544 | { | |
545 | .name = "IRQ_LAST", | |
546 | .start = AB8500_INT_USB_CHARGER_NOT_OKF, | |
547 | .end = AB8500_INT_USB_CHARGER_NOT_OKF, | |
548 | .flags = IORESOURCE_IRQ, | |
549 | }, | |
550 | }; | |
551 | ||
552 | static struct resource ab8500_usb_resources[] = { | |
553 | { | |
554 | .name = "ID_WAKEUP_R", | |
555 | .start = AB8500_INT_ID_WAKEUP_R, | |
556 | .end = AB8500_INT_ID_WAKEUP_R, | |
557 | .flags = IORESOURCE_IRQ, | |
558 | }, | |
559 | { | |
560 | .name = "ID_WAKEUP_F", | |
561 | .start = AB8500_INT_ID_WAKEUP_F, | |
562 | .end = AB8500_INT_ID_WAKEUP_F, | |
563 | .flags = IORESOURCE_IRQ, | |
564 | }, | |
565 | { | |
566 | .name = "VBUS_DET_F", | |
567 | .start = AB8500_INT_VBUS_DET_F, | |
568 | .end = AB8500_INT_VBUS_DET_F, | |
569 | .flags = IORESOURCE_IRQ, | |
570 | }, | |
571 | { | |
572 | .name = "VBUS_DET_R", | |
573 | .start = AB8500_INT_VBUS_DET_R, | |
574 | .end = AB8500_INT_VBUS_DET_R, | |
575 | .flags = IORESOURCE_IRQ, | |
576 | }, | |
92d50a41 MW |
577 | { |
578 | .name = "USB_LINK_STATUS", | |
579 | .start = AB8500_INT_USB_LINK_STATUS, | |
580 | .end = AB8500_INT_USB_LINK_STATUS, | |
581 | .flags = IORESOURCE_IRQ, | |
582 | }, | |
e098aded MW |
583 | }; |
584 | ||
585 | static struct resource ab8500_temp_resources[] = { | |
586 | { | |
587 | .name = "AB8500_TEMP_WARM", | |
588 | .start = AB8500_INT_TEMP_WARM, | |
589 | .end = AB8500_INT_TEMP_WARM, | |
590 | .flags = IORESOURCE_IRQ, | |
591 | }, | |
592 | }; | |
593 | ||
62579266 | 594 | static struct mfd_cell ab8500_devs[] = { |
5814fc35 MW |
595 | #ifdef CONFIG_DEBUG_FS |
596 | { | |
597 | .name = "ab8500-debug", | |
e098aded MW |
598 | .num_resources = ARRAY_SIZE(ab8500_debug_resources), |
599 | .resources = ab8500_debug_resources, | |
5814fc35 MW |
600 | }, |
601 | #endif | |
e098aded MW |
602 | { |
603 | .name = "ab8500-sysctrl", | |
604 | }, | |
605 | { | |
606 | .name = "ab8500-regulator", | |
607 | }, | |
0cb3fcd7 BB |
608 | { |
609 | .name = "ab8500-gpio", | |
610 | .num_resources = ARRAY_SIZE(ab8500_gpio_resources), | |
611 | .resources = ab8500_gpio_resources, | |
612 | }, | |
62579266 RV |
613 | { |
614 | .name = "ab8500-gpadc", | |
615 | .num_resources = ARRAY_SIZE(ab8500_gpadc_resources), | |
616 | .resources = ab8500_gpadc_resources, | |
617 | }, | |
618 | { | |
619 | .name = "ab8500-rtc", | |
620 | .num_resources = ARRAY_SIZE(ab8500_rtc_resources), | |
621 | .resources = ab8500_rtc_resources, | |
622 | }, | |
e098aded MW |
623 | { |
624 | .name = "ab8500-bm", | |
625 | .num_resources = ARRAY_SIZE(ab8500_bm_resources), | |
626 | .resources = ab8500_bm_resources, | |
627 | }, | |
628 | { .name = "ab8500-codec", }, | |
629 | { | |
630 | .name = "ab8500-usb", | |
631 | .num_resources = ARRAY_SIZE(ab8500_usb_resources), | |
632 | .resources = ab8500_usb_resources, | |
633 | }, | |
634 | { | |
635 | .name = "ab8500-poweron-key", | |
636 | .num_resources = ARRAY_SIZE(ab8500_poweronkey_db_resources), | |
637 | .resources = ab8500_poweronkey_db_resources, | |
638 | }, | |
f0f05b1c AM |
639 | { |
640 | .name = "ab8500-pwm", | |
641 | .id = 1, | |
642 | }, | |
643 | { | |
644 | .name = "ab8500-pwm", | |
645 | .id = 2, | |
646 | }, | |
647 | { | |
648 | .name = "ab8500-pwm", | |
649 | .id = 3, | |
650 | }, | |
e098aded | 651 | { .name = "ab8500-leds", }, |
77686517 | 652 | { |
e098aded MW |
653 | .name = "ab8500-denc", |
654 | }, | |
655 | { | |
656 | .name = "ab8500-temp", | |
657 | .num_resources = ARRAY_SIZE(ab8500_temp_resources), | |
658 | .resources = ab8500_temp_resources, | |
77686517 | 659 | }, |
62579266 RV |
660 | }; |
661 | ||
cca69b67 MW |
662 | static ssize_t show_chip_id(struct device *dev, |
663 | struct device_attribute *attr, char *buf) | |
664 | { | |
665 | struct ab8500 *ab8500; | |
666 | ||
667 | ab8500 = dev_get_drvdata(dev); | |
668 | return sprintf(buf, "%#x\n", ab8500 ? ab8500->chip_id : -EINVAL); | |
669 | } | |
670 | ||
e5c238c3 MW |
671 | /* |
672 | * ab8500 has switched off due to (SWITCH_OFF_STATUS): | |
673 | * 0x01 Swoff bit programming | |
674 | * 0x02 Thermal protection activation | |
675 | * 0x04 Vbat lower then BattOk falling threshold | |
676 | * 0x08 Watchdog expired | |
677 | * 0x10 Non presence of 32kHz clock | |
678 | * 0x20 Battery level lower than power on reset threshold | |
679 | * 0x40 Power on key 1 pressed longer than 10 seconds | |
680 | * 0x80 DB8500 thermal shutdown | |
681 | */ | |
682 | static ssize_t show_switch_off_status(struct device *dev, | |
683 | struct device_attribute *attr, char *buf) | |
684 | { | |
685 | int ret; | |
686 | u8 value; | |
687 | struct ab8500 *ab8500; | |
688 | ||
689 | ab8500 = dev_get_drvdata(dev); | |
690 | ret = get_register_interruptible(ab8500, AB8500_RTC, | |
691 | AB8500_SWITCH_OFF_STATUS, &value); | |
692 | if (ret < 0) | |
693 | return ret; | |
694 | return sprintf(buf, "%#x\n", value); | |
695 | } | |
696 | ||
cca69b67 | 697 | static DEVICE_ATTR(chip_id, S_IRUGO, show_chip_id, NULL); |
e5c238c3 | 698 | static DEVICE_ATTR(switch_off_status, S_IRUGO, show_switch_off_status, NULL); |
cca69b67 MW |
699 | |
700 | static struct attribute *ab8500_sysfs_entries[] = { | |
701 | &dev_attr_chip_id.attr, | |
e5c238c3 | 702 | &dev_attr_switch_off_status.attr, |
cca69b67 MW |
703 | NULL, |
704 | }; | |
705 | ||
706 | static struct attribute_group ab8500_attr_group = { | |
707 | .attrs = ab8500_sysfs_entries, | |
708 | }; | |
709 | ||
62579266 RV |
710 | int __devinit ab8500_init(struct ab8500 *ab8500) |
711 | { | |
712 | struct ab8500_platform_data *plat = dev_get_platdata(ab8500->dev); | |
713 | int ret; | |
714 | int i; | |
47c16975 | 715 | u8 value; |
62579266 RV |
716 | |
717 | if (plat) | |
718 | ab8500->irq_base = plat->irq_base; | |
719 | ||
720 | mutex_init(&ab8500->lock); | |
721 | mutex_init(&ab8500->irq_lock); | |
722 | ||
47c16975 MW |
723 | ret = get_register_interruptible(ab8500, AB8500_MISC, |
724 | AB8500_REV_REG, &value); | |
62579266 RV |
725 | if (ret < 0) |
726 | return ret; | |
727 | ||
863dde5b LW |
728 | switch (value) { |
729 | case AB8500_CUTEARLY: | |
730 | case AB8500_CUT1P0: | |
731 | case AB8500_CUT1P1: | |
732 | case AB8500_CUT2P0: | |
733 | case AB8500_CUT3P0: | |
47c16975 | 734 | dev_info(ab8500->dev, "detected chip, revision: %#x\n", value); |
863dde5b LW |
735 | break; |
736 | default: | |
47c16975 | 737 | dev_err(ab8500->dev, "unknown chip, revision: %#x\n", value); |
62579266 RV |
738 | return -EINVAL; |
739 | } | |
47c16975 | 740 | ab8500->chip_id = value; |
62579266 | 741 | |
e5c238c3 MW |
742 | /* |
743 | * ab8500 has switched off due to (SWITCH_OFF_STATUS): | |
744 | * 0x01 Swoff bit programming | |
745 | * 0x02 Thermal protection activation | |
746 | * 0x04 Vbat lower then BattOk falling threshold | |
747 | * 0x08 Watchdog expired | |
748 | * 0x10 Non presence of 32kHz clock | |
749 | * 0x20 Battery level lower than power on reset threshold | |
750 | * 0x40 Power on key 1 pressed longer than 10 seconds | |
751 | * 0x80 DB8500 thermal shutdown | |
752 | */ | |
753 | ||
754 | ret = get_register_interruptible(ab8500, AB8500_RTC, | |
755 | AB8500_SWITCH_OFF_STATUS, &value); | |
756 | if (ret < 0) | |
757 | return ret; | |
758 | dev_info(ab8500->dev, "switch off status: %#x", value); | |
759 | ||
62579266 RV |
760 | if (plat && plat->init) |
761 | plat->init(ab8500); | |
762 | ||
763 | /* Clear and mask all interrupts */ | |
92d50a41 | 764 | for (i = 0; i < AB8500_NUM_IRQ_REGS; i++) { |
863dde5b LW |
765 | /* Interrupt register 12 doesn't exist prior to version 2.0 */ |
766 | if (ab8500_irq_regoffset[i] == 11 && | |
767 | ab8500->chip_id < AB8500_CUT2P0) | |
92d50a41 | 768 | continue; |
62579266 | 769 | |
47c16975 | 770 | get_register_interruptible(ab8500, AB8500_INTERRUPT, |
92d50a41 MW |
771 | AB8500_IT_LATCH1_REG + ab8500_irq_regoffset[i], |
772 | &value); | |
47c16975 | 773 | set_register_interruptible(ab8500, AB8500_INTERRUPT, |
92d50a41 | 774 | AB8500_IT_MASK1_REG + ab8500_irq_regoffset[i], 0xff); |
62579266 RV |
775 | } |
776 | ||
47c16975 MW |
777 | ret = abx500_register_ops(ab8500->dev, &ab8500_ops); |
778 | if (ret) | |
779 | return ret; | |
780 | ||
62579266 RV |
781 | for (i = 0; i < AB8500_NUM_IRQ_REGS; i++) |
782 | ab8500->mask[i] = ab8500->oldmask[i] = 0xff; | |
783 | ||
784 | if (ab8500->irq_base) { | |
785 | ret = ab8500_irq_init(ab8500); | |
786 | if (ret) | |
787 | return ret; | |
788 | ||
789 | ret = request_threaded_irq(ab8500->irq, NULL, ab8500_irq, | |
4f079985 MW |
790 | IRQF_ONESHOT | IRQF_NO_SUSPEND, |
791 | "ab8500", ab8500); | |
62579266 RV |
792 | if (ret) |
793 | goto out_removeirq; | |
794 | } | |
795 | ||
549931f9 | 796 | ret = mfd_add_devices(ab8500->dev, 0, ab8500_devs, |
62579266 RV |
797 | ARRAY_SIZE(ab8500_devs), NULL, |
798 | ab8500->irq_base); | |
799 | if (ret) | |
800 | goto out_freeirq; | |
801 | ||
cca69b67 MW |
802 | ret = sysfs_create_group(&ab8500->dev->kobj, &ab8500_attr_group); |
803 | if (ret) | |
804 | dev_err(ab8500->dev, "error creating sysfs entries\n"); | |
805 | ||
62579266 RV |
806 | return ret; |
807 | ||
808 | out_freeirq: | |
809 | if (ab8500->irq_base) { | |
810 | free_irq(ab8500->irq, ab8500); | |
811 | out_removeirq: | |
812 | ab8500_irq_remove(ab8500); | |
813 | } | |
814 | return ret; | |
815 | } | |
816 | ||
817 | int __devexit ab8500_exit(struct ab8500 *ab8500) | |
818 | { | |
cca69b67 | 819 | sysfs_remove_group(&ab8500->dev->kobj, &ab8500_attr_group); |
62579266 RV |
820 | mfd_remove_devices(ab8500->dev); |
821 | if (ab8500->irq_base) { | |
822 | free_irq(ab8500->irq, ab8500); | |
823 | ab8500_irq_remove(ab8500); | |
824 | } | |
825 | ||
826 | return 0; | |
827 | } | |
828 | ||
adceed62 | 829 | MODULE_AUTHOR("Mattias Wallin, Srinidhi Kasagar, Rabin Vincent"); |
62579266 RV |
830 | MODULE_DESCRIPTION("AB8500 MFD core"); |
831 | MODULE_LICENSE("GPL v2"); |