[deliverable/linux.git] / drivers / mfd / asic3.c

/*
 * driver/mfd/asic3.c
 *
 * Compaq ASIC3 support.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Copyright 2001 Compaq Computer Corporation.
 * Copyright 2004-2005 Phil Blundell
 * Copyright 2007-2008 OpenedHand Ltd.
 *
 * Authors: Phil Blundell <pb@handhelds.org>,
 *	    Samuel Ortiz <sameo@openedhand.com>
 *
 */

#include <linux/version.h>
#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>

#include <linux/mfd/asic3.h>

struct asic3 {
	void __iomem *mapping;
	unsigned int bus_shift;
	unsigned int irq_nr;
	unsigned int irq_base;
	spinlock_t lock;
	u16 irq_bothedge[4];
	struct gpio_chip gpio;
	struct device *dev;
};

static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);

static inline void asic3_write_register(struct asic3 *asic,
				 unsigned int reg, u32 value)
{
	iowrite16(value, asic->mapping +
		  (reg >> asic->bus_shift));
}

static inline u32 asic3_read_register(struct asic3 *asic,
			       unsigned int reg)
{
	return ioread16(asic->mapping +
			(reg >> asic->bus_shift));
}

/* IRQs */
#define MAX_ASIC_ISR_LOOPS    20
#define ASIC3_GPIO_BASE_INCR \
	(ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)

static void asic3_irq_flip_edge(struct asic3 *asic,
				u32 base, int bit)
{
	u16 edge;
	unsigned long flags;

	spin_lock_irqsave(&asic->lock, flags);
	edge = asic3_read_register(asic,
				   base + ASIC3_GPIO_EDGE_TRIGGER);
	edge ^= bit;
	asic3_write_register(asic,
			     base + ASIC3_GPIO_EDGE_TRIGGER, edge);
	spin_unlock_irqrestore(&asic->lock, flags);
}

static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc)
{
	int iter, i;
	unsigned long flags;
	struct asic3 *asic;

	desc->chip->ack(irq);

	asic = desc->handler_data;

	for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
		u32 status;
		int bank;

		spin_lock_irqsave(&asic->lock, flags);
		status = asic3_read_register(asic,
					     ASIC3_OFFSET(INTR, P_INT_STAT));
		spin_unlock_irqrestore(&asic->lock, flags);

		/* Check all ten register bits */
		if ((status & 0x3ff) == 0)
			break;

		/* Handle GPIO IRQs */
		for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {
			if (status & (1 << bank)) {
				unsigned long base, istat;

				base = ASIC3_GPIO_A_BASE
				       + bank * ASIC3_GPIO_BASE_INCR;

				spin_lock_irqsave(&asic->lock, flags);
				istat = asic3_read_register(asic,
							    base +
							    ASIC3_GPIO_INT_STATUS);
				/* Clearing IntStatus */
				asic3_write_register(asic,
						     base +
						     ASIC3_GPIO_INT_STATUS, 0);
				spin_unlock_irqrestore(&asic->lock, flags);

				for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
					int bit = (1 << i);
					unsigned int irqnr;

					if (!(istat & bit))
						continue;

					irqnr = asic->irq_base +
						(ASIC3_GPIOS_PER_BANK * bank)
						+ i;
					desc = irq_desc + irqnr;
					desc->handle_irq(irqnr, desc);
					if (asic->irq_bothedge[bank] & bit)
						asic3_irq_flip_edge(asic, base,
								    bit);
				}
			}
		}

		/* Handle remaining IRQs in the status register */
		for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
			/* They start at bit 4 and go up */
			if (status & (1 << (i - ASIC3_NUM_GPIOS + 4))) {
				desc = irq_desc + asic->irq_base + i;
				desc->handle_irq(asic->irq_base + i,
						 desc);
			}
		}
	}

	if (iter >= MAX_ASIC_ISR_LOOPS)
		dev_err(asic->dev, "interrupt processing overrun\n");
}

static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
{
	int n;

	n = (irq - asic->irq_base) >> 4;

	return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE));
}

static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
{
	return (irq - asic->irq_base) & 0xf;
}

static void asic3_mask_gpio_irq(unsigned int irq)
{
	struct asic3 *asic = get_irq_chip_data(irq);
	u32 val, bank, index;
	unsigned long flags;

	bank = asic3_irq_to_bank(asic, irq);
	index = asic3_irq_to_index(asic, irq);

	spin_lock_irqsave(&asic->lock, flags);
	val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
	val |= 1 << index;
	asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
	spin_unlock_irqrestore(&asic->lock, flags);
}

static void asic3_mask_irq(unsigned int irq)
{
	struct asic3 *asic = get_irq_chip_data(irq);
	int regval;
	unsigned long flags;

	spin_lock_irqsave(&asic->lock, flags);
	regval = asic3_read_register(asic,
				     ASIC3_INTR_BASE +
				     ASIC3_INTR_INT_MASK);

	regval &= ~(ASIC3_INTMASK_MASK0 <<
		    (irq - (asic->irq_base + ASIC3_NUM_GPIOS)));

	asic3_write_register(asic,
			     ASIC3_INTR_BASE +
			     ASIC3_INTR_INT_MASK,
			     regval);
	spin_unlock_irqrestore(&asic->lock, flags);
}

static void asic3_unmask_gpio_irq(unsigned int irq)
{
	struct asic3 *asic = get_irq_chip_data(irq);
	u32 val, bank, index;
	unsigned long flags;

	bank = asic3_irq_to_bank(asic, irq);
	index = asic3_irq_to_index(asic, irq);

	spin_lock_irqsave(&asic->lock, flags);
	val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
	val &= ~(1 << index);
	asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
	spin_unlock_irqrestore(&asic->lock, flags);
}

static void asic3_unmask_irq(unsigned int irq)
{
	struct asic3 *asic = get_irq_chip_data(irq);
	int regval;
	unsigned long flags;

	spin_lock_irqsave(&asic->lock, flags);
	regval = asic3_read_register(asic,
				     ASIC3_INTR_BASE +
				     ASIC3_INTR_INT_MASK);

	regval |= (ASIC3_INTMASK_MASK0 <<
		   (irq - (asic->irq_base + ASIC3_NUM_GPIOS)));

	asic3_write_register(asic,
			     ASIC3_INTR_BASE +
			     ASIC3_INTR_INT_MASK,
			     regval);
	spin_unlock_irqrestore(&asic->lock, flags);
}

static int asic3_gpio_irq_type(unsigned int irq, unsigned int type)
{
	struct asic3 *asic = get_irq_chip_data(irq);
	u32 bank, index;
	u16 trigger, level, edge, bit;
	unsigned long flags;

	bank = asic3_irq_to_bank(asic, irq);
	index = asic3_irq_to_index(asic, irq);
	bit = 1<<index;

	spin_lock_irqsave(&asic->lock, flags);
	level = asic3_read_register(asic,
				    bank + ASIC3_GPIO_LEVEL_TRIGGER);
	edge = asic3_read_register(asic,
				   bank + ASIC3_GPIO_EDGE_TRIGGER);
	trigger = asic3_read_register(asic,
				      bank + ASIC3_GPIO_TRIGGER_TYPE);
	asic->irq_bothedge[(irq - asic->irq_base) >> 4] &= ~bit;

	if (type == IRQT_RISING) {
		trigger |= bit;
		edge |= bit;
	} else if (type == IRQT_FALLING) {
		trigger |= bit;
		edge &= ~bit;
	} else if (type == IRQT_BOTHEDGE) {
		trigger |= bit;
		if (asic3_gpio_get(&asic->gpio, irq - asic->irq_base))
			edge &= ~bit;
		else
			edge |= bit;
		asic->irq_bothedge[(irq - asic->irq_base) >> 4] |= bit;
	} else if (type == IRQT_LOW) {
		trigger &= ~bit;
		level &= ~bit;
	} else if (type == IRQT_HIGH) {
		trigger &= ~bit;
		level |= bit;
	} else {
		/*
		 * if type == IRQT_NOEDGE, we should mask interrupts, but
		 * be careful to not unmask them if mask was also called.
		 * Probably need internal state for mask.
		 */
		dev_notice(asic->dev, "irq type not changed\n");
	}
	asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,
			     level);
	asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,
			     edge);
	asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,
			     trigger);
	spin_unlock_irqrestore(&asic->lock, flags);
	return 0;
}

static struct irq_chip asic3_gpio_irq_chip = {
	.name		= "ASIC3-GPIO",
	.ack		= asic3_mask_gpio_irq,
	.mask		= asic3_mask_gpio_irq,
	.unmask		= asic3_unmask_gpio_irq,
	.set_type	= asic3_gpio_irq_type,
};

static struct irq_chip asic3_irq_chip = {
	.name		= "ASIC3",
	.ack		= asic3_mask_irq,
	.mask		= asic3_mask_irq,
	.unmask		= asic3_unmask_irq,
};

static int __init asic3_irq_probe(struct platform_device *pdev)
{
	struct asic3 *asic = platform_get_drvdata(pdev);
	unsigned long clksel = 0;
	unsigned int irq, irq_base;
	int map_size;

	asic->irq_nr = platform_get_irq(pdev, 0);
	if (asic->irq_nr < 0)
		return asic->irq_nr;

	/* turn on clock to IRQ controller */
	clksel |= CLOCK_SEL_CX;
	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
			     clksel);

	irq_base = asic->irq_base;

	for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
		if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
			set_irq_chip(irq, &asic3_gpio_irq_chip);
		else
			set_irq_chip(irq, &asic3_irq_chip);

		set_irq_chip_data(irq, asic);
		set_irq_handler(irq, handle_level_irq);
		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
	}

	asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
			     ASIC3_INTMASK_GINTMASK);

	set_irq_chained_handler(asic->irq_nr, asic3_irq_demux);
	set_irq_type(asic->irq_nr, IRQT_RISING);
	set_irq_data(asic->irq_nr, asic);

	return 0;
}

static void asic3_irq_remove(struct platform_device *pdev)
{
	struct asic3 *asic = platform_get_drvdata(pdev);
	unsigned int irq, irq_base;

	irq_base = asic->irq_base;

	for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
		set_irq_flags(irq, 0);
		set_irq_handler(irq, NULL);
		set_irq_chip(irq, NULL);
		set_irq_chip_data(irq, NULL);
	}
	set_irq_chained_handler(asic->irq_nr, NULL);
}

/* GPIOs */
static int asic3_gpio_direction(struct gpio_chip *chip,
				unsigned offset, int out)
{
	u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;
	unsigned int gpio_base;
	unsigned long flags;
	struct asic3 *asic;

	asic = container_of(chip, struct asic3, gpio);
	gpio_base = ASIC3_GPIO_TO_BASE(offset);

	if (gpio_base > ASIC3_GPIO_D_BASE) {
		dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
			gpio_base, offset);
		return -EINVAL;
	}

	spin_lock_irqsave(&asic->lock, flags);

	out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);

	/* Input is 0, Output is 1 */
	if (out)
		out_reg |= mask;
	else
		out_reg &= ~mask;

	asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);

	spin_unlock_irqrestore(&asic->lock, flags);

	return 0;

}

static int asic3_gpio_direction_input(struct gpio_chip *chip,
				      unsigned offset)
{
	return asic3_gpio_direction(chip, offset, 0);
}

static int asic3_gpio_direction_output(struct gpio_chip *chip,
				       unsigned offset, int value)
{
	return asic3_gpio_direction(chip, offset, 1);
}

static int asic3_gpio_get(struct gpio_chip *chip,
			  unsigned offset)
{
	unsigned int gpio_base;
	u32 mask = ASIC3_GPIO_TO_MASK(offset);
	struct asic3 *asic;

	asic = container_of(chip, struct asic3, gpio);
	gpio_base = ASIC3_GPIO_TO_BASE(offset);

	if (gpio_base > ASIC3_GPIO_D_BASE) {
		dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
			gpio_base, offset);
		return -EINVAL;
	}

	return asic3_read_register(asic, gpio_base + ASIC3_GPIO_STATUS) & mask;
}

static void asic3_gpio_set(struct gpio_chip *chip,
			   unsigned offset, int value)
{
	u32 mask, out_reg;
	unsigned int gpio_base;
	unsigned long flags;
	struct asic3 *asic;

	asic = container_of(chip, struct asic3, gpio);
	gpio_base = ASIC3_GPIO_TO_BASE(offset);

	if (gpio_base > ASIC3_GPIO_D_BASE) {
		dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
			gpio_base, offset);
		return;
	}

	mask = ASIC3_GPIO_TO_MASK(offset);

	spin_lock_irqsave(&asic->lock, flags);

	out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);

	if (value)
		out_reg |= mask;
	else
		out_reg &= ~mask;

	asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);

	spin_unlock_irqrestore(&asic->lock, flags);

	return;
}

static __init int asic3_gpio_probe(struct platform_device *pdev,
				   u16 *gpio_config, int num)
{
	struct asic3 *asic = platform_get_drvdata(pdev);
	u16 alt_reg[ASIC3_NUM_GPIO_BANKS];
	u16 out_reg[ASIC3_NUM_GPIO_BANKS];
	u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
	int i;

	memzero(alt_reg, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
	memzero(out_reg, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
	memzero(dir_reg, ASIC3_NUM_GPIO_BANKS * sizeof(u16));

	/* Enable all GPIOs */
	asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
	asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff);
	asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff);
	asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);

	for (i = 0; i < num; i++) {
		u8 alt, pin, dir, init, bank_num, bit_num;
		u16 config = gpio_config[i];

		pin = ASIC3_CONFIG_GPIO_PIN(config);
		alt = ASIC3_CONFIG_GPIO_ALT(config);
		dir = ASIC3_CONFIG_GPIO_DIR(config);
		init = ASIC3_CONFIG_GPIO_INIT(config);

		bank_num = ASIC3_GPIO_TO_BANK(pin);
		bit_num = ASIC3_GPIO_TO_BIT(pin);

		alt_reg[bank_num] |= (alt << bit_num);
		out_reg[bank_num] |= (init << bit_num);
		dir_reg[bank_num] |= (dir << bit_num);
	}

	for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {
		asic3_write_register(asic,
				     ASIC3_BANK_TO_BASE(i) +
				     ASIC3_GPIO_DIRECTION,
				     dir_reg[i]);
		asic3_write_register(asic,
				     ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT,
				     out_reg[i]);
		asic3_write_register(asic,
				     ASIC3_BANK_TO_BASE(i) +
				     ASIC3_GPIO_ALT_FUNCTION,
				     alt_reg[i]);
	}

	return gpiochip_add(&asic->gpio);
}

static int asic3_gpio_remove(struct platform_device *pdev)
{
	struct asic3 *asic = platform_get_drvdata(pdev);

	return gpiochip_remove(&asic->gpio);
}


/* Core */
static int __init asic3_probe(struct platform_device *pdev)
{
	struct asic3_platform_data *pdata = pdev->dev.platform_data;
	struct asic3 *asic;
	struct resource *mem;
	unsigned long clksel;
	int ret = 0;

	asic = kzalloc(sizeof(struct asic3), GFP_KERNEL);
	if (asic == NULL) {
		printk(KERN_ERR "kzalloc failed\n");
		return -ENOMEM;
	}

	spin_lock_init(&asic->lock);
	platform_set_drvdata(pdev, asic);
	asic->dev = &pdev->dev;

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!mem) {
		ret = -ENOMEM;
		dev_err(asic->dev, "no MEM resource\n");
		goto out_free;
	}

	map_size = mem->end - mem->start + 1;
	asic->mapping = ioremap(mem->start, map_size);
	if (!asic->mapping) {
		ret = -ENOMEM;
		dev_err(asic->dev, "Couldn't ioremap\n");
		goto out_free;
	}

	asic->irq_base = pdata->irq_base;

	/* calculate bus shift from mem resource */
	asic->bus_shift = 2 - (map_size >> 12);

	clksel = 0;
	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);

	ret = asic3_irq_probe(pdev);
	if (ret < 0) {
		dev_err(asic->dev, "Couldn't probe IRQs\n");
		goto out_unmap;
	}

	asic->gpio.base = pdata->gpio_base;
	asic->gpio.ngpio = ASIC3_NUM_GPIOS;
	asic->gpio.get = asic3_gpio_get;
	asic->gpio.set = asic3_gpio_set;
	asic->gpio.direction_input = asic3_gpio_direction_input;
	asic->gpio.direction_output = asic3_gpio_direction_output;

	ret = asic3_gpio_probe(pdev,
			       pdata->gpio_config,
			       pdata->gpio_config_num);
	if (ret < 0) {
		dev_err(asic->dev, "GPIO probe failed\n");
		goto out_irq;
	}

	dev_info(asic->dev, "ASIC3 Core driver\n");

	return 0;

 out_irq:
	asic3_irq_remove(pdev);

 out_unmap:
	iounmap(asic->mapping);

 out_free:
	kfree(asic);

	return ret;
}

static int asic3_remove(struct platform_device *pdev)
{
	int ret;
	struct asic3 *asic = platform_get_drvdata(pdev);

	ret = asic3_gpio_remove(pdev);
	if (ret < 0)
		return ret;
	asic3_irq_remove(pdev);

	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);

	iounmap(asic->mapping);

	kfree(asic);

	return 0;
}

static void asic3_shutdown(struct platform_device *pdev)
{
}

static struct platform_driver asic3_device_driver = {
	.driver		= {
		.name	= "asic3",
	},
	.remove		= __devexit_p(asic3_remove),
	.shutdown	= asic3_shutdown,
};

static int __init asic3_init(void)
{
	int retval = 0;
	retval = platform_driver_probe(&asic3_device_driver, asic3_probe);
	return retval;
}

subsys_initcall(asic3_init);
Commit	Line	Data
fa9ff4b1 SO	1	/*
	2	* driver/mfd/asic3.c
	3	*
	4	* Compaq ASIC3 support.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* Copyright 2001 Compaq Computer Corporation.
	11	* Copyright 2004-2005 Phil Blundell
6f2384c4	12	* Copyright 2007-2008 OpenedHand Ltd.
fa9ff4b1 SO	13	*
	14	* Authors: Phil Blundell <pb@handhelds.org>,
	15	* Samuel Ortiz <sameo@openedhand.com>
	16	*
	17	*/
	18
	19	#include <linux/version.h>
	20	#include <linux/kernel.h>
	21	#include <linux/irq.h>
6f2384c4	22	#include <linux/gpio.h>
fa9ff4b1 SO	23	#include <linux/io.h>
	24	#include <linux/spinlock.h>
	25	#include <linux/platform_device.h>
	26
	27	#include <linux/mfd/asic3.h>
	28
6f2384c4 SO	29	struct asic3 {
	30	void __iomem *mapping;
	31	unsigned int bus_shift;
	32	unsigned int irq_nr;
	33	unsigned int irq_base;
	34	spinlock_t lock;
	35	u16 irq_bothedge[4];
	36	struct gpio_chip gpio;
	37	struct device *dev;
	38	};
	39
	40	static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);
	41
fa9ff4b1 SO	42	static inline void asic3_write_register(struct asic3 *asic,
	43	unsigned int reg, u32 value)
	44	{
b32661e0	45	iowrite16(value, asic->mapping +
fa9ff4b1 SO	46	(reg >> asic->bus_shift));
	47	}
	48
	49	static inline u32 asic3_read_register(struct asic3 *asic,
	50	unsigned int reg)
	51	{
b32661e0	52	return ioread16(asic->mapping +
fa9ff4b1 SO	53	(reg >> asic->bus_shift));
	54	}
	55
	56	/* IRQs */
	57	#define MAX_ASIC_ISR_LOOPS 20
3b8139f8 SO	58	#define ASIC3_GPIO_BASE_INCR \
3b8139f8 SO	59	(ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
fa9ff4b1 SO	60
	61	static void asic3_irq_flip_edge(struct asic3 *asic,
	62	u32 base, int bit)
	63	{
	64	u16 edge;
	65	unsigned long flags;
	66
	67	spin_lock_irqsave(&asic->lock, flags);
	68	edge = asic3_read_register(asic,
3b8139f8	69	base + ASIC3_GPIO_EDGE_TRIGGER);
fa9ff4b1 SO	70	edge ^= bit;
fa9ff4b1 SO	71	asic3_write_register(asic,
3b8139f8	72	base + ASIC3_GPIO_EDGE_TRIGGER, edge);
fa9ff4b1 SO	73	spin_unlock_irqrestore(&asic->lock, flags);
	74	}
	75
	76	static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc)
	77	{
	78	int iter, i;
	79	unsigned long flags;
	80	struct asic3 *asic;
	81
	82	desc->chip->ack(irq);
	83
	84	asic = desc->handler_data;
	85
	86	for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
	87	u32 status;
	88	int bank;
	89
	90	spin_lock_irqsave(&asic->lock, flags);
	91	status = asic3_read_register(asic,
3b8139f8	92	ASIC3_OFFSET(INTR, P_INT_STAT));
fa9ff4b1 SO	93	spin_unlock_irqrestore(&asic->lock, flags);
	94
	95	/* Check all ten register bits */
	96	if ((status & 0x3ff) == 0)
	97	break;
	98
	99	/* Handle GPIO IRQs */
	100	for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {
	101	if (status & (1 << bank)) {
	102	unsigned long base, istat;
	103
3b8139f8 SO	104	base = ASIC3_GPIO_A_BASE
3b8139f8 SO	105	+ bank * ASIC3_GPIO_BASE_INCR;
fa9ff4b1 SO	106
	107	spin_lock_irqsave(&asic->lock, flags);
	108	istat = asic3_read_register(asic,
	109	base +
3b8139f8	110	ASIC3_GPIO_INT_STATUS);
fa9ff4b1 SO	111	/* Clearing IntStatus */
	112	asic3_write_register(asic,
	113	base +
3b8139f8	114	ASIC3_GPIO_INT_STATUS, 0);
fa9ff4b1 SO	115	spin_unlock_irqrestore(&asic->lock, flags);
	116
	117	for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
	118	int bit = (1 << i);
	119	unsigned int irqnr;
	120
	121	if (!(istat & bit))
	122	continue;
	123
	124	irqnr = asic->irq_base +
	125	(ASIC3_GPIOS_PER_BANK * bank)
	126	+ i;
	127	desc = irq_desc + irqnr;
	128	desc->handle_irq(irqnr, desc);
	129	if (asic->irq_bothedge[bank] & bit)
	130	asic3_irq_flip_edge(asic, base,
	131	bit);
	132	}
	133	}
	134	}
	135
	136	/* Handle remaining IRQs in the status register */
	137	for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
	138	/* They start at bit 4 and go up */
	139	if (status & (1 << (i - ASIC3_NUM_GPIOS + 4))) {
de0d23c1	140	desc = irq_desc + asic->irq_base + i;
fa9ff4b1 SO	141	desc->handle_irq(asic->irq_base + i,
	142	desc);
	143	}
	144	}
	145	}
	146
	147	if (iter >= MAX_ASIC_ISR_LOOPS)
24f4f2ee	148	dev_err(asic->dev, "interrupt processing overrun\n");
fa9ff4b1 SO	149	}
	150
	151	static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
	152	{
	153	int n;
	154
	155	n = (irq - asic->irq_base) >> 4;
	156
3b8139f8	157	return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE));
fa9ff4b1 SO	158	}
	159
	160	static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
	161	{
	162	return (irq - asic->irq_base) & 0xf;
	163	}
	164
	165	static void asic3_mask_gpio_irq(unsigned int irq)
	166	{
	167	struct asic3 *asic = get_irq_chip_data(irq);
	168	u32 val, bank, index;
	169	unsigned long flags;
	170
	171	bank = asic3_irq_to_bank(asic, irq);
	172	index = asic3_irq_to_index(asic, irq);
	173
	174	spin_lock_irqsave(&asic->lock, flags);
3b8139f8	175	val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
fa9ff4b1	176	val \|= 1 << index;
3b8139f8	177	asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
fa9ff4b1 SO	178	spin_unlock_irqrestore(&asic->lock, flags);
	179	}
	180
	181	static void asic3_mask_irq(unsigned int irq)
	182	{
	183	struct asic3 *asic = get_irq_chip_data(irq);
	184	int regval;
	185	unsigned long flags;
	186
	187	spin_lock_irqsave(&asic->lock, flags);
	188	regval = asic3_read_register(asic,
3b8139f8 SO	189	ASIC3_INTR_BASE +
3b8139f8 SO	190	ASIC3_INTR_INT_MASK);
fa9ff4b1 SO	191
	192	regval &= ~(ASIC3_INTMASK_MASK0 <<
	193	(irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
	194
	195	asic3_write_register(asic,
3b8139f8 SO	196	ASIC3_INTR_BASE +
3b8139f8 SO	197	ASIC3_INTR_INT_MASK,
fa9ff4b1 SO	198	regval);
	199	spin_unlock_irqrestore(&asic->lock, flags);
	200	}
	201
	202	static void asic3_unmask_gpio_irq(unsigned int irq)
	203	{
	204	struct asic3 *asic = get_irq_chip_data(irq);
	205	u32 val, bank, index;
	206	unsigned long flags;
	207
	208	bank = asic3_irq_to_bank(asic, irq);
	209	index = asic3_irq_to_index(asic, irq);
	210
	211	spin_lock_irqsave(&asic->lock, flags);
3b8139f8	212	val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
fa9ff4b1	213	val &= ~(1 << index);
3b8139f8	214	asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
fa9ff4b1 SO	215	spin_unlock_irqrestore(&asic->lock, flags);
	216	}
	217
	218	static void asic3_unmask_irq(unsigned int irq)
	219	{
	220	struct asic3 *asic = get_irq_chip_data(irq);
	221	int regval;
	222	unsigned long flags;
	223
	224	spin_lock_irqsave(&asic->lock, flags);
	225	regval = asic3_read_register(asic,
3b8139f8 SO	226	ASIC3_INTR_BASE +
3b8139f8 SO	227	ASIC3_INTR_INT_MASK);
fa9ff4b1 SO	228
	229	regval \|= (ASIC3_INTMASK_MASK0 <<
	230	(irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
	231
	232	asic3_write_register(asic,
3b8139f8 SO	233	ASIC3_INTR_BASE +
3b8139f8 SO	234	ASIC3_INTR_INT_MASK,
fa9ff4b1 SO	235	regval);
	236	spin_unlock_irqrestore(&asic->lock, flags);
	237	}
	238
	239	static int asic3_gpio_irq_type(unsigned int irq, unsigned int type)
	240	{
	241	struct asic3 *asic = get_irq_chip_data(irq);
	242	u32 bank, index;
	243	u16 trigger, level, edge, bit;
	244	unsigned long flags;
	245
	246	bank = asic3_irq_to_bank(asic, irq);
	247	index = asic3_irq_to_index(asic, irq);
	248	bit = 1<<index;
	249
	250	spin_lock_irqsave(&asic->lock, flags);
	251	level = asic3_read_register(asic,
3b8139f8	252	bank + ASIC3_GPIO_LEVEL_TRIGGER);
fa9ff4b1	253	edge = asic3_read_register(asic,
3b8139f8	254	bank + ASIC3_GPIO_EDGE_TRIGGER);
fa9ff4b1	255	trigger = asic3_read_register(asic,
3b8139f8	256	bank + ASIC3_GPIO_TRIGGER_TYPE);
fa9ff4b1 SO	257	asic->irq_bothedge[(irq - asic->irq_base) >> 4] &= ~bit;
	258
	259	if (type == IRQT_RISING) {
	260	trigger \|= bit;
	261	edge \|= bit;
	262	} else if (type == IRQT_FALLING) {
	263	trigger \|= bit;
	264	edge &= ~bit;
	265	} else if (type == IRQT_BOTHEDGE) {
	266	trigger \|= bit;
6f2384c4	267	if (asic3_gpio_get(&asic->gpio, irq - asic->irq_base))
fa9ff4b1 SO	268	edge &= ~bit;
	269	else
	270	edge \|= bit;
	271	asic->irq_bothedge[(irq - asic->irq_base) >> 4] \|= bit;
	272	} else if (type == IRQT_LOW) {
	273	trigger &= ~bit;
	274	level &= ~bit;
	275	} else if (type == IRQT_HIGH) {
	276	trigger &= ~bit;
	277	level \|= bit;
	278	} else {
	279	/*
	280	* if type == IRQT_NOEDGE, we should mask interrupts, but
	281	* be careful to not unmask them if mask was also called.
	282	* Probably need internal state for mask.
	283	*/
24f4f2ee	284	dev_notice(asic->dev, "irq type not changed\n");
fa9ff4b1	285	}
3b8139f8	286	asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,
fa9ff4b1	287	level);
3b8139f8	288	asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,
fa9ff4b1	289	edge);
3b8139f8	290	asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,
fa9ff4b1 SO	291	trigger);
	292	spin_unlock_irqrestore(&asic->lock, flags);
	293	return 0;
	294	}
	295
	296	static struct irq_chip asic3_gpio_irq_chip = {
	297	.name = "ASIC3-GPIO",
	298	.ack = asic3_mask_gpio_irq,
	299	.mask = asic3_mask_gpio_irq,
	300	.unmask = asic3_unmask_gpio_irq,
	301	.set_type = asic3_gpio_irq_type,
	302	};
	303
	304	static struct irq_chip asic3_irq_chip = {
	305	.name = "ASIC3",
	306	.ack = asic3_mask_irq,
	307	.mask = asic3_mask_irq,
	308	.unmask = asic3_unmask_irq,
	309	};
	310
065032f6	311	static int __init asic3_irq_probe(struct platform_device *pdev)
fa9ff4b1 SO	312	{
	313	struct asic3 *asic = platform_get_drvdata(pdev);
	314	unsigned long clksel = 0;
	315	unsigned int irq, irq_base;
99cdb0c8	316	int map_size;
fa9ff4b1 SO	317
	318	asic->irq_nr = platform_get_irq(pdev, 0);
	319	if (asic->irq_nr < 0)
	320	return asic->irq_nr;
	321
	322	/* turn on clock to IRQ controller */
	323	clksel \|= CLOCK_SEL_CX;
	324	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
	325	clksel);
	326
	327	irq_base = asic->irq_base;
	328
	329	for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
	330	if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
	331	set_irq_chip(irq, &asic3_gpio_irq_chip);
	332	else
	333	set_irq_chip(irq, &asic3_irq_chip);
	334
	335	set_irq_chip_data(irq, asic);
	336	set_irq_handler(irq, handle_level_irq);
	337	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	338	}
	339
3b8139f8	340	asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
fa9ff4b1 SO	341	ASIC3_INTMASK_GINTMASK);
	342
	343	set_irq_chained_handler(asic->irq_nr, asic3_irq_demux);
	344	set_irq_type(asic->irq_nr, IRQT_RISING);
	345	set_irq_data(asic->irq_nr, asic);
	346
	347	return 0;
	348	}
	349
	350	static void asic3_irq_remove(struct platform_device *pdev)
	351	{
	352	struct asic3 *asic = platform_get_drvdata(pdev);
	353	unsigned int irq, irq_base;
	354
	355	irq_base = asic->irq_base;
	356
	357	for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
	358	set_irq_flags(irq, 0);
	359	set_irq_handler(irq, NULL);
	360	set_irq_chip(irq, NULL);
	361	set_irq_chip_data(irq, NULL);
	362	}
	363	set_irq_chained_handler(asic->irq_nr, NULL);
	364	}
	365
	366	/* GPIOs */
6f2384c4 SO	367	static int asic3_gpio_direction(struct gpio_chip *chip,
	368	unsigned offset, int out)
	369	{
	370	u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;
	371	unsigned int gpio_base;
	372	unsigned long flags;
	373	struct asic3 *asic;
	374
	375	asic = container_of(chip, struct asic3, gpio);
	376	gpio_base = ASIC3_GPIO_TO_BASE(offset);
	377
3b8139f8	378	if (gpio_base > ASIC3_GPIO_D_BASE) {
24f4f2ee SO	379	dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
24f4f2ee SO	380	gpio_base, offset);
6f2384c4 SO	381	return -EINVAL;
	382	}
	383
	384	spin_lock_irqsave(&asic->lock, flags);
	385
3b8139f8	386	out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);
6f2384c4 SO	387
	388	/* Input is 0, Output is 1 */
	389	if (out)
	390	out_reg \|= mask;
	391	else
	392	out_reg &= ~mask;
	393
3b8139f8	394	asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);
6f2384c4 SO	395
	396	spin_unlock_irqrestore(&asic->lock, flags);
	397
	398	return 0;
	399
	400	}
	401
	402	static int asic3_gpio_direction_input(struct gpio_chip *chip,
	403	unsigned offset)
	404	{
	405	return asic3_gpio_direction(chip, offset, 0);
	406	}
	407
	408	static int asic3_gpio_direction_output(struct gpio_chip *chip,
	409	unsigned offset, int value)
	410	{
	411	return asic3_gpio_direction(chip, offset, 1);
	412	}
	413
	414	static int asic3_gpio_get(struct gpio_chip *chip,
	415	unsigned offset)
	416	{
	417	unsigned int gpio_base;
	418	u32 mask = ASIC3_GPIO_TO_MASK(offset);
	419	struct asic3 *asic;
	420
	421	asic = container_of(chip, struct asic3, gpio);
	422	gpio_base = ASIC3_GPIO_TO_BASE(offset);
	423
3b8139f8	424	if (gpio_base > ASIC3_GPIO_D_BASE) {
24f4f2ee SO	425	dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
24f4f2ee SO	426	gpio_base, offset);
6f2384c4 SO	427	return -EINVAL;
	428	}
	429
3b8139f8	430	return asic3_read_register(asic, gpio_base + ASIC3_GPIO_STATUS) & mask;
6f2384c4 SO	431	}
	432
	433	static void asic3_gpio_set(struct gpio_chip *chip,
	434	unsigned offset, int value)
	435	{
	436	u32 mask, out_reg;
	437	unsigned int gpio_base;
	438	unsigned long flags;
	439	struct asic3 *asic;
	440
	441	asic = container_of(chip, struct asic3, gpio);
	442	gpio_base = ASIC3_GPIO_TO_BASE(offset);
	443
3b8139f8	444	if (gpio_base > ASIC3_GPIO_D_BASE) {
24f4f2ee SO	445	dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
24f4f2ee SO	446	gpio_base, offset);
6f2384c4 SO	447	return;
	448	}
	449
	450	mask = ASIC3_GPIO_TO_MASK(offset);
	451
	452	spin_lock_irqsave(&asic->lock, flags);
	453
3b8139f8	454	out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);
6f2384c4 SO	455
	456	if (value)
	457	out_reg \|= mask;
	458	else
	459	out_reg &= ~mask;
	460
3b8139f8	461	asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);
6f2384c4 SO	462
	463	spin_unlock_irqrestore(&asic->lock, flags);
	464
	465	return;
	466	}
	467
065032f6 PZ	468	static __init int asic3_gpio_probe(struct platform_device *pdev,
065032f6 PZ	469	u16 *gpio_config, int num)
fa9ff4b1	470	{
fa9ff4b1	471	struct asic3 *asic = platform_get_drvdata(pdev);
3b26bf17 SO	472	u16 alt_reg[ASIC3_NUM_GPIO_BANKS];
	473	u16 out_reg[ASIC3_NUM_GPIO_BANKS];
	474	u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
	475	int i;
fa9ff4b1	476
786bef37 PZ	477	memzero(alt_reg, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
	478	memzero(out_reg, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
	479	memzero(dir_reg, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
3b26bf17 SO	480
3b26bf17 SO	481	/* Enable all GPIOs */
3b8139f8 SO	482	asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
	483	asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff);
	484	asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff);
	485	asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);
fa9ff4b1	486
3b26bf17 SO	487	for (i = 0; i < num; i++) {
	488	u8 alt, pin, dir, init, bank_num, bit_num;
	489	u16 config = gpio_config[i];
	490
	491	pin = ASIC3_CONFIG_GPIO_PIN(config);
	492	alt = ASIC3_CONFIG_GPIO_ALT(config);
	493	dir = ASIC3_CONFIG_GPIO_DIR(config);
	494	init = ASIC3_CONFIG_GPIO_INIT(config);
	495
	496	bank_num = ASIC3_GPIO_TO_BANK(pin);
	497	bit_num = ASIC3_GPIO_TO_BIT(pin);
	498
	499	alt_reg[bank_num] \|= (alt << bit_num);
	500	out_reg[bank_num] \|= (init << bit_num);
	501	dir_reg[bank_num] \|= (dir << bit_num);
	502	}
	503
	504	for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {
	505	asic3_write_register(asic,
	506	ASIC3_BANK_TO_BASE(i) +
3b8139f8	507	ASIC3_GPIO_DIRECTION,
3b26bf17 SO	508	dir_reg[i]);
3b26bf17 SO	509	asic3_write_register(asic,
3b8139f8	510	ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT,
3b26bf17 SO	511	out_reg[i]);
	512	asic3_write_register(asic,
	513	ASIC3_BANK_TO_BASE(i) +
3b8139f8	514	ASIC3_GPIO_ALT_FUNCTION,
3b26bf17	515	alt_reg[i]);
fa9ff4b1 SO	516	}
fa9ff4b1 SO	517
6f2384c4	518	return gpiochip_add(&asic->gpio);
fa9ff4b1 SO	519	}
fa9ff4b1 SO	520
6f2384c4	521	static int asic3_gpio_remove(struct platform_device *pdev)
fa9ff4b1	522	{
6f2384c4 SO	523	struct asic3 *asic = platform_get_drvdata(pdev);
	524
	525	return gpiochip_remove(&asic->gpio);
fa9ff4b1 SO	526	}
	527
	528
	529	/* Core */
065032f6	530	static int __init asic3_probe(struct platform_device *pdev)
fa9ff4b1 SO	531	{
	532	struct asic3_platform_data *pdata = pdev->dev.platform_data;
	533	struct asic3 *asic;
	534	struct resource *mem;
	535	unsigned long clksel;
6f2384c4	536	int ret = 0;
fa9ff4b1 SO	537
fa9ff4b1 SO	538	asic = kzalloc(sizeof(struct asic3), GFP_KERNEL);
6f2384c4 SO	539	if (asic == NULL) {
6f2384c4 SO	540	printk(KERN_ERR "kzalloc failed\n");
fa9ff4b1	541	return -ENOMEM;
6f2384c4	542	}
fa9ff4b1 SO	543
	544	spin_lock_init(&asic->lock);
	545	platform_set_drvdata(pdev, asic);
	546	asic->dev = &pdev->dev;
	547
	548	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	549	if (!mem) {
	550	ret = -ENOMEM;
24f4f2ee	551	dev_err(asic->dev, "no MEM resource\n");
6f2384c4	552	goto out_free;
fa9ff4b1 SO	553	}
fa9ff4b1 SO	554
99cdb0c8 PZ	555	map_size = mem->end - mem->start + 1;
99cdb0c8 PZ	556	asic->mapping = ioremap(mem->start, map_size);
fa9ff4b1 SO	557	if (!asic->mapping) {
fa9ff4b1 SO	558	ret = -ENOMEM;
24f4f2ee	559	dev_err(asic->dev, "Couldn't ioremap\n");
6f2384c4	560	goto out_free;
fa9ff4b1 SO	561	}
	562
	563	asic->irq_base = pdata->irq_base;
	564
99cdb0c8 PZ	565	/* calculate bus shift from mem resource */
99cdb0c8 PZ	566	asic->bus_shift = 2 - (map_size >> 12);
fa9ff4b1 SO	567
	568	clksel = 0;
	569	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);
	570
	571	ret = asic3_irq_probe(pdev);
	572	if (ret < 0) {
24f4f2ee	573	dev_err(asic->dev, "Couldn't probe IRQs\n");
6f2384c4 SO	574	goto out_unmap;
	575	}
	576
	577	asic->gpio.base = pdata->gpio_base;
	578	asic->gpio.ngpio = ASIC3_NUM_GPIOS;
	579	asic->gpio.get = asic3_gpio_get;
	580	asic->gpio.set = asic3_gpio_set;
	581	asic->gpio.direction_input = asic3_gpio_direction_input;
	582	asic->gpio.direction_output = asic3_gpio_direction_output;
	583
3b26bf17 SO	584	ret = asic3_gpio_probe(pdev,
	585	pdata->gpio_config,
	586	pdata->gpio_config_num);
6f2384c4	587	if (ret < 0) {
24f4f2ee	588	dev_err(asic->dev, "GPIO probe failed\n");
6f2384c4	589	goto out_irq;
fa9ff4b1	590	}
fa9ff4b1	591
24f4f2ee	592	dev_info(asic->dev, "ASIC3 Core driver\n");
fa9ff4b1 SO	593
	594	return 0;
	595
6f2384c4 SO	596	out_irq:
	597	asic3_irq_remove(pdev);
	598
	599	out_unmap:
fa9ff4b1	600	iounmap(asic->mapping);
6f2384c4 SO	601
6f2384c4 SO	602	out_free:
fa9ff4b1 SO	603	kfree(asic);
	604
	605	return ret;
	606	}
	607
	608	static int asic3_remove(struct platform_device *pdev)
	609	{
6f2384c4	610	int ret;
fa9ff4b1 SO	611	struct asic3 *asic = platform_get_drvdata(pdev);
fa9ff4b1 SO	612
6f2384c4 SO	613	ret = asic3_gpio_remove(pdev);
	614	if (ret < 0)
	615	return ret;
fa9ff4b1 SO	616	asic3_irq_remove(pdev);
	617
	618	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);
	619
	620	iounmap(asic->mapping);
	621
	622	kfree(asic);
	623
	624	return 0;
	625	}
	626
	627	static void asic3_shutdown(struct platform_device *pdev)
	628	{
	629	}
	630
	631	static struct platform_driver asic3_device_driver = {
	632	.driver = {
	633	.name = "asic3",
	634	},
fa9ff4b1 SO	635	.remove = __devexit_p(asic3_remove),
	636	.shutdown = asic3_shutdown,
	637	};
	638
	639	static int __init asic3_init(void)
	640	{
	641	int retval = 0;
065032f6	642	retval = platform_driver_probe(&asic3_device_driver, asic3_probe);
fa9ff4b1 SO	643	return retval;
	644	}
	645
	646	subsys_initcall(asic3_init);