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fa9ff4b1 SO |
1 | /* |
2 | * driver/mfd/asic3.c | |
3 | * | |
4 | * Compaq ASIC3 support. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * Copyright 2001 Compaq Computer Corporation. | |
11 | * Copyright 2004-2005 Phil Blundell | |
6f2384c4 | 12 | * Copyright 2007-2008 OpenedHand Ltd. |
fa9ff4b1 SO |
13 | * |
14 | * Authors: Phil Blundell <pb@handhelds.org>, | |
15 | * Samuel Ortiz <sameo@openedhand.com> | |
16 | * | |
17 | */ | |
18 | ||
fa9ff4b1 SO |
19 | #include <linux/kernel.h> |
20 | #include <linux/irq.h> | |
6f2384c4 | 21 | #include <linux/gpio.h> |
fa9ff4b1 SO |
22 | #include <linux/io.h> |
23 | #include <linux/spinlock.h> | |
24 | #include <linux/platform_device.h> | |
25 | ||
26 | #include <linux/mfd/asic3.h> | |
27 | ||
e956a2a8 PZ |
28 | enum { |
29 | ASIC3_CLOCK_SPI, | |
30 | ASIC3_CLOCK_OWM, | |
31 | ASIC3_CLOCK_PWM0, | |
32 | ASIC3_CLOCK_PWM1, | |
33 | ASIC3_CLOCK_LED0, | |
34 | ASIC3_CLOCK_LED1, | |
35 | ASIC3_CLOCK_LED2, | |
36 | ASIC3_CLOCK_SD_HOST, | |
37 | ASIC3_CLOCK_SD_BUS, | |
38 | ASIC3_CLOCK_SMBUS, | |
39 | ASIC3_CLOCK_EX0, | |
40 | ASIC3_CLOCK_EX1, | |
41 | }; | |
42 | ||
43 | struct asic3_clk { | |
44 | int enabled; | |
45 | unsigned int cdex; | |
46 | unsigned long rate; | |
47 | }; | |
48 | ||
49 | #define INIT_CDEX(_name, _rate) \ | |
50 | [ASIC3_CLOCK_##_name] = { \ | |
51 | .cdex = CLOCK_CDEX_##_name, \ | |
52 | .rate = _rate, \ | |
53 | } | |
54 | ||
55 | struct asic3_clk asic3_clk_init[] __initdata = { | |
56 | INIT_CDEX(SPI, 0), | |
57 | INIT_CDEX(OWM, 5000000), | |
58 | INIT_CDEX(PWM0, 0), | |
59 | INIT_CDEX(PWM1, 0), | |
60 | INIT_CDEX(LED0, 0), | |
61 | INIT_CDEX(LED1, 0), | |
62 | INIT_CDEX(LED2, 0), | |
63 | INIT_CDEX(SD_HOST, 24576000), | |
64 | INIT_CDEX(SD_BUS, 12288000), | |
65 | INIT_CDEX(SMBUS, 0), | |
66 | INIT_CDEX(EX0, 32768), | |
67 | INIT_CDEX(EX1, 24576000), | |
68 | }; | |
69 | ||
6f2384c4 SO |
70 | struct asic3 { |
71 | void __iomem *mapping; | |
72 | unsigned int bus_shift; | |
73 | unsigned int irq_nr; | |
74 | unsigned int irq_base; | |
75 | spinlock_t lock; | |
76 | u16 irq_bothedge[4]; | |
77 | struct gpio_chip gpio; | |
78 | struct device *dev; | |
e956a2a8 PZ |
79 | |
80 | struct asic3_clk clocks[ARRAY_SIZE(asic3_clk_init)]; | |
6f2384c4 SO |
81 | }; |
82 | ||
83 | static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset); | |
84 | ||
fa9ff4b1 SO |
85 | static inline void asic3_write_register(struct asic3 *asic, |
86 | unsigned int reg, u32 value) | |
87 | { | |
b32661e0 | 88 | iowrite16(value, asic->mapping + |
fa9ff4b1 SO |
89 | (reg >> asic->bus_shift)); |
90 | } | |
91 | ||
92 | static inline u32 asic3_read_register(struct asic3 *asic, | |
93 | unsigned int reg) | |
94 | { | |
b32661e0 | 95 | return ioread16(asic->mapping + |
fa9ff4b1 SO |
96 | (reg >> asic->bus_shift)); |
97 | } | |
98 | ||
6483c1b5 PZ |
99 | void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set) |
100 | { | |
101 | unsigned long flags; | |
102 | u32 val; | |
103 | ||
104 | spin_lock_irqsave(&asic->lock, flags); | |
105 | val = asic3_read_register(asic, reg); | |
106 | if (set) | |
107 | val |= bits; | |
108 | else | |
109 | val &= ~bits; | |
110 | asic3_write_register(asic, reg, val); | |
111 | spin_unlock_irqrestore(&asic->lock, flags); | |
112 | } | |
113 | ||
fa9ff4b1 SO |
114 | /* IRQs */ |
115 | #define MAX_ASIC_ISR_LOOPS 20 | |
3b8139f8 SO |
116 | #define ASIC3_GPIO_BASE_INCR \ |
117 | (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE) | |
fa9ff4b1 SO |
118 | |
119 | static void asic3_irq_flip_edge(struct asic3 *asic, | |
120 | u32 base, int bit) | |
121 | { | |
122 | u16 edge; | |
123 | unsigned long flags; | |
124 | ||
125 | spin_lock_irqsave(&asic->lock, flags); | |
126 | edge = asic3_read_register(asic, | |
3b8139f8 | 127 | base + ASIC3_GPIO_EDGE_TRIGGER); |
fa9ff4b1 SO |
128 | edge ^= bit; |
129 | asic3_write_register(asic, | |
3b8139f8 | 130 | base + ASIC3_GPIO_EDGE_TRIGGER, edge); |
fa9ff4b1 SO |
131 | spin_unlock_irqrestore(&asic->lock, flags); |
132 | } | |
133 | ||
134 | static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc) | |
135 | { | |
136 | int iter, i; | |
137 | unsigned long flags; | |
138 | struct asic3 *asic; | |
139 | ||
140 | desc->chip->ack(irq); | |
141 | ||
142 | asic = desc->handler_data; | |
143 | ||
144 | for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) { | |
145 | u32 status; | |
146 | int bank; | |
147 | ||
148 | spin_lock_irqsave(&asic->lock, flags); | |
149 | status = asic3_read_register(asic, | |
3b8139f8 | 150 | ASIC3_OFFSET(INTR, P_INT_STAT)); |
fa9ff4b1 SO |
151 | spin_unlock_irqrestore(&asic->lock, flags); |
152 | ||
153 | /* Check all ten register bits */ | |
154 | if ((status & 0x3ff) == 0) | |
155 | break; | |
156 | ||
157 | /* Handle GPIO IRQs */ | |
158 | for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) { | |
159 | if (status & (1 << bank)) { | |
160 | unsigned long base, istat; | |
161 | ||
3b8139f8 SO |
162 | base = ASIC3_GPIO_A_BASE |
163 | + bank * ASIC3_GPIO_BASE_INCR; | |
fa9ff4b1 SO |
164 | |
165 | spin_lock_irqsave(&asic->lock, flags); | |
166 | istat = asic3_read_register(asic, | |
167 | base + | |
3b8139f8 | 168 | ASIC3_GPIO_INT_STATUS); |
fa9ff4b1 SO |
169 | /* Clearing IntStatus */ |
170 | asic3_write_register(asic, | |
171 | base + | |
3b8139f8 | 172 | ASIC3_GPIO_INT_STATUS, 0); |
fa9ff4b1 SO |
173 | spin_unlock_irqrestore(&asic->lock, flags); |
174 | ||
175 | for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) { | |
176 | int bit = (1 << i); | |
177 | unsigned int irqnr; | |
178 | ||
179 | if (!(istat & bit)) | |
180 | continue; | |
181 | ||
182 | irqnr = asic->irq_base + | |
183 | (ASIC3_GPIOS_PER_BANK * bank) | |
184 | + i; | |
08678b08 | 185 | desc = irq_to_desc(irqnr); |
fa9ff4b1 SO |
186 | desc->handle_irq(irqnr, desc); |
187 | if (asic->irq_bothedge[bank] & bit) | |
188 | asic3_irq_flip_edge(asic, base, | |
189 | bit); | |
190 | } | |
191 | } | |
192 | } | |
193 | ||
194 | /* Handle remaining IRQs in the status register */ | |
195 | for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) { | |
196 | /* They start at bit 4 and go up */ | |
197 | if (status & (1 << (i - ASIC3_NUM_GPIOS + 4))) { | |
08678b08 | 198 | desc = irq_to_desc(asic->irq_base + i); |
fa9ff4b1 SO |
199 | desc->handle_irq(asic->irq_base + i, |
200 | desc); | |
201 | } | |
202 | } | |
203 | } | |
204 | ||
205 | if (iter >= MAX_ASIC_ISR_LOOPS) | |
24f4f2ee | 206 | dev_err(asic->dev, "interrupt processing overrun\n"); |
fa9ff4b1 SO |
207 | } |
208 | ||
209 | static inline int asic3_irq_to_bank(struct asic3 *asic, int irq) | |
210 | { | |
211 | int n; | |
212 | ||
213 | n = (irq - asic->irq_base) >> 4; | |
214 | ||
3b8139f8 | 215 | return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)); |
fa9ff4b1 SO |
216 | } |
217 | ||
218 | static inline int asic3_irq_to_index(struct asic3 *asic, int irq) | |
219 | { | |
220 | return (irq - asic->irq_base) & 0xf; | |
221 | } | |
222 | ||
223 | static void asic3_mask_gpio_irq(unsigned int irq) | |
224 | { | |
225 | struct asic3 *asic = get_irq_chip_data(irq); | |
226 | u32 val, bank, index; | |
227 | unsigned long flags; | |
228 | ||
229 | bank = asic3_irq_to_bank(asic, irq); | |
230 | index = asic3_irq_to_index(asic, irq); | |
231 | ||
232 | spin_lock_irqsave(&asic->lock, flags); | |
3b8139f8 | 233 | val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK); |
fa9ff4b1 | 234 | val |= 1 << index; |
3b8139f8 | 235 | asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val); |
fa9ff4b1 SO |
236 | spin_unlock_irqrestore(&asic->lock, flags); |
237 | } | |
238 | ||
239 | static void asic3_mask_irq(unsigned int irq) | |
240 | { | |
241 | struct asic3 *asic = get_irq_chip_data(irq); | |
242 | int regval; | |
243 | unsigned long flags; | |
244 | ||
245 | spin_lock_irqsave(&asic->lock, flags); | |
246 | regval = asic3_read_register(asic, | |
3b8139f8 SO |
247 | ASIC3_INTR_BASE + |
248 | ASIC3_INTR_INT_MASK); | |
fa9ff4b1 SO |
249 | |
250 | regval &= ~(ASIC3_INTMASK_MASK0 << | |
251 | (irq - (asic->irq_base + ASIC3_NUM_GPIOS))); | |
252 | ||
253 | asic3_write_register(asic, | |
3b8139f8 SO |
254 | ASIC3_INTR_BASE + |
255 | ASIC3_INTR_INT_MASK, | |
fa9ff4b1 SO |
256 | regval); |
257 | spin_unlock_irqrestore(&asic->lock, flags); | |
258 | } | |
259 | ||
260 | static void asic3_unmask_gpio_irq(unsigned int irq) | |
261 | { | |
262 | struct asic3 *asic = get_irq_chip_data(irq); | |
263 | u32 val, bank, index; | |
264 | unsigned long flags; | |
265 | ||
266 | bank = asic3_irq_to_bank(asic, irq); | |
267 | index = asic3_irq_to_index(asic, irq); | |
268 | ||
269 | spin_lock_irqsave(&asic->lock, flags); | |
3b8139f8 | 270 | val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK); |
fa9ff4b1 | 271 | val &= ~(1 << index); |
3b8139f8 | 272 | asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val); |
fa9ff4b1 SO |
273 | spin_unlock_irqrestore(&asic->lock, flags); |
274 | } | |
275 | ||
276 | static void asic3_unmask_irq(unsigned int irq) | |
277 | { | |
278 | struct asic3 *asic = get_irq_chip_data(irq); | |
279 | int regval; | |
280 | unsigned long flags; | |
281 | ||
282 | spin_lock_irqsave(&asic->lock, flags); | |
283 | regval = asic3_read_register(asic, | |
3b8139f8 SO |
284 | ASIC3_INTR_BASE + |
285 | ASIC3_INTR_INT_MASK); | |
fa9ff4b1 SO |
286 | |
287 | regval |= (ASIC3_INTMASK_MASK0 << | |
288 | (irq - (asic->irq_base + ASIC3_NUM_GPIOS))); | |
289 | ||
290 | asic3_write_register(asic, | |
3b8139f8 SO |
291 | ASIC3_INTR_BASE + |
292 | ASIC3_INTR_INT_MASK, | |
fa9ff4b1 SO |
293 | regval); |
294 | spin_unlock_irqrestore(&asic->lock, flags); | |
295 | } | |
296 | ||
297 | static int asic3_gpio_irq_type(unsigned int irq, unsigned int type) | |
298 | { | |
299 | struct asic3 *asic = get_irq_chip_data(irq); | |
300 | u32 bank, index; | |
301 | u16 trigger, level, edge, bit; | |
302 | unsigned long flags; | |
303 | ||
304 | bank = asic3_irq_to_bank(asic, irq); | |
305 | index = asic3_irq_to_index(asic, irq); | |
306 | bit = 1<<index; | |
307 | ||
308 | spin_lock_irqsave(&asic->lock, flags); | |
309 | level = asic3_read_register(asic, | |
3b8139f8 | 310 | bank + ASIC3_GPIO_LEVEL_TRIGGER); |
fa9ff4b1 | 311 | edge = asic3_read_register(asic, |
3b8139f8 | 312 | bank + ASIC3_GPIO_EDGE_TRIGGER); |
fa9ff4b1 | 313 | trigger = asic3_read_register(asic, |
3b8139f8 | 314 | bank + ASIC3_GPIO_TRIGGER_TYPE); |
fa9ff4b1 SO |
315 | asic->irq_bothedge[(irq - asic->irq_base) >> 4] &= ~bit; |
316 | ||
6cab4860 | 317 | if (type == IRQ_TYPE_EDGE_RISING) { |
fa9ff4b1 SO |
318 | trigger |= bit; |
319 | edge |= bit; | |
6cab4860 | 320 | } else if (type == IRQ_TYPE_EDGE_FALLING) { |
fa9ff4b1 SO |
321 | trigger |= bit; |
322 | edge &= ~bit; | |
6cab4860 | 323 | } else if (type == IRQ_TYPE_EDGE_BOTH) { |
fa9ff4b1 | 324 | trigger |= bit; |
6f2384c4 | 325 | if (asic3_gpio_get(&asic->gpio, irq - asic->irq_base)) |
fa9ff4b1 SO |
326 | edge &= ~bit; |
327 | else | |
328 | edge |= bit; | |
329 | asic->irq_bothedge[(irq - asic->irq_base) >> 4] |= bit; | |
6cab4860 | 330 | } else if (type == IRQ_TYPE_LEVEL_LOW) { |
fa9ff4b1 SO |
331 | trigger &= ~bit; |
332 | level &= ~bit; | |
6cab4860 | 333 | } else if (type == IRQ_TYPE_LEVEL_HIGH) { |
fa9ff4b1 SO |
334 | trigger &= ~bit; |
335 | level |= bit; | |
336 | } else { | |
337 | /* | |
6cab4860 | 338 | * if type == IRQ_TYPE_NONE, we should mask interrupts, but |
fa9ff4b1 SO |
339 | * be careful to not unmask them if mask was also called. |
340 | * Probably need internal state for mask. | |
341 | */ | |
24f4f2ee | 342 | dev_notice(asic->dev, "irq type not changed\n"); |
fa9ff4b1 | 343 | } |
3b8139f8 | 344 | asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER, |
fa9ff4b1 | 345 | level); |
3b8139f8 | 346 | asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER, |
fa9ff4b1 | 347 | edge); |
3b8139f8 | 348 | asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE, |
fa9ff4b1 SO |
349 | trigger); |
350 | spin_unlock_irqrestore(&asic->lock, flags); | |
351 | return 0; | |
352 | } | |
353 | ||
354 | static struct irq_chip asic3_gpio_irq_chip = { | |
355 | .name = "ASIC3-GPIO", | |
356 | .ack = asic3_mask_gpio_irq, | |
357 | .mask = asic3_mask_gpio_irq, | |
358 | .unmask = asic3_unmask_gpio_irq, | |
359 | .set_type = asic3_gpio_irq_type, | |
360 | }; | |
361 | ||
362 | static struct irq_chip asic3_irq_chip = { | |
363 | .name = "ASIC3", | |
364 | .ack = asic3_mask_irq, | |
365 | .mask = asic3_mask_irq, | |
366 | .unmask = asic3_unmask_irq, | |
367 | }; | |
368 | ||
065032f6 | 369 | static int __init asic3_irq_probe(struct platform_device *pdev) |
fa9ff4b1 SO |
370 | { |
371 | struct asic3 *asic = platform_get_drvdata(pdev); | |
372 | unsigned long clksel = 0; | |
373 | unsigned int irq, irq_base; | |
c491b2ff | 374 | int ret; |
fa9ff4b1 | 375 | |
c491b2ff RK |
376 | ret = platform_get_irq(pdev, 0); |
377 | if (ret < 0) | |
378 | return ret; | |
379 | asic->irq_nr = ret; | |
fa9ff4b1 SO |
380 | |
381 | /* turn on clock to IRQ controller */ | |
382 | clksel |= CLOCK_SEL_CX; | |
383 | asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), | |
384 | clksel); | |
385 | ||
386 | irq_base = asic->irq_base; | |
387 | ||
388 | for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) { | |
389 | if (irq < asic->irq_base + ASIC3_NUM_GPIOS) | |
390 | set_irq_chip(irq, &asic3_gpio_irq_chip); | |
391 | else | |
392 | set_irq_chip(irq, &asic3_irq_chip); | |
393 | ||
394 | set_irq_chip_data(irq, asic); | |
395 | set_irq_handler(irq, handle_level_irq); | |
396 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | |
397 | } | |
398 | ||
3b8139f8 | 399 | asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK), |
fa9ff4b1 SO |
400 | ASIC3_INTMASK_GINTMASK); |
401 | ||
402 | set_irq_chained_handler(asic->irq_nr, asic3_irq_demux); | |
6cab4860 | 403 | set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING); |
fa9ff4b1 SO |
404 | set_irq_data(asic->irq_nr, asic); |
405 | ||
406 | return 0; | |
407 | } | |
408 | ||
409 | static void asic3_irq_remove(struct platform_device *pdev) | |
410 | { | |
411 | struct asic3 *asic = platform_get_drvdata(pdev); | |
412 | unsigned int irq, irq_base; | |
413 | ||
414 | irq_base = asic->irq_base; | |
415 | ||
416 | for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) { | |
417 | set_irq_flags(irq, 0); | |
418 | set_irq_handler(irq, NULL); | |
419 | set_irq_chip(irq, NULL); | |
420 | set_irq_chip_data(irq, NULL); | |
421 | } | |
422 | set_irq_chained_handler(asic->irq_nr, NULL); | |
423 | } | |
424 | ||
425 | /* GPIOs */ | |
6f2384c4 SO |
426 | static int asic3_gpio_direction(struct gpio_chip *chip, |
427 | unsigned offset, int out) | |
428 | { | |
429 | u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg; | |
430 | unsigned int gpio_base; | |
431 | unsigned long flags; | |
432 | struct asic3 *asic; | |
433 | ||
434 | asic = container_of(chip, struct asic3, gpio); | |
435 | gpio_base = ASIC3_GPIO_TO_BASE(offset); | |
436 | ||
3b8139f8 | 437 | if (gpio_base > ASIC3_GPIO_D_BASE) { |
24f4f2ee SO |
438 | dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n", |
439 | gpio_base, offset); | |
6f2384c4 SO |
440 | return -EINVAL; |
441 | } | |
442 | ||
443 | spin_lock_irqsave(&asic->lock, flags); | |
444 | ||
3b8139f8 | 445 | out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION); |
6f2384c4 SO |
446 | |
447 | /* Input is 0, Output is 1 */ | |
448 | if (out) | |
449 | out_reg |= mask; | |
450 | else | |
451 | out_reg &= ~mask; | |
452 | ||
3b8139f8 | 453 | asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg); |
6f2384c4 SO |
454 | |
455 | spin_unlock_irqrestore(&asic->lock, flags); | |
456 | ||
457 | return 0; | |
458 | ||
459 | } | |
460 | ||
461 | static int asic3_gpio_direction_input(struct gpio_chip *chip, | |
462 | unsigned offset) | |
463 | { | |
464 | return asic3_gpio_direction(chip, offset, 0); | |
465 | } | |
466 | ||
467 | static int asic3_gpio_direction_output(struct gpio_chip *chip, | |
468 | unsigned offset, int value) | |
469 | { | |
470 | return asic3_gpio_direction(chip, offset, 1); | |
471 | } | |
472 | ||
473 | static int asic3_gpio_get(struct gpio_chip *chip, | |
474 | unsigned offset) | |
475 | { | |
476 | unsigned int gpio_base; | |
477 | u32 mask = ASIC3_GPIO_TO_MASK(offset); | |
478 | struct asic3 *asic; | |
479 | ||
480 | asic = container_of(chip, struct asic3, gpio); | |
481 | gpio_base = ASIC3_GPIO_TO_BASE(offset); | |
482 | ||
3b8139f8 | 483 | if (gpio_base > ASIC3_GPIO_D_BASE) { |
24f4f2ee SO |
484 | dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n", |
485 | gpio_base, offset); | |
6f2384c4 SO |
486 | return -EINVAL; |
487 | } | |
488 | ||
3b8139f8 | 489 | return asic3_read_register(asic, gpio_base + ASIC3_GPIO_STATUS) & mask; |
6f2384c4 SO |
490 | } |
491 | ||
492 | static void asic3_gpio_set(struct gpio_chip *chip, | |
493 | unsigned offset, int value) | |
494 | { | |
495 | u32 mask, out_reg; | |
496 | unsigned int gpio_base; | |
497 | unsigned long flags; | |
498 | struct asic3 *asic; | |
499 | ||
500 | asic = container_of(chip, struct asic3, gpio); | |
501 | gpio_base = ASIC3_GPIO_TO_BASE(offset); | |
502 | ||
3b8139f8 | 503 | if (gpio_base > ASIC3_GPIO_D_BASE) { |
24f4f2ee SO |
504 | dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n", |
505 | gpio_base, offset); | |
6f2384c4 SO |
506 | return; |
507 | } | |
508 | ||
509 | mask = ASIC3_GPIO_TO_MASK(offset); | |
510 | ||
511 | spin_lock_irqsave(&asic->lock, flags); | |
512 | ||
3b8139f8 | 513 | out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT); |
6f2384c4 SO |
514 | |
515 | if (value) | |
516 | out_reg |= mask; | |
517 | else | |
518 | out_reg &= ~mask; | |
519 | ||
3b8139f8 | 520 | asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg); |
6f2384c4 SO |
521 | |
522 | spin_unlock_irqrestore(&asic->lock, flags); | |
523 | ||
524 | return; | |
525 | } | |
526 | ||
065032f6 PZ |
527 | static __init int asic3_gpio_probe(struct platform_device *pdev, |
528 | u16 *gpio_config, int num) | |
fa9ff4b1 | 529 | { |
fa9ff4b1 | 530 | struct asic3 *asic = platform_get_drvdata(pdev); |
3b26bf17 SO |
531 | u16 alt_reg[ASIC3_NUM_GPIO_BANKS]; |
532 | u16 out_reg[ASIC3_NUM_GPIO_BANKS]; | |
533 | u16 dir_reg[ASIC3_NUM_GPIO_BANKS]; | |
534 | int i; | |
fa9ff4b1 | 535 | |
59f0cb0f RK |
536 | memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16)); |
537 | memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16)); | |
538 | memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16)); | |
3b26bf17 SO |
539 | |
540 | /* Enable all GPIOs */ | |
3b8139f8 SO |
541 | asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff); |
542 | asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff); | |
543 | asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff); | |
544 | asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff); | |
fa9ff4b1 | 545 | |
3b26bf17 SO |
546 | for (i = 0; i < num; i++) { |
547 | u8 alt, pin, dir, init, bank_num, bit_num; | |
548 | u16 config = gpio_config[i]; | |
549 | ||
550 | pin = ASIC3_CONFIG_GPIO_PIN(config); | |
551 | alt = ASIC3_CONFIG_GPIO_ALT(config); | |
552 | dir = ASIC3_CONFIG_GPIO_DIR(config); | |
553 | init = ASIC3_CONFIG_GPIO_INIT(config); | |
554 | ||
555 | bank_num = ASIC3_GPIO_TO_BANK(pin); | |
556 | bit_num = ASIC3_GPIO_TO_BIT(pin); | |
557 | ||
558 | alt_reg[bank_num] |= (alt << bit_num); | |
559 | out_reg[bank_num] |= (init << bit_num); | |
560 | dir_reg[bank_num] |= (dir << bit_num); | |
561 | } | |
562 | ||
563 | for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) { | |
564 | asic3_write_register(asic, | |
565 | ASIC3_BANK_TO_BASE(i) + | |
3b8139f8 | 566 | ASIC3_GPIO_DIRECTION, |
3b26bf17 SO |
567 | dir_reg[i]); |
568 | asic3_write_register(asic, | |
3b8139f8 | 569 | ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT, |
3b26bf17 SO |
570 | out_reg[i]); |
571 | asic3_write_register(asic, | |
572 | ASIC3_BANK_TO_BASE(i) + | |
3b8139f8 | 573 | ASIC3_GPIO_ALT_FUNCTION, |
3b26bf17 | 574 | alt_reg[i]); |
fa9ff4b1 SO |
575 | } |
576 | ||
6f2384c4 | 577 | return gpiochip_add(&asic->gpio); |
fa9ff4b1 SO |
578 | } |
579 | ||
6f2384c4 | 580 | static int asic3_gpio_remove(struct platform_device *pdev) |
fa9ff4b1 | 581 | { |
6f2384c4 SO |
582 | struct asic3 *asic = platform_get_drvdata(pdev); |
583 | ||
584 | return gpiochip_remove(&asic->gpio); | |
fa9ff4b1 SO |
585 | } |
586 | ||
e956a2a8 PZ |
587 | static int asic3_clk_enable(struct asic3 *asic, struct asic3_clk *clk) |
588 | { | |
589 | unsigned long flags; | |
590 | u32 cdex; | |
591 | ||
592 | spin_lock_irqsave(&asic->lock, flags); | |
593 | if (clk->enabled++ == 0) { | |
594 | cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX)); | |
595 | cdex |= clk->cdex; | |
596 | asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex); | |
597 | } | |
598 | spin_unlock_irqrestore(&asic->lock, flags); | |
599 | ||
600 | return 0; | |
601 | } | |
602 | ||
603 | static void asic3_clk_disable(struct asic3 *asic, struct asic3_clk *clk) | |
604 | { | |
605 | unsigned long flags; | |
606 | u32 cdex; | |
607 | ||
608 | WARN_ON(clk->enabled == 0); | |
609 | ||
610 | spin_lock_irqsave(&asic->lock, flags); | |
611 | if (--clk->enabled == 0) { | |
612 | cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX)); | |
613 | cdex &= ~clk->cdex; | |
614 | asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex); | |
615 | } | |
616 | spin_unlock_irqrestore(&asic->lock, flags); | |
617 | } | |
fa9ff4b1 SO |
618 | |
619 | /* Core */ | |
065032f6 | 620 | static int __init asic3_probe(struct platform_device *pdev) |
fa9ff4b1 SO |
621 | { |
622 | struct asic3_platform_data *pdata = pdev->dev.platform_data; | |
623 | struct asic3 *asic; | |
624 | struct resource *mem; | |
625 | unsigned long clksel; | |
6f2384c4 | 626 | int ret = 0; |
fa9ff4b1 SO |
627 | |
628 | asic = kzalloc(sizeof(struct asic3), GFP_KERNEL); | |
6f2384c4 SO |
629 | if (asic == NULL) { |
630 | printk(KERN_ERR "kzalloc failed\n"); | |
fa9ff4b1 | 631 | return -ENOMEM; |
6f2384c4 | 632 | } |
fa9ff4b1 SO |
633 | |
634 | spin_lock_init(&asic->lock); | |
635 | platform_set_drvdata(pdev, asic); | |
636 | asic->dev = &pdev->dev; | |
637 | ||
638 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
639 | if (!mem) { | |
640 | ret = -ENOMEM; | |
24f4f2ee | 641 | dev_err(asic->dev, "no MEM resource\n"); |
6f2384c4 | 642 | goto out_free; |
fa9ff4b1 SO |
643 | } |
644 | ||
be584bd5 | 645 | asic->mapping = ioremap(mem->start, resource_size(mem)); |
fa9ff4b1 SO |
646 | if (!asic->mapping) { |
647 | ret = -ENOMEM; | |
24f4f2ee | 648 | dev_err(asic->dev, "Couldn't ioremap\n"); |
6f2384c4 | 649 | goto out_free; |
fa9ff4b1 SO |
650 | } |
651 | ||
652 | asic->irq_base = pdata->irq_base; | |
653 | ||
99cdb0c8 | 654 | /* calculate bus shift from mem resource */ |
be584bd5 | 655 | asic->bus_shift = 2 - (resource_size(mem) >> 12); |
fa9ff4b1 SO |
656 | |
657 | clksel = 0; | |
658 | asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel); | |
659 | ||
660 | ret = asic3_irq_probe(pdev); | |
661 | if (ret < 0) { | |
24f4f2ee | 662 | dev_err(asic->dev, "Couldn't probe IRQs\n"); |
6f2384c4 SO |
663 | goto out_unmap; |
664 | } | |
665 | ||
666 | asic->gpio.base = pdata->gpio_base; | |
667 | asic->gpio.ngpio = ASIC3_NUM_GPIOS; | |
668 | asic->gpio.get = asic3_gpio_get; | |
669 | asic->gpio.set = asic3_gpio_set; | |
670 | asic->gpio.direction_input = asic3_gpio_direction_input; | |
671 | asic->gpio.direction_output = asic3_gpio_direction_output; | |
672 | ||
3b26bf17 SO |
673 | ret = asic3_gpio_probe(pdev, |
674 | pdata->gpio_config, | |
675 | pdata->gpio_config_num); | |
6f2384c4 | 676 | if (ret < 0) { |
24f4f2ee | 677 | dev_err(asic->dev, "GPIO probe failed\n"); |
6f2384c4 | 678 | goto out_irq; |
fa9ff4b1 | 679 | } |
fa9ff4b1 | 680 | |
e956a2a8 PZ |
681 | /* Making a per-device copy is only needed for the |
682 | * theoretical case of multiple ASIC3s on one board: | |
683 | */ | |
684 | memcpy(asic->clocks, asic3_clk_init, sizeof(asic3_clk_init)); | |
685 | ||
24f4f2ee | 686 | dev_info(asic->dev, "ASIC3 Core driver\n"); |
fa9ff4b1 SO |
687 | |
688 | return 0; | |
689 | ||
6f2384c4 SO |
690 | out_irq: |
691 | asic3_irq_remove(pdev); | |
692 | ||
693 | out_unmap: | |
fa9ff4b1 | 694 | iounmap(asic->mapping); |
6f2384c4 SO |
695 | |
696 | out_free: | |
fa9ff4b1 SO |
697 | kfree(asic); |
698 | ||
699 | return ret; | |
700 | } | |
701 | ||
702 | static int asic3_remove(struct platform_device *pdev) | |
703 | { | |
6f2384c4 | 704 | int ret; |
fa9ff4b1 SO |
705 | struct asic3 *asic = platform_get_drvdata(pdev); |
706 | ||
6f2384c4 SO |
707 | ret = asic3_gpio_remove(pdev); |
708 | if (ret < 0) | |
709 | return ret; | |
fa9ff4b1 SO |
710 | asic3_irq_remove(pdev); |
711 | ||
712 | asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0); | |
713 | ||
714 | iounmap(asic->mapping); | |
715 | ||
716 | kfree(asic); | |
717 | ||
718 | return 0; | |
719 | } | |
720 | ||
721 | static void asic3_shutdown(struct platform_device *pdev) | |
722 | { | |
723 | } | |
724 | ||
725 | static struct platform_driver asic3_device_driver = { | |
726 | .driver = { | |
727 | .name = "asic3", | |
728 | }, | |
fa9ff4b1 SO |
729 | .remove = __devexit_p(asic3_remove), |
730 | .shutdown = asic3_shutdown, | |
731 | }; | |
732 | ||
733 | static int __init asic3_init(void) | |
734 | { | |
735 | int retval = 0; | |
065032f6 | 736 | retval = platform_driver_probe(&asic3_device_driver, asic3_probe); |
fa9ff4b1 SO |
737 | return retval; |
738 | } | |
739 | ||
740 | subsys_initcall(asic3_init); |