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e3726fcf | 1 | /* |
e0befb23 MP |
2 | * Copyright (C) STMicroelectronics 2009 |
3 | * Copyright (C) ST-Ericsson SA 2010 | |
e3726fcf LW |
4 | * |
5 | * License Terms: GNU General Public License v2 | |
e0befb23 MP |
6 | * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> |
7 | * Author: Sundar Iyer <sundar.iyer@stericsson.com> | |
e3726fcf LW |
8 | * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> |
9 | * | |
e0befb23 MP |
10 | * U8500 PRCM Unit interface driver |
11 | * | |
e3726fcf | 12 | */ |
e3726fcf | 13 | #include <linux/module.h> |
3df57bcf MN |
14 | #include <linux/kernel.h> |
15 | #include <linux/delay.h> | |
e3726fcf LW |
16 | #include <linux/errno.h> |
17 | #include <linux/err.h> | |
3df57bcf | 18 | #include <linux/spinlock.h> |
e3726fcf | 19 | #include <linux/io.h> |
3df57bcf | 20 | #include <linux/slab.h> |
e3726fcf LW |
21 | #include <linux/mutex.h> |
22 | #include <linux/completion.h> | |
3df57bcf | 23 | #include <linux/irq.h> |
e3726fcf LW |
24 | #include <linux/jiffies.h> |
25 | #include <linux/bitops.h> | |
3df57bcf | 26 | #include <linux/fs.h> |
d98a5384 | 27 | #include <linux/of.h> |
f864c46a | 28 | #include <linux/of_irq.h> |
3df57bcf MN |
29 | #include <linux/platform_device.h> |
30 | #include <linux/uaccess.h> | |
31 | #include <linux/mfd/core.h> | |
73180f85 | 32 | #include <linux/mfd/dbx500-prcmu.h> |
3a8e39c9 | 33 | #include <linux/mfd/abx500/ab8500.h> |
1032fbfd BJ |
34 | #include <linux/regulator/db8500-prcmu.h> |
35 | #include <linux/regulator/machine.h> | |
c280f45f | 36 | #include <linux/cpufreq.h> |
b3aac62b | 37 | #include <linux/platform_data/ux500_wdt.h> |
55b175d7 | 38 | #include <linux/platform_data/db8500_thermal.h> |
73180f85 | 39 | #include "dbx500-prcmu-regs.h" |
3df57bcf | 40 | |
3df57bcf MN |
41 | /* Index of different voltages to be used when accessing AVSData */ |
42 | #define PRCM_AVS_BASE 0x2FC | |
43 | #define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0) | |
44 | #define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1) | |
45 | #define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2) | |
46 | #define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3) | |
47 | #define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4) | |
48 | #define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5) | |
49 | #define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6) | |
50 | #define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7) | |
51 | #define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8) | |
52 | #define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9) | |
53 | #define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA) | |
54 | #define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB) | |
55 | #define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC) | |
56 | ||
57 | #define PRCM_AVS_VOLTAGE 0 | |
58 | #define PRCM_AVS_VOLTAGE_MASK 0x3f | |
59 | #define PRCM_AVS_ISSLOWSTARTUP 6 | |
60 | #define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP) | |
61 | #define PRCM_AVS_ISMODEENABLE 7 | |
62 | #define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE) | |
63 | ||
64 | #define PRCM_BOOT_STATUS 0xFFF | |
65 | #define PRCM_ROMCODE_A2P 0xFFE | |
66 | #define PRCM_ROMCODE_P2A 0xFFD | |
67 | #define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */ | |
68 | ||
69 | #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */ | |
70 | ||
71 | #define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */ | |
72 | #define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0) | |
73 | #define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1) | |
74 | #define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2) | |
75 | #define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3) | |
76 | #define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4) | |
77 | #define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5) | |
78 | #define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8) | |
79 | ||
80 | /* Req Mailboxes */ | |
81 | #define PRCM_REQ_MB0 0xFDC /* 12 bytes */ | |
82 | #define PRCM_REQ_MB1 0xFD0 /* 12 bytes */ | |
83 | #define PRCM_REQ_MB2 0xFC0 /* 16 bytes */ | |
84 | #define PRCM_REQ_MB3 0xE4C /* 372 bytes */ | |
85 | #define PRCM_REQ_MB4 0xE48 /* 4 bytes */ | |
86 | #define PRCM_REQ_MB5 0xE44 /* 4 bytes */ | |
87 | ||
88 | /* Ack Mailboxes */ | |
89 | #define PRCM_ACK_MB0 0xE08 /* 52 bytes */ | |
90 | #define PRCM_ACK_MB1 0xE04 /* 4 bytes */ | |
91 | #define PRCM_ACK_MB2 0xE00 /* 4 bytes */ | |
92 | #define PRCM_ACK_MB3 0xDFC /* 4 bytes */ | |
93 | #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */ | |
94 | #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */ | |
95 | ||
96 | /* Mailbox 0 headers */ | |
97 | #define MB0H_POWER_STATE_TRANS 0 | |
98 | #define MB0H_CONFIG_WAKEUPS_EXE 1 | |
99 | #define MB0H_READ_WAKEUP_ACK 3 | |
100 | #define MB0H_CONFIG_WAKEUPS_SLEEP 4 | |
101 | ||
102 | #define MB0H_WAKEUP_EXE 2 | |
103 | #define MB0H_WAKEUP_SLEEP 5 | |
104 | ||
105 | /* Mailbox 0 REQs */ | |
106 | #define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0) | |
107 | #define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1) | |
108 | #define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2) | |
109 | #define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3) | |
110 | #define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4) | |
111 | #define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8) | |
112 | ||
113 | /* Mailbox 0 ACKs */ | |
114 | #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0) | |
115 | #define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1) | |
116 | #define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4) | |
117 | #define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8) | |
118 | #define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C) | |
119 | #define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20) | |
120 | #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20 | |
121 | ||
122 | /* Mailbox 1 headers */ | |
123 | #define MB1H_ARM_APE_OPP 0x0 | |
124 | #define MB1H_RESET_MODEM 0x2 | |
125 | #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3 | |
126 | #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4 | |
127 | #define MB1H_RELEASE_USB_WAKEUP 0x5 | |
a592c2e2 | 128 | #define MB1H_PLL_ON_OFF 0x6 |
3df57bcf MN |
129 | |
130 | /* Mailbox 1 Requests */ | |
131 | #define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0) | |
132 | #define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1) | |
a592c2e2 | 133 | #define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4) |
6b6fae2b MN |
134 | #define PLL_SOC0_OFF 0x1 |
135 | #define PLL_SOC0_ON 0x2 | |
a592c2e2 MN |
136 | #define PLL_SOC1_OFF 0x4 |
137 | #define PLL_SOC1_ON 0x8 | |
3df57bcf MN |
138 | |
139 | /* Mailbox 1 ACKs */ | |
140 | #define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0) | |
141 | #define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1) | |
142 | #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2) | |
143 | #define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3) | |
144 | ||
145 | /* Mailbox 2 headers */ | |
146 | #define MB2H_DPS 0x0 | |
147 | #define MB2H_AUTO_PWR 0x1 | |
148 | ||
149 | /* Mailbox 2 REQs */ | |
150 | #define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0) | |
151 | #define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1) | |
152 | #define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2) | |
153 | #define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3) | |
154 | #define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4) | |
155 | #define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5) | |
156 | #define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6) | |
157 | #define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7) | |
158 | #define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8) | |
159 | #define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC) | |
160 | ||
161 | /* Mailbox 2 ACKs */ | |
162 | #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0) | |
163 | #define HWACC_PWR_ST_OK 0xFE | |
164 | ||
165 | /* Mailbox 3 headers */ | |
166 | #define MB3H_ANC 0x0 | |
167 | #define MB3H_SIDETONE 0x1 | |
168 | #define MB3H_SYSCLK 0xE | |
169 | ||
170 | /* Mailbox 3 Requests */ | |
171 | #define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0) | |
172 | #define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20) | |
173 | #define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60) | |
174 | #define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64) | |
175 | #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68) | |
176 | #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C) | |
177 | #define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C) | |
178 | ||
179 | /* Mailbox 4 headers */ | |
180 | #define MB4H_DDR_INIT 0x0 | |
181 | #define MB4H_MEM_ST 0x1 | |
182 | #define MB4H_HOTDOG 0x12 | |
183 | #define MB4H_HOTMON 0x13 | |
184 | #define MB4H_HOT_PERIOD 0x14 | |
a592c2e2 MN |
185 | #define MB4H_A9WDOG_CONF 0x16 |
186 | #define MB4H_A9WDOG_EN 0x17 | |
187 | #define MB4H_A9WDOG_DIS 0x18 | |
188 | #define MB4H_A9WDOG_LOAD 0x19 | |
189 | #define MB4H_A9WDOG_KICK 0x20 | |
3df57bcf MN |
190 | |
191 | /* Mailbox 4 Requests */ | |
192 | #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0) | |
193 | #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1) | |
194 | #define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3) | |
195 | #define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0) | |
196 | #define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0) | |
197 | #define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1) | |
198 | #define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2) | |
199 | #define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0) | |
200 | #define HOTMON_CONFIG_LOW BIT(0) | |
201 | #define HOTMON_CONFIG_HIGH BIT(1) | |
a592c2e2 MN |
202 | #define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0) |
203 | #define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1) | |
204 | #define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2) | |
205 | #define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3) | |
206 | #define A9WDOG_AUTO_OFF_EN BIT(7) | |
207 | #define A9WDOG_AUTO_OFF_DIS 0 | |
208 | #define A9WDOG_ID_MASK 0xf | |
3df57bcf MN |
209 | |
210 | /* Mailbox 5 Requests */ | |
211 | #define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0) | |
212 | #define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1) | |
213 | #define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2) | |
214 | #define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3) | |
7a4f2609 LW |
215 | #define PRCMU_I2C_WRITE(slave) (((slave) << 1) | BIT(6)) |
216 | #define PRCMU_I2C_READ(slave) (((slave) << 1) | BIT(0) | BIT(6)) | |
3df57bcf MN |
217 | #define PRCMU_I2C_STOP_EN BIT(3) |
218 | ||
219 | /* Mailbox 5 ACKs */ | |
220 | #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1) | |
221 | #define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3) | |
222 | #define I2C_WR_OK 0x1 | |
223 | #define I2C_RD_OK 0x2 | |
224 | ||
225 | #define NUM_MB 8 | |
226 | #define MBOX_BIT BIT | |
227 | #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1) | |
228 | ||
229 | /* | |
230 | * Wakeups/IRQs | |
231 | */ | |
232 | ||
233 | #define WAKEUP_BIT_RTC BIT(0) | |
234 | #define WAKEUP_BIT_RTT0 BIT(1) | |
235 | #define WAKEUP_BIT_RTT1 BIT(2) | |
236 | #define WAKEUP_BIT_HSI0 BIT(3) | |
237 | #define WAKEUP_BIT_HSI1 BIT(4) | |
238 | #define WAKEUP_BIT_CA_WAKE BIT(5) | |
239 | #define WAKEUP_BIT_USB BIT(6) | |
240 | #define WAKEUP_BIT_ABB BIT(7) | |
241 | #define WAKEUP_BIT_ABB_FIFO BIT(8) | |
242 | #define WAKEUP_BIT_SYSCLK_OK BIT(9) | |
243 | #define WAKEUP_BIT_CA_SLEEP BIT(10) | |
244 | #define WAKEUP_BIT_AC_WAKE_ACK BIT(11) | |
245 | #define WAKEUP_BIT_SIDE_TONE_OK BIT(12) | |
246 | #define WAKEUP_BIT_ANC_OK BIT(13) | |
247 | #define WAKEUP_BIT_SW_ERROR BIT(14) | |
248 | #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15) | |
249 | #define WAKEUP_BIT_ARM BIT(17) | |
250 | #define WAKEUP_BIT_HOTMON_LOW BIT(18) | |
251 | #define WAKEUP_BIT_HOTMON_HIGH BIT(19) | |
252 | #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20) | |
253 | #define WAKEUP_BIT_GPIO0 BIT(23) | |
254 | #define WAKEUP_BIT_GPIO1 BIT(24) | |
255 | #define WAKEUP_BIT_GPIO2 BIT(25) | |
256 | #define WAKEUP_BIT_GPIO3 BIT(26) | |
257 | #define WAKEUP_BIT_GPIO4 BIT(27) | |
258 | #define WAKEUP_BIT_GPIO5 BIT(28) | |
259 | #define WAKEUP_BIT_GPIO6 BIT(29) | |
260 | #define WAKEUP_BIT_GPIO7 BIT(30) | |
261 | #define WAKEUP_BIT_GPIO8 BIT(31) | |
262 | ||
b58d12fe MN |
263 | static struct { |
264 | bool valid; | |
265 | struct prcmu_fw_version version; | |
266 | } fw_info; | |
267 | ||
f3f1f0a1 LJ |
268 | static struct irq_domain *db8500_irq_domain; |
269 | ||
3df57bcf MN |
270 | /* |
271 | * This vector maps irq numbers to the bits in the bit field used in | |
272 | * communication with the PRCMU firmware. | |
273 | * | |
274 | * The reason for having this is to keep the irq numbers contiguous even though | |
275 | * the bits in the bit field are not. (The bits also have a tendency to move | |
276 | * around, to further complicate matters.) | |
277 | */ | |
55b175d7 | 278 | #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name)) |
3df57bcf | 279 | #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name) |
55b175d7 AB |
280 | |
281 | #define IRQ_PRCMU_RTC 0 | |
282 | #define IRQ_PRCMU_RTT0 1 | |
283 | #define IRQ_PRCMU_RTT1 2 | |
284 | #define IRQ_PRCMU_HSI0 3 | |
285 | #define IRQ_PRCMU_HSI1 4 | |
286 | #define IRQ_PRCMU_CA_WAKE 5 | |
287 | #define IRQ_PRCMU_USB 6 | |
288 | #define IRQ_PRCMU_ABB 7 | |
289 | #define IRQ_PRCMU_ABB_FIFO 8 | |
290 | #define IRQ_PRCMU_ARM 9 | |
291 | #define IRQ_PRCMU_MODEM_SW_RESET_REQ 10 | |
292 | #define IRQ_PRCMU_GPIO0 11 | |
293 | #define IRQ_PRCMU_GPIO1 12 | |
294 | #define IRQ_PRCMU_GPIO2 13 | |
295 | #define IRQ_PRCMU_GPIO3 14 | |
296 | #define IRQ_PRCMU_GPIO4 15 | |
297 | #define IRQ_PRCMU_GPIO5 16 | |
298 | #define IRQ_PRCMU_GPIO6 17 | |
299 | #define IRQ_PRCMU_GPIO7 18 | |
300 | #define IRQ_PRCMU_GPIO8 19 | |
301 | #define IRQ_PRCMU_CA_SLEEP 20 | |
302 | #define IRQ_PRCMU_HOTMON_LOW 21 | |
303 | #define IRQ_PRCMU_HOTMON_HIGH 22 | |
304 | #define NUM_PRCMU_WAKEUPS 23 | |
305 | ||
3df57bcf MN |
306 | static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = { |
307 | IRQ_ENTRY(RTC), | |
308 | IRQ_ENTRY(RTT0), | |
309 | IRQ_ENTRY(RTT1), | |
310 | IRQ_ENTRY(HSI0), | |
311 | IRQ_ENTRY(HSI1), | |
312 | IRQ_ENTRY(CA_WAKE), | |
313 | IRQ_ENTRY(USB), | |
314 | IRQ_ENTRY(ABB), | |
315 | IRQ_ENTRY(ABB_FIFO), | |
316 | IRQ_ENTRY(CA_SLEEP), | |
317 | IRQ_ENTRY(ARM), | |
318 | IRQ_ENTRY(HOTMON_LOW), | |
319 | IRQ_ENTRY(HOTMON_HIGH), | |
320 | IRQ_ENTRY(MODEM_SW_RESET_REQ), | |
321 | IRQ_ENTRY(GPIO0), | |
322 | IRQ_ENTRY(GPIO1), | |
323 | IRQ_ENTRY(GPIO2), | |
324 | IRQ_ENTRY(GPIO3), | |
325 | IRQ_ENTRY(GPIO4), | |
326 | IRQ_ENTRY(GPIO5), | |
327 | IRQ_ENTRY(GPIO6), | |
328 | IRQ_ENTRY(GPIO7), | |
329 | IRQ_ENTRY(GPIO8) | |
330 | }; | |
331 | ||
332 | #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1) | |
333 | #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name) | |
334 | static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = { | |
335 | WAKEUP_ENTRY(RTC), | |
336 | WAKEUP_ENTRY(RTT0), | |
337 | WAKEUP_ENTRY(RTT1), | |
338 | WAKEUP_ENTRY(HSI0), | |
339 | WAKEUP_ENTRY(HSI1), | |
340 | WAKEUP_ENTRY(USB), | |
341 | WAKEUP_ENTRY(ABB), | |
342 | WAKEUP_ENTRY(ABB_FIFO), | |
343 | WAKEUP_ENTRY(ARM) | |
344 | }; | |
345 | ||
346 | /* | |
347 | * mb0_transfer - state needed for mailbox 0 communication. | |
348 | * @lock: The transaction lock. | |
349 | * @dbb_events_lock: A lock used to handle concurrent access to (parts of) | |
350 | * the request data. | |
351 | * @mask_work: Work structure used for (un)masking wakeup interrupts. | |
352 | * @req: Request data that need to persist between requests. | |
353 | */ | |
354 | static struct { | |
355 | spinlock_t lock; | |
356 | spinlock_t dbb_irqs_lock; | |
357 | struct work_struct mask_work; | |
358 | struct mutex ac_wake_lock; | |
359 | struct completion ac_wake_work; | |
360 | struct { | |
361 | u32 dbb_irqs; | |
362 | u32 dbb_wakeups; | |
363 | u32 abb_events; | |
364 | } req; | |
365 | } mb0_transfer; | |
366 | ||
367 | /* | |
368 | * mb1_transfer - state needed for mailbox 1 communication. | |
369 | * @lock: The transaction lock. | |
370 | * @work: The transaction completion structure. | |
4d64d2e3 | 371 | * @ape_opp: The current APE OPP. |
3df57bcf MN |
372 | * @ack: Reply ("acknowledge") data. |
373 | */ | |
374 | static struct { | |
375 | struct mutex lock; | |
376 | struct completion work; | |
4d64d2e3 | 377 | u8 ape_opp; |
3df57bcf MN |
378 | struct { |
379 | u8 header; | |
380 | u8 arm_opp; | |
381 | u8 ape_opp; | |
382 | u8 ape_voltage_status; | |
383 | } ack; | |
384 | } mb1_transfer; | |
385 | ||
386 | /* | |
387 | * mb2_transfer - state needed for mailbox 2 communication. | |
388 | * @lock: The transaction lock. | |
389 | * @work: The transaction completion structure. | |
390 | * @auto_pm_lock: The autonomous power management configuration lock. | |
391 | * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled. | |
392 | * @req: Request data that need to persist between requests. | |
393 | * @ack: Reply ("acknowledge") data. | |
394 | */ | |
395 | static struct { | |
396 | struct mutex lock; | |
397 | struct completion work; | |
398 | spinlock_t auto_pm_lock; | |
399 | bool auto_pm_enabled; | |
400 | struct { | |
401 | u8 status; | |
402 | } ack; | |
403 | } mb2_transfer; | |
404 | ||
405 | /* | |
406 | * mb3_transfer - state needed for mailbox 3 communication. | |
407 | * @lock: The request lock. | |
408 | * @sysclk_lock: A lock used to handle concurrent sysclk requests. | |
409 | * @sysclk_work: Work structure used for sysclk requests. | |
410 | */ | |
411 | static struct { | |
412 | spinlock_t lock; | |
413 | struct mutex sysclk_lock; | |
414 | struct completion sysclk_work; | |
415 | } mb3_transfer; | |
416 | ||
417 | /* | |
418 | * mb4_transfer - state needed for mailbox 4 communication. | |
419 | * @lock: The transaction lock. | |
420 | * @work: The transaction completion structure. | |
421 | */ | |
422 | static struct { | |
423 | struct mutex lock; | |
424 | struct completion work; | |
425 | } mb4_transfer; | |
426 | ||
427 | /* | |
428 | * mb5_transfer - state needed for mailbox 5 communication. | |
429 | * @lock: The transaction lock. | |
430 | * @work: The transaction completion structure. | |
431 | * @ack: Reply ("acknowledge") data. | |
432 | */ | |
433 | static struct { | |
434 | struct mutex lock; | |
435 | struct completion work; | |
436 | struct { | |
437 | u8 status; | |
438 | u8 value; | |
439 | } ack; | |
440 | } mb5_transfer; | |
441 | ||
442 | static atomic_t ac_wake_req_state = ATOMIC_INIT(0); | |
443 | ||
444 | /* Spinlocks */ | |
b4a6dbd5 | 445 | static DEFINE_SPINLOCK(prcmu_lock); |
3df57bcf | 446 | static DEFINE_SPINLOCK(clkout_lock); |
3df57bcf MN |
447 | |
448 | /* Global var to runtime determine TCDM base for v2 or v1 */ | |
449 | static __iomem void *tcdm_base; | |
b047d981 | 450 | static __iomem void *prcmu_base; |
3df57bcf MN |
451 | |
452 | struct clk_mgt { | |
b047d981 | 453 | u32 offset; |
3df57bcf | 454 | u32 pllsw; |
6b6fae2b MN |
455 | int branch; |
456 | bool clk38div; | |
457 | }; | |
458 | ||
459 | enum { | |
460 | PLL_RAW, | |
461 | PLL_FIX, | |
462 | PLL_DIV | |
3df57bcf MN |
463 | }; |
464 | ||
465 | static DEFINE_SPINLOCK(clk_mgt_lock); | |
466 | ||
6b6fae2b MN |
467 | #define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \ |
468 | { (PRCM_##_name##_MGT), 0 , _branch, _clk38div} | |
6746f232 | 469 | static struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = { |
6b6fae2b MN |
470 | CLK_MGT_ENTRY(SGACLK, PLL_DIV, false), |
471 | CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true), | |
472 | CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true), | |
473 | CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true), | |
474 | CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true), | |
475 | CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true), | |
476 | CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true), | |
477 | CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true), | |
478 | CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true), | |
479 | CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true), | |
480 | CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true), | |
481 | CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true), | |
482 | CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true), | |
483 | CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true), | |
484 | CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true), | |
485 | CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true), | |
486 | CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true), | |
487 | CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false), | |
488 | CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true), | |
489 | CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true), | |
490 | CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true), | |
491 | CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true), | |
492 | CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false), | |
493 | CLK_MGT_ENTRY(DMACLK, PLL_DIV, true), | |
494 | CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true), | |
495 | CLK_MGT_ENTRY(TVCLK, PLL_FIX, true), | |
496 | CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true), | |
497 | CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true), | |
498 | CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false), | |
499 | }; | |
500 | ||
501 | struct dsiclk { | |
502 | u32 divsel_mask; | |
503 | u32 divsel_shift; | |
504 | u32 divsel; | |
505 | }; | |
506 | ||
507 | static struct dsiclk dsiclk[2] = { | |
508 | { | |
509 | .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK, | |
510 | .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT, | |
511 | .divsel = PRCM_DSI_PLLOUT_SEL_PHI, | |
512 | }, | |
513 | { | |
514 | .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK, | |
515 | .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT, | |
516 | .divsel = PRCM_DSI_PLLOUT_SEL_PHI, | |
517 | } | |
518 | }; | |
519 | ||
520 | struct dsiescclk { | |
521 | u32 en; | |
522 | u32 div_mask; | |
523 | u32 div_shift; | |
524 | }; | |
525 | ||
526 | static struct dsiescclk dsiescclk[3] = { | |
527 | { | |
528 | .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN, | |
529 | .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK, | |
530 | .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT, | |
531 | }, | |
532 | { | |
533 | .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN, | |
534 | .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK, | |
535 | .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT, | |
536 | }, | |
537 | { | |
538 | .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN, | |
539 | .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK, | |
540 | .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT, | |
541 | } | |
3df57bcf MN |
542 | }; |
543 | ||
20aee5b6 | 544 | |
3df57bcf MN |
545 | /* |
546 | * Used by MCDE to setup all necessary PRCMU registers | |
547 | */ | |
548 | #define PRCMU_RESET_DSIPLL 0x00004000 | |
549 | #define PRCMU_UNCLAMP_DSIPLL 0x00400800 | |
550 | ||
551 | #define PRCMU_CLK_PLL_DIV_SHIFT 0 | |
552 | #define PRCMU_CLK_PLL_SW_SHIFT 5 | |
553 | #define PRCMU_CLK_38 (1 << 9) | |
554 | #define PRCMU_CLK_38_SRC (1 << 10) | |
555 | #define PRCMU_CLK_38_DIV (1 << 11) | |
556 | ||
557 | /* PLLDIV=12, PLLSW=4 (PLLDDR) */ | |
558 | #define PRCMU_DSI_CLOCK_SETTING 0x0000008C | |
559 | ||
3df57bcf MN |
560 | /* DPI 50000000 Hz */ |
561 | #define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \ | |
562 | (16 << PRCMU_CLK_PLL_DIV_SHIFT)) | |
563 | #define PRCMU_DSI_LP_CLOCK_SETTING 0x00000E00 | |
564 | ||
565 | /* D=101, N=1, R=4, SELDIV2=0 */ | |
566 | #define PRCMU_PLLDSI_FREQ_SETTING 0x00040165 | |
567 | ||
3df57bcf MN |
568 | #define PRCMU_ENABLE_PLLDSI 0x00000001 |
569 | #define PRCMU_DISABLE_PLLDSI 0x00000000 | |
570 | #define PRCMU_RELEASE_RESET_DSS 0x0000400C | |
571 | #define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000202 | |
572 | /* ESC clk, div0=1, div1=1, div2=3 */ | |
573 | #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x07030101 | |
574 | #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00030101 | |
575 | #define PRCMU_DSI_RESET_SW 0x00000007 | |
576 | ||
577 | #define PRCMU_PLLDSI_LOCKP_LOCKED 0x3 | |
578 | ||
73180f85 | 579 | int db8500_prcmu_enable_dsipll(void) |
3df57bcf MN |
580 | { |
581 | int i; | |
3df57bcf MN |
582 | |
583 | /* Clear DSIPLL_RESETN */ | |
c553b3ca | 584 | writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR); |
3df57bcf | 585 | /* Unclamp DSIPLL in/out */ |
c553b3ca | 586 | writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR); |
3df57bcf | 587 | |
3df57bcf | 588 | /* Set DSI PLL FREQ */ |
c72fe851 | 589 | writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ); |
c553b3ca | 590 | writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL); |
3df57bcf | 591 | /* Enable Escape clocks */ |
c553b3ca | 592 | writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); |
3df57bcf MN |
593 | |
594 | /* Start DSI PLL */ | |
c553b3ca | 595 | writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE); |
3df57bcf | 596 | /* Reset DSI PLL */ |
c553b3ca | 597 | writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET); |
3df57bcf | 598 | for (i = 0; i < 10; i++) { |
c553b3ca | 599 | if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED) |
3df57bcf MN |
600 | == PRCMU_PLLDSI_LOCKP_LOCKED) |
601 | break; | |
602 | udelay(100); | |
603 | } | |
604 | /* Set DSIPLL_RESETN */ | |
c553b3ca | 605 | writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET); |
3df57bcf MN |
606 | return 0; |
607 | } | |
608 | ||
73180f85 | 609 | int db8500_prcmu_disable_dsipll(void) |
3df57bcf MN |
610 | { |
611 | /* Disable dsi pll */ | |
c553b3ca | 612 | writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE); |
3df57bcf | 613 | /* Disable escapeclock */ |
c553b3ca | 614 | writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); |
3df57bcf MN |
615 | return 0; |
616 | } | |
617 | ||
73180f85 | 618 | int db8500_prcmu_set_display_clocks(void) |
3df57bcf MN |
619 | { |
620 | unsigned long flags; | |
3df57bcf MN |
621 | |
622 | spin_lock_irqsave(&clk_mgt_lock, flags); | |
623 | ||
624 | /* Grab the HW semaphore. */ | |
c553b3ca | 625 | while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) |
3df57bcf MN |
626 | cpu_relax(); |
627 | ||
b047d981 LW |
628 | writel(PRCMU_DSI_CLOCK_SETTING, prcmu_base + PRCM_HDMICLK_MGT); |
629 | writel(PRCMU_DSI_LP_CLOCK_SETTING, prcmu_base + PRCM_TVCLK_MGT); | |
630 | writel(PRCMU_DPI_CLOCK_SETTING, prcmu_base + PRCM_LCDCLK_MGT); | |
3df57bcf MN |
631 | |
632 | /* Release the HW semaphore. */ | |
c553b3ca | 633 | writel(0, PRCM_SEM); |
3df57bcf MN |
634 | |
635 | spin_unlock_irqrestore(&clk_mgt_lock, flags); | |
636 | ||
637 | return 0; | |
638 | } | |
639 | ||
b4a6dbd5 MN |
640 | u32 db8500_prcmu_read(unsigned int reg) |
641 | { | |
b047d981 | 642 | return readl(prcmu_base + reg); |
b4a6dbd5 MN |
643 | } |
644 | ||
645 | void db8500_prcmu_write(unsigned int reg, u32 value) | |
3df57bcf | 646 | { |
3df57bcf MN |
647 | unsigned long flags; |
648 | ||
b4a6dbd5 | 649 | spin_lock_irqsave(&prcmu_lock, flags); |
b047d981 | 650 | writel(value, (prcmu_base + reg)); |
b4a6dbd5 | 651 | spin_unlock_irqrestore(&prcmu_lock, flags); |
3df57bcf MN |
652 | } |
653 | ||
b4a6dbd5 | 654 | void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value) |
3df57bcf | 655 | { |
b4a6dbd5 | 656 | u32 val; |
3df57bcf MN |
657 | unsigned long flags; |
658 | ||
b4a6dbd5 | 659 | spin_lock_irqsave(&prcmu_lock, flags); |
b047d981 | 660 | val = readl(prcmu_base + reg); |
b4a6dbd5 | 661 | val = ((val & ~mask) | (value & mask)); |
b047d981 | 662 | writel(val, (prcmu_base + reg)); |
b4a6dbd5 | 663 | spin_unlock_irqrestore(&prcmu_lock, flags); |
3df57bcf MN |
664 | } |
665 | ||
b58d12fe MN |
666 | struct prcmu_fw_version *prcmu_get_fw_version(void) |
667 | { | |
668 | return fw_info.valid ? &fw_info.version : NULL; | |
669 | } | |
670 | ||
3df57bcf MN |
671 | bool prcmu_has_arm_maxopp(void) |
672 | { | |
673 | return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) & | |
674 | PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK; | |
675 | } | |
676 | ||
3df57bcf MN |
677 | /** |
678 | * prcmu_set_rc_a2p - This function is used to run few power state sequences | |
679 | * @val: Value to be set, i.e. transition requested | |
680 | * Returns: 0 on success, -EINVAL on invalid argument | |
681 | * | |
682 | * This function is used to run the following power state sequences - | |
683 | * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep | |
684 | */ | |
685 | int prcmu_set_rc_a2p(enum romcode_write val) | |
686 | { | |
687 | if (val < RDY_2_DS || val > RDY_2_XP70_RST) | |
688 | return -EINVAL; | |
689 | writeb(val, (tcdm_base + PRCM_ROMCODE_A2P)); | |
690 | return 0; | |
691 | } | |
692 | ||
693 | /** | |
694 | * prcmu_get_rc_p2a - This function is used to get power state sequences | |
695 | * Returns: the power transition that has last happened | |
696 | * | |
697 | * This function can return the following transitions- | |
698 | * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep | |
699 | */ | |
700 | enum romcode_read prcmu_get_rc_p2a(void) | |
701 | { | |
702 | return readb(tcdm_base + PRCM_ROMCODE_P2A); | |
703 | } | |
704 | ||
705 | /** | |
706 | * prcmu_get_current_mode - Return the current XP70 power mode | |
707 | * Returns: Returns the current AP(ARM) power mode: init, | |
708 | * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset | |
709 | */ | |
710 | enum ap_pwrst prcmu_get_xp70_current_state(void) | |
711 | { | |
712 | return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE); | |
713 | } | |
714 | ||
715 | /** | |
716 | * prcmu_config_clkout - Configure one of the programmable clock outputs. | |
717 | * @clkout: The CLKOUT number (0 or 1). | |
718 | * @source: The clock to be used (one of the PRCMU_CLKSRC_*). | |
719 | * @div: The divider to be applied. | |
720 | * | |
721 | * Configures one of the programmable clock outputs (CLKOUTs). | |
722 | * @div should be in the range [1,63] to request a configuration, or 0 to | |
723 | * inform that the configuration is no longer requested. | |
724 | */ | |
725 | int prcmu_config_clkout(u8 clkout, u8 source, u8 div) | |
726 | { | |
727 | static int requests[2]; | |
728 | int r = 0; | |
729 | unsigned long flags; | |
730 | u32 val; | |
731 | u32 bits; | |
732 | u32 mask; | |
733 | u32 div_mask; | |
734 | ||
735 | BUG_ON(clkout > 1); | |
736 | BUG_ON(div > 63); | |
737 | BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009)); | |
738 | ||
739 | if (!div && !requests[clkout]) | |
740 | return -EINVAL; | |
741 | ||
742 | switch (clkout) { | |
743 | case 0: | |
744 | div_mask = PRCM_CLKOCR_CLKODIV0_MASK; | |
745 | mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK); | |
746 | bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) | | |
747 | (div << PRCM_CLKOCR_CLKODIV0_SHIFT)); | |
748 | break; | |
749 | case 1: | |
750 | div_mask = PRCM_CLKOCR_CLKODIV1_MASK; | |
751 | mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK | | |
752 | PRCM_CLKOCR_CLK1TYPE); | |
753 | bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) | | |
754 | (div << PRCM_CLKOCR_CLKODIV1_SHIFT)); | |
755 | break; | |
756 | } | |
757 | bits &= mask; | |
758 | ||
759 | spin_lock_irqsave(&clkout_lock, flags); | |
760 | ||
c553b3ca | 761 | val = readl(PRCM_CLKOCR); |
3df57bcf MN |
762 | if (val & div_mask) { |
763 | if (div) { | |
764 | if ((val & mask) != bits) { | |
765 | r = -EBUSY; | |
766 | goto unlock_and_return; | |
767 | } | |
768 | } else { | |
769 | if ((val & mask & ~div_mask) != bits) { | |
770 | r = -EINVAL; | |
771 | goto unlock_and_return; | |
772 | } | |
773 | } | |
774 | } | |
c553b3ca | 775 | writel((bits | (val & ~mask)), PRCM_CLKOCR); |
3df57bcf MN |
776 | requests[clkout] += (div ? 1 : -1); |
777 | ||
778 | unlock_and_return: | |
779 | spin_unlock_irqrestore(&clkout_lock, flags); | |
780 | ||
781 | return r; | |
782 | } | |
783 | ||
73180f85 | 784 | int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll) |
3df57bcf MN |
785 | { |
786 | unsigned long flags; | |
787 | ||
788 | BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state)); | |
789 | ||
790 | spin_lock_irqsave(&mb0_transfer.lock, flags); | |
791 | ||
c553b3ca | 792 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) |
3df57bcf MN |
793 | cpu_relax(); |
794 | ||
795 | writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); | |
796 | writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE)); | |
797 | writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE)); | |
798 | writeb((keep_ulp_clk ? 1 : 0), | |
799 | (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE)); | |
800 | writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI)); | |
c553b3ca | 801 | writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
802 | |
803 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); | |
804 | ||
805 | return 0; | |
806 | } | |
807 | ||
4d64d2e3 MN |
808 | u8 db8500_prcmu_get_power_state_result(void) |
809 | { | |
810 | return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS); | |
811 | } | |
812 | ||
3df57bcf MN |
813 | /* This function should only be called while mb0_transfer.lock is held. */ |
814 | static void config_wakeups(void) | |
815 | { | |
816 | const u8 header[2] = { | |
817 | MB0H_CONFIG_WAKEUPS_EXE, | |
818 | MB0H_CONFIG_WAKEUPS_SLEEP | |
819 | }; | |
820 | static u32 last_dbb_events; | |
821 | static u32 last_abb_events; | |
822 | u32 dbb_events; | |
823 | u32 abb_events; | |
824 | unsigned int i; | |
825 | ||
826 | dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups; | |
827 | dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK); | |
828 | ||
829 | abb_events = mb0_transfer.req.abb_events; | |
830 | ||
831 | if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events)) | |
832 | return; | |
833 | ||
834 | for (i = 0; i < 2; i++) { | |
c553b3ca | 835 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) |
3df57bcf MN |
836 | cpu_relax(); |
837 | writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500)); | |
838 | writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500)); | |
839 | writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); | |
c553b3ca | 840 | writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
841 | } |
842 | last_dbb_events = dbb_events; | |
843 | last_abb_events = abb_events; | |
844 | } | |
845 | ||
73180f85 | 846 | void db8500_prcmu_enable_wakeups(u32 wakeups) |
3df57bcf MN |
847 | { |
848 | unsigned long flags; | |
849 | u32 bits; | |
850 | int i; | |
851 | ||
852 | BUG_ON(wakeups != (wakeups & VALID_WAKEUPS)); | |
853 | ||
854 | for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) { | |
855 | if (wakeups & BIT(i)) | |
856 | bits |= prcmu_wakeup_bit[i]; | |
857 | } | |
858 | ||
859 | spin_lock_irqsave(&mb0_transfer.lock, flags); | |
860 | ||
861 | mb0_transfer.req.dbb_wakeups = bits; | |
862 | config_wakeups(); | |
863 | ||
864 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); | |
865 | } | |
866 | ||
73180f85 | 867 | void db8500_prcmu_config_abb_event_readout(u32 abb_events) |
3df57bcf MN |
868 | { |
869 | unsigned long flags; | |
870 | ||
871 | spin_lock_irqsave(&mb0_transfer.lock, flags); | |
872 | ||
873 | mb0_transfer.req.abb_events = abb_events; | |
874 | config_wakeups(); | |
875 | ||
876 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); | |
877 | } | |
878 | ||
73180f85 | 879 | void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) |
3df57bcf MN |
880 | { |
881 | if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) | |
882 | *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500); | |
883 | else | |
884 | *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500); | |
885 | } | |
886 | ||
887 | /** | |
73180f85 | 888 | * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP |
3df57bcf MN |
889 | * @opp: The new ARM operating point to which transition is to be made |
890 | * Returns: 0 on success, non-zero on failure | |
891 | * | |
892 | * This function sets the the operating point of the ARM. | |
893 | */ | |
73180f85 | 894 | int db8500_prcmu_set_arm_opp(u8 opp) |
3df57bcf MN |
895 | { |
896 | int r; | |
897 | ||
898 | if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK) | |
899 | return -EINVAL; | |
900 | ||
901 | r = 0; | |
902 | ||
903 | mutex_lock(&mb1_transfer.lock); | |
904 | ||
c553b3ca | 905 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
3df57bcf MN |
906 | cpu_relax(); |
907 | ||
908 | writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
909 | writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); | |
910 | writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP)); | |
911 | ||
c553b3ca | 912 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
913 | wait_for_completion(&mb1_transfer.work); |
914 | ||
915 | if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || | |
916 | (mb1_transfer.ack.arm_opp != opp)) | |
917 | r = -EIO; | |
918 | ||
919 | mutex_unlock(&mb1_transfer.lock); | |
920 | ||
921 | return r; | |
922 | } | |
923 | ||
924 | /** | |
73180f85 | 925 | * db8500_prcmu_get_arm_opp - get the current ARM OPP |
3df57bcf MN |
926 | * |
927 | * Returns: the current ARM OPP | |
928 | */ | |
73180f85 | 929 | int db8500_prcmu_get_arm_opp(void) |
3df57bcf MN |
930 | { |
931 | return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP); | |
932 | } | |
933 | ||
934 | /** | |
0508901c | 935 | * db8500_prcmu_get_ddr_opp - get the current DDR OPP |
3df57bcf MN |
936 | * |
937 | * Returns: the current DDR OPP | |
938 | */ | |
0508901c | 939 | int db8500_prcmu_get_ddr_opp(void) |
3df57bcf | 940 | { |
c553b3ca | 941 | return readb(PRCM_DDR_SUBSYS_APE_MINBW); |
3df57bcf MN |
942 | } |
943 | ||
944 | /** | |
0508901c | 945 | * db8500_set_ddr_opp - set the appropriate DDR OPP |
3df57bcf MN |
946 | * @opp: The new DDR operating point to which transition is to be made |
947 | * Returns: 0 on success, non-zero on failure | |
948 | * | |
949 | * This function sets the operating point of the DDR. | |
950 | */ | |
7a4f2609 | 951 | static bool enable_set_ddr_opp; |
0508901c | 952 | int db8500_prcmu_set_ddr_opp(u8 opp) |
3df57bcf MN |
953 | { |
954 | if (opp < DDR_100_OPP || opp > DDR_25_OPP) | |
955 | return -EINVAL; | |
956 | /* Changing the DDR OPP can hang the hardware pre-v21 */ | |
7a4f2609 | 957 | if (enable_set_ddr_opp) |
c553b3ca | 958 | writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW); |
3df57bcf MN |
959 | |
960 | return 0; | |
961 | } | |
6b6fae2b | 962 | |
4d64d2e3 MN |
963 | /* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */ |
964 | static void request_even_slower_clocks(bool enable) | |
965 | { | |
b047d981 | 966 | u32 clock_reg[] = { |
4d64d2e3 MN |
967 | PRCM_ACLK_MGT, |
968 | PRCM_DMACLK_MGT | |
969 | }; | |
970 | unsigned long flags; | |
971 | unsigned int i; | |
972 | ||
973 | spin_lock_irqsave(&clk_mgt_lock, flags); | |
974 | ||
975 | /* Grab the HW semaphore. */ | |
976 | while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) | |
977 | cpu_relax(); | |
978 | ||
979 | for (i = 0; i < ARRAY_SIZE(clock_reg); i++) { | |
980 | u32 val; | |
981 | u32 div; | |
982 | ||
b047d981 | 983 | val = readl(prcmu_base + clock_reg[i]); |
4d64d2e3 MN |
984 | div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK); |
985 | if (enable) { | |
986 | if ((div <= 1) || (div > 15)) { | |
987 | pr_err("prcmu: Bad clock divider %d in %s\n", | |
988 | div, __func__); | |
989 | goto unlock_and_return; | |
990 | } | |
991 | div <<= 1; | |
992 | } else { | |
993 | if (div <= 2) | |
994 | goto unlock_and_return; | |
995 | div >>= 1; | |
996 | } | |
997 | val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) | | |
998 | (div & PRCM_CLK_MGT_CLKPLLDIV_MASK)); | |
b047d981 | 999 | writel(val, prcmu_base + clock_reg[i]); |
4d64d2e3 MN |
1000 | } |
1001 | ||
1002 | unlock_and_return: | |
1003 | /* Release the HW semaphore. */ | |
1004 | writel(0, PRCM_SEM); | |
1005 | ||
1006 | spin_unlock_irqrestore(&clk_mgt_lock, flags); | |
1007 | } | |
1008 | ||
3df57bcf | 1009 | /** |
0508901c | 1010 | * db8500_set_ape_opp - set the appropriate APE OPP |
3df57bcf MN |
1011 | * @opp: The new APE operating point to which transition is to be made |
1012 | * Returns: 0 on success, non-zero on failure | |
1013 | * | |
1014 | * This function sets the operating point of the APE. | |
1015 | */ | |
0508901c | 1016 | int db8500_prcmu_set_ape_opp(u8 opp) |
3df57bcf MN |
1017 | { |
1018 | int r = 0; | |
1019 | ||
4d64d2e3 MN |
1020 | if (opp == mb1_transfer.ape_opp) |
1021 | return 0; | |
1022 | ||
3df57bcf MN |
1023 | mutex_lock(&mb1_transfer.lock); |
1024 | ||
4d64d2e3 MN |
1025 | if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP) |
1026 | request_even_slower_clocks(false); | |
1027 | ||
1028 | if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP)) | |
1029 | goto skip_message; | |
1030 | ||
c553b3ca | 1031 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
3df57bcf MN |
1032 | cpu_relax(); |
1033 | ||
1034 | writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
1035 | writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); | |
4d64d2e3 MN |
1036 | writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp), |
1037 | (tcdm_base + PRCM_REQ_MB1_APE_OPP)); | |
3df57bcf | 1038 | |
c553b3ca | 1039 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1040 | wait_for_completion(&mb1_transfer.work); |
1041 | ||
1042 | if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || | |
1043 | (mb1_transfer.ack.ape_opp != opp)) | |
1044 | r = -EIO; | |
1045 | ||
4d64d2e3 MN |
1046 | skip_message: |
1047 | if ((!r && (opp == APE_50_PARTLY_25_OPP)) || | |
1048 | (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP))) | |
1049 | request_even_slower_clocks(true); | |
1050 | if (!r) | |
1051 | mb1_transfer.ape_opp = opp; | |
1052 | ||
3df57bcf MN |
1053 | mutex_unlock(&mb1_transfer.lock); |
1054 | ||
1055 | return r; | |
1056 | } | |
1057 | ||
1058 | /** | |
0508901c | 1059 | * db8500_prcmu_get_ape_opp - get the current APE OPP |
3df57bcf MN |
1060 | * |
1061 | * Returns: the current APE OPP | |
1062 | */ | |
0508901c | 1063 | int db8500_prcmu_get_ape_opp(void) |
3df57bcf MN |
1064 | { |
1065 | return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP); | |
1066 | } | |
1067 | ||
1068 | /** | |
686f871b | 1069 | * db8500_prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage |
3df57bcf MN |
1070 | * @enable: true to request the higher voltage, false to drop a request. |
1071 | * | |
1072 | * Calls to this function to enable and disable requests must be balanced. | |
1073 | */ | |
686f871b | 1074 | int db8500_prcmu_request_ape_opp_100_voltage(bool enable) |
3df57bcf MN |
1075 | { |
1076 | int r = 0; | |
1077 | u8 header; | |
1078 | static unsigned int requests; | |
1079 | ||
1080 | mutex_lock(&mb1_transfer.lock); | |
1081 | ||
1082 | if (enable) { | |
1083 | if (0 != requests++) | |
1084 | goto unlock_and_return; | |
1085 | header = MB1H_REQUEST_APE_OPP_100_VOLT; | |
1086 | } else { | |
1087 | if (requests == 0) { | |
1088 | r = -EIO; | |
1089 | goto unlock_and_return; | |
1090 | } else if (1 != requests--) { | |
1091 | goto unlock_and_return; | |
1092 | } | |
1093 | header = MB1H_RELEASE_APE_OPP_100_VOLT; | |
1094 | } | |
1095 | ||
c553b3ca | 1096 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
3df57bcf MN |
1097 | cpu_relax(); |
1098 | ||
1099 | writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
1100 | ||
c553b3ca | 1101 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1102 | wait_for_completion(&mb1_transfer.work); |
1103 | ||
1104 | if ((mb1_transfer.ack.header != header) || | |
1105 | ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) | |
1106 | r = -EIO; | |
1107 | ||
1108 | unlock_and_return: | |
1109 | mutex_unlock(&mb1_transfer.lock); | |
1110 | ||
1111 | return r; | |
1112 | } | |
1113 | ||
1114 | /** | |
1115 | * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup | |
1116 | * | |
1117 | * This function releases the power state requirements of a USB wakeup. | |
1118 | */ | |
1119 | int prcmu_release_usb_wakeup_state(void) | |
1120 | { | |
1121 | int r = 0; | |
1122 | ||
1123 | mutex_lock(&mb1_transfer.lock); | |
1124 | ||
c553b3ca | 1125 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
3df57bcf MN |
1126 | cpu_relax(); |
1127 | ||
1128 | writeb(MB1H_RELEASE_USB_WAKEUP, | |
1129 | (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
1130 | ||
c553b3ca | 1131 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1132 | wait_for_completion(&mb1_transfer.work); |
1133 | ||
1134 | if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) || | |
1135 | ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) | |
1136 | r = -EIO; | |
1137 | ||
1138 | mutex_unlock(&mb1_transfer.lock); | |
1139 | ||
1140 | return r; | |
1141 | } | |
1142 | ||
0837bb72 MN |
1143 | static int request_pll(u8 clock, bool enable) |
1144 | { | |
1145 | int r = 0; | |
1146 | ||
6b6fae2b MN |
1147 | if (clock == PRCMU_PLLSOC0) |
1148 | clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF); | |
1149 | else if (clock == PRCMU_PLLSOC1) | |
0837bb72 MN |
1150 | clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF); |
1151 | else | |
1152 | return -EINVAL; | |
1153 | ||
1154 | mutex_lock(&mb1_transfer.lock); | |
1155 | ||
1156 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) | |
1157 | cpu_relax(); | |
1158 | ||
1159 | writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
1160 | writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF)); | |
1161 | ||
1162 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); | |
1163 | wait_for_completion(&mb1_transfer.work); | |
1164 | ||
1165 | if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF) | |
1166 | r = -EIO; | |
1167 | ||
1168 | mutex_unlock(&mb1_transfer.lock); | |
1169 | ||
1170 | return r; | |
1171 | } | |
1172 | ||
3df57bcf | 1173 | /** |
73180f85 | 1174 | * db8500_prcmu_set_epod - set the state of a EPOD (power domain) |
3df57bcf MN |
1175 | * @epod_id: The EPOD to set |
1176 | * @epod_state: The new EPOD state | |
1177 | * | |
1178 | * This function sets the state of a EPOD (power domain). It may not be called | |
1179 | * from interrupt context. | |
1180 | */ | |
73180f85 | 1181 | int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state) |
3df57bcf MN |
1182 | { |
1183 | int r = 0; | |
1184 | bool ram_retention = false; | |
1185 | int i; | |
1186 | ||
1187 | /* check argument */ | |
1188 | BUG_ON(epod_id >= NUM_EPOD_ID); | |
1189 | ||
1190 | /* set flag if retention is possible */ | |
1191 | switch (epod_id) { | |
1192 | case EPOD_ID_SVAMMDSP: | |
1193 | case EPOD_ID_SIAMMDSP: | |
1194 | case EPOD_ID_ESRAM12: | |
1195 | case EPOD_ID_ESRAM34: | |
1196 | ram_retention = true; | |
1197 | break; | |
1198 | } | |
1199 | ||
1200 | /* check argument */ | |
1201 | BUG_ON(epod_state > EPOD_STATE_ON); | |
1202 | BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention); | |
1203 | ||
1204 | /* get lock */ | |
1205 | mutex_lock(&mb2_transfer.lock); | |
1206 | ||
1207 | /* wait for mailbox */ | |
c553b3ca | 1208 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2)) |
3df57bcf MN |
1209 | cpu_relax(); |
1210 | ||
1211 | /* fill in mailbox */ | |
1212 | for (i = 0; i < NUM_EPOD_ID; i++) | |
1213 | writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i)); | |
1214 | writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id)); | |
1215 | ||
1216 | writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2)); | |
1217 | ||
c553b3ca | 1218 | writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1219 | |
1220 | /* | |
1221 | * The current firmware version does not handle errors correctly, | |
1222 | * and we cannot recover if there is an error. | |
1223 | * This is expected to change when the firmware is updated. | |
1224 | */ | |
1225 | if (!wait_for_completion_timeout(&mb2_transfer.work, | |
1226 | msecs_to_jiffies(20000))) { | |
1227 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", | |
1228 | __func__); | |
1229 | r = -EIO; | |
1230 | goto unlock_and_return; | |
1231 | } | |
1232 | ||
1233 | if (mb2_transfer.ack.status != HWACC_PWR_ST_OK) | |
1234 | r = -EIO; | |
1235 | ||
1236 | unlock_and_return: | |
1237 | mutex_unlock(&mb2_transfer.lock); | |
1238 | return r; | |
1239 | } | |
1240 | ||
1241 | /** | |
1242 | * prcmu_configure_auto_pm - Configure autonomous power management. | |
1243 | * @sleep: Configuration for ApSleep. | |
1244 | * @idle: Configuration for ApIdle. | |
1245 | */ | |
1246 | void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, | |
1247 | struct prcmu_auto_pm_config *idle) | |
1248 | { | |
1249 | u32 sleep_cfg; | |
1250 | u32 idle_cfg; | |
1251 | unsigned long flags; | |
e3726fcf | 1252 | |
3df57bcf | 1253 | BUG_ON((sleep == NULL) || (idle == NULL)); |
650c2a21 | 1254 | |
3df57bcf MN |
1255 | sleep_cfg = (sleep->sva_auto_pm_enable & 0xF); |
1256 | sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF)); | |
1257 | sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF)); | |
1258 | sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF)); | |
1259 | sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF)); | |
1260 | sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF)); | |
e3726fcf | 1261 | |
3df57bcf MN |
1262 | idle_cfg = (idle->sva_auto_pm_enable & 0xF); |
1263 | idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF)); | |
1264 | idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF)); | |
1265 | idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF)); | |
1266 | idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF)); | |
1267 | idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF)); | |
e3726fcf | 1268 | |
3df57bcf | 1269 | spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags); |
e0befb23 | 1270 | |
3df57bcf MN |
1271 | /* |
1272 | * The autonomous power management configuration is done through | |
1273 | * fields in mailbox 2, but these fields are only used as shared | |
1274 | * variables - i.e. there is no need to send a message. | |
1275 | */ | |
1276 | writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP)); | |
1277 | writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE)); | |
e0befb23 | 1278 | |
3df57bcf MN |
1279 | mb2_transfer.auto_pm_enabled = |
1280 | ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || | |
1281 | (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) || | |
1282 | (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || | |
1283 | (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON)); | |
e0befb23 | 1284 | |
3df57bcf MN |
1285 | spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags); |
1286 | } | |
1287 | EXPORT_SYMBOL(prcmu_configure_auto_pm); | |
e3726fcf | 1288 | |
3df57bcf MN |
1289 | bool prcmu_is_auto_pm_enabled(void) |
1290 | { | |
1291 | return mb2_transfer.auto_pm_enabled; | |
1292 | } | |
e0befb23 | 1293 | |
3df57bcf MN |
1294 | static int request_sysclk(bool enable) |
1295 | { | |
1296 | int r; | |
1297 | unsigned long flags; | |
e3726fcf | 1298 | |
3df57bcf | 1299 | r = 0; |
e3726fcf | 1300 | |
3df57bcf | 1301 | mutex_lock(&mb3_transfer.sysclk_lock); |
e0befb23 | 1302 | |
3df57bcf | 1303 | spin_lock_irqsave(&mb3_transfer.lock, flags); |
e0befb23 | 1304 | |
c553b3ca | 1305 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3)) |
3df57bcf | 1306 | cpu_relax(); |
e0befb23 | 1307 | |
3df57bcf | 1308 | writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT)); |
e3726fcf | 1309 | |
3df57bcf | 1310 | writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3)); |
c553b3ca | 1311 | writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET); |
e3726fcf | 1312 | |
3df57bcf MN |
1313 | spin_unlock_irqrestore(&mb3_transfer.lock, flags); |
1314 | ||
1315 | /* | |
1316 | * The firmware only sends an ACK if we want to enable the | |
1317 | * SysClk, and it succeeds. | |
1318 | */ | |
1319 | if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work, | |
1320 | msecs_to_jiffies(20000))) { | |
1321 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", | |
1322 | __func__); | |
1323 | r = -EIO; | |
1324 | } | |
1325 | ||
1326 | mutex_unlock(&mb3_transfer.sysclk_lock); | |
1327 | ||
1328 | return r; | |
1329 | } | |
1330 | ||
1331 | static int request_timclk(bool enable) | |
1332 | { | |
1333 | u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK); | |
1334 | ||
1335 | if (!enable) | |
1336 | val |= PRCM_TCR_STOP_TIMERS; | |
c553b3ca | 1337 | writel(val, PRCM_TCR); |
3df57bcf MN |
1338 | |
1339 | return 0; | |
1340 | } | |
1341 | ||
6b6fae2b | 1342 | static int request_clock(u8 clock, bool enable) |
3df57bcf MN |
1343 | { |
1344 | u32 val; | |
1345 | unsigned long flags; | |
1346 | ||
1347 | spin_lock_irqsave(&clk_mgt_lock, flags); | |
1348 | ||
1349 | /* Grab the HW semaphore. */ | |
c553b3ca | 1350 | while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) |
3df57bcf MN |
1351 | cpu_relax(); |
1352 | ||
b047d981 | 1353 | val = readl(prcmu_base + clk_mgt[clock].offset); |
3df57bcf MN |
1354 | if (enable) { |
1355 | val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw); | |
1356 | } else { | |
1357 | clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); | |
1358 | val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK); | |
1359 | } | |
b047d981 | 1360 | writel(val, prcmu_base + clk_mgt[clock].offset); |
3df57bcf MN |
1361 | |
1362 | /* Release the HW semaphore. */ | |
c553b3ca | 1363 | writel(0, PRCM_SEM); |
3df57bcf MN |
1364 | |
1365 | spin_unlock_irqrestore(&clk_mgt_lock, flags); | |
1366 | ||
1367 | return 0; | |
1368 | } | |
1369 | ||
0837bb72 MN |
1370 | static int request_sga_clock(u8 clock, bool enable) |
1371 | { | |
1372 | u32 val; | |
1373 | int ret; | |
1374 | ||
1375 | if (enable) { | |
1376 | val = readl(PRCM_CGATING_BYPASS); | |
1377 | writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); | |
1378 | } | |
1379 | ||
6b6fae2b | 1380 | ret = request_clock(clock, enable); |
0837bb72 MN |
1381 | |
1382 | if (!ret && !enable) { | |
1383 | val = readl(PRCM_CGATING_BYPASS); | |
1384 | writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); | |
1385 | } | |
1386 | ||
1387 | return ret; | |
1388 | } | |
1389 | ||
6b6fae2b MN |
1390 | static inline bool plldsi_locked(void) |
1391 | { | |
1392 | return (readl(PRCM_PLLDSI_LOCKP) & | |
1393 | (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 | | |
1394 | PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) == | |
1395 | (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 | | |
1396 | PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3); | |
1397 | } | |
1398 | ||
1399 | static int request_plldsi(bool enable) | |
1400 | { | |
1401 | int r = 0; | |
1402 | u32 val; | |
1403 | ||
1404 | writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP | | |
1405 | PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ? | |
1406 | PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET)); | |
1407 | ||
1408 | val = readl(PRCM_PLLDSI_ENABLE); | |
1409 | if (enable) | |
1410 | val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; | |
1411 | else | |
1412 | val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; | |
1413 | writel(val, PRCM_PLLDSI_ENABLE); | |
1414 | ||
1415 | if (enable) { | |
1416 | unsigned int i; | |
1417 | bool locked = plldsi_locked(); | |
1418 | ||
1419 | for (i = 10; !locked && (i > 0); --i) { | |
1420 | udelay(100); | |
1421 | locked = plldsi_locked(); | |
1422 | } | |
1423 | if (locked) { | |
1424 | writel(PRCM_APE_RESETN_DSIPLL_RESETN, | |
1425 | PRCM_APE_RESETN_SET); | |
1426 | } else { | |
1427 | writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP | | |
1428 | PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), | |
1429 | PRCM_MMIP_LS_CLAMP_SET); | |
1430 | val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; | |
1431 | writel(val, PRCM_PLLDSI_ENABLE); | |
1432 | r = -EAGAIN; | |
1433 | } | |
1434 | } else { | |
1435 | writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR); | |
1436 | } | |
1437 | return r; | |
1438 | } | |
1439 | ||
1440 | static int request_dsiclk(u8 n, bool enable) | |
1441 | { | |
1442 | u32 val; | |
1443 | ||
1444 | val = readl(PRCM_DSI_PLLOUT_SEL); | |
1445 | val &= ~dsiclk[n].divsel_mask; | |
1446 | val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) << | |
1447 | dsiclk[n].divsel_shift); | |
1448 | writel(val, PRCM_DSI_PLLOUT_SEL); | |
1449 | return 0; | |
1450 | } | |
1451 | ||
1452 | static int request_dsiescclk(u8 n, bool enable) | |
1453 | { | |
1454 | u32 val; | |
1455 | ||
1456 | val = readl(PRCM_DSITVCLK_DIV); | |
1457 | enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en); | |
1458 | writel(val, PRCM_DSITVCLK_DIV); | |
1459 | return 0; | |
1460 | } | |
1461 | ||
3df57bcf | 1462 | /** |
73180f85 | 1463 | * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled. |
3df57bcf MN |
1464 | * @clock: The clock for which the request is made. |
1465 | * @enable: Whether the clock should be enabled (true) or disabled (false). | |
1466 | * | |
1467 | * This function should only be used by the clock implementation. | |
1468 | * Do not use it from any other place! | |
1469 | */ | |
73180f85 | 1470 | int db8500_prcmu_request_clock(u8 clock, bool enable) |
3df57bcf | 1471 | { |
6b6fae2b | 1472 | if (clock == PRCMU_SGACLK) |
0837bb72 | 1473 | return request_sga_clock(clock, enable); |
6b6fae2b MN |
1474 | else if (clock < PRCMU_NUM_REG_CLOCKS) |
1475 | return request_clock(clock, enable); | |
1476 | else if (clock == PRCMU_TIMCLK) | |
3df57bcf | 1477 | return request_timclk(enable); |
6b6fae2b MN |
1478 | else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) |
1479 | return request_dsiclk((clock - PRCMU_DSI0CLK), enable); | |
1480 | else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) | |
1481 | return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable); | |
1482 | else if (clock == PRCMU_PLLDSI) | |
1483 | return request_plldsi(enable); | |
1484 | else if (clock == PRCMU_SYSCLK) | |
3df57bcf | 1485 | return request_sysclk(enable); |
6b6fae2b | 1486 | else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1)) |
0837bb72 | 1487 | return request_pll(clock, enable); |
6b6fae2b MN |
1488 | else |
1489 | return -EINVAL; | |
1490 | } | |
1491 | ||
1492 | static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate, | |
1493 | int branch) | |
1494 | { | |
1495 | u64 rate; | |
1496 | u32 val; | |
1497 | u32 d; | |
1498 | u32 div = 1; | |
1499 | ||
1500 | val = readl(reg); | |
1501 | ||
1502 | rate = src_rate; | |
1503 | rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT); | |
1504 | ||
1505 | d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT); | |
1506 | if (d > 1) | |
1507 | div *= d; | |
1508 | ||
1509 | d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT); | |
1510 | if (d > 1) | |
1511 | div *= d; | |
1512 | ||
1513 | if (val & PRCM_PLL_FREQ_SELDIV2) | |
1514 | div *= 2; | |
1515 | ||
1516 | if ((branch == PLL_FIX) || ((branch == PLL_DIV) && | |
1517 | (val & PRCM_PLL_FREQ_DIV2EN) && | |
1518 | ((reg == PRCM_PLLSOC0_FREQ) || | |
20aee5b6 | 1519 | (reg == PRCM_PLLARM_FREQ) || |
6b6fae2b MN |
1520 | (reg == PRCM_PLLDDR_FREQ)))) |
1521 | div *= 2; | |
1522 | ||
1523 | (void)do_div(rate, div); | |
1524 | ||
1525 | return (unsigned long)rate; | |
1526 | } | |
1527 | ||
1528 | #define ROOT_CLOCK_RATE 38400000 | |
1529 | ||
1530 | static unsigned long clock_rate(u8 clock) | |
1531 | { | |
1532 | u32 val; | |
1533 | u32 pllsw; | |
1534 | unsigned long rate = ROOT_CLOCK_RATE; | |
1535 | ||
b047d981 | 1536 | val = readl(prcmu_base + clk_mgt[clock].offset); |
6b6fae2b MN |
1537 | |
1538 | if (val & PRCM_CLK_MGT_CLK38) { | |
1539 | if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV)) | |
1540 | rate /= 2; | |
1541 | return rate; | |
1542 | } | |
1543 | ||
1544 | val |= clk_mgt[clock].pllsw; | |
1545 | pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); | |
1546 | ||
1547 | if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0) | |
1548 | rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch); | |
1549 | else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1) | |
1550 | rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch); | |
1551 | else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR) | |
1552 | rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch); | |
1553 | else | |
1554 | return 0; | |
1555 | ||
1556 | if ((clock == PRCMU_SGACLK) && | |
1557 | (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) { | |
1558 | u64 r = (rate * 10); | |
1559 | ||
1560 | (void)do_div(r, 25); | |
1561 | return (unsigned long)r; | |
1562 | } | |
1563 | val &= PRCM_CLK_MGT_CLKPLLDIV_MASK; | |
1564 | if (val) | |
1565 | return rate / val; | |
1566 | else | |
1567 | return 0; | |
1568 | } | |
20aee5b6 | 1569 | |
b2302c87 | 1570 | static unsigned long armss_rate(void) |
20aee5b6 MJ |
1571 | { |
1572 | u32 r; | |
1573 | unsigned long rate; | |
1574 | ||
1575 | r = readl(PRCM_ARM_CHGCLKREQ); | |
1576 | ||
1577 | if (r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ) { | |
1578 | /* External ARMCLKFIX clock */ | |
1579 | ||
1580 | rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX); | |
1581 | ||
1582 | /* Check PRCM_ARM_CHGCLKREQ divider */ | |
1583 | if (!(r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL)) | |
1584 | rate /= 2; | |
1585 | ||
1586 | /* Check PRCM_ARMCLKFIX_MGT divider */ | |
1587 | r = readl(PRCM_ARMCLKFIX_MGT); | |
1588 | r &= PRCM_CLK_MGT_CLKPLLDIV_MASK; | |
1589 | rate /= r; | |
1590 | ||
1591 | } else {/* ARM PLL */ | |
1592 | rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV); | |
1593 | } | |
1594 | ||
b2302c87 | 1595 | return rate; |
20aee5b6 | 1596 | } |
6b6fae2b MN |
1597 | |
1598 | static unsigned long dsiclk_rate(u8 n) | |
1599 | { | |
1600 | u32 divsel; | |
1601 | u32 div = 1; | |
1602 | ||
1603 | divsel = readl(PRCM_DSI_PLLOUT_SEL); | |
1604 | divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift); | |
1605 | ||
1606 | if (divsel == PRCM_DSI_PLLOUT_SEL_OFF) | |
1607 | divsel = dsiclk[n].divsel; | |
e9d7b4b5 UH |
1608 | else |
1609 | dsiclk[n].divsel = divsel; | |
6b6fae2b MN |
1610 | |
1611 | switch (divsel) { | |
1612 | case PRCM_DSI_PLLOUT_SEL_PHI_4: | |
1613 | div *= 2; | |
1614 | case PRCM_DSI_PLLOUT_SEL_PHI_2: | |
1615 | div *= 2; | |
1616 | case PRCM_DSI_PLLOUT_SEL_PHI: | |
1617 | return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), | |
1618 | PLL_RAW) / div; | |
e62ccf3a | 1619 | default: |
6b6fae2b | 1620 | return 0; |
e62ccf3a | 1621 | } |
6b6fae2b MN |
1622 | } |
1623 | ||
1624 | static unsigned long dsiescclk_rate(u8 n) | |
1625 | { | |
1626 | u32 div; | |
1627 | ||
1628 | div = readl(PRCM_DSITVCLK_DIV); | |
1629 | div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift)); | |
1630 | return clock_rate(PRCMU_TVCLK) / max((u32)1, div); | |
1631 | } | |
1632 | ||
1633 | unsigned long prcmu_clock_rate(u8 clock) | |
1634 | { | |
e62ccf3a | 1635 | if (clock < PRCMU_NUM_REG_CLOCKS) |
6b6fae2b MN |
1636 | return clock_rate(clock); |
1637 | else if (clock == PRCMU_TIMCLK) | |
1638 | return ROOT_CLOCK_RATE / 16; | |
1639 | else if (clock == PRCMU_SYSCLK) | |
1640 | return ROOT_CLOCK_RATE; | |
1641 | else if (clock == PRCMU_PLLSOC0) | |
1642 | return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW); | |
1643 | else if (clock == PRCMU_PLLSOC1) | |
1644 | return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW); | |
20aee5b6 MJ |
1645 | else if (clock == PRCMU_ARMSS) |
1646 | return armss_rate(); | |
6b6fae2b MN |
1647 | else if (clock == PRCMU_PLLDDR) |
1648 | return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW); | |
1649 | else if (clock == PRCMU_PLLDSI) | |
1650 | return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), | |
1651 | PLL_RAW); | |
1652 | else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) | |
1653 | return dsiclk_rate(clock - PRCMU_DSI0CLK); | |
1654 | else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) | |
1655 | return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK); | |
1656 | else | |
1657 | return 0; | |
1658 | } | |
1659 | ||
1660 | static unsigned long clock_source_rate(u32 clk_mgt_val, int branch) | |
1661 | { | |
1662 | if (clk_mgt_val & PRCM_CLK_MGT_CLK38) | |
1663 | return ROOT_CLOCK_RATE; | |
1664 | clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK; | |
1665 | if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0) | |
1666 | return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch); | |
1667 | else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1) | |
1668 | return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch); | |
1669 | else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR) | |
1670 | return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch); | |
1671 | else | |
1672 | return 0; | |
1673 | } | |
1674 | ||
1675 | static u32 clock_divider(unsigned long src_rate, unsigned long rate) | |
1676 | { | |
1677 | u32 div; | |
1678 | ||
1679 | div = (src_rate / rate); | |
1680 | if (div == 0) | |
1681 | return 1; | |
1682 | if (rate < (src_rate / div)) | |
1683 | div++; | |
1684 | return div; | |
1685 | } | |
1686 | ||
1687 | static long round_clock_rate(u8 clock, unsigned long rate) | |
1688 | { | |
1689 | u32 val; | |
1690 | u32 div; | |
1691 | unsigned long src_rate; | |
1692 | long rounded_rate; | |
1693 | ||
b047d981 | 1694 | val = readl(prcmu_base + clk_mgt[clock].offset); |
6b6fae2b MN |
1695 | src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), |
1696 | clk_mgt[clock].branch); | |
1697 | div = clock_divider(src_rate, rate); | |
1698 | if (val & PRCM_CLK_MGT_CLK38) { | |
1699 | if (clk_mgt[clock].clk38div) { | |
1700 | if (div > 2) | |
1701 | div = 2; | |
1702 | } else { | |
1703 | div = 1; | |
1704 | } | |
1705 | } else if ((clock == PRCMU_SGACLK) && (div == 3)) { | |
1706 | u64 r = (src_rate * 10); | |
1707 | ||
1708 | (void)do_div(r, 25); | |
1709 | if (r <= rate) | |
1710 | return (unsigned long)r; | |
1711 | } | |
1712 | rounded_rate = (src_rate / min(div, (u32)31)); | |
1713 | ||
1714 | return rounded_rate; | |
1715 | } | |
1716 | ||
b2302c87 UH |
1717 | /* CPU FREQ table, may be changed due to if MAX_OPP is supported. */ |
1718 | static struct cpufreq_frequency_table db8500_cpufreq_table[] = { | |
50701588 VK |
1719 | { .frequency = 200000, .driver_data = ARM_EXTCLK,}, |
1720 | { .frequency = 400000, .driver_data = ARM_50_OPP,}, | |
1721 | { .frequency = 800000, .driver_data = ARM_100_OPP,}, | |
b2302c87 UH |
1722 | { .frequency = CPUFREQ_TABLE_END,}, /* To be used for MAX_OPP. */ |
1723 | { .frequency = CPUFREQ_TABLE_END,}, | |
1724 | }; | |
1725 | ||
1726 | static long round_armss_rate(unsigned long rate) | |
1727 | { | |
fdb56c45 | 1728 | struct cpufreq_frequency_table *pos; |
b2302c87 | 1729 | long freq = 0; |
b2302c87 UH |
1730 | |
1731 | /* cpufreq table frequencies is in KHz. */ | |
1732 | rate = rate / 1000; | |
1733 | ||
1734 | /* Find the corresponding arm opp from the cpufreq table. */ | |
fdb56c45 SK |
1735 | cpufreq_for_each_entry(pos, db8500_cpufreq_table) { |
1736 | freq = pos->frequency; | |
b2302c87 UH |
1737 | if (freq == rate) |
1738 | break; | |
b2302c87 UH |
1739 | } |
1740 | ||
1741 | /* Return the last valid value, even if a match was not found. */ | |
1742 | return freq * 1000; | |
1743 | } | |
1744 | ||
6b6fae2b MN |
1745 | #define MIN_PLL_VCO_RATE 600000000ULL |
1746 | #define MAX_PLL_VCO_RATE 1680640000ULL | |
1747 | ||
1748 | static long round_plldsi_rate(unsigned long rate) | |
1749 | { | |
1750 | long rounded_rate = 0; | |
1751 | unsigned long src_rate; | |
1752 | unsigned long rem; | |
1753 | u32 r; | |
1754 | ||
1755 | src_rate = clock_rate(PRCMU_HDMICLK); | |
1756 | rem = rate; | |
1757 | ||
1758 | for (r = 7; (rem > 0) && (r > 0); r--) { | |
1759 | u64 d; | |
1760 | ||
1761 | d = (r * rate); | |
1762 | (void)do_div(d, src_rate); | |
1763 | if (d < 6) | |
1764 | d = 6; | |
1765 | else if (d > 255) | |
1766 | d = 255; | |
1767 | d *= src_rate; | |
1768 | if (((2 * d) < (r * MIN_PLL_VCO_RATE)) || | |
1769 | ((r * MAX_PLL_VCO_RATE) < (2 * d))) | |
1770 | continue; | |
1771 | (void)do_div(d, r); | |
1772 | if (rate < d) { | |
1773 | if (rounded_rate == 0) | |
1774 | rounded_rate = (long)d; | |
1775 | break; | |
1776 | } | |
1777 | if ((rate - d) < rem) { | |
1778 | rem = (rate - d); | |
1779 | rounded_rate = (long)d; | |
1780 | } | |
1781 | } | |
1782 | return rounded_rate; | |
1783 | } | |
1784 | ||
1785 | static long round_dsiclk_rate(unsigned long rate) | |
1786 | { | |
1787 | u32 div; | |
1788 | unsigned long src_rate; | |
1789 | long rounded_rate; | |
1790 | ||
1791 | src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), | |
1792 | PLL_RAW); | |
1793 | div = clock_divider(src_rate, rate); | |
1794 | rounded_rate = (src_rate / ((div > 2) ? 4 : div)); | |
1795 | ||
1796 | return rounded_rate; | |
1797 | } | |
1798 | ||
1799 | static long round_dsiescclk_rate(unsigned long rate) | |
1800 | { | |
1801 | u32 div; | |
1802 | unsigned long src_rate; | |
1803 | long rounded_rate; | |
1804 | ||
1805 | src_rate = clock_rate(PRCMU_TVCLK); | |
1806 | div = clock_divider(src_rate, rate); | |
1807 | rounded_rate = (src_rate / min(div, (u32)255)); | |
1808 | ||
1809 | return rounded_rate; | |
1810 | } | |
1811 | ||
1812 | long prcmu_round_clock_rate(u8 clock, unsigned long rate) | |
1813 | { | |
1814 | if (clock < PRCMU_NUM_REG_CLOCKS) | |
1815 | return round_clock_rate(clock, rate); | |
b2302c87 UH |
1816 | else if (clock == PRCMU_ARMSS) |
1817 | return round_armss_rate(rate); | |
6b6fae2b MN |
1818 | else if (clock == PRCMU_PLLDSI) |
1819 | return round_plldsi_rate(rate); | |
1820 | else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) | |
1821 | return round_dsiclk_rate(rate); | |
1822 | else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) | |
1823 | return round_dsiescclk_rate(rate); | |
1824 | else | |
1825 | return (long)prcmu_clock_rate(clock); | |
1826 | } | |
1827 | ||
1828 | static void set_clock_rate(u8 clock, unsigned long rate) | |
1829 | { | |
1830 | u32 val; | |
1831 | u32 div; | |
1832 | unsigned long src_rate; | |
1833 | unsigned long flags; | |
1834 | ||
1835 | spin_lock_irqsave(&clk_mgt_lock, flags); | |
1836 | ||
1837 | /* Grab the HW semaphore. */ | |
1838 | while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) | |
1839 | cpu_relax(); | |
1840 | ||
b047d981 | 1841 | val = readl(prcmu_base + clk_mgt[clock].offset); |
6b6fae2b MN |
1842 | src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), |
1843 | clk_mgt[clock].branch); | |
1844 | div = clock_divider(src_rate, rate); | |
1845 | if (val & PRCM_CLK_MGT_CLK38) { | |
1846 | if (clk_mgt[clock].clk38div) { | |
1847 | if (div > 1) | |
1848 | val |= PRCM_CLK_MGT_CLK38DIV; | |
1849 | else | |
1850 | val &= ~PRCM_CLK_MGT_CLK38DIV; | |
1851 | } | |
1852 | } else if (clock == PRCMU_SGACLK) { | |
1853 | val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK | | |
1854 | PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN); | |
1855 | if (div == 3) { | |
1856 | u64 r = (src_rate * 10); | |
1857 | ||
1858 | (void)do_div(r, 25); | |
1859 | if (r <= rate) { | |
1860 | val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN; | |
1861 | div = 0; | |
1862 | } | |
1863 | } | |
1864 | val |= min(div, (u32)31); | |
1865 | } else { | |
1866 | val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK; | |
1867 | val |= min(div, (u32)31); | |
1868 | } | |
b047d981 | 1869 | writel(val, prcmu_base + clk_mgt[clock].offset); |
6b6fae2b MN |
1870 | |
1871 | /* Release the HW semaphore. */ | |
1872 | writel(0, PRCM_SEM); | |
1873 | ||
1874 | spin_unlock_irqrestore(&clk_mgt_lock, flags); | |
1875 | } | |
1876 | ||
b2302c87 UH |
1877 | static int set_armss_rate(unsigned long rate) |
1878 | { | |
fdb56c45 | 1879 | struct cpufreq_frequency_table *pos; |
b2302c87 UH |
1880 | |
1881 | /* cpufreq table frequencies is in KHz. */ | |
1882 | rate = rate / 1000; | |
1883 | ||
1884 | /* Find the corresponding arm opp from the cpufreq table. */ | |
fdb56c45 SK |
1885 | cpufreq_for_each_entry(pos, db8500_cpufreq_table) |
1886 | if (pos->frequency == rate) | |
b2302c87 | 1887 | break; |
b2302c87 | 1888 | |
fdb56c45 | 1889 | if (pos->frequency != rate) |
b2302c87 UH |
1890 | return -EINVAL; |
1891 | ||
1892 | /* Set the new arm opp. */ | |
fdb56c45 | 1893 | return db8500_prcmu_set_arm_opp(pos->driver_data); |
b2302c87 UH |
1894 | } |
1895 | ||
6b6fae2b MN |
1896 | static int set_plldsi_rate(unsigned long rate) |
1897 | { | |
1898 | unsigned long src_rate; | |
1899 | unsigned long rem; | |
1900 | u32 pll_freq = 0; | |
1901 | u32 r; | |
1902 | ||
1903 | src_rate = clock_rate(PRCMU_HDMICLK); | |
1904 | rem = rate; | |
1905 | ||
1906 | for (r = 7; (rem > 0) && (r > 0); r--) { | |
1907 | u64 d; | |
1908 | u64 hwrate; | |
1909 | ||
1910 | d = (r * rate); | |
1911 | (void)do_div(d, src_rate); | |
1912 | if (d < 6) | |
1913 | d = 6; | |
1914 | else if (d > 255) | |
1915 | d = 255; | |
1916 | hwrate = (d * src_rate); | |
1917 | if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) || | |
1918 | ((r * MAX_PLL_VCO_RATE) < (2 * hwrate))) | |
1919 | continue; | |
1920 | (void)do_div(hwrate, r); | |
1921 | if (rate < hwrate) { | |
1922 | if (pll_freq == 0) | |
1923 | pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) | | |
1924 | (r << PRCM_PLL_FREQ_R_SHIFT)); | |
1925 | break; | |
1926 | } | |
1927 | if ((rate - hwrate) < rem) { | |
1928 | rem = (rate - hwrate); | |
1929 | pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) | | |
1930 | (r << PRCM_PLL_FREQ_R_SHIFT)); | |
1931 | } | |
1932 | } | |
1933 | if (pll_freq == 0) | |
1934 | return -EINVAL; | |
1935 | ||
1936 | pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT); | |
1937 | writel(pll_freq, PRCM_PLLDSI_FREQ); | |
1938 | ||
1939 | return 0; | |
1940 | } | |
1941 | ||
1942 | static void set_dsiclk_rate(u8 n, unsigned long rate) | |
1943 | { | |
1944 | u32 val; | |
1945 | u32 div; | |
1946 | ||
1947 | div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ, | |
1948 | clock_rate(PRCMU_HDMICLK), PLL_RAW), rate); | |
1949 | ||
1950 | dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI : | |
1951 | (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 : | |
1952 | /* else */ PRCM_DSI_PLLOUT_SEL_PHI_4; | |
1953 | ||
1954 | val = readl(PRCM_DSI_PLLOUT_SEL); | |
1955 | val &= ~dsiclk[n].divsel_mask; | |
1956 | val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift); | |
1957 | writel(val, PRCM_DSI_PLLOUT_SEL); | |
1958 | } | |
1959 | ||
1960 | static void set_dsiescclk_rate(u8 n, unsigned long rate) | |
1961 | { | |
1962 | u32 val; | |
1963 | u32 div; | |
1964 | ||
1965 | div = clock_divider(clock_rate(PRCMU_TVCLK), rate); | |
1966 | val = readl(PRCM_DSITVCLK_DIV); | |
1967 | val &= ~dsiescclk[n].div_mask; | |
1968 | val |= (min(div, (u32)255) << dsiescclk[n].div_shift); | |
1969 | writel(val, PRCM_DSITVCLK_DIV); | |
1970 | } | |
1971 | ||
1972 | int prcmu_set_clock_rate(u8 clock, unsigned long rate) | |
1973 | { | |
1974 | if (clock < PRCMU_NUM_REG_CLOCKS) | |
1975 | set_clock_rate(clock, rate); | |
b2302c87 UH |
1976 | else if (clock == PRCMU_ARMSS) |
1977 | return set_armss_rate(rate); | |
6b6fae2b MN |
1978 | else if (clock == PRCMU_PLLDSI) |
1979 | return set_plldsi_rate(rate); | |
1980 | else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) | |
1981 | set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate); | |
1982 | else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) | |
1983 | set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate); | |
1984 | return 0; | |
3df57bcf MN |
1985 | } |
1986 | ||
73180f85 | 1987 | int db8500_prcmu_config_esram0_deep_sleep(u8 state) |
3df57bcf MN |
1988 | { |
1989 | if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) || | |
1990 | (state < ESRAM0_DEEP_SLEEP_STATE_OFF)) | |
1991 | return -EINVAL; | |
1992 | ||
1993 | mutex_lock(&mb4_transfer.lock); | |
1994 | ||
c553b3ca | 1995 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
3df57bcf MN |
1996 | cpu_relax(); |
1997 | ||
1998 | writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); | |
1999 | writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON), | |
2000 | (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE)); | |
2001 | writeb(DDR_PWR_STATE_ON, | |
2002 | (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE)); | |
2003 | writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST)); | |
2004 | ||
c553b3ca | 2005 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
2006 | wait_for_completion(&mb4_transfer.work); |
2007 | ||
2008 | mutex_unlock(&mb4_transfer.lock); | |
2009 | ||
2010 | return 0; | |
2011 | } | |
2012 | ||
0508901c | 2013 | int db8500_prcmu_config_hotdog(u8 threshold) |
3df57bcf MN |
2014 | { |
2015 | mutex_lock(&mb4_transfer.lock); | |
2016 | ||
c553b3ca | 2017 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
3df57bcf MN |
2018 | cpu_relax(); |
2019 | ||
2020 | writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD)); | |
2021 | writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); | |
2022 | ||
c553b3ca | 2023 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
2024 | wait_for_completion(&mb4_transfer.work); |
2025 | ||
2026 | mutex_unlock(&mb4_transfer.lock); | |
2027 | ||
2028 | return 0; | |
2029 | } | |
2030 | ||
0508901c | 2031 | int db8500_prcmu_config_hotmon(u8 low, u8 high) |
3df57bcf MN |
2032 | { |
2033 | mutex_lock(&mb4_transfer.lock); | |
2034 | ||
c553b3ca | 2035 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
3df57bcf MN |
2036 | cpu_relax(); |
2037 | ||
2038 | writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW)); | |
2039 | writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH)); | |
2040 | writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH), | |
2041 | (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG)); | |
2042 | writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); | |
2043 | ||
c553b3ca | 2044 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
2045 | wait_for_completion(&mb4_transfer.work); |
2046 | ||
2047 | mutex_unlock(&mb4_transfer.lock); | |
2048 | ||
2049 | return 0; | |
2050 | } | |
2051 | ||
2052 | static int config_hot_period(u16 val) | |
2053 | { | |
2054 | mutex_lock(&mb4_transfer.lock); | |
2055 | ||
c553b3ca | 2056 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
3df57bcf MN |
2057 | cpu_relax(); |
2058 | ||
2059 | writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD)); | |
2060 | writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); | |
2061 | ||
c553b3ca | 2062 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
2063 | wait_for_completion(&mb4_transfer.work); |
2064 | ||
2065 | mutex_unlock(&mb4_transfer.lock); | |
2066 | ||
2067 | return 0; | |
2068 | } | |
2069 | ||
0508901c | 2070 | int db8500_prcmu_start_temp_sense(u16 cycles32k) |
3df57bcf MN |
2071 | { |
2072 | if (cycles32k == 0xFFFF) | |
2073 | return -EINVAL; | |
2074 | ||
2075 | return config_hot_period(cycles32k); | |
2076 | } | |
2077 | ||
0508901c | 2078 | int db8500_prcmu_stop_temp_sense(void) |
3df57bcf MN |
2079 | { |
2080 | return config_hot_period(0xFFFF); | |
2081 | } | |
2082 | ||
84165b80 JA |
2083 | static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3) |
2084 | { | |
2085 | ||
2086 | mutex_lock(&mb4_transfer.lock); | |
2087 | ||
2088 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) | |
2089 | cpu_relax(); | |
2090 | ||
2091 | writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0)); | |
2092 | writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1)); | |
2093 | writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2)); | |
2094 | writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3)); | |
2095 | ||
2096 | writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); | |
2097 | ||
2098 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); | |
2099 | wait_for_completion(&mb4_transfer.work); | |
2100 | ||
2101 | mutex_unlock(&mb4_transfer.lock); | |
2102 | ||
2103 | return 0; | |
2104 | ||
2105 | } | |
2106 | ||
0508901c | 2107 | int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off) |
84165b80 JA |
2108 | { |
2109 | BUG_ON(num == 0 || num > 0xf); | |
2110 | return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0, | |
2111 | sleep_auto_off ? A9WDOG_AUTO_OFF_EN : | |
2112 | A9WDOG_AUTO_OFF_DIS); | |
2113 | } | |
6f8cfa99 | 2114 | EXPORT_SYMBOL(db8500_prcmu_config_a9wdog); |
84165b80 | 2115 | |
0508901c | 2116 | int db8500_prcmu_enable_a9wdog(u8 id) |
84165b80 JA |
2117 | { |
2118 | return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0); | |
2119 | } | |
6f8cfa99 | 2120 | EXPORT_SYMBOL(db8500_prcmu_enable_a9wdog); |
84165b80 | 2121 | |
0508901c | 2122 | int db8500_prcmu_disable_a9wdog(u8 id) |
84165b80 JA |
2123 | { |
2124 | return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0); | |
2125 | } | |
6f8cfa99 | 2126 | EXPORT_SYMBOL(db8500_prcmu_disable_a9wdog); |
84165b80 | 2127 | |
0508901c | 2128 | int db8500_prcmu_kick_a9wdog(u8 id) |
84165b80 JA |
2129 | { |
2130 | return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0); | |
2131 | } | |
6f8cfa99 | 2132 | EXPORT_SYMBOL(db8500_prcmu_kick_a9wdog); |
84165b80 JA |
2133 | |
2134 | /* | |
2135 | * timeout is 28 bit, in ms. | |
2136 | */ | |
0508901c | 2137 | int db8500_prcmu_load_a9wdog(u8 id, u32 timeout) |
84165b80 | 2138 | { |
84165b80 JA |
2139 | return prcmu_a9wdog(MB4H_A9WDOG_LOAD, |
2140 | (id & A9WDOG_ID_MASK) | | |
2141 | /* | |
2142 | * Put the lowest 28 bits of timeout at | |
2143 | * offset 4. Four first bits are used for id. | |
2144 | */ | |
2145 | (u8)((timeout << 4) & 0xf0), | |
2146 | (u8)((timeout >> 4) & 0xff), | |
2147 | (u8)((timeout >> 12) & 0xff), | |
2148 | (u8)((timeout >> 20) & 0xff)); | |
2149 | } | |
6f8cfa99 | 2150 | EXPORT_SYMBOL(db8500_prcmu_load_a9wdog); |
84165b80 | 2151 | |
e3726fcf LW |
2152 | /** |
2153 | * prcmu_abb_read() - Read register value(s) from the ABB. | |
2154 | * @slave: The I2C slave address. | |
2155 | * @reg: The (start) register address. | |
2156 | * @value: The read out value(s). | |
2157 | * @size: The number of registers to read. | |
2158 | * | |
2159 | * Reads register value(s) from the ABB. | |
2160 | * @size has to be 1 for the current firmware version. | |
2161 | */ | |
2162 | int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) | |
2163 | { | |
2164 | int r; | |
2165 | ||
2166 | if (size != 1) | |
2167 | return -EINVAL; | |
2168 | ||
3df57bcf | 2169 | mutex_lock(&mb5_transfer.lock); |
e3726fcf | 2170 | |
c553b3ca | 2171 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) |
e3726fcf LW |
2172 | cpu_relax(); |
2173 | ||
3c3e4898 | 2174 | writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5)); |
3df57bcf MN |
2175 | writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); |
2176 | writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); | |
2177 | writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); | |
2178 | writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); | |
2179 | ||
c553b3ca | 2180 | writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); |
e3726fcf | 2181 | |
e3726fcf | 2182 | if (!wait_for_completion_timeout(&mb5_transfer.work, |
3df57bcf MN |
2183 | msecs_to_jiffies(20000))) { |
2184 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", | |
2185 | __func__); | |
e3726fcf | 2186 | r = -EIO; |
3df57bcf MN |
2187 | } else { |
2188 | r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO); | |
e3726fcf | 2189 | } |
3df57bcf | 2190 | |
e3726fcf LW |
2191 | if (!r) |
2192 | *value = mb5_transfer.ack.value; | |
2193 | ||
e3726fcf | 2194 | mutex_unlock(&mb5_transfer.lock); |
3df57bcf | 2195 | |
e3726fcf LW |
2196 | return r; |
2197 | } | |
e3726fcf LW |
2198 | |
2199 | /** | |
3c3e4898 | 2200 | * prcmu_abb_write_masked() - Write masked register value(s) to the ABB. |
e3726fcf LW |
2201 | * @slave: The I2C slave address. |
2202 | * @reg: The (start) register address. | |
2203 | * @value: The value(s) to write. | |
3c3e4898 | 2204 | * @mask: The mask(s) to use. |
e3726fcf LW |
2205 | * @size: The number of registers to write. |
2206 | * | |
3c3e4898 MN |
2207 | * Writes masked register value(s) to the ABB. |
2208 | * For each @value, only the bits set to 1 in the corresponding @mask | |
2209 | * will be written. The other bits are not changed. | |
e3726fcf LW |
2210 | * @size has to be 1 for the current firmware version. |
2211 | */ | |
3c3e4898 | 2212 | int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size) |
e3726fcf LW |
2213 | { |
2214 | int r; | |
2215 | ||
2216 | if (size != 1) | |
2217 | return -EINVAL; | |
2218 | ||
3df57bcf | 2219 | mutex_lock(&mb5_transfer.lock); |
e3726fcf | 2220 | |
c553b3ca | 2221 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) |
e3726fcf LW |
2222 | cpu_relax(); |
2223 | ||
3c3e4898 | 2224 | writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5)); |
3df57bcf MN |
2225 | writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); |
2226 | writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); | |
2227 | writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); | |
2228 | writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); | |
2229 | ||
c553b3ca | 2230 | writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); |
e3726fcf | 2231 | |
e3726fcf | 2232 | if (!wait_for_completion_timeout(&mb5_transfer.work, |
3df57bcf MN |
2233 | msecs_to_jiffies(20000))) { |
2234 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", | |
2235 | __func__); | |
e3726fcf | 2236 | r = -EIO; |
3df57bcf MN |
2237 | } else { |
2238 | r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO); | |
e3726fcf | 2239 | } |
e3726fcf | 2240 | |
e3726fcf | 2241 | mutex_unlock(&mb5_transfer.lock); |
3df57bcf | 2242 | |
e3726fcf LW |
2243 | return r; |
2244 | } | |
e3726fcf | 2245 | |
3c3e4898 MN |
2246 | /** |
2247 | * prcmu_abb_write() - Write register value(s) to the ABB. | |
2248 | * @slave: The I2C slave address. | |
2249 | * @reg: The (start) register address. | |
2250 | * @value: The value(s) to write. | |
2251 | * @size: The number of registers to write. | |
2252 | * | |
2253 | * Writes register value(s) to the ABB. | |
2254 | * @size has to be 1 for the current firmware version. | |
2255 | */ | |
2256 | int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) | |
2257 | { | |
2258 | u8 mask = ~0; | |
2259 | ||
2260 | return prcmu_abb_write_masked(slave, reg, value, &mask, size); | |
2261 | } | |
2262 | ||
3df57bcf MN |
2263 | /** |
2264 | * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem | |
2265 | */ | |
5261e101 | 2266 | int prcmu_ac_wake_req(void) |
e0befb23 | 2267 | { |
3df57bcf | 2268 | u32 val; |
5261e101 | 2269 | int ret = 0; |
e0befb23 | 2270 | |
3df57bcf | 2271 | mutex_lock(&mb0_transfer.ac_wake_lock); |
e0befb23 | 2272 | |
c553b3ca | 2273 | val = readl(PRCM_HOSTACCESS_REQ); |
3df57bcf MN |
2274 | if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ) |
2275 | goto unlock_and_return; | |
e0befb23 | 2276 | |
3df57bcf | 2277 | atomic_set(&ac_wake_req_state, 1); |
e0befb23 | 2278 | |
5261e101 AM |
2279 | /* |
2280 | * Force Modem Wake-up before hostaccess_req ping-pong. | |
2281 | * It prevents Modem to enter in Sleep while acking the hostaccess | |
2282 | * request. The 31us delay has been calculated by HWI. | |
2283 | */ | |
2284 | val |= PRCM_HOSTACCESS_REQ_WAKE_REQ; | |
2285 | writel(val, PRCM_HOSTACCESS_REQ); | |
2286 | ||
2287 | udelay(31); | |
2288 | ||
2289 | val |= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ; | |
2290 | writel(val, PRCM_HOSTACCESS_REQ); | |
e0befb23 | 2291 | |
3df57bcf | 2292 | if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, |
d6e3002e | 2293 | msecs_to_jiffies(5000))) { |
57265bc1 | 2294 | pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", |
d6e3002e | 2295 | __func__); |
5261e101 | 2296 | ret = -EFAULT; |
3df57bcf | 2297 | } |
e0befb23 | 2298 | |
3df57bcf MN |
2299 | unlock_and_return: |
2300 | mutex_unlock(&mb0_transfer.ac_wake_lock); | |
5261e101 | 2301 | return ret; |
e0befb23 MP |
2302 | } |
2303 | ||
2304 | /** | |
3df57bcf | 2305 | * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem |
e0befb23 | 2306 | */ |
ffb01160 | 2307 | void prcmu_ac_sleep_req(void) |
e0befb23 | 2308 | { |
3df57bcf MN |
2309 | u32 val; |
2310 | ||
2311 | mutex_lock(&mb0_transfer.ac_wake_lock); | |
2312 | ||
c553b3ca | 2313 | val = readl(PRCM_HOSTACCESS_REQ); |
3df57bcf MN |
2314 | if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)) |
2315 | goto unlock_and_return; | |
2316 | ||
2317 | writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ), | |
c553b3ca | 2318 | PRCM_HOSTACCESS_REQ); |
3df57bcf MN |
2319 | |
2320 | if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, | |
d6e3002e | 2321 | msecs_to_jiffies(5000))) { |
57265bc1 | 2322 | pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", |
3df57bcf MN |
2323 | __func__); |
2324 | } | |
2325 | ||
2326 | atomic_set(&ac_wake_req_state, 0); | |
2327 | ||
2328 | unlock_and_return: | |
2329 | mutex_unlock(&mb0_transfer.ac_wake_lock); | |
e0befb23 | 2330 | } |
e0befb23 | 2331 | |
73180f85 | 2332 | bool db8500_prcmu_is_ac_wake_requested(void) |
e0befb23 | 2333 | { |
3df57bcf | 2334 | return (atomic_read(&ac_wake_req_state) != 0); |
e0befb23 | 2335 | } |
e0befb23 MP |
2336 | |
2337 | /** | |
73180f85 | 2338 | * db8500_prcmu_system_reset - System reset |
e0befb23 | 2339 | * |
73180f85 | 2340 | * Saves the reset reason code and then sets the APE_SOFTRST register which |
3df57bcf | 2341 | * fires interrupt to fw |
e0befb23 | 2342 | */ |
73180f85 | 2343 | void db8500_prcmu_system_reset(u16 reset_code) |
e0befb23 | 2344 | { |
3df57bcf | 2345 | writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON)); |
c553b3ca | 2346 | writel(1, PRCM_APE_SOFTRST); |
e0befb23 | 2347 | } |
e0befb23 | 2348 | |
597045de SR |
2349 | /** |
2350 | * db8500_prcmu_get_reset_code - Retrieve SW reset reason code | |
2351 | * | |
2352 | * Retrieves the reset reason code stored by prcmu_system_reset() before | |
2353 | * last restart. | |
2354 | */ | |
2355 | u16 db8500_prcmu_get_reset_code(void) | |
2356 | { | |
2357 | return readw(tcdm_base + PRCM_SW_RST_REASON); | |
2358 | } | |
2359 | ||
e0befb23 | 2360 | /** |
0508901c | 2361 | * db8500_prcmu_reset_modem - ask the PRCMU to reset modem |
e0befb23 | 2362 | */ |
0508901c | 2363 | void db8500_prcmu_modem_reset(void) |
e0befb23 | 2364 | { |
3df57bcf MN |
2365 | mutex_lock(&mb1_transfer.lock); |
2366 | ||
c553b3ca | 2367 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
3df57bcf MN |
2368 | cpu_relax(); |
2369 | ||
2370 | writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
c553b3ca | 2371 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
2372 | wait_for_completion(&mb1_transfer.work); |
2373 | ||
2374 | /* | |
2375 | * No need to check return from PRCMU as modem should go in reset state | |
2376 | * This state is already managed by upper layer | |
2377 | */ | |
2378 | ||
2379 | mutex_unlock(&mb1_transfer.lock); | |
e0befb23 | 2380 | } |
e0befb23 | 2381 | |
3df57bcf | 2382 | static void ack_dbb_wakeup(void) |
e0befb23 | 2383 | { |
3df57bcf MN |
2384 | unsigned long flags; |
2385 | ||
2386 | spin_lock_irqsave(&mb0_transfer.lock, flags); | |
2387 | ||
c553b3ca | 2388 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) |
3df57bcf MN |
2389 | cpu_relax(); |
2390 | ||
2391 | writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); | |
c553b3ca | 2392 | writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
2393 | |
2394 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); | |
e0befb23 | 2395 | } |
e0befb23 | 2396 | |
3df57bcf | 2397 | static inline void print_unknown_header_warning(u8 n, u8 header) |
e0befb23 | 2398 | { |
3df57bcf MN |
2399 | pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n", |
2400 | header, n); | |
e0befb23 MP |
2401 | } |
2402 | ||
3df57bcf | 2403 | static bool read_mailbox_0(void) |
e3726fcf | 2404 | { |
3df57bcf MN |
2405 | bool r; |
2406 | u32 ev; | |
2407 | unsigned int n; | |
2408 | u8 header; | |
2409 | ||
2410 | header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0); | |
2411 | switch (header) { | |
2412 | case MB0H_WAKEUP_EXE: | |
2413 | case MB0H_WAKEUP_SLEEP: | |
2414 | if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) | |
2415 | ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500); | |
2416 | else | |
2417 | ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500); | |
2418 | ||
2419 | if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK)) | |
2420 | complete(&mb0_transfer.ac_wake_work); | |
2421 | if (ev & WAKEUP_BIT_SYSCLK_OK) | |
2422 | complete(&mb3_transfer.sysclk_work); | |
2423 | ||
2424 | ev &= mb0_transfer.req.dbb_irqs; | |
2425 | ||
2426 | for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) { | |
2427 | if (ev & prcmu_irq_bit[n]) | |
89d9b1c9 | 2428 | generic_handle_irq(irq_find_mapping(db8500_irq_domain, n)); |
3df57bcf MN |
2429 | } |
2430 | r = true; | |
2431 | break; | |
2432 | default: | |
2433 | print_unknown_header_warning(0, header); | |
2434 | r = false; | |
2435 | break; | |
2436 | } | |
c553b3ca | 2437 | writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR); |
3df57bcf | 2438 | return r; |
e3726fcf LW |
2439 | } |
2440 | ||
3df57bcf | 2441 | static bool read_mailbox_1(void) |
e3726fcf | 2442 | { |
3df57bcf MN |
2443 | mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1); |
2444 | mb1_transfer.ack.arm_opp = readb(tcdm_base + | |
2445 | PRCM_ACK_MB1_CURRENT_ARM_OPP); | |
2446 | mb1_transfer.ack.ape_opp = readb(tcdm_base + | |
2447 | PRCM_ACK_MB1_CURRENT_APE_OPP); | |
2448 | mb1_transfer.ack.ape_voltage_status = readb(tcdm_base + | |
2449 | PRCM_ACK_MB1_APE_VOLTAGE_STATUS); | |
c553b3ca | 2450 | writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR); |
e0befb23 | 2451 | complete(&mb1_transfer.work); |
3df57bcf | 2452 | return false; |
e3726fcf LW |
2453 | } |
2454 | ||
3df57bcf | 2455 | static bool read_mailbox_2(void) |
e3726fcf | 2456 | { |
3df57bcf | 2457 | mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS); |
c553b3ca | 2458 | writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR); |
3df57bcf MN |
2459 | complete(&mb2_transfer.work); |
2460 | return false; | |
e3726fcf LW |
2461 | } |
2462 | ||
3df57bcf | 2463 | static bool read_mailbox_3(void) |
e3726fcf | 2464 | { |
c553b3ca | 2465 | writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR); |
3df57bcf | 2466 | return false; |
e3726fcf LW |
2467 | } |
2468 | ||
3df57bcf | 2469 | static bool read_mailbox_4(void) |
e3726fcf | 2470 | { |
3df57bcf MN |
2471 | u8 header; |
2472 | bool do_complete = true; | |
2473 | ||
2474 | header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4); | |
2475 | switch (header) { | |
2476 | case MB4H_MEM_ST: | |
2477 | case MB4H_HOTDOG: | |
2478 | case MB4H_HOTMON: | |
2479 | case MB4H_HOT_PERIOD: | |
a592c2e2 MN |
2480 | case MB4H_A9WDOG_CONF: |
2481 | case MB4H_A9WDOG_EN: | |
2482 | case MB4H_A9WDOG_DIS: | |
2483 | case MB4H_A9WDOG_LOAD: | |
2484 | case MB4H_A9WDOG_KICK: | |
3df57bcf MN |
2485 | break; |
2486 | default: | |
2487 | print_unknown_header_warning(4, header); | |
2488 | do_complete = false; | |
2489 | break; | |
2490 | } | |
2491 | ||
c553b3ca | 2492 | writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR); |
3df57bcf MN |
2493 | |
2494 | if (do_complete) | |
2495 | complete(&mb4_transfer.work); | |
2496 | ||
2497 | return false; | |
e3726fcf LW |
2498 | } |
2499 | ||
3df57bcf | 2500 | static bool read_mailbox_5(void) |
e3726fcf | 2501 | { |
3df57bcf MN |
2502 | mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS); |
2503 | mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL); | |
c553b3ca | 2504 | writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR); |
e3726fcf | 2505 | complete(&mb5_transfer.work); |
3df57bcf | 2506 | return false; |
e3726fcf LW |
2507 | } |
2508 | ||
3df57bcf | 2509 | static bool read_mailbox_6(void) |
e3726fcf | 2510 | { |
c553b3ca | 2511 | writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR); |
3df57bcf | 2512 | return false; |
e3726fcf LW |
2513 | } |
2514 | ||
3df57bcf | 2515 | static bool read_mailbox_7(void) |
e3726fcf | 2516 | { |
c553b3ca | 2517 | writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR); |
3df57bcf | 2518 | return false; |
e3726fcf LW |
2519 | } |
2520 | ||
3df57bcf | 2521 | static bool (* const read_mailbox[NUM_MB])(void) = { |
e3726fcf LW |
2522 | read_mailbox_0, |
2523 | read_mailbox_1, | |
2524 | read_mailbox_2, | |
2525 | read_mailbox_3, | |
2526 | read_mailbox_4, | |
2527 | read_mailbox_5, | |
2528 | read_mailbox_6, | |
2529 | read_mailbox_7 | |
2530 | }; | |
2531 | ||
2532 | static irqreturn_t prcmu_irq_handler(int irq, void *data) | |
2533 | { | |
2534 | u32 bits; | |
2535 | u8 n; | |
3df57bcf | 2536 | irqreturn_t r; |
e3726fcf | 2537 | |
c553b3ca | 2538 | bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS); |
e3726fcf LW |
2539 | if (unlikely(!bits)) |
2540 | return IRQ_NONE; | |
2541 | ||
3df57bcf | 2542 | r = IRQ_HANDLED; |
e3726fcf LW |
2543 | for (n = 0; bits; n++) { |
2544 | if (bits & MBOX_BIT(n)) { | |
2545 | bits -= MBOX_BIT(n); | |
3df57bcf MN |
2546 | if (read_mailbox[n]()) |
2547 | r = IRQ_WAKE_THREAD; | |
e3726fcf LW |
2548 | } |
2549 | } | |
3df57bcf MN |
2550 | return r; |
2551 | } | |
2552 | ||
2553 | static irqreturn_t prcmu_irq_thread_fn(int irq, void *data) | |
2554 | { | |
2555 | ack_dbb_wakeup(); | |
e3726fcf LW |
2556 | return IRQ_HANDLED; |
2557 | } | |
2558 | ||
3df57bcf MN |
2559 | static void prcmu_mask_work(struct work_struct *work) |
2560 | { | |
2561 | unsigned long flags; | |
2562 | ||
2563 | spin_lock_irqsave(&mb0_transfer.lock, flags); | |
2564 | ||
2565 | config_wakeups(); | |
2566 | ||
2567 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); | |
2568 | } | |
2569 | ||
2570 | static void prcmu_irq_mask(struct irq_data *d) | |
2571 | { | |
2572 | unsigned long flags; | |
2573 | ||
2574 | spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); | |
2575 | ||
f3f1f0a1 | 2576 | mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->hwirq]; |
3df57bcf MN |
2577 | |
2578 | spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); | |
2579 | ||
2580 | if (d->irq != IRQ_PRCMU_CA_SLEEP) | |
2581 | schedule_work(&mb0_transfer.mask_work); | |
2582 | } | |
2583 | ||
2584 | static void prcmu_irq_unmask(struct irq_data *d) | |
2585 | { | |
2586 | unsigned long flags; | |
2587 | ||
2588 | spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); | |
2589 | ||
f3f1f0a1 | 2590 | mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->hwirq]; |
3df57bcf MN |
2591 | |
2592 | spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); | |
2593 | ||
2594 | if (d->irq != IRQ_PRCMU_CA_SLEEP) | |
2595 | schedule_work(&mb0_transfer.mask_work); | |
2596 | } | |
2597 | ||
2598 | static void noop(struct irq_data *d) | |
2599 | { | |
2600 | } | |
2601 | ||
2602 | static struct irq_chip prcmu_irq_chip = { | |
2603 | .name = "prcmu", | |
2604 | .irq_disable = prcmu_irq_mask, | |
2605 | .irq_ack = noop, | |
2606 | .irq_mask = prcmu_irq_mask, | |
2607 | .irq_unmask = prcmu_irq_unmask, | |
2608 | }; | |
2609 | ||
05ec260e | 2610 | static __init char *fw_project_name(u32 project) |
b58d12fe MN |
2611 | { |
2612 | switch (project) { | |
2613 | case PRCMU_FW_PROJECT_U8500: | |
2614 | return "U8500"; | |
05ec260e LW |
2615 | case PRCMU_FW_PROJECT_U8400: |
2616 | return "U8400"; | |
b58d12fe MN |
2617 | case PRCMU_FW_PROJECT_U9500: |
2618 | return "U9500"; | |
05ec260e LW |
2619 | case PRCMU_FW_PROJECT_U8500_MBB: |
2620 | return "U8500 MBB"; | |
2621 | case PRCMU_FW_PROJECT_U8500_C1: | |
2622 | return "U8500 C1"; | |
2623 | case PRCMU_FW_PROJECT_U8500_C2: | |
2624 | return "U8500 C2"; | |
2625 | case PRCMU_FW_PROJECT_U8500_C3: | |
2626 | return "U8500 C3"; | |
2627 | case PRCMU_FW_PROJECT_U8500_C4: | |
2628 | return "U8500 C4"; | |
2629 | case PRCMU_FW_PROJECT_U9500_MBL: | |
2630 | return "U9500 MBL"; | |
2631 | case PRCMU_FW_PROJECT_U8500_MBL: | |
2632 | return "U8500 MBL"; | |
2633 | case PRCMU_FW_PROJECT_U8500_MBL2: | |
2634 | return "U8500 MBL2"; | |
5f96a1a6 | 2635 | case PRCMU_FW_PROJECT_U8520: |
05ec260e | 2636 | return "U8520 MBL"; |
1927ddf6 BJ |
2637 | case PRCMU_FW_PROJECT_U8420: |
2638 | return "U8420"; | |
05ec260e LW |
2639 | case PRCMU_FW_PROJECT_U9540: |
2640 | return "U9540"; | |
2641 | case PRCMU_FW_PROJECT_A9420: | |
2642 | return "A9420"; | |
2643 | case PRCMU_FW_PROJECT_L8540: | |
2644 | return "L8540"; | |
2645 | case PRCMU_FW_PROJECT_L8580: | |
2646 | return "L8580"; | |
b58d12fe MN |
2647 | default: |
2648 | return "Unknown"; | |
2649 | } | |
2650 | } | |
2651 | ||
f3f1f0a1 LJ |
2652 | static int db8500_irq_map(struct irq_domain *d, unsigned int virq, |
2653 | irq_hw_number_t hwirq) | |
2654 | { | |
2655 | irq_set_chip_and_handler(virq, &prcmu_irq_chip, | |
2656 | handle_simple_irq); | |
f3f1f0a1 LJ |
2657 | |
2658 | return 0; | |
2659 | } | |
2660 | ||
7ce7b26f | 2661 | static const struct irq_domain_ops db8500_irq_ops = { |
89d9b1c9 LW |
2662 | .map = db8500_irq_map, |
2663 | .xlate = irq_domain_xlate_twocell, | |
f3f1f0a1 LJ |
2664 | }; |
2665 | ||
f864c46a | 2666 | static int db8500_irq_init(struct device_node *np) |
f3f1f0a1 | 2667 | { |
89d9b1c9 | 2668 | int i; |
a7238e43 | 2669 | |
a7238e43 | 2670 | db8500_irq_domain = irq_domain_add_simple( |
f864c46a | 2671 | np, NUM_PRCMU_WAKEUPS, 0, |
a7238e43 | 2672 | &db8500_irq_ops, NULL); |
f3f1f0a1 LJ |
2673 | |
2674 | if (!db8500_irq_domain) { | |
2675 | pr_err("Failed to create irqdomain\n"); | |
2676 | return -ENOSYS; | |
2677 | } | |
2678 | ||
89d9b1c9 LW |
2679 | /* All wakeups will be used, so create mappings for all */ |
2680 | for (i = 0; i < NUM_PRCMU_WAKEUPS; i++) | |
2681 | irq_create_mapping(db8500_irq_domain, i); | |
2682 | ||
f3f1f0a1 LJ |
2683 | return 0; |
2684 | } | |
2685 | ||
05ec260e LW |
2686 | static void dbx500_fw_version_init(struct platform_device *pdev, |
2687 | u32 version_offset) | |
fcbd458e | 2688 | { |
05ec260e LW |
2689 | struct resource *res; |
2690 | void __iomem *tcpm_base; | |
741cdecf | 2691 | u32 version; |
3df57bcf | 2692 | |
05ec260e LW |
2693 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
2694 | "prcmu-tcpm"); | |
2695 | if (!res) { | |
2696 | dev_err(&pdev->dev, | |
2697 | "Error: no prcmu tcpm memory region provided\n"); | |
2698 | return; | |
2699 | } | |
2700 | tcpm_base = ioremap(res->start, resource_size(res)); | |
741cdecf LJ |
2701 | if (!tcpm_base) { |
2702 | dev_err(&pdev->dev, "no prcmu tcpm mem region provided\n"); | |
2703 | return; | |
fcbd458e | 2704 | } |
741cdecf LJ |
2705 | |
2706 | version = readl(tcpm_base + version_offset); | |
2707 | fw_info.version.project = (version & 0xFF); | |
2708 | fw_info.version.api_version = (version >> 8) & 0xFF; | |
2709 | fw_info.version.func_version = (version >> 16) & 0xFF; | |
2710 | fw_info.version.errata = (version >> 24) & 0xFF; | |
2711 | strncpy(fw_info.version.project_name, | |
2712 | fw_project_name(fw_info.version.project), | |
2713 | PRCMU_FW_PROJECT_NAME_LEN); | |
2714 | fw_info.valid = true; | |
2715 | pr_info("PRCMU firmware: %s(%d), version %d.%d.%d\n", | |
2716 | fw_info.version.project_name, | |
2717 | fw_info.version.project, | |
2718 | fw_info.version.api_version, | |
2719 | fw_info.version.func_version, | |
2720 | fw_info.version.errata); | |
2721 | iounmap(tcpm_base); | |
05ec260e | 2722 | } |
e0befb23 | 2723 | |
9a47a8dc | 2724 | void __init db8500_prcmu_early_init(u32 phy_base, u32 size) |
05ec260e | 2725 | { |
9a47a8dc LW |
2726 | /* |
2727 | * This is a temporary remap to bring up the clocks. It is | |
2728 | * subsequently replaces with a real remap. After the merge of | |
2729 | * the mailbox subsystem all of this early code goes away, and the | |
2730 | * clock driver can probe independently. An early initcall will | |
2731 | * still be needed, but it can be diverted into drivers/clk/ux500. | |
2732 | */ | |
2733 | prcmu_base = ioremap(phy_base, size); | |
2734 | if (!prcmu_base) | |
2735 | pr_err("%s: ioremap() of prcmu registers failed!\n", __func__); | |
2736 | ||
3df57bcf MN |
2737 | spin_lock_init(&mb0_transfer.lock); |
2738 | spin_lock_init(&mb0_transfer.dbb_irqs_lock); | |
2739 | mutex_init(&mb0_transfer.ac_wake_lock); | |
2740 | init_completion(&mb0_transfer.ac_wake_work); | |
e0befb23 MP |
2741 | mutex_init(&mb1_transfer.lock); |
2742 | init_completion(&mb1_transfer.work); | |
4d64d2e3 | 2743 | mb1_transfer.ape_opp = APE_NO_CHANGE; |
3df57bcf MN |
2744 | mutex_init(&mb2_transfer.lock); |
2745 | init_completion(&mb2_transfer.work); | |
2746 | spin_lock_init(&mb2_transfer.auto_pm_lock); | |
2747 | spin_lock_init(&mb3_transfer.lock); | |
2748 | mutex_init(&mb3_transfer.sysclk_lock); | |
2749 | init_completion(&mb3_transfer.sysclk_work); | |
2750 | mutex_init(&mb4_transfer.lock); | |
2751 | init_completion(&mb4_transfer.work); | |
e3726fcf LW |
2752 | mutex_init(&mb5_transfer.lock); |
2753 | init_completion(&mb5_transfer.work); | |
2754 | ||
3df57bcf | 2755 | INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work); |
3df57bcf MN |
2756 | } |
2757 | ||
0508901c | 2758 | static void __init init_prcm_registers(void) |
d65e12d7 MN |
2759 | { |
2760 | u32 val; | |
2761 | ||
2762 | val = readl(PRCM_A9PL_FORCE_CLKEN); | |
2763 | val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN | | |
2764 | PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN); | |
2765 | writel(val, (PRCM_A9PL_FORCE_CLKEN)); | |
2766 | } | |
2767 | ||
1032fbfd BJ |
2768 | /* |
2769 | * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC | |
2770 | */ | |
2771 | static struct regulator_consumer_supply db8500_vape_consumers[] = { | |
2772 | REGULATOR_SUPPLY("v-ape", NULL), | |
2773 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"), | |
2774 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"), | |
2775 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"), | |
2776 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"), | |
ae840635 | 2777 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.4"), |
1032fbfd BJ |
2778 | /* "v-mmc" changed to "vcore" in the mainline kernel */ |
2779 | REGULATOR_SUPPLY("vcore", "sdi0"), | |
2780 | REGULATOR_SUPPLY("vcore", "sdi1"), | |
2781 | REGULATOR_SUPPLY("vcore", "sdi2"), | |
2782 | REGULATOR_SUPPLY("vcore", "sdi3"), | |
2783 | REGULATOR_SUPPLY("vcore", "sdi4"), | |
2784 | REGULATOR_SUPPLY("v-dma", "dma40.0"), | |
2785 | REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"), | |
2786 | /* "v-uart" changed to "vcore" in the mainline kernel */ | |
2787 | REGULATOR_SUPPLY("vcore", "uart0"), | |
2788 | REGULATOR_SUPPLY("vcore", "uart1"), | |
2789 | REGULATOR_SUPPLY("vcore", "uart2"), | |
2790 | REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"), | |
992b133a | 2791 | REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"), |
bc367481 | 2792 | REGULATOR_SUPPLY("vddvario", "smsc911x.0"), |
1032fbfd BJ |
2793 | }; |
2794 | ||
2795 | static struct regulator_consumer_supply db8500_vsmps2_consumers[] = { | |
1032fbfd BJ |
2796 | REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"), |
2797 | /* AV8100 regulator */ | |
2798 | REGULATOR_SUPPLY("hdmi_1v8", "0-0070"), | |
2799 | }; | |
2800 | ||
2801 | static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = { | |
992b133a | 2802 | REGULATOR_SUPPLY("vsupply", "b2r2_bus"), |
624e87c2 BJ |
2803 | REGULATOR_SUPPLY("vsupply", "mcde"), |
2804 | }; | |
2805 | ||
2806 | /* SVA MMDSP regulator switch */ | |
2807 | static struct regulator_consumer_supply db8500_svammdsp_consumers[] = { | |
2808 | REGULATOR_SUPPLY("sva-mmdsp", "cm_control"), | |
2809 | }; | |
2810 | ||
2811 | /* SVA pipe regulator switch */ | |
2812 | static struct regulator_consumer_supply db8500_svapipe_consumers[] = { | |
2813 | REGULATOR_SUPPLY("sva-pipe", "cm_control"), | |
2814 | }; | |
2815 | ||
2816 | /* SIA MMDSP regulator switch */ | |
2817 | static struct regulator_consumer_supply db8500_siammdsp_consumers[] = { | |
2818 | REGULATOR_SUPPLY("sia-mmdsp", "cm_control"), | |
2819 | }; | |
2820 | ||
2821 | /* SIA pipe regulator switch */ | |
2822 | static struct regulator_consumer_supply db8500_siapipe_consumers[] = { | |
2823 | REGULATOR_SUPPLY("sia-pipe", "cm_control"), | |
2824 | }; | |
2825 | ||
2826 | static struct regulator_consumer_supply db8500_sga_consumers[] = { | |
2827 | REGULATOR_SUPPLY("v-mali", NULL), | |
2828 | }; | |
2829 | ||
2830 | /* ESRAM1 and 2 regulator switch */ | |
2831 | static struct regulator_consumer_supply db8500_esram12_consumers[] = { | |
2832 | REGULATOR_SUPPLY("esram12", "cm_control"), | |
2833 | }; | |
2834 | ||
2835 | /* ESRAM3 and 4 regulator switch */ | |
2836 | static struct regulator_consumer_supply db8500_esram34_consumers[] = { | |
2837 | REGULATOR_SUPPLY("v-esram34", "mcde"), | |
2838 | REGULATOR_SUPPLY("esram34", "cm_control"), | |
992b133a | 2839 | REGULATOR_SUPPLY("lcla_esram", "dma40.0"), |
1032fbfd BJ |
2840 | }; |
2841 | ||
2842 | static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = { | |
2843 | [DB8500_REGULATOR_VAPE] = { | |
2844 | .constraints = { | |
2845 | .name = "db8500-vape", | |
2846 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
1e45860f | 2847 | .always_on = true, |
1032fbfd BJ |
2848 | }, |
2849 | .consumer_supplies = db8500_vape_consumers, | |
2850 | .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers), | |
2851 | }, | |
2852 | [DB8500_REGULATOR_VARM] = { | |
2853 | .constraints = { | |
2854 | .name = "db8500-varm", | |
2855 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2856 | }, | |
2857 | }, | |
2858 | [DB8500_REGULATOR_VMODEM] = { | |
2859 | .constraints = { | |
2860 | .name = "db8500-vmodem", | |
2861 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2862 | }, | |
2863 | }, | |
2864 | [DB8500_REGULATOR_VPLL] = { | |
2865 | .constraints = { | |
2866 | .name = "db8500-vpll", | |
2867 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2868 | }, | |
2869 | }, | |
2870 | [DB8500_REGULATOR_VSMPS1] = { | |
2871 | .constraints = { | |
2872 | .name = "db8500-vsmps1", | |
2873 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2874 | }, | |
2875 | }, | |
2876 | [DB8500_REGULATOR_VSMPS2] = { | |
2877 | .constraints = { | |
2878 | .name = "db8500-vsmps2", | |
2879 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2880 | }, | |
2881 | .consumer_supplies = db8500_vsmps2_consumers, | |
2882 | .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers), | |
2883 | }, | |
2884 | [DB8500_REGULATOR_VSMPS3] = { | |
2885 | .constraints = { | |
2886 | .name = "db8500-vsmps3", | |
2887 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2888 | }, | |
2889 | }, | |
2890 | [DB8500_REGULATOR_VRF1] = { | |
2891 | .constraints = { | |
2892 | .name = "db8500-vrf1", | |
2893 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2894 | }, | |
2895 | }, | |
2896 | [DB8500_REGULATOR_SWITCH_SVAMMDSP] = { | |
992b133a | 2897 | /* dependency to u8500-vape is handled outside regulator framework */ |
1032fbfd BJ |
2898 | .constraints = { |
2899 | .name = "db8500-sva-mmdsp", | |
2900 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2901 | }, | |
624e87c2 BJ |
2902 | .consumer_supplies = db8500_svammdsp_consumers, |
2903 | .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers), | |
1032fbfd BJ |
2904 | }, |
2905 | [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = { | |
2906 | .constraints = { | |
2907 | /* "ret" means "retention" */ | |
2908 | .name = "db8500-sva-mmdsp-ret", | |
2909 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2910 | }, | |
2911 | }, | |
2912 | [DB8500_REGULATOR_SWITCH_SVAPIPE] = { | |
992b133a | 2913 | /* dependency to u8500-vape is handled outside regulator framework */ |
1032fbfd BJ |
2914 | .constraints = { |
2915 | .name = "db8500-sva-pipe", | |
2916 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2917 | }, | |
624e87c2 BJ |
2918 | .consumer_supplies = db8500_svapipe_consumers, |
2919 | .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers), | |
1032fbfd BJ |
2920 | }, |
2921 | [DB8500_REGULATOR_SWITCH_SIAMMDSP] = { | |
992b133a | 2922 | /* dependency to u8500-vape is handled outside regulator framework */ |
1032fbfd BJ |
2923 | .constraints = { |
2924 | .name = "db8500-sia-mmdsp", | |
2925 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2926 | }, | |
624e87c2 BJ |
2927 | .consumer_supplies = db8500_siammdsp_consumers, |
2928 | .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers), | |
1032fbfd BJ |
2929 | }, |
2930 | [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = { | |
2931 | .constraints = { | |
2932 | .name = "db8500-sia-mmdsp-ret", | |
2933 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2934 | }, | |
2935 | }, | |
2936 | [DB8500_REGULATOR_SWITCH_SIAPIPE] = { | |
992b133a | 2937 | /* dependency to u8500-vape is handled outside regulator framework */ |
1032fbfd BJ |
2938 | .constraints = { |
2939 | .name = "db8500-sia-pipe", | |
2940 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2941 | }, | |
624e87c2 BJ |
2942 | .consumer_supplies = db8500_siapipe_consumers, |
2943 | .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers), | |
1032fbfd BJ |
2944 | }, |
2945 | [DB8500_REGULATOR_SWITCH_SGA] = { | |
2946 | .supply_regulator = "db8500-vape", | |
2947 | .constraints = { | |
2948 | .name = "db8500-sga", | |
2949 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2950 | }, | |
624e87c2 BJ |
2951 | .consumer_supplies = db8500_sga_consumers, |
2952 | .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers), | |
2953 | ||
1032fbfd BJ |
2954 | }, |
2955 | [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = { | |
2956 | .supply_regulator = "db8500-vape", | |
2957 | .constraints = { | |
2958 | .name = "db8500-b2r2-mcde", | |
2959 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2960 | }, | |
2961 | .consumer_supplies = db8500_b2r2_mcde_consumers, | |
2962 | .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers), | |
2963 | }, | |
2964 | [DB8500_REGULATOR_SWITCH_ESRAM12] = { | |
992b133a BJ |
2965 | /* |
2966 | * esram12 is set in retention and supplied by Vsafe when Vape is off, | |
2967 | * no need to hold Vape | |
2968 | */ | |
1032fbfd BJ |
2969 | .constraints = { |
2970 | .name = "db8500-esram12", | |
2971 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2972 | }, | |
624e87c2 BJ |
2973 | .consumer_supplies = db8500_esram12_consumers, |
2974 | .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers), | |
1032fbfd BJ |
2975 | }, |
2976 | [DB8500_REGULATOR_SWITCH_ESRAM12RET] = { | |
2977 | .constraints = { | |
2978 | .name = "db8500-esram12-ret", | |
2979 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2980 | }, | |
2981 | }, | |
2982 | [DB8500_REGULATOR_SWITCH_ESRAM34] = { | |
992b133a BJ |
2983 | /* |
2984 | * esram34 is set in retention and supplied by Vsafe when Vape is off, | |
2985 | * no need to hold Vape | |
2986 | */ | |
1032fbfd BJ |
2987 | .constraints = { |
2988 | .name = "db8500-esram34", | |
2989 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2990 | }, | |
624e87c2 BJ |
2991 | .consumer_supplies = db8500_esram34_consumers, |
2992 | .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers), | |
1032fbfd BJ |
2993 | }, |
2994 | [DB8500_REGULATOR_SWITCH_ESRAM34RET] = { | |
2995 | .constraints = { | |
2996 | .name = "db8500-esram34-ret", | |
2997 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2998 | }, | |
2999 | }, | |
3000 | }; | |
3001 | ||
b3aac62b FB |
3002 | static struct ux500_wdt_data db8500_wdt_pdata = { |
3003 | .timeout = 600, /* 10 minutes */ | |
3004 | .has_28_bits_resolution = true, | |
3005 | }; | |
55b175d7 AB |
3006 | /* |
3007 | * Thermal Sensor | |
3008 | */ | |
3009 | ||
3010 | static struct resource db8500_thsens_resources[] = { | |
3011 | { | |
3012 | .name = "IRQ_HOTMON_LOW", | |
3013 | .start = IRQ_PRCMU_HOTMON_LOW, | |
3014 | .end = IRQ_PRCMU_HOTMON_LOW, | |
3015 | .flags = IORESOURCE_IRQ, | |
3016 | }, | |
3017 | { | |
3018 | .name = "IRQ_HOTMON_HIGH", | |
3019 | .start = IRQ_PRCMU_HOTMON_HIGH, | |
3020 | .end = IRQ_PRCMU_HOTMON_HIGH, | |
3021 | .flags = IORESOURCE_IRQ, | |
3022 | }, | |
3023 | }; | |
3024 | ||
3025 | static struct db8500_thsens_platform_data db8500_thsens_data = { | |
3026 | .trip_points[0] = { | |
3027 | .temp = 70000, | |
3028 | .type = THERMAL_TRIP_ACTIVE, | |
3029 | .cdev_name = { | |
3030 | [0] = "thermal-cpufreq-0", | |
3031 | }, | |
3032 | }, | |
3033 | .trip_points[1] = { | |
3034 | .temp = 75000, | |
3035 | .type = THERMAL_TRIP_ACTIVE, | |
3036 | .cdev_name = { | |
3037 | [0] = "thermal-cpufreq-0", | |
3038 | }, | |
3039 | }, | |
3040 | .trip_points[2] = { | |
3041 | .temp = 80000, | |
3042 | .type = THERMAL_TRIP_ACTIVE, | |
3043 | .cdev_name = { | |
3044 | [0] = "thermal-cpufreq-0", | |
3045 | }, | |
3046 | }, | |
3047 | .trip_points[3] = { | |
3048 | .temp = 85000, | |
3049 | .type = THERMAL_TRIP_CRITICAL, | |
3050 | }, | |
3051 | .num_trips = 4, | |
3052 | }; | |
b3aac62b | 3053 | |
5ac98553 | 3054 | static const struct mfd_cell common_prcmu_devs[] = { |
d98a5384 LJ |
3055 | { |
3056 | .name = "ux500_wdt", | |
3057 | .platform_data = &db8500_wdt_pdata, | |
3058 | .pdata_size = sizeof(db8500_wdt_pdata), | |
3059 | .id = -1, | |
3060 | }, | |
3061 | }; | |
3062 | ||
5ac98553 | 3063 | static const struct mfd_cell db8500_prcmu_devs[] = { |
3df57bcf MN |
3064 | { |
3065 | .name = "db8500-prcmu-regulators", | |
5d90322b | 3066 | .of_compatible = "stericsson,db8500-prcmu-regulator", |
1ed7891f MW |
3067 | .platform_data = &db8500_regulators, |
3068 | .pdata_size = sizeof(db8500_regulators), | |
3df57bcf MN |
3069 | }, |
3070 | { | |
84c7c20f LJ |
3071 | .name = "cpufreq-ux500", |
3072 | .of_compatible = "stericsson,cpufreq-ux500", | |
c280f45f UH |
3073 | .platform_data = &db8500_cpufreq_table, |
3074 | .pdata_size = sizeof(db8500_cpufreq_table), | |
3df57bcf | 3075 | }, |
8025395f LW |
3076 | { |
3077 | .name = "cpuidle-dbx500", | |
3078 | .of_compatible = "stericsson,cpuidle-dbx500", | |
3079 | }, | |
6d11d135 | 3080 | { |
55b175d7 AB |
3081 | .name = "db8500-thermal", |
3082 | .num_resources = ARRAY_SIZE(db8500_thsens_resources), | |
3083 | .resources = db8500_thsens_resources, | |
3084 | .platform_data = &db8500_thsens_data, | |
a3ef0deb | 3085 | .pdata_size = sizeof(db8500_thsens_data), |
6d11d135 | 3086 | }, |
3df57bcf MN |
3087 | }; |
3088 | ||
c280f45f UH |
3089 | static void db8500_prcmu_update_cpufreq(void) |
3090 | { | |
3091 | if (prcmu_has_arm_maxopp()) { | |
3092 | db8500_cpufreq_table[3].frequency = 1000000; | |
50701588 | 3093 | db8500_cpufreq_table[3].driver_data = ARM_MAX_OPP; |
c280f45f UH |
3094 | } |
3095 | } | |
3096 | ||
55b175d7 | 3097 | static int db8500_prcmu_register_ab8500(struct device *parent, |
f864c46a | 3098 | struct ab8500_platform_data *pdata) |
55b175d7 | 3099 | { |
f864c46a LW |
3100 | struct device_node *np; |
3101 | struct resource ab8500_resource; | |
5785a97e | 3102 | const struct mfd_cell ab8500_cell = { |
55b175d7 AB |
3103 | .name = "ab8500-core", |
3104 | .of_compatible = "stericsson,ab8500", | |
3105 | .id = AB8500_VERSION_AB8500, | |
3106 | .platform_data = pdata, | |
3107 | .pdata_size = sizeof(struct ab8500_platform_data), | |
3108 | .resources = &ab8500_resource, | |
3109 | .num_resources = 1, | |
3110 | }; | |
3111 | ||
f864c46a LW |
3112 | if (!parent->of_node) |
3113 | return -ENODEV; | |
3114 | ||
3115 | /* Look up the device node, sneak the IRQ out of it */ | |
3116 | for_each_child_of_node(parent->of_node, np) { | |
3117 | if (of_device_is_compatible(np, ab8500_cell.of_compatible)) | |
3118 | break; | |
3119 | } | |
3120 | if (!np) { | |
3121 | dev_info(parent, "could not find AB8500 node in the device tree\n"); | |
3122 | return -ENODEV; | |
3123 | } | |
3124 | of_irq_to_resource_table(np, &ab8500_resource, 1); | |
3125 | ||
55b175d7 AB |
3126 | return mfd_add_devices(parent, 0, &ab8500_cell, 1, NULL, 0, NULL); |
3127 | } | |
3128 | ||
3df57bcf MN |
3129 | /** |
3130 | * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic | |
3131 | * | |
3132 | */ | |
f791be49 | 3133 | static int db8500_prcmu_probe(struct platform_device *pdev) |
3df57bcf | 3134 | { |
ca7edd16 | 3135 | struct device_node *np = pdev->dev.of_node; |
05ec260e | 3136 | struct prcmu_pdata *pdata = dev_get_platdata(&pdev->dev); |
55b175d7 | 3137 | int irq = 0, err = 0; |
05ec260e | 3138 | struct resource *res; |
3df57bcf | 3139 | |
b047d981 LW |
3140 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu"); |
3141 | if (!res) { | |
3142 | dev_err(&pdev->dev, "no prcmu memory region provided\n"); | |
6bdf891a | 3143 | return -EINVAL; |
b047d981 LW |
3144 | } |
3145 | prcmu_base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); | |
3146 | if (!prcmu_base) { | |
3147 | dev_err(&pdev->dev, | |
3148 | "failed to ioremap prcmu register memory\n"); | |
6bdf891a | 3149 | return -ENOMEM; |
b047d981 | 3150 | } |
0508901c | 3151 | init_prcm_registers(); |
05ec260e LW |
3152 | dbx500_fw_version_init(pdev, pdata->version_offset); |
3153 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu-tcdm"); | |
3154 | if (!res) { | |
3155 | dev_err(&pdev->dev, "no prcmu tcdm region provided\n"); | |
6bdf891a | 3156 | return -EINVAL; |
05ec260e LW |
3157 | } |
3158 | tcdm_base = devm_ioremap(&pdev->dev, res->start, | |
3159 | resource_size(res)); | |
51a7e02b PG |
3160 | if (!tcdm_base) { |
3161 | dev_err(&pdev->dev, | |
3162 | "failed to ioremap prcmu-tcdm register memory\n"); | |
6bdf891a | 3163 | return -ENOMEM; |
51a7e02b | 3164 | } |
05ec260e | 3165 | |
e3726fcf | 3166 | /* Clean up the mailbox interrupts after pre-kernel code. */ |
c553b3ca | 3167 | writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR); |
3df57bcf | 3168 | |
05ec260e LW |
3169 | irq = platform_get_irq(pdev, 0); |
3170 | if (irq <= 0) { | |
3171 | dev_err(&pdev->dev, "no prcmu irq provided\n"); | |
6bdf891a | 3172 | return irq; |
05ec260e | 3173 | } |
ca7edd16 LJ |
3174 | |
3175 | err = request_threaded_irq(irq, prcmu_irq_handler, | |
3176 | prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL); | |
3df57bcf MN |
3177 | if (err < 0) { |
3178 | pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n"); | |
6bdf891a | 3179 | return err; |
3df57bcf MN |
3180 | } |
3181 | ||
f864c46a | 3182 | db8500_irq_init(np); |
3a8e39c9 | 3183 | |
7a4f2609 | 3184 | prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET); |
3df57bcf | 3185 | |
c280f45f UH |
3186 | db8500_prcmu_update_cpufreq(); |
3187 | ||
d98a5384 LJ |
3188 | err = mfd_add_devices(&pdev->dev, 0, common_prcmu_devs, |
3189 | ARRAY_SIZE(common_prcmu_devs), NULL, 0, db8500_irq_domain); | |
5d90322b LJ |
3190 | if (err) { |
3191 | pr_err("prcmu: Failed to add subdevices\n"); | |
3192 | return err; | |
ca7edd16 | 3193 | } |
e3726fcf | 3194 | |
d98a5384 LJ |
3195 | /* TODO: Remove restriction when clk definitions are available. */ |
3196 | if (!of_machine_is_compatible("st-ericsson,u8540")) { | |
3197 | err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs, | |
3198 | ARRAY_SIZE(db8500_prcmu_devs), NULL, 0, | |
3199 | db8500_irq_domain); | |
3200 | if (err) { | |
3201 | mfd_remove_devices(&pdev->dev); | |
3202 | pr_err("prcmu: Failed to add subdevices\n"); | |
6bdf891a | 3203 | return err; |
d98a5384 LJ |
3204 | } |
3205 | } | |
3206 | ||
f864c46a | 3207 | err = db8500_prcmu_register_ab8500(&pdev->dev, pdata->ab_platdata); |
55b175d7 AB |
3208 | if (err) { |
3209 | mfd_remove_devices(&pdev->dev); | |
3210 | pr_err("prcmu: Failed to add ab8500 subdevice\n"); | |
6bdf891a | 3211 | return err; |
55b175d7 AB |
3212 | } |
3213 | ||
ca7edd16 | 3214 | pr_info("DB8500 PRCMU initialized\n"); |
3df57bcf MN |
3215 | return err; |
3216 | } | |
3c144762 LJ |
3217 | static const struct of_device_id db8500_prcmu_match[] = { |
3218 | { .compatible = "stericsson,db8500-prcmu"}, | |
3219 | { }, | |
3220 | }; | |
3df57bcf MN |
3221 | |
3222 | static struct platform_driver db8500_prcmu_driver = { | |
3223 | .driver = { | |
3224 | .name = "db8500-prcmu", | |
3c144762 | 3225 | .of_match_table = db8500_prcmu_match, |
3df57bcf | 3226 | }, |
9fc63f67 | 3227 | .probe = db8500_prcmu_probe, |
3df57bcf MN |
3228 | }; |
3229 | ||
3230 | static int __init db8500_prcmu_init(void) | |
3231 | { | |
9fc63f67 | 3232 | return platform_driver_register(&db8500_prcmu_driver); |
e3726fcf LW |
3233 | } |
3234 | ||
a661aca4 | 3235 | core_initcall(db8500_prcmu_init); |
3df57bcf MN |
3236 | |
3237 | MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>"); | |
3238 | MODULE_DESCRIPTION("DB8500 PRCM Unit driver"); | |
3239 | MODULE_LICENSE("GPL v2"); |