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4630b130 AS |
1 | /* |
2 | * lpc_ich.c - LPC interface for Intel ICH | |
3 | * | |
4 | * LPC bridge function of the Intel ICH contains many other | |
5 | * functional units, such as Interrupt controllers, Timers, | |
6 | * Power Management, System Management, GPIO, RTC, and LPC | |
7 | * Configuration Registers. | |
8 | * | |
9 | * This driver is derived from lpc_sch. | |
10 | ||
11 | * Copyright (c) 2011 Extreme Engineering Solution, Inc. | |
12 | * Author: Aaron Sierra <asierra@xes-inc.com> | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License 2 as published | |
16 | * by the Free Software Foundation. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; see the file COPYING. If not, write to | |
25 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
26 | * | |
27 | * This driver supports the following I/O Controller hubs: | |
28 | * (See the intel documentation on http://developer.intel.com.) | |
29 | * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO) | |
30 | * document number 290687-002, 298242-027: 82801BA (ICH2) | |
31 | * document number 290733-003, 290739-013: 82801CA (ICH3-S) | |
32 | * document number 290716-001, 290718-007: 82801CAM (ICH3-M) | |
33 | * document number 290744-001, 290745-025: 82801DB (ICH4) | |
34 | * document number 252337-001, 252663-008: 82801DBM (ICH4-M) | |
35 | * document number 273599-001, 273645-002: 82801E (C-ICH) | |
36 | * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R) | |
37 | * document number 300641-004, 300884-013: 6300ESB | |
38 | * document number 301473-002, 301474-026: 82801F (ICH6) | |
39 | * document number 313082-001, 313075-006: 631xESB, 632xESB | |
40 | * document number 307013-003, 307014-024: 82801G (ICH7) | |
41 | * document number 322896-001, 322897-001: NM10 | |
42 | * document number 313056-003, 313057-017: 82801H (ICH8) | |
43 | * document number 316972-004, 316973-012: 82801I (ICH9) | |
44 | * document number 319973-002, 319974-002: 82801J (ICH10) | |
45 | * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH) | |
46 | * document number 320066-003, 320257-008: EP80597 (IICH) | |
47 | * document number 324645-001, 324646-001: Cougar Point (CPT) | |
48 | * document number TBD : Patsburg (PBG) | |
49 | * document number TBD : DH89xxCC | |
50 | * document number TBD : Panther Point | |
51 | * document number TBD : Lynx Point | |
7fb9c1a4 | 52 | * document number TBD : Lynx Point-LP |
6e6680e3 | 53 | * document number TBD : Wellsburg |
8477128f | 54 | * document number TBD : Avoton SoC |
283aae8a | 55 | * document number TBD : Coleto Creek |
5e90169c | 56 | * document number TBD : Wildcat Point-LP |
4630b130 AS |
57 | */ |
58 | ||
59 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
60 | ||
61 | #include <linux/init.h> | |
62 | #include <linux/kernel.h> | |
63 | #include <linux/module.h> | |
64 | #include <linux/errno.h> | |
65 | #include <linux/acpi.h> | |
66 | #include <linux/pci.h> | |
67 | #include <linux/mfd/core.h> | |
68 | #include <linux/mfd/lpc_ich.h> | |
69 | ||
70 | #define ACPIBASE 0x40 | |
71 | #define ACPIBASE_GPE_OFF 0x28 | |
72 | #define ACPIBASE_GPE_END 0x2f | |
887c8ec7 AS |
73 | #define ACPIBASE_SMI_OFF 0x30 |
74 | #define ACPIBASE_SMI_END 0x33 | |
75 | #define ACPIBASE_TCO_OFF 0x60 | |
76 | #define ACPIBASE_TCO_END 0x7f | |
4630b130 AS |
77 | #define ACPICTRL 0x44 |
78 | ||
887c8ec7 AS |
79 | #define ACPIBASE_GCS_OFF 0x3410 |
80 | #define ACPIBASE_GCS_END 0x3414 | |
81 | ||
01560f6b AS |
82 | #define GPIOBASE_ICH0 0x58 |
83 | #define GPIOCTRL_ICH0 0x5C | |
84 | #define GPIOBASE_ICH6 0x48 | |
85 | #define GPIOCTRL_ICH6 0x4C | |
4630b130 | 86 | |
887c8ec7 AS |
87 | #define RCBABASE 0xf0 |
88 | ||
89 | #define wdt_io_res(i) wdt_res(0, i) | |
90 | #define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i) | |
91 | #define wdt_res(b, i) (&wdt_ich_res[(b) + (i)]) | |
92 | ||
01560f6b AS |
93 | struct lpc_ich_cfg { |
94 | int base; | |
95 | int ctrl; | |
96 | int save; | |
97 | }; | |
98 | ||
99 | struct lpc_ich_priv { | |
100 | int chipset; | |
101 | struct lpc_ich_cfg acpi; | |
102 | struct lpc_ich_cfg gpio; | |
103 | }; | |
4630b130 | 104 | |
887c8ec7 AS |
105 | static struct resource wdt_ich_res[] = { |
106 | /* ACPI - TCO */ | |
107 | { | |
108 | .flags = IORESOURCE_IO, | |
109 | }, | |
110 | /* ACPI - SMI */ | |
111 | { | |
112 | .flags = IORESOURCE_IO, | |
113 | }, | |
114 | /* GCS */ | |
115 | { | |
116 | .flags = IORESOURCE_MEM, | |
117 | }, | |
118 | }; | |
119 | ||
4630b130 AS |
120 | static struct resource gpio_ich_res[] = { |
121 | /* GPIO */ | |
122 | { | |
123 | .flags = IORESOURCE_IO, | |
124 | }, | |
125 | /* ACPI - GPE0 */ | |
126 | { | |
127 | .flags = IORESOURCE_IO, | |
128 | }, | |
129 | }; | |
130 | ||
131 | enum lpc_cells { | |
887c8ec7 AS |
132 | LPC_WDT = 0, |
133 | LPC_GPIO, | |
4630b130 AS |
134 | }; |
135 | ||
136 | static struct mfd_cell lpc_ich_cells[] = { | |
887c8ec7 AS |
137 | [LPC_WDT] = { |
138 | .name = "iTCO_wdt", | |
139 | .num_resources = ARRAY_SIZE(wdt_ich_res), | |
140 | .resources = wdt_ich_res, | |
141 | .ignore_resource_conflicts = true, | |
142 | }, | |
4630b130 AS |
143 | [LPC_GPIO] = { |
144 | .name = "gpio_ich", | |
145 | .num_resources = ARRAY_SIZE(gpio_ich_res), | |
146 | .resources = gpio_ich_res, | |
147 | .ignore_resource_conflicts = true, | |
148 | }, | |
149 | }; | |
150 | ||
151 | /* chipset related info */ | |
152 | enum lpc_chipsets { | |
153 | LPC_ICH = 0, /* ICH */ | |
154 | LPC_ICH0, /* ICH0 */ | |
155 | LPC_ICH2, /* ICH2 */ | |
156 | LPC_ICH2M, /* ICH2-M */ | |
157 | LPC_ICH3, /* ICH3-S */ | |
158 | LPC_ICH3M, /* ICH3-M */ | |
159 | LPC_ICH4, /* ICH4 */ | |
160 | LPC_ICH4M, /* ICH4-M */ | |
161 | LPC_CICH, /* C-ICH */ | |
162 | LPC_ICH5, /* ICH5 & ICH5R */ | |
163 | LPC_6300ESB, /* 6300ESB */ | |
164 | LPC_ICH6, /* ICH6 & ICH6R */ | |
165 | LPC_ICH6M, /* ICH6-M */ | |
166 | LPC_ICH6W, /* ICH6W & ICH6RW */ | |
167 | LPC_631XESB, /* 631xESB/632xESB */ | |
168 | LPC_ICH7, /* ICH7 & ICH7R */ | |
169 | LPC_ICH7DH, /* ICH7DH */ | |
170 | LPC_ICH7M, /* ICH7-M & ICH7-U */ | |
171 | LPC_ICH7MDH, /* ICH7-M DH */ | |
172 | LPC_NM10, /* NM10 */ | |
173 | LPC_ICH8, /* ICH8 & ICH8R */ | |
174 | LPC_ICH8DH, /* ICH8DH */ | |
175 | LPC_ICH8DO, /* ICH8DO */ | |
176 | LPC_ICH8M, /* ICH8M */ | |
177 | LPC_ICH8ME, /* ICH8M-E */ | |
178 | LPC_ICH9, /* ICH9 */ | |
179 | LPC_ICH9R, /* ICH9R */ | |
180 | LPC_ICH9DH, /* ICH9DH */ | |
181 | LPC_ICH9DO, /* ICH9DO */ | |
182 | LPC_ICH9M, /* ICH9M */ | |
183 | LPC_ICH9ME, /* ICH9M-E */ | |
184 | LPC_ICH10, /* ICH10 */ | |
185 | LPC_ICH10R, /* ICH10R */ | |
186 | LPC_ICH10D, /* ICH10D */ | |
187 | LPC_ICH10DO, /* ICH10DO */ | |
188 | LPC_PCH, /* PCH Desktop Full Featured */ | |
189 | LPC_PCHM, /* PCH Mobile Full Featured */ | |
190 | LPC_P55, /* P55 */ | |
191 | LPC_PM55, /* PM55 */ | |
192 | LPC_H55, /* H55 */ | |
193 | LPC_QM57, /* QM57 */ | |
194 | LPC_H57, /* H57 */ | |
195 | LPC_HM55, /* HM55 */ | |
196 | LPC_Q57, /* Q57 */ | |
197 | LPC_HM57, /* HM57 */ | |
198 | LPC_PCHMSFF, /* PCH Mobile SFF Full Featured */ | |
199 | LPC_QS57, /* QS57 */ | |
200 | LPC_3400, /* 3400 */ | |
201 | LPC_3420, /* 3420 */ | |
202 | LPC_3450, /* 3450 */ | |
203 | LPC_EP80579, /* EP80579 */ | |
204 | LPC_CPT, /* Cougar Point */ | |
205 | LPC_CPTD, /* Cougar Point Desktop */ | |
206 | LPC_CPTM, /* Cougar Point Mobile */ | |
207 | LPC_PBG, /* Patsburg */ | |
208 | LPC_DH89XXCC, /* DH89xxCC */ | |
209 | LPC_PPT, /* Panther Point */ | |
210 | LPC_LPT, /* Lynx Point */ | |
7fb9c1a4 | 211 | LPC_LPT_LP, /* Lynx Point-LP */ |
6e6680e3 | 212 | LPC_WBG, /* Wellsburg */ |
8477128f | 213 | LPC_AVN, /* Avoton SoC */ |
283aae8a | 214 | LPC_COLETO, /* Coleto Creek */ |
5e90169c | 215 | LPC_WPT_LP, /* Wildcat Point-LP */ |
4630b130 AS |
216 | }; |
217 | ||
a1ca138f | 218 | static struct lpc_ich_info lpc_chipset_info[] = { |
4630b130 AS |
219 | [LPC_ICH] = { |
220 | .name = "ICH", | |
887c8ec7 | 221 | .iTCO_version = 1, |
4630b130 AS |
222 | }, |
223 | [LPC_ICH0] = { | |
224 | .name = "ICH0", | |
887c8ec7 | 225 | .iTCO_version = 1, |
4630b130 AS |
226 | }, |
227 | [LPC_ICH2] = { | |
228 | .name = "ICH2", | |
887c8ec7 | 229 | .iTCO_version = 1, |
4630b130 AS |
230 | }, |
231 | [LPC_ICH2M] = { | |
232 | .name = "ICH2-M", | |
887c8ec7 | 233 | .iTCO_version = 1, |
4630b130 AS |
234 | }, |
235 | [LPC_ICH3] = { | |
236 | .name = "ICH3-S", | |
887c8ec7 | 237 | .iTCO_version = 1, |
4630b130 AS |
238 | }, |
239 | [LPC_ICH3M] = { | |
240 | .name = "ICH3-M", | |
887c8ec7 | 241 | .iTCO_version = 1, |
4630b130 AS |
242 | }, |
243 | [LPC_ICH4] = { | |
244 | .name = "ICH4", | |
887c8ec7 | 245 | .iTCO_version = 1, |
4630b130 AS |
246 | }, |
247 | [LPC_ICH4M] = { | |
248 | .name = "ICH4-M", | |
887c8ec7 | 249 | .iTCO_version = 1, |
4630b130 AS |
250 | }, |
251 | [LPC_CICH] = { | |
252 | .name = "C-ICH", | |
887c8ec7 | 253 | .iTCO_version = 1, |
4630b130 AS |
254 | }, |
255 | [LPC_ICH5] = { | |
256 | .name = "ICH5 or ICH5R", | |
887c8ec7 | 257 | .iTCO_version = 1, |
4630b130 AS |
258 | }, |
259 | [LPC_6300ESB] = { | |
260 | .name = "6300ESB", | |
887c8ec7 | 261 | .iTCO_version = 1, |
4630b130 AS |
262 | }, |
263 | [LPC_ICH6] = { | |
264 | .name = "ICH6 or ICH6R", | |
887c8ec7 | 265 | .iTCO_version = 2, |
4630b130 AS |
266 | .gpio_version = ICH_V6_GPIO, |
267 | }, | |
268 | [LPC_ICH6M] = { | |
269 | .name = "ICH6-M", | |
887c8ec7 | 270 | .iTCO_version = 2, |
4630b130 AS |
271 | .gpio_version = ICH_V6_GPIO, |
272 | }, | |
273 | [LPC_ICH6W] = { | |
274 | .name = "ICH6W or ICH6RW", | |
887c8ec7 | 275 | .iTCO_version = 2, |
4630b130 AS |
276 | .gpio_version = ICH_V6_GPIO, |
277 | }, | |
278 | [LPC_631XESB] = { | |
279 | .name = "631xESB/632xESB", | |
887c8ec7 | 280 | .iTCO_version = 2, |
4630b130 AS |
281 | .gpio_version = ICH_V6_GPIO, |
282 | }, | |
283 | [LPC_ICH7] = { | |
284 | .name = "ICH7 or ICH7R", | |
887c8ec7 | 285 | .iTCO_version = 2, |
4630b130 AS |
286 | .gpio_version = ICH_V7_GPIO, |
287 | }, | |
288 | [LPC_ICH7DH] = { | |
289 | .name = "ICH7DH", | |
887c8ec7 | 290 | .iTCO_version = 2, |
4630b130 AS |
291 | .gpio_version = ICH_V7_GPIO, |
292 | }, | |
293 | [LPC_ICH7M] = { | |
294 | .name = "ICH7-M or ICH7-U", | |
887c8ec7 | 295 | .iTCO_version = 2, |
4630b130 AS |
296 | .gpio_version = ICH_V7_GPIO, |
297 | }, | |
298 | [LPC_ICH7MDH] = { | |
299 | .name = "ICH7-M DH", | |
887c8ec7 | 300 | .iTCO_version = 2, |
4630b130 AS |
301 | .gpio_version = ICH_V7_GPIO, |
302 | }, | |
303 | [LPC_NM10] = { | |
304 | .name = "NM10", | |
887c8ec7 | 305 | .iTCO_version = 2, |
4630b130 AS |
306 | }, |
307 | [LPC_ICH8] = { | |
308 | .name = "ICH8 or ICH8R", | |
887c8ec7 | 309 | .iTCO_version = 2, |
4630b130 AS |
310 | .gpio_version = ICH_V7_GPIO, |
311 | }, | |
312 | [LPC_ICH8DH] = { | |
313 | .name = "ICH8DH", | |
887c8ec7 | 314 | .iTCO_version = 2, |
4630b130 AS |
315 | .gpio_version = ICH_V7_GPIO, |
316 | }, | |
317 | [LPC_ICH8DO] = { | |
318 | .name = "ICH8DO", | |
887c8ec7 | 319 | .iTCO_version = 2, |
4630b130 AS |
320 | .gpio_version = ICH_V7_GPIO, |
321 | }, | |
322 | [LPC_ICH8M] = { | |
323 | .name = "ICH8M", | |
887c8ec7 | 324 | .iTCO_version = 2, |
4630b130 AS |
325 | .gpio_version = ICH_V7_GPIO, |
326 | }, | |
327 | [LPC_ICH8ME] = { | |
328 | .name = "ICH8M-E", | |
887c8ec7 | 329 | .iTCO_version = 2, |
4630b130 AS |
330 | .gpio_version = ICH_V7_GPIO, |
331 | }, | |
332 | [LPC_ICH9] = { | |
333 | .name = "ICH9", | |
887c8ec7 | 334 | .iTCO_version = 2, |
4630b130 AS |
335 | .gpio_version = ICH_V9_GPIO, |
336 | }, | |
337 | [LPC_ICH9R] = { | |
338 | .name = "ICH9R", | |
887c8ec7 | 339 | .iTCO_version = 2, |
4630b130 AS |
340 | .gpio_version = ICH_V9_GPIO, |
341 | }, | |
342 | [LPC_ICH9DH] = { | |
343 | .name = "ICH9DH", | |
887c8ec7 | 344 | .iTCO_version = 2, |
4630b130 AS |
345 | .gpio_version = ICH_V9_GPIO, |
346 | }, | |
347 | [LPC_ICH9DO] = { | |
348 | .name = "ICH9DO", | |
887c8ec7 | 349 | .iTCO_version = 2, |
4630b130 AS |
350 | .gpio_version = ICH_V9_GPIO, |
351 | }, | |
352 | [LPC_ICH9M] = { | |
353 | .name = "ICH9M", | |
887c8ec7 | 354 | .iTCO_version = 2, |
4630b130 AS |
355 | .gpio_version = ICH_V9_GPIO, |
356 | }, | |
357 | [LPC_ICH9ME] = { | |
358 | .name = "ICH9M-E", | |
887c8ec7 | 359 | .iTCO_version = 2, |
4630b130 AS |
360 | .gpio_version = ICH_V9_GPIO, |
361 | }, | |
362 | [LPC_ICH10] = { | |
363 | .name = "ICH10", | |
887c8ec7 | 364 | .iTCO_version = 2, |
4630b130 AS |
365 | .gpio_version = ICH_V10CONS_GPIO, |
366 | }, | |
367 | [LPC_ICH10R] = { | |
368 | .name = "ICH10R", | |
887c8ec7 | 369 | .iTCO_version = 2, |
4630b130 AS |
370 | .gpio_version = ICH_V10CONS_GPIO, |
371 | }, | |
372 | [LPC_ICH10D] = { | |
373 | .name = "ICH10D", | |
887c8ec7 | 374 | .iTCO_version = 2, |
4630b130 AS |
375 | .gpio_version = ICH_V10CORP_GPIO, |
376 | }, | |
377 | [LPC_ICH10DO] = { | |
378 | .name = "ICH10DO", | |
887c8ec7 | 379 | .iTCO_version = 2, |
4630b130 AS |
380 | .gpio_version = ICH_V10CORP_GPIO, |
381 | }, | |
382 | [LPC_PCH] = { | |
383 | .name = "PCH Desktop Full Featured", | |
887c8ec7 | 384 | .iTCO_version = 2, |
4630b130 AS |
385 | .gpio_version = ICH_V5_GPIO, |
386 | }, | |
387 | [LPC_PCHM] = { | |
388 | .name = "PCH Mobile Full Featured", | |
887c8ec7 | 389 | .iTCO_version = 2, |
4630b130 AS |
390 | .gpio_version = ICH_V5_GPIO, |
391 | }, | |
392 | [LPC_P55] = { | |
393 | .name = "P55", | |
887c8ec7 | 394 | .iTCO_version = 2, |
4630b130 AS |
395 | .gpio_version = ICH_V5_GPIO, |
396 | }, | |
397 | [LPC_PM55] = { | |
398 | .name = "PM55", | |
887c8ec7 | 399 | .iTCO_version = 2, |
4630b130 AS |
400 | .gpio_version = ICH_V5_GPIO, |
401 | }, | |
402 | [LPC_H55] = { | |
403 | .name = "H55", | |
887c8ec7 | 404 | .iTCO_version = 2, |
4630b130 AS |
405 | .gpio_version = ICH_V5_GPIO, |
406 | }, | |
407 | [LPC_QM57] = { | |
408 | .name = "QM57", | |
887c8ec7 | 409 | .iTCO_version = 2, |
4630b130 AS |
410 | .gpio_version = ICH_V5_GPIO, |
411 | }, | |
412 | [LPC_H57] = { | |
413 | .name = "H57", | |
887c8ec7 | 414 | .iTCO_version = 2, |
4630b130 AS |
415 | .gpio_version = ICH_V5_GPIO, |
416 | }, | |
417 | [LPC_HM55] = { | |
418 | .name = "HM55", | |
887c8ec7 | 419 | .iTCO_version = 2, |
4630b130 AS |
420 | .gpio_version = ICH_V5_GPIO, |
421 | }, | |
422 | [LPC_Q57] = { | |
423 | .name = "Q57", | |
887c8ec7 | 424 | .iTCO_version = 2, |
4630b130 AS |
425 | .gpio_version = ICH_V5_GPIO, |
426 | }, | |
427 | [LPC_HM57] = { | |
428 | .name = "HM57", | |
887c8ec7 | 429 | .iTCO_version = 2, |
4630b130 AS |
430 | .gpio_version = ICH_V5_GPIO, |
431 | }, | |
432 | [LPC_PCHMSFF] = { | |
433 | .name = "PCH Mobile SFF Full Featured", | |
887c8ec7 | 434 | .iTCO_version = 2, |
4630b130 AS |
435 | .gpio_version = ICH_V5_GPIO, |
436 | }, | |
437 | [LPC_QS57] = { | |
438 | .name = "QS57", | |
887c8ec7 | 439 | .iTCO_version = 2, |
4630b130 AS |
440 | .gpio_version = ICH_V5_GPIO, |
441 | }, | |
442 | [LPC_3400] = { | |
443 | .name = "3400", | |
887c8ec7 | 444 | .iTCO_version = 2, |
4630b130 AS |
445 | .gpio_version = ICH_V5_GPIO, |
446 | }, | |
447 | [LPC_3420] = { | |
448 | .name = "3420", | |
887c8ec7 | 449 | .iTCO_version = 2, |
4630b130 AS |
450 | .gpio_version = ICH_V5_GPIO, |
451 | }, | |
452 | [LPC_3450] = { | |
453 | .name = "3450", | |
887c8ec7 | 454 | .iTCO_version = 2, |
4630b130 AS |
455 | .gpio_version = ICH_V5_GPIO, |
456 | }, | |
457 | [LPC_EP80579] = { | |
458 | .name = "EP80579", | |
887c8ec7 | 459 | .iTCO_version = 2, |
4630b130 AS |
460 | }, |
461 | [LPC_CPT] = { | |
462 | .name = "Cougar Point", | |
887c8ec7 | 463 | .iTCO_version = 2, |
4630b130 AS |
464 | .gpio_version = ICH_V5_GPIO, |
465 | }, | |
466 | [LPC_CPTD] = { | |
467 | .name = "Cougar Point Desktop", | |
887c8ec7 | 468 | .iTCO_version = 2, |
4630b130 AS |
469 | .gpio_version = ICH_V5_GPIO, |
470 | }, | |
471 | [LPC_CPTM] = { | |
472 | .name = "Cougar Point Mobile", | |
887c8ec7 | 473 | .iTCO_version = 2, |
4630b130 AS |
474 | .gpio_version = ICH_V5_GPIO, |
475 | }, | |
476 | [LPC_PBG] = { | |
477 | .name = "Patsburg", | |
887c8ec7 | 478 | .iTCO_version = 2, |
4630b130 AS |
479 | }, |
480 | [LPC_DH89XXCC] = { | |
481 | .name = "DH89xxCC", | |
887c8ec7 | 482 | .iTCO_version = 2, |
4630b130 AS |
483 | }, |
484 | [LPC_PPT] = { | |
485 | .name = "Panther Point", | |
887c8ec7 | 486 | .iTCO_version = 2, |
4630b130 AS |
487 | }, |
488 | [LPC_LPT] = { | |
489 | .name = "Lynx Point", | |
887c8ec7 | 490 | .iTCO_version = 2, |
4630b130 | 491 | }, |
7fb9c1a4 JR |
492 | [LPC_LPT_LP] = { |
493 | .name = "Lynx Point_LP", | |
494 | .iTCO_version = 2, | |
495 | }, | |
6e6680e3 JR |
496 | [LPC_WBG] = { |
497 | .name = "Wellsburg", | |
498 | .iTCO_version = 2, | |
499 | }, | |
8477128f JR |
500 | [LPC_AVN] = { |
501 | .name = "Avoton SoC", | |
502 | .iTCO_version = 1, | |
503 | }, | |
283aae8a SH |
504 | [LPC_COLETO] = { |
505 | .name = "Coleto Creek", | |
506 | .iTCO_version = 2, | |
507 | }, | |
5e90169c | 508 | [LPC_WPT_LP] = { |
a8822df9 | 509 | .name = "Wildcat Point_LP", |
5e90169c JR |
510 | .iTCO_version = 2, |
511 | }, | |
4630b130 AS |
512 | }; |
513 | ||
514 | /* | |
515 | * This data only exists for exporting the supported PCI ids | |
516 | * via MODULE_DEVICE_TABLE. We do not actually register a | |
517 | * pci_driver, because the I/O Controller Hub has also other | |
518 | * functions that probably will be registered by other drivers. | |
519 | */ | |
520 | static DEFINE_PCI_DEVICE_TABLE(lpc_ich_ids) = { | |
521 | { PCI_VDEVICE(INTEL, 0x2410), LPC_ICH}, | |
522 | { PCI_VDEVICE(INTEL, 0x2420), LPC_ICH0}, | |
523 | { PCI_VDEVICE(INTEL, 0x2440), LPC_ICH2}, | |
524 | { PCI_VDEVICE(INTEL, 0x244c), LPC_ICH2M}, | |
525 | { PCI_VDEVICE(INTEL, 0x2480), LPC_ICH3}, | |
526 | { PCI_VDEVICE(INTEL, 0x248c), LPC_ICH3M}, | |
527 | { PCI_VDEVICE(INTEL, 0x24c0), LPC_ICH4}, | |
528 | { PCI_VDEVICE(INTEL, 0x24cc), LPC_ICH4M}, | |
529 | { PCI_VDEVICE(INTEL, 0x2450), LPC_CICH}, | |
530 | { PCI_VDEVICE(INTEL, 0x24d0), LPC_ICH5}, | |
531 | { PCI_VDEVICE(INTEL, 0x25a1), LPC_6300ESB}, | |
532 | { PCI_VDEVICE(INTEL, 0x2640), LPC_ICH6}, | |
533 | { PCI_VDEVICE(INTEL, 0x2641), LPC_ICH6M}, | |
534 | { PCI_VDEVICE(INTEL, 0x2642), LPC_ICH6W}, | |
535 | { PCI_VDEVICE(INTEL, 0x2670), LPC_631XESB}, | |
536 | { PCI_VDEVICE(INTEL, 0x2671), LPC_631XESB}, | |
537 | { PCI_VDEVICE(INTEL, 0x2672), LPC_631XESB}, | |
538 | { PCI_VDEVICE(INTEL, 0x2673), LPC_631XESB}, | |
539 | { PCI_VDEVICE(INTEL, 0x2674), LPC_631XESB}, | |
540 | { PCI_VDEVICE(INTEL, 0x2675), LPC_631XESB}, | |
541 | { PCI_VDEVICE(INTEL, 0x2676), LPC_631XESB}, | |
542 | { PCI_VDEVICE(INTEL, 0x2677), LPC_631XESB}, | |
543 | { PCI_VDEVICE(INTEL, 0x2678), LPC_631XESB}, | |
544 | { PCI_VDEVICE(INTEL, 0x2679), LPC_631XESB}, | |
545 | { PCI_VDEVICE(INTEL, 0x267a), LPC_631XESB}, | |
546 | { PCI_VDEVICE(INTEL, 0x267b), LPC_631XESB}, | |
547 | { PCI_VDEVICE(INTEL, 0x267c), LPC_631XESB}, | |
548 | { PCI_VDEVICE(INTEL, 0x267d), LPC_631XESB}, | |
549 | { PCI_VDEVICE(INTEL, 0x267e), LPC_631XESB}, | |
550 | { PCI_VDEVICE(INTEL, 0x267f), LPC_631XESB}, | |
551 | { PCI_VDEVICE(INTEL, 0x27b8), LPC_ICH7}, | |
552 | { PCI_VDEVICE(INTEL, 0x27b0), LPC_ICH7DH}, | |
553 | { PCI_VDEVICE(INTEL, 0x27b9), LPC_ICH7M}, | |
554 | { PCI_VDEVICE(INTEL, 0x27bd), LPC_ICH7MDH}, | |
555 | { PCI_VDEVICE(INTEL, 0x27bc), LPC_NM10}, | |
556 | { PCI_VDEVICE(INTEL, 0x2810), LPC_ICH8}, | |
557 | { PCI_VDEVICE(INTEL, 0x2812), LPC_ICH8DH}, | |
558 | { PCI_VDEVICE(INTEL, 0x2814), LPC_ICH8DO}, | |
559 | { PCI_VDEVICE(INTEL, 0x2815), LPC_ICH8M}, | |
560 | { PCI_VDEVICE(INTEL, 0x2811), LPC_ICH8ME}, | |
561 | { PCI_VDEVICE(INTEL, 0x2918), LPC_ICH9}, | |
562 | { PCI_VDEVICE(INTEL, 0x2916), LPC_ICH9R}, | |
563 | { PCI_VDEVICE(INTEL, 0x2912), LPC_ICH9DH}, | |
564 | { PCI_VDEVICE(INTEL, 0x2914), LPC_ICH9DO}, | |
565 | { PCI_VDEVICE(INTEL, 0x2919), LPC_ICH9M}, | |
566 | { PCI_VDEVICE(INTEL, 0x2917), LPC_ICH9ME}, | |
567 | { PCI_VDEVICE(INTEL, 0x3a18), LPC_ICH10}, | |
568 | { PCI_VDEVICE(INTEL, 0x3a16), LPC_ICH10R}, | |
569 | { PCI_VDEVICE(INTEL, 0x3a1a), LPC_ICH10D}, | |
570 | { PCI_VDEVICE(INTEL, 0x3a14), LPC_ICH10DO}, | |
571 | { PCI_VDEVICE(INTEL, 0x3b00), LPC_PCH}, | |
572 | { PCI_VDEVICE(INTEL, 0x3b01), LPC_PCHM}, | |
573 | { PCI_VDEVICE(INTEL, 0x3b02), LPC_P55}, | |
574 | { PCI_VDEVICE(INTEL, 0x3b03), LPC_PM55}, | |
575 | { PCI_VDEVICE(INTEL, 0x3b06), LPC_H55}, | |
576 | { PCI_VDEVICE(INTEL, 0x3b07), LPC_QM57}, | |
577 | { PCI_VDEVICE(INTEL, 0x3b08), LPC_H57}, | |
578 | { PCI_VDEVICE(INTEL, 0x3b09), LPC_HM55}, | |
579 | { PCI_VDEVICE(INTEL, 0x3b0a), LPC_Q57}, | |
580 | { PCI_VDEVICE(INTEL, 0x3b0b), LPC_HM57}, | |
581 | { PCI_VDEVICE(INTEL, 0x3b0d), LPC_PCHMSFF}, | |
582 | { PCI_VDEVICE(INTEL, 0x3b0f), LPC_QS57}, | |
583 | { PCI_VDEVICE(INTEL, 0x3b12), LPC_3400}, | |
584 | { PCI_VDEVICE(INTEL, 0x3b14), LPC_3420}, | |
585 | { PCI_VDEVICE(INTEL, 0x3b16), LPC_3450}, | |
586 | { PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579}, | |
587 | { PCI_VDEVICE(INTEL, 0x1c41), LPC_CPT}, | |
588 | { PCI_VDEVICE(INTEL, 0x1c42), LPC_CPTD}, | |
589 | { PCI_VDEVICE(INTEL, 0x1c43), LPC_CPTM}, | |
590 | { PCI_VDEVICE(INTEL, 0x1c44), LPC_CPT}, | |
591 | { PCI_VDEVICE(INTEL, 0x1c45), LPC_CPT}, | |
592 | { PCI_VDEVICE(INTEL, 0x1c46), LPC_CPT}, | |
593 | { PCI_VDEVICE(INTEL, 0x1c47), LPC_CPT}, | |
594 | { PCI_VDEVICE(INTEL, 0x1c48), LPC_CPT}, | |
595 | { PCI_VDEVICE(INTEL, 0x1c49), LPC_CPT}, | |
596 | { PCI_VDEVICE(INTEL, 0x1c4a), LPC_CPT}, | |
597 | { PCI_VDEVICE(INTEL, 0x1c4b), LPC_CPT}, | |
598 | { PCI_VDEVICE(INTEL, 0x1c4c), LPC_CPT}, | |
599 | { PCI_VDEVICE(INTEL, 0x1c4d), LPC_CPT}, | |
600 | { PCI_VDEVICE(INTEL, 0x1c4e), LPC_CPT}, | |
601 | { PCI_VDEVICE(INTEL, 0x1c4f), LPC_CPT}, | |
602 | { PCI_VDEVICE(INTEL, 0x1c50), LPC_CPT}, | |
603 | { PCI_VDEVICE(INTEL, 0x1c51), LPC_CPT}, | |
604 | { PCI_VDEVICE(INTEL, 0x1c52), LPC_CPT}, | |
605 | { PCI_VDEVICE(INTEL, 0x1c53), LPC_CPT}, | |
606 | { PCI_VDEVICE(INTEL, 0x1c54), LPC_CPT}, | |
607 | { PCI_VDEVICE(INTEL, 0x1c55), LPC_CPT}, | |
608 | { PCI_VDEVICE(INTEL, 0x1c56), LPC_CPT}, | |
609 | { PCI_VDEVICE(INTEL, 0x1c57), LPC_CPT}, | |
610 | { PCI_VDEVICE(INTEL, 0x1c58), LPC_CPT}, | |
611 | { PCI_VDEVICE(INTEL, 0x1c59), LPC_CPT}, | |
612 | { PCI_VDEVICE(INTEL, 0x1c5a), LPC_CPT}, | |
613 | { PCI_VDEVICE(INTEL, 0x1c5b), LPC_CPT}, | |
614 | { PCI_VDEVICE(INTEL, 0x1c5c), LPC_CPT}, | |
615 | { PCI_VDEVICE(INTEL, 0x1c5d), LPC_CPT}, | |
616 | { PCI_VDEVICE(INTEL, 0x1c5e), LPC_CPT}, | |
617 | { PCI_VDEVICE(INTEL, 0x1c5f), LPC_CPT}, | |
618 | { PCI_VDEVICE(INTEL, 0x1d40), LPC_PBG}, | |
619 | { PCI_VDEVICE(INTEL, 0x1d41), LPC_PBG}, | |
620 | { PCI_VDEVICE(INTEL, 0x2310), LPC_DH89XXCC}, | |
621 | { PCI_VDEVICE(INTEL, 0x1e40), LPC_PPT}, | |
622 | { PCI_VDEVICE(INTEL, 0x1e41), LPC_PPT}, | |
623 | { PCI_VDEVICE(INTEL, 0x1e42), LPC_PPT}, | |
624 | { PCI_VDEVICE(INTEL, 0x1e43), LPC_PPT}, | |
625 | { PCI_VDEVICE(INTEL, 0x1e44), LPC_PPT}, | |
626 | { PCI_VDEVICE(INTEL, 0x1e45), LPC_PPT}, | |
627 | { PCI_VDEVICE(INTEL, 0x1e46), LPC_PPT}, | |
628 | { PCI_VDEVICE(INTEL, 0x1e47), LPC_PPT}, | |
629 | { PCI_VDEVICE(INTEL, 0x1e48), LPC_PPT}, | |
630 | { PCI_VDEVICE(INTEL, 0x1e49), LPC_PPT}, | |
631 | { PCI_VDEVICE(INTEL, 0x1e4a), LPC_PPT}, | |
632 | { PCI_VDEVICE(INTEL, 0x1e4b), LPC_PPT}, | |
633 | { PCI_VDEVICE(INTEL, 0x1e4c), LPC_PPT}, | |
634 | { PCI_VDEVICE(INTEL, 0x1e4d), LPC_PPT}, | |
635 | { PCI_VDEVICE(INTEL, 0x1e4e), LPC_PPT}, | |
636 | { PCI_VDEVICE(INTEL, 0x1e4f), LPC_PPT}, | |
637 | { PCI_VDEVICE(INTEL, 0x1e50), LPC_PPT}, | |
638 | { PCI_VDEVICE(INTEL, 0x1e51), LPC_PPT}, | |
639 | { PCI_VDEVICE(INTEL, 0x1e52), LPC_PPT}, | |
640 | { PCI_VDEVICE(INTEL, 0x1e53), LPC_PPT}, | |
641 | { PCI_VDEVICE(INTEL, 0x1e54), LPC_PPT}, | |
642 | { PCI_VDEVICE(INTEL, 0x1e55), LPC_PPT}, | |
643 | { PCI_VDEVICE(INTEL, 0x1e56), LPC_PPT}, | |
644 | { PCI_VDEVICE(INTEL, 0x1e57), LPC_PPT}, | |
645 | { PCI_VDEVICE(INTEL, 0x1e58), LPC_PPT}, | |
646 | { PCI_VDEVICE(INTEL, 0x1e59), LPC_PPT}, | |
647 | { PCI_VDEVICE(INTEL, 0x1e5a), LPC_PPT}, | |
648 | { PCI_VDEVICE(INTEL, 0x1e5b), LPC_PPT}, | |
649 | { PCI_VDEVICE(INTEL, 0x1e5c), LPC_PPT}, | |
650 | { PCI_VDEVICE(INTEL, 0x1e5d), LPC_PPT}, | |
651 | { PCI_VDEVICE(INTEL, 0x1e5e), LPC_PPT}, | |
652 | { PCI_VDEVICE(INTEL, 0x1e5f), LPC_PPT}, | |
653 | { PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT}, | |
654 | { PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT}, | |
655 | { PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT}, | |
656 | { PCI_VDEVICE(INTEL, 0x8c43), LPC_LPT}, | |
657 | { PCI_VDEVICE(INTEL, 0x8c44), LPC_LPT}, | |
658 | { PCI_VDEVICE(INTEL, 0x8c45), LPC_LPT}, | |
659 | { PCI_VDEVICE(INTEL, 0x8c46), LPC_LPT}, | |
660 | { PCI_VDEVICE(INTEL, 0x8c47), LPC_LPT}, | |
661 | { PCI_VDEVICE(INTEL, 0x8c48), LPC_LPT}, | |
662 | { PCI_VDEVICE(INTEL, 0x8c49), LPC_LPT}, | |
663 | { PCI_VDEVICE(INTEL, 0x8c4a), LPC_LPT}, | |
664 | { PCI_VDEVICE(INTEL, 0x8c4b), LPC_LPT}, | |
665 | { PCI_VDEVICE(INTEL, 0x8c4c), LPC_LPT}, | |
666 | { PCI_VDEVICE(INTEL, 0x8c4d), LPC_LPT}, | |
667 | { PCI_VDEVICE(INTEL, 0x8c4e), LPC_LPT}, | |
668 | { PCI_VDEVICE(INTEL, 0x8c4f), LPC_LPT}, | |
669 | { PCI_VDEVICE(INTEL, 0x8c50), LPC_LPT}, | |
670 | { PCI_VDEVICE(INTEL, 0x8c51), LPC_LPT}, | |
671 | { PCI_VDEVICE(INTEL, 0x8c52), LPC_LPT}, | |
672 | { PCI_VDEVICE(INTEL, 0x8c53), LPC_LPT}, | |
673 | { PCI_VDEVICE(INTEL, 0x8c54), LPC_LPT}, | |
674 | { PCI_VDEVICE(INTEL, 0x8c55), LPC_LPT}, | |
675 | { PCI_VDEVICE(INTEL, 0x8c56), LPC_LPT}, | |
676 | { PCI_VDEVICE(INTEL, 0x8c57), LPC_LPT}, | |
677 | { PCI_VDEVICE(INTEL, 0x8c58), LPC_LPT}, | |
678 | { PCI_VDEVICE(INTEL, 0x8c59), LPC_LPT}, | |
679 | { PCI_VDEVICE(INTEL, 0x8c5a), LPC_LPT}, | |
680 | { PCI_VDEVICE(INTEL, 0x8c5b), LPC_LPT}, | |
681 | { PCI_VDEVICE(INTEL, 0x8c5c), LPC_LPT}, | |
682 | { PCI_VDEVICE(INTEL, 0x8c5d), LPC_LPT}, | |
683 | { PCI_VDEVICE(INTEL, 0x8c5e), LPC_LPT}, | |
684 | { PCI_VDEVICE(INTEL, 0x8c5f), LPC_LPT}, | |
7fb9c1a4 JR |
685 | { PCI_VDEVICE(INTEL, 0x9c40), LPC_LPT_LP}, |
686 | { PCI_VDEVICE(INTEL, 0x9c41), LPC_LPT_LP}, | |
687 | { PCI_VDEVICE(INTEL, 0x9c42), LPC_LPT_LP}, | |
688 | { PCI_VDEVICE(INTEL, 0x9c43), LPC_LPT_LP}, | |
689 | { PCI_VDEVICE(INTEL, 0x9c44), LPC_LPT_LP}, | |
690 | { PCI_VDEVICE(INTEL, 0x9c45), LPC_LPT_LP}, | |
691 | { PCI_VDEVICE(INTEL, 0x9c46), LPC_LPT_LP}, | |
692 | { PCI_VDEVICE(INTEL, 0x9c47), LPC_LPT_LP}, | |
6e6680e3 JR |
693 | { PCI_VDEVICE(INTEL, 0x8d40), LPC_WBG}, |
694 | { PCI_VDEVICE(INTEL, 0x8d41), LPC_WBG}, | |
695 | { PCI_VDEVICE(INTEL, 0x8d42), LPC_WBG}, | |
696 | { PCI_VDEVICE(INTEL, 0x8d43), LPC_WBG}, | |
697 | { PCI_VDEVICE(INTEL, 0x8d44), LPC_WBG}, | |
698 | { PCI_VDEVICE(INTEL, 0x8d45), LPC_WBG}, | |
699 | { PCI_VDEVICE(INTEL, 0x8d46), LPC_WBG}, | |
700 | { PCI_VDEVICE(INTEL, 0x8d47), LPC_WBG}, | |
701 | { PCI_VDEVICE(INTEL, 0x8d48), LPC_WBG}, | |
702 | { PCI_VDEVICE(INTEL, 0x8d49), LPC_WBG}, | |
703 | { PCI_VDEVICE(INTEL, 0x8d4a), LPC_WBG}, | |
704 | { PCI_VDEVICE(INTEL, 0x8d4b), LPC_WBG}, | |
705 | { PCI_VDEVICE(INTEL, 0x8d4c), LPC_WBG}, | |
706 | { PCI_VDEVICE(INTEL, 0x8d4d), LPC_WBG}, | |
707 | { PCI_VDEVICE(INTEL, 0x8d4e), LPC_WBG}, | |
708 | { PCI_VDEVICE(INTEL, 0x8d4f), LPC_WBG}, | |
709 | { PCI_VDEVICE(INTEL, 0x8d50), LPC_WBG}, | |
710 | { PCI_VDEVICE(INTEL, 0x8d51), LPC_WBG}, | |
711 | { PCI_VDEVICE(INTEL, 0x8d52), LPC_WBG}, | |
712 | { PCI_VDEVICE(INTEL, 0x8d53), LPC_WBG}, | |
713 | { PCI_VDEVICE(INTEL, 0x8d54), LPC_WBG}, | |
714 | { PCI_VDEVICE(INTEL, 0x8d55), LPC_WBG}, | |
715 | { PCI_VDEVICE(INTEL, 0x8d56), LPC_WBG}, | |
716 | { PCI_VDEVICE(INTEL, 0x8d57), LPC_WBG}, | |
717 | { PCI_VDEVICE(INTEL, 0x8d58), LPC_WBG}, | |
718 | { PCI_VDEVICE(INTEL, 0x8d59), LPC_WBG}, | |
719 | { PCI_VDEVICE(INTEL, 0x8d5a), LPC_WBG}, | |
720 | { PCI_VDEVICE(INTEL, 0x8d5b), LPC_WBG}, | |
721 | { PCI_VDEVICE(INTEL, 0x8d5c), LPC_WBG}, | |
722 | { PCI_VDEVICE(INTEL, 0x8d5d), LPC_WBG}, | |
723 | { PCI_VDEVICE(INTEL, 0x8d5e), LPC_WBG}, | |
724 | { PCI_VDEVICE(INTEL, 0x8d5f), LPC_WBG}, | |
8477128f JR |
725 | { PCI_VDEVICE(INTEL, 0x1f38), LPC_AVN}, |
726 | { PCI_VDEVICE(INTEL, 0x1f39), LPC_AVN}, | |
727 | { PCI_VDEVICE(INTEL, 0x1f3a), LPC_AVN}, | |
728 | { PCI_VDEVICE(INTEL, 0x1f3b), LPC_AVN}, | |
283aae8a | 729 | { PCI_VDEVICE(INTEL, 0x2390), LPC_COLETO}, |
5e90169c JR |
730 | { PCI_VDEVICE(INTEL, 0x9cc1), LPC_WPT_LP}, |
731 | { PCI_VDEVICE(INTEL, 0x9cc2), LPC_WPT_LP}, | |
732 | { PCI_VDEVICE(INTEL, 0x9cc3), LPC_WPT_LP}, | |
733 | { PCI_VDEVICE(INTEL, 0x9cc5), LPC_WPT_LP}, | |
734 | { PCI_VDEVICE(INTEL, 0x9cc6), LPC_WPT_LP}, | |
735 | { PCI_VDEVICE(INTEL, 0x9cc7), LPC_WPT_LP}, | |
736 | { PCI_VDEVICE(INTEL, 0x9cc9), LPC_WPT_LP}, | |
4630b130 AS |
737 | { 0, }, /* End of list */ |
738 | }; | |
739 | MODULE_DEVICE_TABLE(pci, lpc_ich_ids); | |
740 | ||
741 | static void lpc_ich_restore_config_space(struct pci_dev *dev) | |
742 | { | |
01560f6b AS |
743 | struct lpc_ich_priv *priv = pci_get_drvdata(dev); |
744 | ||
745 | if (priv->acpi.save >= 0) { | |
746 | pci_write_config_byte(dev, priv->acpi.ctrl, priv->acpi.save); | |
747 | priv->acpi.save = -1; | |
4630b130 AS |
748 | } |
749 | ||
01560f6b AS |
750 | if (priv->gpio.save >= 0) { |
751 | pci_write_config_byte(dev, priv->gpio.ctrl, priv->gpio.save); | |
752 | priv->gpio.save = -1; | |
4630b130 AS |
753 | } |
754 | } | |
755 | ||
f791be49 | 756 | static void lpc_ich_enable_acpi_space(struct pci_dev *dev) |
4630b130 | 757 | { |
01560f6b | 758 | struct lpc_ich_priv *priv = pci_get_drvdata(dev); |
4630b130 AS |
759 | u8 reg_save; |
760 | ||
01560f6b AS |
761 | pci_read_config_byte(dev, priv->acpi.ctrl, ®_save); |
762 | pci_write_config_byte(dev, priv->acpi.ctrl, reg_save | 0x10); | |
763 | priv->acpi.save = reg_save; | |
4630b130 AS |
764 | } |
765 | ||
f791be49 | 766 | static void lpc_ich_enable_gpio_space(struct pci_dev *dev) |
4630b130 | 767 | { |
01560f6b | 768 | struct lpc_ich_priv *priv = pci_get_drvdata(dev); |
4630b130 AS |
769 | u8 reg_save; |
770 | ||
01560f6b AS |
771 | pci_read_config_byte(dev, priv->gpio.ctrl, ®_save); |
772 | pci_write_config_byte(dev, priv->gpio.ctrl, reg_save | 0x10); | |
773 | priv->gpio.save = reg_save; | |
4630b130 AS |
774 | } |
775 | ||
01560f6b | 776 | static void lpc_ich_finalize_cell(struct pci_dev *dev, struct mfd_cell *cell) |
4630b130 | 777 | { |
01560f6b AS |
778 | struct lpc_ich_priv *priv = pci_get_drvdata(dev); |
779 | ||
780 | cell->platform_data = &lpc_chipset_info[priv->chipset]; | |
4630b130 AS |
781 | cell->pdata_size = sizeof(struct lpc_ich_info); |
782 | } | |
783 | ||
4f600ada JD |
784 | /* |
785 | * We don't check for resource conflict globally. There are 2 or 3 independent | |
786 | * GPIO groups and it's enough to have access to one of these to instantiate | |
787 | * the device. | |
788 | */ | |
f791be49 | 789 | static int lpc_ich_check_conflict_gpio(struct resource *res) |
4f600ada JD |
790 | { |
791 | int ret; | |
792 | u8 use_gpio = 0; | |
793 | ||
794 | if (resource_size(res) >= 0x50 && | |
795 | !acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3")) | |
796 | use_gpio |= 1 << 2; | |
797 | ||
798 | if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2")) | |
799 | use_gpio |= 1 << 1; | |
800 | ||
801 | ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1"); | |
802 | if (!ret) | |
803 | use_gpio |= 1 << 0; | |
804 | ||
805 | return use_gpio ? use_gpio : ret; | |
806 | } | |
807 | ||
01560f6b | 808 | static int lpc_ich_init_gpio(struct pci_dev *dev) |
4630b130 | 809 | { |
01560f6b | 810 | struct lpc_ich_priv *priv = pci_get_drvdata(dev); |
4630b130 AS |
811 | u32 base_addr_cfg; |
812 | u32 base_addr; | |
813 | int ret; | |
814 | bool acpi_conflict = false; | |
815 | struct resource *res; | |
816 | ||
817 | /* Setup power management base register */ | |
01560f6b | 818 | pci_read_config_dword(dev, priv->acpi.base, &base_addr_cfg); |
4630b130 AS |
819 | base_addr = base_addr_cfg & 0x0000ff80; |
820 | if (!base_addr) { | |
0c418844 | 821 | dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n"); |
4630b130 AS |
822 | lpc_ich_cells[LPC_GPIO].num_resources--; |
823 | goto gpe0_done; | |
824 | } | |
825 | ||
826 | res = &gpio_ich_res[ICH_RES_GPE0]; | |
827 | res->start = base_addr + ACPIBASE_GPE_OFF; | |
828 | res->end = base_addr + ACPIBASE_GPE_END; | |
829 | ret = acpi_check_resource_conflict(res); | |
830 | if (ret) { | |
831 | /* | |
832 | * This isn't fatal for the GPIO, but we have to make sure that | |
833 | * the platform_device subsystem doesn't see this resource | |
834 | * or it will register an invalid region. | |
835 | */ | |
836 | lpc_ich_cells[LPC_GPIO].num_resources--; | |
837 | acpi_conflict = true; | |
838 | } else { | |
839 | lpc_ich_enable_acpi_space(dev); | |
840 | } | |
841 | ||
842 | gpe0_done: | |
843 | /* Setup GPIO base register */ | |
01560f6b | 844 | pci_read_config_dword(dev, priv->gpio.base, &base_addr_cfg); |
4630b130 AS |
845 | base_addr = base_addr_cfg & 0x0000ff80; |
846 | if (!base_addr) { | |
0c418844 | 847 | dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n"); |
4630b130 AS |
848 | ret = -ENODEV; |
849 | goto gpio_done; | |
850 | } | |
851 | ||
852 | /* Older devices provide fewer GPIO and have a smaller resource size. */ | |
853 | res = &gpio_ich_res[ICH_RES_GPIO]; | |
854 | res->start = base_addr; | |
01560f6b | 855 | switch (lpc_chipset_info[priv->chipset].gpio_version) { |
4630b130 AS |
856 | case ICH_V5_GPIO: |
857 | case ICH_V10CORP_GPIO: | |
858 | res->end = res->start + 128 - 1; | |
859 | break; | |
860 | default: | |
861 | res->end = res->start + 64 - 1; | |
862 | break; | |
863 | } | |
864 | ||
4f600ada JD |
865 | ret = lpc_ich_check_conflict_gpio(res); |
866 | if (ret < 0) { | |
4630b130 AS |
867 | /* this isn't necessarily fatal for the GPIO */ |
868 | acpi_conflict = true; | |
869 | goto gpio_done; | |
870 | } | |
01560f6b | 871 | lpc_chipset_info[priv->chipset].use_gpio = ret; |
4630b130 AS |
872 | lpc_ich_enable_gpio_space(dev); |
873 | ||
01560f6b | 874 | lpc_ich_finalize_cell(dev, &lpc_ich_cells[LPC_GPIO]); |
4630b130 | 875 | ret = mfd_add_devices(&dev->dev, -1, &lpc_ich_cells[LPC_GPIO], |
55692af5 | 876 | 1, NULL, 0, NULL); |
4630b130 AS |
877 | |
878 | gpio_done: | |
879 | if (acpi_conflict) | |
880 | pr_warn("Resource conflict(s) found affecting %s\n", | |
881 | lpc_ich_cells[LPC_GPIO].name); | |
882 | return ret; | |
883 | } | |
884 | ||
01560f6b | 885 | static int lpc_ich_init_wdt(struct pci_dev *dev) |
887c8ec7 | 886 | { |
01560f6b | 887 | struct lpc_ich_priv *priv = pci_get_drvdata(dev); |
887c8ec7 AS |
888 | u32 base_addr_cfg; |
889 | u32 base_addr; | |
890 | int ret; | |
887c8ec7 AS |
891 | struct resource *res; |
892 | ||
893 | /* Setup power management base register */ | |
01560f6b | 894 | pci_read_config_dword(dev, priv->acpi.base, &base_addr_cfg); |
887c8ec7 AS |
895 | base_addr = base_addr_cfg & 0x0000ff80; |
896 | if (!base_addr) { | |
0c418844 | 897 | dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n"); |
887c8ec7 AS |
898 | ret = -ENODEV; |
899 | goto wdt_done; | |
900 | } | |
901 | ||
902 | res = wdt_io_res(ICH_RES_IO_TCO); | |
903 | res->start = base_addr + ACPIBASE_TCO_OFF; | |
904 | res->end = base_addr + ACPIBASE_TCO_END; | |
887c8ec7 AS |
905 | |
906 | res = wdt_io_res(ICH_RES_IO_SMI); | |
907 | res->start = base_addr + ACPIBASE_SMI_OFF; | |
908 | res->end = base_addr + ACPIBASE_SMI_END; | |
092369ef | 909 | |
887c8ec7 AS |
910 | lpc_ich_enable_acpi_space(dev); |
911 | ||
912 | /* | |
913 | * Get the Memory-Mapped GCS register. To get access to it | |
914 | * we have to read RCBA from PCI Config space 0xf0 and use | |
915 | * it as base. GCS = RCBA + ICH6_GCS(0x3410). | |
916 | */ | |
01560f6b | 917 | if (lpc_chipset_info[priv->chipset].iTCO_version == 1) { |
e294bc91 PH |
918 | /* Don't register iomem for TCO ver 1 */ |
919 | lpc_ich_cells[LPC_WDT].num_resources--; | |
920 | } else { | |
887c8ec7 AS |
921 | pci_read_config_dword(dev, RCBABASE, &base_addr_cfg); |
922 | base_addr = base_addr_cfg & 0xffffc000; | |
923 | if (!(base_addr_cfg & 1)) { | |
0c418844 PB |
924 | dev_notice(&dev->dev, "RCBA is disabled by " |
925 | "hardware/BIOS, device disabled\n"); | |
887c8ec7 AS |
926 | ret = -ENODEV; |
927 | goto wdt_done; | |
928 | } | |
929 | res = wdt_mem_res(ICH_RES_MEM_GCS); | |
930 | res->start = base_addr + ACPIBASE_GCS_OFF; | |
931 | res->end = base_addr + ACPIBASE_GCS_END; | |
887c8ec7 AS |
932 | } |
933 | ||
01560f6b | 934 | lpc_ich_finalize_cell(dev, &lpc_ich_cells[LPC_WDT]); |
887c8ec7 | 935 | ret = mfd_add_devices(&dev->dev, -1, &lpc_ich_cells[LPC_WDT], |
55692af5 | 936 | 1, NULL, 0, NULL); |
887c8ec7 AS |
937 | |
938 | wdt_done: | |
887c8ec7 AS |
939 | return ret; |
940 | } | |
941 | ||
f791be49 | 942 | static int lpc_ich_probe(struct pci_dev *dev, |
4630b130 AS |
943 | const struct pci_device_id *id) |
944 | { | |
01560f6b | 945 | struct lpc_ich_priv *priv; |
4630b130 AS |
946 | int ret; |
947 | bool cell_added = false; | |
948 | ||
ff7109fa AS |
949 | priv = devm_kzalloc(&dev->dev, |
950 | sizeof(struct lpc_ich_priv), GFP_KERNEL); | |
01560f6b AS |
951 | if (!priv) |
952 | return -ENOMEM; | |
953 | ||
954 | priv->chipset = id->driver_data; | |
955 | priv->acpi.save = -1; | |
956 | priv->acpi.base = ACPIBASE; | |
957 | priv->acpi.ctrl = ACPICTRL; | |
958 | ||
959 | priv->gpio.save = -1; | |
960 | if (priv->chipset <= LPC_ICH5) { | |
961 | priv->gpio.base = GPIOBASE_ICH0; | |
962 | priv->gpio.ctrl = GPIOCTRL_ICH0; | |
963 | } else { | |
964 | priv->gpio.base = GPIOBASE_ICH6; | |
965 | priv->gpio.ctrl = GPIOCTRL_ICH6; | |
966 | } | |
967 | ||
968 | pci_set_drvdata(dev, priv); | |
969 | ||
970 | ret = lpc_ich_init_wdt(dev); | |
887c8ec7 AS |
971 | if (!ret) |
972 | cell_added = true; | |
973 | ||
01560f6b | 974 | ret = lpc_ich_init_gpio(dev); |
4630b130 AS |
975 | if (!ret) |
976 | cell_added = true; | |
977 | ||
978 | /* | |
979 | * We only care if at least one or none of the cells registered | |
980 | * successfully. | |
981 | */ | |
982 | if (!cell_added) { | |
0c418844 | 983 | dev_warn(&dev->dev, "No MFD cells added\n"); |
4630b130 AS |
984 | lpc_ich_restore_config_space(dev); |
985 | return -ENODEV; | |
986 | } | |
987 | ||
988 | return 0; | |
989 | } | |
990 | ||
4740f73f | 991 | static void lpc_ich_remove(struct pci_dev *dev) |
4630b130 AS |
992 | { |
993 | mfd_remove_devices(&dev->dev); | |
994 | lpc_ich_restore_config_space(dev); | |
995 | } | |
996 | ||
997 | static struct pci_driver lpc_ich_driver = { | |
998 | .name = "lpc_ich", | |
999 | .id_table = lpc_ich_ids, | |
1000 | .probe = lpc_ich_probe, | |
84449216 | 1001 | .remove = lpc_ich_remove, |
4630b130 AS |
1002 | }; |
1003 | ||
b4d0fe9c | 1004 | module_pci_driver(lpc_ich_driver); |
4630b130 AS |
1005 | |
1006 | MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>"); | |
1007 | MODULE_DESCRIPTION("LPC interface for Intel ICH"); | |
1008 | MODULE_LICENSE("GPL"); |