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mfd: max77693: Improve support for the flash cell
[deliverable/linux.git] / drivers / mfd / lpc_ich.c
CommitLineData
4630b130
AS		 1/*
2 * lpc_ich.c - LPC interface for Intel ICH
3 *
4 * LPC bridge function of the Intel ICH contains many other
5 * functional units, such as Interrupt controllers, Timers,
6 * Power Management, System Management, GPIO, RTC, and LPC
7 * Configuration Registers.
8 *
9 * This driver is derived from lpc_sch.
10
11 * Copyright (c) 2011 Extreme Engineering Solution, Inc.
12 * Author: Aaron Sierra <asierra@xes-inc.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License 2 as published
16 * by the Free Software Foundation.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; see the file COPYING. If not, write to
25 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 * This driver supports the following I/O Controller hubs:
28 * (See the intel documentation on http://developer.intel.com.)
29 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
30 * document number 290687-002, 298242-027: 82801BA (ICH2)
31 * document number 290733-003, 290739-013: 82801CA (ICH3-S)
32 * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
33 * document number 290744-001, 290745-025: 82801DB (ICH4)
34 * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
35 * document number 273599-001, 273645-002: 82801E (C-ICH)
36 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
37 * document number 300641-004, 300884-013: 6300ESB
38 * document number 301473-002, 301474-026: 82801F (ICH6)
39 * document number 313082-001, 313075-006: 631xESB, 632xESB
40 * document number 307013-003, 307014-024: 82801G (ICH7)
41 * document number 322896-001, 322897-001: NM10
42 * document number 313056-003, 313057-017: 82801H (ICH8)
43 * document number 316972-004, 316973-012: 82801I (ICH9)
44 * document number 319973-002, 319974-002: 82801J (ICH10)
45 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
46 * document number 320066-003, 320257-008: EP80597 (IICH)
47 * document number 324645-001, 324646-001: Cougar Point (CPT)
48 * document number TBD : Patsburg (PBG)
49 * document number TBD : DH89xxCC
50 * document number TBD : Panther Point
51 * document number TBD : Lynx Point
7fb9c1a4 52 * document number TBD : Lynx Point-LP
6e6680e3 53 * document number TBD : Wellsburg
8477128f 54 * document number TBD : Avoton SoC
283aae8a 55 * document number TBD : Coleto Creek
5e90169c 56 * document number TBD : Wildcat Point-LP
4630b130
AS		 57 */
58
59#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
60
4630b130
AS		 61#include <linux/kernel.h>
62#include <linux/module.h>
63#include <linux/errno.h>
64#include <linux/acpi.h>
65#include <linux/pci.h>
66#include <linux/mfd/core.h>
67#include <linux/mfd/lpc_ich.h>
68
69#define ACPIBASE 0x40
70#define ACPIBASE_GPE_OFF 0x28
71#define ACPIBASE_GPE_END 0x2f
887c8ec7
AS		 72#define ACPIBASE_SMI_OFF 0x30
73#define ACPIBASE_SMI_END 0x33
eb71d4de
PT		 74#define ACPIBASE_PMC_OFF 0x08
75#define ACPIBASE_PMC_END 0x0c
887c8ec7
AS		 76#define ACPIBASE_TCO_OFF 0x60
77#define ACPIBASE_TCO_END 0x7f
eb71d4de 78#define ACPICTRL_PMCBASE 0x44
4630b130 79
887c8ec7
AS		 80#define ACPIBASE_GCS_OFF 0x3410
81#define ACPIBASE_GCS_END 0x3414
82
01560f6b
AS		 83#define GPIOBASE_ICH0 0x58
84#define GPIOCTRL_ICH0 0x5C
85#define GPIOBASE_ICH6 0x48
86#define GPIOCTRL_ICH6 0x4C
4630b130 87
887c8ec7
AS		 88#define RCBABASE 0xf0
89
90#define wdt_io_res(i) wdt_res(0, i)
91#define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i)
92#define wdt_res(b, i) (&wdt_ich_res[(b) + (i)])
93
01560f6b
AS		 94struct lpc_ich_priv {
95 int chipset;
429b941a
PT		 96
97 int abase; /* ACPI base */
eb71d4de 98 int actrl_pbase; /* ACPI control or PMC base */
429b941a
PT		 99 int gbase; /* GPIO base */
100 int gctrl; /* GPIO control */
101
eb71d4de
PT		 102 int abase_save; /* Cached ACPI base value */
103 int actrl_pbase_save; /* Cached ACPI control or PMC base value */
429b941a 104 int gctrl_save; /* Cached GPIO control value */
01560f6b 105};
4630b130 106
887c8ec7
AS		 107static struct resource wdt_ich_res[] = {
108 /* ACPI - TCO */
109 {
110 .flags = IORESOURCE_IO,
111 },
112 /* ACPI - SMI */
113 {
114 .flags = IORESOURCE_IO,
115 },
eb71d4de 116 /* GCS or PMC */
887c8ec7
AS		 117 {
118 .flags = IORESOURCE_MEM,
119 },
120};
121
4630b130
AS		 122static struct resource gpio_ich_res[] = {
123 /* GPIO */
124 {
125 .flags = IORESOURCE_IO,
126 },
127 /* ACPI - GPE0 */
128 {
129 .flags = IORESOURCE_IO,
130 },
131};
132
133enum lpc_cells {
887c8ec7
AS		 134 LPC_WDT = 0,
135 LPC_GPIO,
4630b130
AS		 136};
137
138static struct mfd_cell lpc_ich_cells[] = {
887c8ec7
AS		 139 [LPC_WDT] = {
140 .name = "iTCO_wdt",
141 .num_resources = ARRAY_SIZE(wdt_ich_res),
142 .resources = wdt_ich_res,
143 .ignore_resource_conflicts = true,
144 },
4630b130
AS		 145 [LPC_GPIO] = {
146 .name = "gpio_ich",
147 .num_resources = ARRAY_SIZE(gpio_ich_res),
148 .resources = gpio_ich_res,
149 .ignore_resource_conflicts = true,
150 },
151};
152
153/* chipset related info */
154enum lpc_chipsets {
155 LPC_ICH = 0, /* ICH */
156 LPC_ICH0, /* ICH0 */
157 LPC_ICH2, /* ICH2 */
158 LPC_ICH2M, /* ICH2-M */
159 LPC_ICH3, /* ICH3-S */
160 LPC_ICH3M, /* ICH3-M */
161 LPC_ICH4, /* ICH4 */
162 LPC_ICH4M, /* ICH4-M */
163 LPC_CICH, /* C-ICH */
164 LPC_ICH5, /* ICH5 & ICH5R */
165 LPC_6300ESB, /* 6300ESB */
166 LPC_ICH6, /* ICH6 & ICH6R */
167 LPC_ICH6M, /* ICH6-M */
168 LPC_ICH6W, /* ICH6W & ICH6RW */
169 LPC_631XESB, /* 631xESB/632xESB */
170 LPC_ICH7, /* ICH7 & ICH7R */
171 LPC_ICH7DH, /* ICH7DH */
172 LPC_ICH7M, /* ICH7-M & ICH7-U */
173 LPC_ICH7MDH, /* ICH7-M DH */
174 LPC_NM10, /* NM10 */
175 LPC_ICH8, /* ICH8 & ICH8R */
176 LPC_ICH8DH, /* ICH8DH */
177 LPC_ICH8DO, /* ICH8DO */
178 LPC_ICH8M, /* ICH8M */
179 LPC_ICH8ME, /* ICH8M-E */
180 LPC_ICH9, /* ICH9 */
181 LPC_ICH9R, /* ICH9R */
182 LPC_ICH9DH, /* ICH9DH */
183 LPC_ICH9DO, /* ICH9DO */
184 LPC_ICH9M, /* ICH9M */
185 LPC_ICH9ME, /* ICH9M-E */
186 LPC_ICH10, /* ICH10 */
187 LPC_ICH10R, /* ICH10R */
188 LPC_ICH10D, /* ICH10D */
189 LPC_ICH10DO, /* ICH10DO */
190 LPC_PCH, /* PCH Desktop Full Featured */
191 LPC_PCHM, /* PCH Mobile Full Featured */
192 LPC_P55, /* P55 */
193 LPC_PM55, /* PM55 */
194 LPC_H55, /* H55 */
195 LPC_QM57, /* QM57 */
196 LPC_H57, /* H57 */
197 LPC_HM55, /* HM55 */
198 LPC_Q57, /* Q57 */
199 LPC_HM57, /* HM57 */
200 LPC_PCHMSFF, /* PCH Mobile SFF Full Featured */
201 LPC_QS57, /* QS57 */
202 LPC_3400, /* 3400 */
203 LPC_3420, /* 3420 */
204 LPC_3450, /* 3450 */
205 LPC_EP80579, /* EP80579 */
206 LPC_CPT, /* Cougar Point */
207 LPC_CPTD, /* Cougar Point Desktop */
208 LPC_CPTM, /* Cougar Point Mobile */
209 LPC_PBG, /* Patsburg */
210 LPC_DH89XXCC, /* DH89xxCC */
211 LPC_PPT, /* Panther Point */
212 LPC_LPT, /* Lynx Point */
7fb9c1a4 213 LPC_LPT_LP, /* Lynx Point-LP */
6e6680e3 214 LPC_WBG, /* Wellsburg */
8477128f 215 LPC_AVN, /* Avoton SoC */
6111ec70 216 LPC_BAYTRAIL, /* Bay Trail SoC */
283aae8a 217 LPC_COLETO, /* Coleto Creek */
5e90169c 218 LPC_WPT_LP, /* Wildcat Point-LP */
ff0c9da0 219 LPC_BRASWELL, /* Braswell SoC */
4630b130
AS		 220};
221
a1ca138f 222static struct lpc_ich_info lpc_chipset_info[] = {
4630b130
AS		 223 [LPC_ICH] = {
224 .name = "ICH",
887c8ec7 225 .iTCO_version = 1,
4630b130
AS		 226 },
227 [LPC_ICH0] = {
228 .name = "ICH0",
887c8ec7 229 .iTCO_version = 1,
4630b130
AS		 230 },
231 [LPC_ICH2] = {
232 .name = "ICH2",
887c8ec7 233 .iTCO_version = 1,
4630b130
AS		 234 },
235 [LPC_ICH2M] = {
236 .name = "ICH2-M",
887c8ec7 237 .iTCO_version = 1,
4630b130
AS		 238 },
239 [LPC_ICH3] = {
240 .name = "ICH3-S",
887c8ec7 241 .iTCO_version = 1,
4630b130
AS		 242 },
243 [LPC_ICH3M] = {
244 .name = "ICH3-M",
887c8ec7 245 .iTCO_version = 1,
4630b130
AS		 246 },
247 [LPC_ICH4] = {
248 .name = "ICH4",
887c8ec7 249 .iTCO_version = 1,
4630b130
AS		 250 },
251 [LPC_ICH4M] = {
252 .name = "ICH4-M",
887c8ec7 253 .iTCO_version = 1,
4630b130
AS		 254 },
255 [LPC_CICH] = {
256 .name = "C-ICH",
887c8ec7 257 .iTCO_version = 1,
4630b130
AS		 258 },
259 [LPC_ICH5] = {
260 .name = "ICH5 or ICH5R",
887c8ec7 261 .iTCO_version = 1,
4630b130
AS		 262 },
263 [LPC_6300ESB] = {
264 .name = "6300ESB",
887c8ec7 265 .iTCO_version = 1,
4630b130
AS		 266 },
267 [LPC_ICH6] = {
268 .name = "ICH6 or ICH6R",
887c8ec7 269 .iTCO_version = 2,
4630b130
AS		 270 .gpio_version = ICH_V6_GPIO,
271 },
272 [LPC_ICH6M] = {
273 .name = "ICH6-M",
887c8ec7 274 .iTCO_version = 2,
4630b130
AS		 275 .gpio_version = ICH_V6_GPIO,
276 },
277 [LPC_ICH6W] = {
278 .name = "ICH6W or ICH6RW",
887c8ec7 279 .iTCO_version = 2,
4630b130
AS		 280 .gpio_version = ICH_V6_GPIO,
281 },
282 [LPC_631XESB] = {
283 .name = "631xESB/632xESB",
887c8ec7 284 .iTCO_version = 2,
4630b130
AS		 285 .gpio_version = ICH_V6_GPIO,
286 },
287 [LPC_ICH7] = {
288 .name = "ICH7 or ICH7R",
887c8ec7 289 .iTCO_version = 2,
4630b130
AS		 290 .gpio_version = ICH_V7_GPIO,
291 },
292 [LPC_ICH7DH] = {
293 .name = "ICH7DH",
887c8ec7 294 .iTCO_version = 2,
4630b130
AS		 295 .gpio_version = ICH_V7_GPIO,
296 },
297 [LPC_ICH7M] = {
298 .name = "ICH7-M or ICH7-U",
887c8ec7 299 .iTCO_version = 2,
4630b130
AS		 300 .gpio_version = ICH_V7_GPIO,
301 },
302 [LPC_ICH7MDH] = {
303 .name = "ICH7-M DH",
887c8ec7 304 .iTCO_version = 2,
4630b130
AS		 305 .gpio_version = ICH_V7_GPIO,
306 },
307 [LPC_NM10] = {
308 .name = "NM10",
887c8ec7 309 .iTCO_version = 2,
117bbfe2 310 .gpio_version = ICH_V7_GPIO,
4630b130
AS		 311 },
312 [LPC_ICH8] = {
313 .name = "ICH8 or ICH8R",
887c8ec7 314 .iTCO_version = 2,
4630b130
AS		 315 .gpio_version = ICH_V7_GPIO,
316 },
317 [LPC_ICH8DH] = {
318 .name = "ICH8DH",
887c8ec7 319 .iTCO_version = 2,
4630b130
AS		 320 .gpio_version = ICH_V7_GPIO,
321 },
322 [LPC_ICH8DO] = {
323 .name = "ICH8DO",
887c8ec7 324 .iTCO_version = 2,
4630b130
AS		 325 .gpio_version = ICH_V7_GPIO,
326 },
327 [LPC_ICH8M] = {
328 .name = "ICH8M",
887c8ec7 329 .iTCO_version = 2,
4630b130
AS		 330 .gpio_version = ICH_V7_GPIO,
331 },
332 [LPC_ICH8ME] = {
333 .name = "ICH8M-E",
887c8ec7 334 .iTCO_version = 2,
4630b130
AS		 335 .gpio_version = ICH_V7_GPIO,
336 },
337 [LPC_ICH9] = {
338 .name = "ICH9",
887c8ec7 339 .iTCO_version = 2,
4630b130
AS		 340 .gpio_version = ICH_V9_GPIO,
341 },
342 [LPC_ICH9R] = {
343 .name = "ICH9R",
887c8ec7 344 .iTCO_version = 2,
4630b130
AS		 345 .gpio_version = ICH_V9_GPIO,
346 },
347 [LPC_ICH9DH] = {
348 .name = "ICH9DH",
887c8ec7 349 .iTCO_version = 2,
4630b130
AS		 350 .gpio_version = ICH_V9_GPIO,
351 },
352 [LPC_ICH9DO] = {
353 .name = "ICH9DO",
887c8ec7 354 .iTCO_version = 2,
4630b130
AS		 355 .gpio_version = ICH_V9_GPIO,
356 },
357 [LPC_ICH9M] = {
358 .name = "ICH9M",
887c8ec7 359 .iTCO_version = 2,
4630b130
AS		 360 .gpio_version = ICH_V9_GPIO,
361 },
362 [LPC_ICH9ME] = {
363 .name = "ICH9M-E",
887c8ec7 364 .iTCO_version = 2,
4630b130
AS		 365 .gpio_version = ICH_V9_GPIO,
366 },
367 [LPC_ICH10] = {
368 .name = "ICH10",
887c8ec7 369 .iTCO_version = 2,
4630b130
AS		 370 .gpio_version = ICH_V10CONS_GPIO,
371 },
372 [LPC_ICH10R] = {
373 .name = "ICH10R",
887c8ec7 374 .iTCO_version = 2,
4630b130
AS		 375 .gpio_version = ICH_V10CONS_GPIO,
376 },
377 [LPC_ICH10D] = {
378 .name = "ICH10D",
887c8ec7 379 .iTCO_version = 2,
4630b130
AS		 380 .gpio_version = ICH_V10CORP_GPIO,
381 },
382 [LPC_ICH10DO] = {
383 .name = "ICH10DO",
887c8ec7 384 .iTCO_version = 2,
4630b130
AS		 385 .gpio_version = ICH_V10CORP_GPIO,
386 },
387 [LPC_PCH] = {
388 .name = "PCH Desktop Full Featured",
887c8ec7 389 .iTCO_version = 2,
4630b130
AS		 390 .gpio_version = ICH_V5_GPIO,
391 },
392 [LPC_PCHM] = {
393 .name = "PCH Mobile Full Featured",
887c8ec7 394 .iTCO_version = 2,
4630b130
AS		 395 .gpio_version = ICH_V5_GPIO,
396 },
397 [LPC_P55] = {
398 .name = "P55",
887c8ec7 399 .iTCO_version = 2,
4630b130
AS		 400 .gpio_version = ICH_V5_GPIO,
401 },
402 [LPC_PM55] = {
403 .name = "PM55",
887c8ec7 404 .iTCO_version = 2,
4630b130
AS		 405 .gpio_version = ICH_V5_GPIO,
406 },
407 [LPC_H55] = {
408 .name = "H55",
887c8ec7 409 .iTCO_version = 2,
4630b130
AS		 410 .gpio_version = ICH_V5_GPIO,
411 },
412 [LPC_QM57] = {
413 .name = "QM57",
887c8ec7 414 .iTCO_version = 2,
4630b130
AS		 415 .gpio_version = ICH_V5_GPIO,
416 },
417 [LPC_H57] = {
418 .name = "H57",
887c8ec7 419 .iTCO_version = 2,
4630b130
AS		 420 .gpio_version = ICH_V5_GPIO,
421 },
422 [LPC_HM55] = {
423 .name = "HM55",
887c8ec7 424 .iTCO_version = 2,
4630b130
AS		 425 .gpio_version = ICH_V5_GPIO,
426 },
427 [LPC_Q57] = {
428 .name = "Q57",
887c8ec7 429 .iTCO_version = 2,
4630b130
AS		 430 .gpio_version = ICH_V5_GPIO,
431 },
432 [LPC_HM57] = {
433 .name = "HM57",
887c8ec7 434 .iTCO_version = 2,
4630b130
AS		 435 .gpio_version = ICH_V5_GPIO,
436 },
437 [LPC_PCHMSFF] = {
438 .name = "PCH Mobile SFF Full Featured",
887c8ec7 439 .iTCO_version = 2,
4630b130
AS		 440 .gpio_version = ICH_V5_GPIO,
441 },
442 [LPC_QS57] = {
443 .name = "QS57",
887c8ec7 444 .iTCO_version = 2,
4630b130
AS		 445 .gpio_version = ICH_V5_GPIO,
446 },
447 [LPC_3400] = {
448 .name = "3400",
887c8ec7 449 .iTCO_version = 2,
4630b130
AS		 450 .gpio_version = ICH_V5_GPIO,
451 },
452 [LPC_3420] = {
453 .name = "3420",
887c8ec7 454 .iTCO_version = 2,
4630b130
AS		 455 .gpio_version = ICH_V5_GPIO,
456 },
457 [LPC_3450] = {
458 .name = "3450",
887c8ec7 459 .iTCO_version = 2,
4630b130
AS		 460 .gpio_version = ICH_V5_GPIO,
461 },
462 [LPC_EP80579] = {
463 .name = "EP80579",
887c8ec7 464 .iTCO_version = 2,
4630b130
AS		 465 },
466 [LPC_CPT] = {
467 .name = "Cougar Point",
887c8ec7 468 .iTCO_version = 2,
4630b130
AS		 469 .gpio_version = ICH_V5_GPIO,
470 },
471 [LPC_CPTD] = {
472 .name = "Cougar Point Desktop",
887c8ec7 473 .iTCO_version = 2,
4630b130
AS		 474 .gpio_version = ICH_V5_GPIO,
475 },
476 [LPC_CPTM] = {
477 .name = "Cougar Point Mobile",
887c8ec7 478 .iTCO_version = 2,
4630b130
AS		 479 .gpio_version = ICH_V5_GPIO,
480 },
481 [LPC_PBG] = {
482 .name = "Patsburg",
887c8ec7 483 .iTCO_version = 2,
4630b130
AS		 484 },
485 [LPC_DH89XXCC] = {
486 .name = "DH89xxCC",
887c8ec7 487 .iTCO_version = 2,
4630b130
AS		 488 },
489 [LPC_PPT] = {
490 .name = "Panther Point",
887c8ec7 491 .iTCO_version = 2,
62cf2cdb 492 .gpio_version = ICH_V5_GPIO,
4630b130
AS		 493 },
494 [LPC_LPT] = {
495 .name = "Lynx Point",
887c8ec7 496 .iTCO_version = 2,
4630b130 497 },
7fb9c1a4
JR		 498 [LPC_LPT_LP] = {
499 .name = "Lynx Point_LP",
500 .iTCO_version = 2,
501 },
6e6680e3
JR		 502 [LPC_WBG] = {
503 .name = "Wellsburg",
504 .iTCO_version = 2,
505 },
8477128f
JR		 506 [LPC_AVN] = {
507 .name = "Avoton SoC",
c48cf598 508 .iTCO_version = 3,
facd9939 509 .gpio_version = AVOTON_GPIO,
8477128f 510 },
6111ec70
PT		 511 [LPC_BAYTRAIL] = {
512 .name = "Bay Trail SoC",
513 .iTCO_version = 3,
514 },
283aae8a
SH		 515 [LPC_COLETO] = {
516 .name = "Coleto Creek",
517 .iTCO_version = 2,
518 },
5e90169c 519 [LPC_WPT_LP] = {
a8822df9 520 .name = "Wildcat Point_LP",
5e90169c
JR		 521 .iTCO_version = 2,
522 },
ff0c9da0
AC		 523 [LPC_BRASWELL] = {
524 .name = "Braswell SoC",
525 .iTCO_version = 3,
526 },
4630b130
AS		 527};
528
529/*
530 * This data only exists for exporting the supported PCI ids
531 * via MODULE_DEVICE_TABLE. We do not actually register a
532 * pci_driver, because the I/O Controller Hub has also other
533 * functions that probably will be registered by other drivers.
534 */
36fcd06c 535static const struct pci_device_id lpc_ich_ids[] = {
4630b130
AS		 536 { PCI_VDEVICE(INTEL, 0x2410), LPC_ICH},
537 { PCI_VDEVICE(INTEL, 0x2420), LPC_ICH0},
538 { PCI_VDEVICE(INTEL, 0x2440), LPC_ICH2},
539 { PCI_VDEVICE(INTEL, 0x244c), LPC_ICH2M},
540 { PCI_VDEVICE(INTEL, 0x2480), LPC_ICH3},
541 { PCI_VDEVICE(INTEL, 0x248c), LPC_ICH3M},
542 { PCI_VDEVICE(INTEL, 0x24c0), LPC_ICH4},
543 { PCI_VDEVICE(INTEL, 0x24cc), LPC_ICH4M},
544 { PCI_VDEVICE(INTEL, 0x2450), LPC_CICH},
545 { PCI_VDEVICE(INTEL, 0x24d0), LPC_ICH5},
546 { PCI_VDEVICE(INTEL, 0x25a1), LPC_6300ESB},
547 { PCI_VDEVICE(INTEL, 0x2640), LPC_ICH6},
548 { PCI_VDEVICE(INTEL, 0x2641), LPC_ICH6M},
549 { PCI_VDEVICE(INTEL, 0x2642), LPC_ICH6W},
550 { PCI_VDEVICE(INTEL, 0x2670), LPC_631XESB},
551 { PCI_VDEVICE(INTEL, 0x2671), LPC_631XESB},
552 { PCI_VDEVICE(INTEL, 0x2672), LPC_631XESB},
553 { PCI_VDEVICE(INTEL, 0x2673), LPC_631XESB},
554 { PCI_VDEVICE(INTEL, 0x2674), LPC_631XESB},
555 { PCI_VDEVICE(INTEL, 0x2675), LPC_631XESB},
556 { PCI_VDEVICE(INTEL, 0x2676), LPC_631XESB},
557 { PCI_VDEVICE(INTEL, 0x2677), LPC_631XESB},
558 { PCI_VDEVICE(INTEL, 0x2678), LPC_631XESB},
559 { PCI_VDEVICE(INTEL, 0x2679), LPC_631XESB},
560 { PCI_VDEVICE(INTEL, 0x267a), LPC_631XESB},
561 { PCI_VDEVICE(INTEL, 0x267b), LPC_631XESB},
562 { PCI_VDEVICE(INTEL, 0x267c), LPC_631XESB},
563 { PCI_VDEVICE(INTEL, 0x267d), LPC_631XESB},
564 { PCI_VDEVICE(INTEL, 0x267e), LPC_631XESB},
565 { PCI_VDEVICE(INTEL, 0x267f), LPC_631XESB},
566 { PCI_VDEVICE(INTEL, 0x27b8), LPC_ICH7},
567 { PCI_VDEVICE(INTEL, 0x27b0), LPC_ICH7DH},
568 { PCI_VDEVICE(INTEL, 0x27b9), LPC_ICH7M},
569 { PCI_VDEVICE(INTEL, 0x27bd), LPC_ICH7MDH},
570 { PCI_VDEVICE(INTEL, 0x27bc), LPC_NM10},
571 { PCI_VDEVICE(INTEL, 0x2810), LPC_ICH8},
572 { PCI_VDEVICE(INTEL, 0x2812), LPC_ICH8DH},
573 { PCI_VDEVICE(INTEL, 0x2814), LPC_ICH8DO},
574 { PCI_VDEVICE(INTEL, 0x2815), LPC_ICH8M},
575 { PCI_VDEVICE(INTEL, 0x2811), LPC_ICH8ME},
576 { PCI_VDEVICE(INTEL, 0x2918), LPC_ICH9},
577 { PCI_VDEVICE(INTEL, 0x2916), LPC_ICH9R},
578 { PCI_VDEVICE(INTEL, 0x2912), LPC_ICH9DH},
579 { PCI_VDEVICE(INTEL, 0x2914), LPC_ICH9DO},
580 { PCI_VDEVICE(INTEL, 0x2919), LPC_ICH9M},
581 { PCI_VDEVICE(INTEL, 0x2917), LPC_ICH9ME},
582 { PCI_VDEVICE(INTEL, 0x3a18), LPC_ICH10},
583 { PCI_VDEVICE(INTEL, 0x3a16), LPC_ICH10R},
584 { PCI_VDEVICE(INTEL, 0x3a1a), LPC_ICH10D},
585 { PCI_VDEVICE(INTEL, 0x3a14), LPC_ICH10DO},
586 { PCI_VDEVICE(INTEL, 0x3b00), LPC_PCH},
587 { PCI_VDEVICE(INTEL, 0x3b01), LPC_PCHM},
588 { PCI_VDEVICE(INTEL, 0x3b02), LPC_P55},
589 { PCI_VDEVICE(INTEL, 0x3b03), LPC_PM55},
590 { PCI_VDEVICE(INTEL, 0x3b06), LPC_H55},
591 { PCI_VDEVICE(INTEL, 0x3b07), LPC_QM57},
592 { PCI_VDEVICE(INTEL, 0x3b08), LPC_H57},
593 { PCI_VDEVICE(INTEL, 0x3b09), LPC_HM55},
594 { PCI_VDEVICE(INTEL, 0x3b0a), LPC_Q57},
595 { PCI_VDEVICE(INTEL, 0x3b0b), LPC_HM57},
596 { PCI_VDEVICE(INTEL, 0x3b0d), LPC_PCHMSFF},
597 { PCI_VDEVICE(INTEL, 0x3b0f), LPC_QS57},
598 { PCI_VDEVICE(INTEL, 0x3b12), LPC_3400},
599 { PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
600 { PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
601 { PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
602 { PCI_VDEVICE(INTEL, 0x1c41), LPC_CPT},
603 { PCI_VDEVICE(INTEL, 0x1c42), LPC_CPTD},
604 { PCI_VDEVICE(INTEL, 0x1c43), LPC_CPTM},
605 { PCI_VDEVICE(INTEL, 0x1c44), LPC_CPT},
606 { PCI_VDEVICE(INTEL, 0x1c45), LPC_CPT},
607 { PCI_VDEVICE(INTEL, 0x1c46), LPC_CPT},
608 { PCI_VDEVICE(INTEL, 0x1c47), LPC_CPT},
609 { PCI_VDEVICE(INTEL, 0x1c48), LPC_CPT},
610 { PCI_VDEVICE(INTEL, 0x1c49), LPC_CPT},
611 { PCI_VDEVICE(INTEL, 0x1c4a), LPC_CPT},
612 { PCI_VDEVICE(INTEL, 0x1c4b), LPC_CPT},
613 { PCI_VDEVICE(INTEL, 0x1c4c), LPC_CPT},
614 { PCI_VDEVICE(INTEL, 0x1c4d), LPC_CPT},
615 { PCI_VDEVICE(INTEL, 0x1c4e), LPC_CPT},
616 { PCI_VDEVICE(INTEL, 0x1c4f), LPC_CPT},
617 { PCI_VDEVICE(INTEL, 0x1c50), LPC_CPT},
618 { PCI_VDEVICE(INTEL, 0x1c51), LPC_CPT},
619 { PCI_VDEVICE(INTEL, 0x1c52), LPC_CPT},
620 { PCI_VDEVICE(INTEL, 0x1c53), LPC_CPT},
621 { PCI_VDEVICE(INTEL, 0x1c54), LPC_CPT},
622 { PCI_VDEVICE(INTEL, 0x1c55), LPC_CPT},
623 { PCI_VDEVICE(INTEL, 0x1c56), LPC_CPT},
624 { PCI_VDEVICE(INTEL, 0x1c57), LPC_CPT},
625 { PCI_VDEVICE(INTEL, 0x1c58), LPC_CPT},
626 { PCI_VDEVICE(INTEL, 0x1c59), LPC_CPT},
627 { PCI_VDEVICE(INTEL, 0x1c5a), LPC_CPT},
628 { PCI_VDEVICE(INTEL, 0x1c5b), LPC_CPT},
629 { PCI_VDEVICE(INTEL, 0x1c5c), LPC_CPT},
630 { PCI_VDEVICE(INTEL, 0x1c5d), LPC_CPT},
631 { PCI_VDEVICE(INTEL, 0x1c5e), LPC_CPT},
632 { PCI_VDEVICE(INTEL, 0x1c5f), LPC_CPT},
633 { PCI_VDEVICE(INTEL, 0x1d40), LPC_PBG},
634 { PCI_VDEVICE(INTEL, 0x1d41), LPC_PBG},
635 { PCI_VDEVICE(INTEL, 0x2310), LPC_DH89XXCC},
636 { PCI_VDEVICE(INTEL, 0x1e40), LPC_PPT},
637 { PCI_VDEVICE(INTEL, 0x1e41), LPC_PPT},
638 { PCI_VDEVICE(INTEL, 0x1e42), LPC_PPT},
639 { PCI_VDEVICE(INTEL, 0x1e43), LPC_PPT},
640 { PCI_VDEVICE(INTEL, 0x1e44), LPC_PPT},
641 { PCI_VDEVICE(INTEL, 0x1e45), LPC_PPT},
642 { PCI_VDEVICE(INTEL, 0x1e46), LPC_PPT},
643 { PCI_VDEVICE(INTEL, 0x1e47), LPC_PPT},
644 { PCI_VDEVICE(INTEL, 0x1e48), LPC_PPT},
645 { PCI_VDEVICE(INTEL, 0x1e49), LPC_PPT},
646 { PCI_VDEVICE(INTEL, 0x1e4a), LPC_PPT},
647 { PCI_VDEVICE(INTEL, 0x1e4b), LPC_PPT},
648 { PCI_VDEVICE(INTEL, 0x1e4c), LPC_PPT},
649 { PCI_VDEVICE(INTEL, 0x1e4d), LPC_PPT},
650 { PCI_VDEVICE(INTEL, 0x1e4e), LPC_PPT},
651 { PCI_VDEVICE(INTEL, 0x1e4f), LPC_PPT},
652 { PCI_VDEVICE(INTEL, 0x1e50), LPC_PPT},
653 { PCI_VDEVICE(INTEL, 0x1e51), LPC_PPT},
654 { PCI_VDEVICE(INTEL, 0x1e52), LPC_PPT},
655 { PCI_VDEVICE(INTEL, 0x1e53), LPC_PPT},
656 { PCI_VDEVICE(INTEL, 0x1e54), LPC_PPT},
657 { PCI_VDEVICE(INTEL, 0x1e55), LPC_PPT},
658 { PCI_VDEVICE(INTEL, 0x1e56), LPC_PPT},
659 { PCI_VDEVICE(INTEL, 0x1e57), LPC_PPT},
660 { PCI_VDEVICE(INTEL, 0x1e58), LPC_PPT},
661 { PCI_VDEVICE(INTEL, 0x1e59), LPC_PPT},
662 { PCI_VDEVICE(INTEL, 0x1e5a), LPC_PPT},
663 { PCI_VDEVICE(INTEL, 0x1e5b), LPC_PPT},
664 { PCI_VDEVICE(INTEL, 0x1e5c), LPC_PPT},
665 { PCI_VDEVICE(INTEL, 0x1e5d), LPC_PPT},
666 { PCI_VDEVICE(INTEL, 0x1e5e), LPC_PPT},
667 { PCI_VDEVICE(INTEL, 0x1e5f), LPC_PPT},
668 { PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
669 { PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
670 { PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
671 { PCI_VDEVICE(INTEL, 0x8c43), LPC_LPT},
672 { PCI_VDEVICE(INTEL, 0x8c44), LPC_LPT},
673 { PCI_VDEVICE(INTEL, 0x8c45), LPC_LPT},
674 { PCI_VDEVICE(INTEL, 0x8c46), LPC_LPT},
675 { PCI_VDEVICE(INTEL, 0x8c47), LPC_LPT},
676 { PCI_VDEVICE(INTEL, 0x8c48), LPC_LPT},
677 { PCI_VDEVICE(INTEL, 0x8c49), LPC_LPT},
678 { PCI_VDEVICE(INTEL, 0x8c4a), LPC_LPT},
679 { PCI_VDEVICE(INTEL, 0x8c4b), LPC_LPT},
680 { PCI_VDEVICE(INTEL, 0x8c4c), LPC_LPT},
681 { PCI_VDEVICE(INTEL, 0x8c4d), LPC_LPT},
682 { PCI_VDEVICE(INTEL, 0x8c4e), LPC_LPT},
683 { PCI_VDEVICE(INTEL, 0x8c4f), LPC_LPT},
684 { PCI_VDEVICE(INTEL, 0x8c50), LPC_LPT},
685 { PCI_VDEVICE(INTEL, 0x8c51), LPC_LPT},
686 { PCI_VDEVICE(INTEL, 0x8c52), LPC_LPT},
687 { PCI_VDEVICE(INTEL, 0x8c53), LPC_LPT},
688 { PCI_VDEVICE(INTEL, 0x8c54), LPC_LPT},
689 { PCI_VDEVICE(INTEL, 0x8c55), LPC_LPT},
690 { PCI_VDEVICE(INTEL, 0x8c56), LPC_LPT},
691 { PCI_VDEVICE(INTEL, 0x8c57), LPC_LPT},
692 { PCI_VDEVICE(INTEL, 0x8c58), LPC_LPT},
693 { PCI_VDEVICE(INTEL, 0x8c59), LPC_LPT},
694 { PCI_VDEVICE(INTEL, 0x8c5a), LPC_LPT},
695 { PCI_VDEVICE(INTEL, 0x8c5b), LPC_LPT},
696 { PCI_VDEVICE(INTEL, 0x8c5c), LPC_LPT},
697 { PCI_VDEVICE(INTEL, 0x8c5d), LPC_LPT},
698 { PCI_VDEVICE(INTEL, 0x8c5e), LPC_LPT},
699 { PCI_VDEVICE(INTEL, 0x8c5f), LPC_LPT},
7fb9c1a4
JR		 700 { PCI_VDEVICE(INTEL, 0x9c40), LPC_LPT_LP},
701 { PCI_VDEVICE(INTEL, 0x9c41), LPC_LPT_LP},
702 { PCI_VDEVICE(INTEL, 0x9c42), LPC_LPT_LP},
703 { PCI_VDEVICE(INTEL, 0x9c43), LPC_LPT_LP},
704 { PCI_VDEVICE(INTEL, 0x9c44), LPC_LPT_LP},
705 { PCI_VDEVICE(INTEL, 0x9c45), LPC_LPT_LP},
706 { PCI_VDEVICE(INTEL, 0x9c46), LPC_LPT_LP},
707 { PCI_VDEVICE(INTEL, 0x9c47), LPC_LPT_LP},
6e6680e3
JR		 708 { PCI_VDEVICE(INTEL, 0x8d40), LPC_WBG},
709 { PCI_VDEVICE(INTEL, 0x8d41), LPC_WBG},
710 { PCI_VDEVICE(INTEL, 0x8d42), LPC_WBG},
711 { PCI_VDEVICE(INTEL, 0x8d43), LPC_WBG},
712 { PCI_VDEVICE(INTEL, 0x8d44), LPC_WBG},
713 { PCI_VDEVICE(INTEL, 0x8d45), LPC_WBG},
714 { PCI_VDEVICE(INTEL, 0x8d46), LPC_WBG},
715 { PCI_VDEVICE(INTEL, 0x8d47), LPC_WBG},
716 { PCI_VDEVICE(INTEL, 0x8d48), LPC_WBG},
717 { PCI_VDEVICE(INTEL, 0x8d49), LPC_WBG},
718 { PCI_VDEVICE(INTEL, 0x8d4a), LPC_WBG},
719 { PCI_VDEVICE(INTEL, 0x8d4b), LPC_WBG},
720 { PCI_VDEVICE(INTEL, 0x8d4c), LPC_WBG},
721 { PCI_VDEVICE(INTEL, 0x8d4d), LPC_WBG},
722 { PCI_VDEVICE(INTEL, 0x8d4e), LPC_WBG},
723 { PCI_VDEVICE(INTEL, 0x8d4f), LPC_WBG},
724 { PCI_VDEVICE(INTEL, 0x8d50), LPC_WBG},
725 { PCI_VDEVICE(INTEL, 0x8d51), LPC_WBG},
726 { PCI_VDEVICE(INTEL, 0x8d52), LPC_WBG},
727 { PCI_VDEVICE(INTEL, 0x8d53), LPC_WBG},
728 { PCI_VDEVICE(INTEL, 0x8d54), LPC_WBG},
729 { PCI_VDEVICE(INTEL, 0x8d55), LPC_WBG},
730 { PCI_VDEVICE(INTEL, 0x8d56), LPC_WBG},
731 { PCI_VDEVICE(INTEL, 0x8d57), LPC_WBG},
732 { PCI_VDEVICE(INTEL, 0x8d58), LPC_WBG},
733 { PCI_VDEVICE(INTEL, 0x8d59), LPC_WBG},
734 { PCI_VDEVICE(INTEL, 0x8d5a), LPC_WBG},
735 { PCI_VDEVICE(INTEL, 0x8d5b), LPC_WBG},
736 { PCI_VDEVICE(INTEL, 0x8d5c), LPC_WBG},
737 { PCI_VDEVICE(INTEL, 0x8d5d), LPC_WBG},
738 { PCI_VDEVICE(INTEL, 0x8d5e), LPC_WBG},
739 { PCI_VDEVICE(INTEL, 0x8d5f), LPC_WBG},
8477128f
JR		 740 { PCI_VDEVICE(INTEL, 0x1f38), LPC_AVN},
741 { PCI_VDEVICE(INTEL, 0x1f39), LPC_AVN},
742 { PCI_VDEVICE(INTEL, 0x1f3a), LPC_AVN},
743 { PCI_VDEVICE(INTEL, 0x1f3b), LPC_AVN},
6111ec70 744 { PCI_VDEVICE(INTEL, 0x0f1c), LPC_BAYTRAIL},
283aae8a 745 { PCI_VDEVICE(INTEL, 0x2390), LPC_COLETO},
5e90169c
JR		 746 { PCI_VDEVICE(INTEL, 0x9cc1), LPC_WPT_LP},
747 { PCI_VDEVICE(INTEL, 0x9cc2), LPC_WPT_LP},
748 { PCI_VDEVICE(INTEL, 0x9cc3), LPC_WPT_LP},
749 { PCI_VDEVICE(INTEL, 0x9cc5), LPC_WPT_LP},
750 { PCI_VDEVICE(INTEL, 0x9cc6), LPC_WPT_LP},
751 { PCI_VDEVICE(INTEL, 0x9cc7), LPC_WPT_LP},
752 { PCI_VDEVICE(INTEL, 0x9cc9), LPC_WPT_LP},
ff0c9da0 753 { PCI_VDEVICE(INTEL, 0x229c), LPC_BRASWELL},
4630b130
AS		 754 { 0, }, /* End of list */
755};
756MODULE_DEVICE_TABLE(pci, lpc_ich_ids);
757
758static void lpc_ich_restore_config_space(struct pci_dev *dev)
759{
01560f6b
AS		 760 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
761
eb71d4de
PT		 762 if (priv->abase_save >= 0) {
763 pci_write_config_byte(dev, priv->abase, priv->abase_save);
764 priv->abase_save = -1;
765 }
766
767 if (priv->actrl_pbase_save >= 0) {
768 pci_write_config_byte(dev, priv->actrl_pbase,
769 priv->actrl_pbase_save);
770 priv->actrl_pbase_save = -1;
4630b130
AS		 771 }
772
429b941a
PT		 773 if (priv->gctrl_save >= 0) {
774 pci_write_config_byte(dev, priv->gctrl, priv->gctrl_save);
775 priv->gctrl_save = -1;
4630b130
AS		 776 }
777}
778
f791be49 779static void lpc_ich_enable_acpi_space(struct pci_dev *dev)
4630b130 780{
01560f6b 781 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
4630b130
AS		 782 u8 reg_save;
783
eb71d4de
PT		 784 switch (lpc_chipset_info[priv->chipset].iTCO_version) {
785 case 3:
786 /*
787 * Some chipsets (eg Avoton) enable the ACPI space in the
788 * ACPI BASE register.
789 */
790 pci_read_config_byte(dev, priv->abase, &reg_save);
791 pci_write_config_byte(dev, priv->abase, reg_save | 0x2);
792 priv->abase_save = reg_save;
793 break;
794 default:
795 /*
796 * Most chipsets enable the ACPI space in the ACPI control
797 * register.
798 */
799 pci_read_config_byte(dev, priv->actrl_pbase, &reg_save);
800 pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x80);
801 priv->actrl_pbase_save = reg_save;
802 break;
803 }
4630b130
AS		 804}
805
f791be49 806static void lpc_ich_enable_gpio_space(struct pci_dev *dev)
4630b130 807{
01560f6b 808 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
4630b130
AS		 809 u8 reg_save;
810
429b941a
PT		 811 pci_read_config_byte(dev, priv->gctrl, &reg_save);
812 pci_write_config_byte(dev, priv->gctrl, reg_save | 0x10);
813 priv->gctrl_save = reg_save;
4630b130
AS		 814}
815
eb71d4de
PT		 816static void lpc_ich_enable_pmc_space(struct pci_dev *dev)
817{
818 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
819 u8 reg_save;
820
821 pci_read_config_byte(dev, priv->actrl_pbase, &reg_save);
822 pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x2);
823
824 priv->actrl_pbase_save = reg_save;
825}
826
01560f6b 827static void lpc_ich_finalize_cell(struct pci_dev *dev, struct mfd_cell *cell)
4630b130 828{
01560f6b
AS		 829 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
830
831 cell->platform_data = &lpc_chipset_info[priv->chipset];
4630b130
AS		 832 cell->pdata_size = sizeof(struct lpc_ich_info);
833}
834
4f600ada
JD		 835/*
836 * We don't check for resource conflict globally. There are 2 or 3 independent
837 * GPIO groups and it's enough to have access to one of these to instantiate
838 * the device.
839 */
f791be49 840static int lpc_ich_check_conflict_gpio(struct resource *res)
4f600ada
JD		 841{
842 int ret;
843 u8 use_gpio = 0;
844
845 if (resource_size(res) >= 0x50 &&
846 !acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3"))
847 use_gpio |= 1 << 2;
848
849 if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2"))
850 use_gpio |= 1 << 1;
851
852 ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1");
853 if (!ret)
854 use_gpio |= 1 << 0;
855
856 return use_gpio ? use_gpio : ret;
857}
858
01560f6b 859static int lpc_ich_init_gpio(struct pci_dev *dev)
4630b130 860{
01560f6b 861 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
4630b130
AS		 862 u32 base_addr_cfg;
863 u32 base_addr;
864 int ret;
865 bool acpi_conflict = false;
866 struct resource *res;
867
868 /* Setup power management base register */
429b941a 869 pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
4630b130
AS		 870 base_addr = base_addr_cfg & 0x0000ff80;
871 if (!base_addr) {
0c418844 872 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
4630b130
AS		 873 lpc_ich_cells[LPC_GPIO].num_resources--;
874 goto gpe0_done;
875 }
876
877 res = &gpio_ich_res[ICH_RES_GPE0];
878 res->start = base_addr + ACPIBASE_GPE_OFF;
879 res->end = base_addr + ACPIBASE_GPE_END;
880 ret = acpi_check_resource_conflict(res);
881 if (ret) {
882 /*
883 * This isn't fatal for the GPIO, but we have to make sure that
884 * the platform_device subsystem doesn't see this resource
885 * or it will register an invalid region.
886 */
887 lpc_ich_cells[LPC_GPIO].num_resources--;
888 acpi_conflict = true;
889 } else {
890 lpc_ich_enable_acpi_space(dev);
891 }
892
893gpe0_done:
894 /* Setup GPIO base register */
429b941a 895 pci_read_config_dword(dev, priv->gbase, &base_addr_cfg);
4630b130
AS		 896 base_addr = base_addr_cfg & 0x0000ff80;
897 if (!base_addr) {
0c418844 898 dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n");
4630b130
AS		 899 ret = -ENODEV;
900 goto gpio_done;
901 }
902
903 /* Older devices provide fewer GPIO and have a smaller resource size. */
904 res = &gpio_ich_res[ICH_RES_GPIO];
905 res->start = base_addr;
01560f6b 906 switch (lpc_chipset_info[priv->chipset].gpio_version) {
4630b130
AS		 907 case ICH_V5_GPIO:
908 case ICH_V10CORP_GPIO:
909 res->end = res->start + 128 - 1;
910 break;
911 default:
912 res->end = res->start + 64 - 1;
913 break;
914 }
915
4f600ada
JD		 916 ret = lpc_ich_check_conflict_gpio(res);
917 if (ret < 0) {
4630b130
AS		 918 /* this isn't necessarily fatal for the GPIO */
919 acpi_conflict = true;
920 goto gpio_done;
921 }
01560f6b 922 lpc_chipset_info[priv->chipset].use_gpio = ret;
4630b130
AS		 923 lpc_ich_enable_gpio_space(dev);
924
01560f6b 925 lpc_ich_finalize_cell(dev, &lpc_ich_cells[LPC_GPIO]);
4630b130 926 ret = mfd_add_devices(&dev->dev, -1, &lpc_ich_cells[LPC_GPIO],
55692af5 927 1, NULL, 0, NULL);
4630b130
AS		 928
929gpio_done:
930 if (acpi_conflict)
931 pr_warn("Resource conflict(s) found affecting %s\n",
932 lpc_ich_cells[LPC_GPIO].name);
933 return ret;
934}
935
01560f6b 936static int lpc_ich_init_wdt(struct pci_dev *dev)
887c8ec7 937{
01560f6b 938 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
887c8ec7
AS		 939 u32 base_addr_cfg;
940 u32 base_addr;
941 int ret;
887c8ec7
AS		 942 struct resource *res;
943
944 /* Setup power management base register */
429b941a 945 pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
887c8ec7
AS		 946 base_addr = base_addr_cfg & 0x0000ff80;
947 if (!base_addr) {
0c418844 948 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
887c8ec7
AS		 949 ret = -ENODEV;
950 goto wdt_done;
951 }
952
953 res = wdt_io_res(ICH_RES_IO_TCO);
954 res->start = base_addr + ACPIBASE_TCO_OFF;
955 res->end = base_addr + ACPIBASE_TCO_END;
887c8ec7
AS		 956
957 res = wdt_io_res(ICH_RES_IO_SMI);
958 res->start = base_addr + ACPIBASE_SMI_OFF;
959 res->end = base_addr + ACPIBASE_SMI_END;
092369ef 960
887c8ec7
AS		 961 lpc_ich_enable_acpi_space(dev);
962
963 /*
eb71d4de 964 * iTCO v2:
887c8ec7
AS		 965 * Get the Memory-Mapped GCS register. To get access to it
966 * we have to read RCBA from PCI Config space 0xf0 and use
967 * it as base. GCS = RCBA + ICH6_GCS(0x3410).
eb71d4de
PT		 968 *
969 * iTCO v3:
970 * Get the Power Management Configuration register. To get access
971 * to it we have to read the PMC BASE from config space and address
972 * the register at offset 0x8.
887c8ec7 973 */
01560f6b 974 if (lpc_chipset_info[priv->chipset].iTCO_version == 1) {
e294bc91
PH		 975 /* Don't register iomem for TCO ver 1 */
976 lpc_ich_cells[LPC_WDT].num_resources--;
eb71d4de 977 } else if (lpc_chipset_info[priv->chipset].iTCO_version == 2) {
887c8ec7
AS		 978 pci_read_config_dword(dev, RCBABASE, &base_addr_cfg);
979 base_addr = base_addr_cfg & 0xffffc000;
980 if (!(base_addr_cfg & 1)) {
0c418844
PB		 981 dev_notice(&dev->dev, "RCBA is disabled by "
982 "hardware/BIOS, device disabled\n");
887c8ec7
AS		 983 ret = -ENODEV;
984 goto wdt_done;
985 }
eb71d4de 986 res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
887c8ec7
AS		 987 res->start = base_addr + ACPIBASE_GCS_OFF;
988 res->end = base_addr + ACPIBASE_GCS_END;
eb71d4de
PT		 989 } else if (lpc_chipset_info[priv->chipset].iTCO_version == 3) {
990 lpc_ich_enable_pmc_space(dev);
991 pci_read_config_dword(dev, ACPICTRL_PMCBASE, &base_addr_cfg);
992 base_addr = base_addr_cfg & 0xfffffe00;
993
994 res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
995 res->start = base_addr + ACPIBASE_PMC_OFF;
996 res->end = base_addr + ACPIBASE_PMC_END;
887c8ec7
AS		 997 }
998
01560f6b 999 lpc_ich_finalize_cell(dev, &lpc_ich_cells[LPC_WDT]);
887c8ec7 1000 ret = mfd_add_devices(&dev->dev, -1, &lpc_ich_cells[LPC_WDT],
55692af5 1001 1, NULL, 0, NULL);
887c8ec7
AS		 1002
1003wdt_done:
887c8ec7
AS		 1004 return ret;
1005}
1006
f791be49 1007static int lpc_ich_probe(struct pci_dev *dev,
4630b130
AS		 1008 const struct pci_device_id *id)
1009{
01560f6b 1010 struct lpc_ich_priv *priv;
4630b130
AS		 1011 int ret;
1012 bool cell_added = false;
1013
ff7109fa
AS		 1014 priv = devm_kzalloc(&dev->dev,
1015 sizeof(struct lpc_ich_priv), GFP_KERNEL);
01560f6b
AS		 1016 if (!priv)
1017 return -ENOMEM;
1018
1019 priv->chipset = id->driver_data;
01560f6b 1020
eb71d4de
PT		 1021 priv->actrl_pbase_save = -1;
1022 priv->abase_save = -1;
1023
429b941a 1024 priv->abase = ACPIBASE;
eb71d4de 1025 priv->actrl_pbase = ACPICTRL_PMCBASE;
429b941a
PT		 1026
1027 priv->gctrl_save = -1;
01560f6b 1028 if (priv->chipset <= LPC_ICH5) {
429b941a
PT		 1029 priv->gbase = GPIOBASE_ICH0;
1030 priv->gctrl = GPIOCTRL_ICH0;
01560f6b 1031 } else {
429b941a
PT		 1032 priv->gbase = GPIOBASE_ICH6;
1033 priv->gctrl = GPIOCTRL_ICH6;
01560f6b
AS		 1034 }
1035
1036 pci_set_drvdata(dev, priv);
1037
f0776b8c
PT		 1038 if (lpc_chipset_info[priv->chipset].iTCO_version) {
1039 ret = lpc_ich_init_wdt(dev);
1040 if (!ret)
1041 cell_added = true;
1042 }
887c8ec7 1043
f0776b8c
PT		 1044 if (lpc_chipset_info[priv->chipset].gpio_version) {
1045 ret = lpc_ich_init_gpio(dev);
1046 if (!ret)
1047 cell_added = true;
1048 }
4630b130
AS		 1049
1050 /*
1051 * We only care if at least one or none of the cells registered
1052 * successfully.
1053 */
1054 if (!cell_added) {
0c418844 1055 dev_warn(&dev->dev, "No MFD cells added\n");
4630b130
AS		 1056 lpc_ich_restore_config_space(dev);
1057 return -ENODEV;
1058 }
1059
1060 return 0;
1061}
1062
4740f73f 1063static void lpc_ich_remove(struct pci_dev *dev)
4630b130
AS		 1064{
1065 mfd_remove_devices(&dev->dev);
1066 lpc_ich_restore_config_space(dev);
1067}
1068
1069static struct pci_driver lpc_ich_driver = {
1070 .name = "lpc_ich",
1071 .id_table = lpc_ich_ids,
1072 .probe = lpc_ich_probe,
84449216 1073 .remove = lpc_ich_remove,
4630b130
AS		 1074};
1075
b4d0fe9c 1076module_pci_driver(lpc_ich_driver);
4630b130
AS		 1077
1078MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>");
1079MODULE_DESCRIPTION("LPC interface for Intel ICH");
1080MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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