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4630b130 AS |
1 | /* |
2 | * lpc_ich.c - LPC interface for Intel ICH | |
3 | * | |
4 | * LPC bridge function of the Intel ICH contains many other | |
5 | * functional units, such as Interrupt controllers, Timers, | |
6 | * Power Management, System Management, GPIO, RTC, and LPC | |
7 | * Configuration Registers. | |
8 | * | |
9 | * This driver is derived from lpc_sch. | |
10 | ||
11 | * Copyright (c) 2011 Extreme Engineering Solution, Inc. | |
12 | * Author: Aaron Sierra <asierra@xes-inc.com> | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License 2 as published | |
16 | * by the Free Software Foundation. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; see the file COPYING. If not, write to | |
25 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
26 | * | |
27 | * This driver supports the following I/O Controller hubs: | |
28 | * (See the intel documentation on http://developer.intel.com.) | |
29 | * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO) | |
30 | * document number 290687-002, 298242-027: 82801BA (ICH2) | |
31 | * document number 290733-003, 290739-013: 82801CA (ICH3-S) | |
32 | * document number 290716-001, 290718-007: 82801CAM (ICH3-M) | |
33 | * document number 290744-001, 290745-025: 82801DB (ICH4) | |
34 | * document number 252337-001, 252663-008: 82801DBM (ICH4-M) | |
35 | * document number 273599-001, 273645-002: 82801E (C-ICH) | |
36 | * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R) | |
37 | * document number 300641-004, 300884-013: 6300ESB | |
38 | * document number 301473-002, 301474-026: 82801F (ICH6) | |
39 | * document number 313082-001, 313075-006: 631xESB, 632xESB | |
40 | * document number 307013-003, 307014-024: 82801G (ICH7) | |
41 | * document number 322896-001, 322897-001: NM10 | |
42 | * document number 313056-003, 313057-017: 82801H (ICH8) | |
43 | * document number 316972-004, 316973-012: 82801I (ICH9) | |
44 | * document number 319973-002, 319974-002: 82801J (ICH10) | |
45 | * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH) | |
46 | * document number 320066-003, 320257-008: EP80597 (IICH) | |
47 | * document number 324645-001, 324646-001: Cougar Point (CPT) | |
48 | * document number TBD : Patsburg (PBG) | |
49 | * document number TBD : DH89xxCC | |
50 | * document number TBD : Panther Point | |
51 | * document number TBD : Lynx Point | |
7fb9c1a4 | 52 | * document number TBD : Lynx Point-LP |
6e6680e3 | 53 | * document number TBD : Wellsburg |
8477128f | 54 | * document number TBD : Avoton SoC |
283aae8a | 55 | * document number TBD : Coleto Creek |
5e90169c | 56 | * document number TBD : Wildcat Point-LP |
4630b130 AS |
57 | */ |
58 | ||
59 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
60 | ||
4630b130 AS |
61 | #include <linux/kernel.h> |
62 | #include <linux/module.h> | |
63 | #include <linux/errno.h> | |
64 | #include <linux/acpi.h> | |
65 | #include <linux/pci.h> | |
66 | #include <linux/mfd/core.h> | |
67 | #include <linux/mfd/lpc_ich.h> | |
68 | ||
69 | #define ACPIBASE 0x40 | |
70 | #define ACPIBASE_GPE_OFF 0x28 | |
71 | #define ACPIBASE_GPE_END 0x2f | |
887c8ec7 AS |
72 | #define ACPIBASE_SMI_OFF 0x30 |
73 | #define ACPIBASE_SMI_END 0x33 | |
eb71d4de PT |
74 | #define ACPIBASE_PMC_OFF 0x08 |
75 | #define ACPIBASE_PMC_END 0x0c | |
887c8ec7 AS |
76 | #define ACPIBASE_TCO_OFF 0x60 |
77 | #define ACPIBASE_TCO_END 0x7f | |
eb71d4de | 78 | #define ACPICTRL_PMCBASE 0x44 |
4630b130 | 79 | |
887c8ec7 AS |
80 | #define ACPIBASE_GCS_OFF 0x3410 |
81 | #define ACPIBASE_GCS_END 0x3414 | |
82 | ||
01560f6b AS |
83 | #define GPIOBASE_ICH0 0x58 |
84 | #define GPIOCTRL_ICH0 0x5C | |
85 | #define GPIOBASE_ICH6 0x48 | |
86 | #define GPIOCTRL_ICH6 0x4C | |
4630b130 | 87 | |
887c8ec7 AS |
88 | #define RCBABASE 0xf0 |
89 | ||
90 | #define wdt_io_res(i) wdt_res(0, i) | |
91 | #define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i) | |
92 | #define wdt_res(b, i) (&wdt_ich_res[(b) + (i)]) | |
93 | ||
01560f6b AS |
94 | struct lpc_ich_priv { |
95 | int chipset; | |
429b941a PT |
96 | |
97 | int abase; /* ACPI base */ | |
eb71d4de | 98 | int actrl_pbase; /* ACPI control or PMC base */ |
429b941a PT |
99 | int gbase; /* GPIO base */ |
100 | int gctrl; /* GPIO control */ | |
101 | ||
eb71d4de PT |
102 | int abase_save; /* Cached ACPI base value */ |
103 | int actrl_pbase_save; /* Cached ACPI control or PMC base value */ | |
429b941a | 104 | int gctrl_save; /* Cached GPIO control value */ |
01560f6b | 105 | }; |
4630b130 | 106 | |
887c8ec7 AS |
107 | static struct resource wdt_ich_res[] = { |
108 | /* ACPI - TCO */ | |
109 | { | |
110 | .flags = IORESOURCE_IO, | |
111 | }, | |
112 | /* ACPI - SMI */ | |
113 | { | |
114 | .flags = IORESOURCE_IO, | |
115 | }, | |
eb71d4de | 116 | /* GCS or PMC */ |
887c8ec7 AS |
117 | { |
118 | .flags = IORESOURCE_MEM, | |
119 | }, | |
120 | }; | |
121 | ||
4630b130 AS |
122 | static struct resource gpio_ich_res[] = { |
123 | /* GPIO */ | |
124 | { | |
125 | .flags = IORESOURCE_IO, | |
126 | }, | |
127 | /* ACPI - GPE0 */ | |
128 | { | |
129 | .flags = IORESOURCE_IO, | |
130 | }, | |
131 | }; | |
132 | ||
133 | enum lpc_cells { | |
887c8ec7 AS |
134 | LPC_WDT = 0, |
135 | LPC_GPIO, | |
4630b130 AS |
136 | }; |
137 | ||
138 | static struct mfd_cell lpc_ich_cells[] = { | |
887c8ec7 AS |
139 | [LPC_WDT] = { |
140 | .name = "iTCO_wdt", | |
141 | .num_resources = ARRAY_SIZE(wdt_ich_res), | |
142 | .resources = wdt_ich_res, | |
143 | .ignore_resource_conflicts = true, | |
144 | }, | |
4630b130 AS |
145 | [LPC_GPIO] = { |
146 | .name = "gpio_ich", | |
147 | .num_resources = ARRAY_SIZE(gpio_ich_res), | |
148 | .resources = gpio_ich_res, | |
149 | .ignore_resource_conflicts = true, | |
150 | }, | |
151 | }; | |
152 | ||
153 | /* chipset related info */ | |
154 | enum lpc_chipsets { | |
155 | LPC_ICH = 0, /* ICH */ | |
156 | LPC_ICH0, /* ICH0 */ | |
157 | LPC_ICH2, /* ICH2 */ | |
158 | LPC_ICH2M, /* ICH2-M */ | |
159 | LPC_ICH3, /* ICH3-S */ | |
160 | LPC_ICH3M, /* ICH3-M */ | |
161 | LPC_ICH4, /* ICH4 */ | |
162 | LPC_ICH4M, /* ICH4-M */ | |
163 | LPC_CICH, /* C-ICH */ | |
164 | LPC_ICH5, /* ICH5 & ICH5R */ | |
165 | LPC_6300ESB, /* 6300ESB */ | |
166 | LPC_ICH6, /* ICH6 & ICH6R */ | |
167 | LPC_ICH6M, /* ICH6-M */ | |
168 | LPC_ICH6W, /* ICH6W & ICH6RW */ | |
169 | LPC_631XESB, /* 631xESB/632xESB */ | |
170 | LPC_ICH7, /* ICH7 & ICH7R */ | |
171 | LPC_ICH7DH, /* ICH7DH */ | |
172 | LPC_ICH7M, /* ICH7-M & ICH7-U */ | |
173 | LPC_ICH7MDH, /* ICH7-M DH */ | |
174 | LPC_NM10, /* NM10 */ | |
175 | LPC_ICH8, /* ICH8 & ICH8R */ | |
176 | LPC_ICH8DH, /* ICH8DH */ | |
177 | LPC_ICH8DO, /* ICH8DO */ | |
178 | LPC_ICH8M, /* ICH8M */ | |
179 | LPC_ICH8ME, /* ICH8M-E */ | |
180 | LPC_ICH9, /* ICH9 */ | |
181 | LPC_ICH9R, /* ICH9R */ | |
182 | LPC_ICH9DH, /* ICH9DH */ | |
183 | LPC_ICH9DO, /* ICH9DO */ | |
184 | LPC_ICH9M, /* ICH9M */ | |
185 | LPC_ICH9ME, /* ICH9M-E */ | |
186 | LPC_ICH10, /* ICH10 */ | |
187 | LPC_ICH10R, /* ICH10R */ | |
188 | LPC_ICH10D, /* ICH10D */ | |
189 | LPC_ICH10DO, /* ICH10DO */ | |
190 | LPC_PCH, /* PCH Desktop Full Featured */ | |
191 | LPC_PCHM, /* PCH Mobile Full Featured */ | |
192 | LPC_P55, /* P55 */ | |
193 | LPC_PM55, /* PM55 */ | |
194 | LPC_H55, /* H55 */ | |
195 | LPC_QM57, /* QM57 */ | |
196 | LPC_H57, /* H57 */ | |
197 | LPC_HM55, /* HM55 */ | |
198 | LPC_Q57, /* Q57 */ | |
199 | LPC_HM57, /* HM57 */ | |
200 | LPC_PCHMSFF, /* PCH Mobile SFF Full Featured */ | |
201 | LPC_QS57, /* QS57 */ | |
202 | LPC_3400, /* 3400 */ | |
203 | LPC_3420, /* 3420 */ | |
204 | LPC_3450, /* 3450 */ | |
205 | LPC_EP80579, /* EP80579 */ | |
206 | LPC_CPT, /* Cougar Point */ | |
207 | LPC_CPTD, /* Cougar Point Desktop */ | |
208 | LPC_CPTM, /* Cougar Point Mobile */ | |
209 | LPC_PBG, /* Patsburg */ | |
210 | LPC_DH89XXCC, /* DH89xxCC */ | |
211 | LPC_PPT, /* Panther Point */ | |
212 | LPC_LPT, /* Lynx Point */ | |
7fb9c1a4 | 213 | LPC_LPT_LP, /* Lynx Point-LP */ |
6e6680e3 | 214 | LPC_WBG, /* Wellsburg */ |
8477128f | 215 | LPC_AVN, /* Avoton SoC */ |
283aae8a | 216 | LPC_COLETO, /* Coleto Creek */ |
5e90169c | 217 | LPC_WPT_LP, /* Wildcat Point-LP */ |
4630b130 AS |
218 | }; |
219 | ||
a1ca138f | 220 | static struct lpc_ich_info lpc_chipset_info[] = { |
4630b130 AS |
221 | [LPC_ICH] = { |
222 | .name = "ICH", | |
887c8ec7 | 223 | .iTCO_version = 1, |
4630b130 AS |
224 | }, |
225 | [LPC_ICH0] = { | |
226 | .name = "ICH0", | |
887c8ec7 | 227 | .iTCO_version = 1, |
4630b130 AS |
228 | }, |
229 | [LPC_ICH2] = { | |
230 | .name = "ICH2", | |
887c8ec7 | 231 | .iTCO_version = 1, |
4630b130 AS |
232 | }, |
233 | [LPC_ICH2M] = { | |
234 | .name = "ICH2-M", | |
887c8ec7 | 235 | .iTCO_version = 1, |
4630b130 AS |
236 | }, |
237 | [LPC_ICH3] = { | |
238 | .name = "ICH3-S", | |
887c8ec7 | 239 | .iTCO_version = 1, |
4630b130 AS |
240 | }, |
241 | [LPC_ICH3M] = { | |
242 | .name = "ICH3-M", | |
887c8ec7 | 243 | .iTCO_version = 1, |
4630b130 AS |
244 | }, |
245 | [LPC_ICH4] = { | |
246 | .name = "ICH4", | |
887c8ec7 | 247 | .iTCO_version = 1, |
4630b130 AS |
248 | }, |
249 | [LPC_ICH4M] = { | |
250 | .name = "ICH4-M", | |
887c8ec7 | 251 | .iTCO_version = 1, |
4630b130 AS |
252 | }, |
253 | [LPC_CICH] = { | |
254 | .name = "C-ICH", | |
887c8ec7 | 255 | .iTCO_version = 1, |
4630b130 AS |
256 | }, |
257 | [LPC_ICH5] = { | |
258 | .name = "ICH5 or ICH5R", | |
887c8ec7 | 259 | .iTCO_version = 1, |
4630b130 AS |
260 | }, |
261 | [LPC_6300ESB] = { | |
262 | .name = "6300ESB", | |
887c8ec7 | 263 | .iTCO_version = 1, |
4630b130 AS |
264 | }, |
265 | [LPC_ICH6] = { | |
266 | .name = "ICH6 or ICH6R", | |
887c8ec7 | 267 | .iTCO_version = 2, |
4630b130 AS |
268 | .gpio_version = ICH_V6_GPIO, |
269 | }, | |
270 | [LPC_ICH6M] = { | |
271 | .name = "ICH6-M", | |
887c8ec7 | 272 | .iTCO_version = 2, |
4630b130 AS |
273 | .gpio_version = ICH_V6_GPIO, |
274 | }, | |
275 | [LPC_ICH6W] = { | |
276 | .name = "ICH6W or ICH6RW", | |
887c8ec7 | 277 | .iTCO_version = 2, |
4630b130 AS |
278 | .gpio_version = ICH_V6_GPIO, |
279 | }, | |
280 | [LPC_631XESB] = { | |
281 | .name = "631xESB/632xESB", | |
887c8ec7 | 282 | .iTCO_version = 2, |
4630b130 AS |
283 | .gpio_version = ICH_V6_GPIO, |
284 | }, | |
285 | [LPC_ICH7] = { | |
286 | .name = "ICH7 or ICH7R", | |
887c8ec7 | 287 | .iTCO_version = 2, |
4630b130 AS |
288 | .gpio_version = ICH_V7_GPIO, |
289 | }, | |
290 | [LPC_ICH7DH] = { | |
291 | .name = "ICH7DH", | |
887c8ec7 | 292 | .iTCO_version = 2, |
4630b130 AS |
293 | .gpio_version = ICH_V7_GPIO, |
294 | }, | |
295 | [LPC_ICH7M] = { | |
296 | .name = "ICH7-M or ICH7-U", | |
887c8ec7 | 297 | .iTCO_version = 2, |
4630b130 AS |
298 | .gpio_version = ICH_V7_GPIO, |
299 | }, | |
300 | [LPC_ICH7MDH] = { | |
301 | .name = "ICH7-M DH", | |
887c8ec7 | 302 | .iTCO_version = 2, |
4630b130 AS |
303 | .gpio_version = ICH_V7_GPIO, |
304 | }, | |
305 | [LPC_NM10] = { | |
306 | .name = "NM10", | |
887c8ec7 | 307 | .iTCO_version = 2, |
4630b130 AS |
308 | }, |
309 | [LPC_ICH8] = { | |
310 | .name = "ICH8 or ICH8R", | |
887c8ec7 | 311 | .iTCO_version = 2, |
4630b130 AS |
312 | .gpio_version = ICH_V7_GPIO, |
313 | }, | |
314 | [LPC_ICH8DH] = { | |
315 | .name = "ICH8DH", | |
887c8ec7 | 316 | .iTCO_version = 2, |
4630b130 AS |
317 | .gpio_version = ICH_V7_GPIO, |
318 | }, | |
319 | [LPC_ICH8DO] = { | |
320 | .name = "ICH8DO", | |
887c8ec7 | 321 | .iTCO_version = 2, |
4630b130 AS |
322 | .gpio_version = ICH_V7_GPIO, |
323 | }, | |
324 | [LPC_ICH8M] = { | |
325 | .name = "ICH8M", | |
887c8ec7 | 326 | .iTCO_version = 2, |
4630b130 AS |
327 | .gpio_version = ICH_V7_GPIO, |
328 | }, | |
329 | [LPC_ICH8ME] = { | |
330 | .name = "ICH8M-E", | |
887c8ec7 | 331 | .iTCO_version = 2, |
4630b130 AS |
332 | .gpio_version = ICH_V7_GPIO, |
333 | }, | |
334 | [LPC_ICH9] = { | |
335 | .name = "ICH9", | |
887c8ec7 | 336 | .iTCO_version = 2, |
4630b130 AS |
337 | .gpio_version = ICH_V9_GPIO, |
338 | }, | |
339 | [LPC_ICH9R] = { | |
340 | .name = "ICH9R", | |
887c8ec7 | 341 | .iTCO_version = 2, |
4630b130 AS |
342 | .gpio_version = ICH_V9_GPIO, |
343 | }, | |
344 | [LPC_ICH9DH] = { | |
345 | .name = "ICH9DH", | |
887c8ec7 | 346 | .iTCO_version = 2, |
4630b130 AS |
347 | .gpio_version = ICH_V9_GPIO, |
348 | }, | |
349 | [LPC_ICH9DO] = { | |
350 | .name = "ICH9DO", | |
887c8ec7 | 351 | .iTCO_version = 2, |
4630b130 AS |
352 | .gpio_version = ICH_V9_GPIO, |
353 | }, | |
354 | [LPC_ICH9M] = { | |
355 | .name = "ICH9M", | |
887c8ec7 | 356 | .iTCO_version = 2, |
4630b130 AS |
357 | .gpio_version = ICH_V9_GPIO, |
358 | }, | |
359 | [LPC_ICH9ME] = { | |
360 | .name = "ICH9M-E", | |
887c8ec7 | 361 | .iTCO_version = 2, |
4630b130 AS |
362 | .gpio_version = ICH_V9_GPIO, |
363 | }, | |
364 | [LPC_ICH10] = { | |
365 | .name = "ICH10", | |
887c8ec7 | 366 | .iTCO_version = 2, |
4630b130 AS |
367 | .gpio_version = ICH_V10CONS_GPIO, |
368 | }, | |
369 | [LPC_ICH10R] = { | |
370 | .name = "ICH10R", | |
887c8ec7 | 371 | .iTCO_version = 2, |
4630b130 AS |
372 | .gpio_version = ICH_V10CONS_GPIO, |
373 | }, | |
374 | [LPC_ICH10D] = { | |
375 | .name = "ICH10D", | |
887c8ec7 | 376 | .iTCO_version = 2, |
4630b130 AS |
377 | .gpio_version = ICH_V10CORP_GPIO, |
378 | }, | |
379 | [LPC_ICH10DO] = { | |
380 | .name = "ICH10DO", | |
887c8ec7 | 381 | .iTCO_version = 2, |
4630b130 AS |
382 | .gpio_version = ICH_V10CORP_GPIO, |
383 | }, | |
384 | [LPC_PCH] = { | |
385 | .name = "PCH Desktop Full Featured", | |
887c8ec7 | 386 | .iTCO_version = 2, |
4630b130 AS |
387 | .gpio_version = ICH_V5_GPIO, |
388 | }, | |
389 | [LPC_PCHM] = { | |
390 | .name = "PCH Mobile Full Featured", | |
887c8ec7 | 391 | .iTCO_version = 2, |
4630b130 AS |
392 | .gpio_version = ICH_V5_GPIO, |
393 | }, | |
394 | [LPC_P55] = { | |
395 | .name = "P55", | |
887c8ec7 | 396 | .iTCO_version = 2, |
4630b130 AS |
397 | .gpio_version = ICH_V5_GPIO, |
398 | }, | |
399 | [LPC_PM55] = { | |
400 | .name = "PM55", | |
887c8ec7 | 401 | .iTCO_version = 2, |
4630b130 AS |
402 | .gpio_version = ICH_V5_GPIO, |
403 | }, | |
404 | [LPC_H55] = { | |
405 | .name = "H55", | |
887c8ec7 | 406 | .iTCO_version = 2, |
4630b130 AS |
407 | .gpio_version = ICH_V5_GPIO, |
408 | }, | |
409 | [LPC_QM57] = { | |
410 | .name = "QM57", | |
887c8ec7 | 411 | .iTCO_version = 2, |
4630b130 AS |
412 | .gpio_version = ICH_V5_GPIO, |
413 | }, | |
414 | [LPC_H57] = { | |
415 | .name = "H57", | |
887c8ec7 | 416 | .iTCO_version = 2, |
4630b130 AS |
417 | .gpio_version = ICH_V5_GPIO, |
418 | }, | |
419 | [LPC_HM55] = { | |
420 | .name = "HM55", | |
887c8ec7 | 421 | .iTCO_version = 2, |
4630b130 AS |
422 | .gpio_version = ICH_V5_GPIO, |
423 | }, | |
424 | [LPC_Q57] = { | |
425 | .name = "Q57", | |
887c8ec7 | 426 | .iTCO_version = 2, |
4630b130 AS |
427 | .gpio_version = ICH_V5_GPIO, |
428 | }, | |
429 | [LPC_HM57] = { | |
430 | .name = "HM57", | |
887c8ec7 | 431 | .iTCO_version = 2, |
4630b130 AS |
432 | .gpio_version = ICH_V5_GPIO, |
433 | }, | |
434 | [LPC_PCHMSFF] = { | |
435 | .name = "PCH Mobile SFF Full Featured", | |
887c8ec7 | 436 | .iTCO_version = 2, |
4630b130 AS |
437 | .gpio_version = ICH_V5_GPIO, |
438 | }, | |
439 | [LPC_QS57] = { | |
440 | .name = "QS57", | |
887c8ec7 | 441 | .iTCO_version = 2, |
4630b130 AS |
442 | .gpio_version = ICH_V5_GPIO, |
443 | }, | |
444 | [LPC_3400] = { | |
445 | .name = "3400", | |
887c8ec7 | 446 | .iTCO_version = 2, |
4630b130 AS |
447 | .gpio_version = ICH_V5_GPIO, |
448 | }, | |
449 | [LPC_3420] = { | |
450 | .name = "3420", | |
887c8ec7 | 451 | .iTCO_version = 2, |
4630b130 AS |
452 | .gpio_version = ICH_V5_GPIO, |
453 | }, | |
454 | [LPC_3450] = { | |
455 | .name = "3450", | |
887c8ec7 | 456 | .iTCO_version = 2, |
4630b130 AS |
457 | .gpio_version = ICH_V5_GPIO, |
458 | }, | |
459 | [LPC_EP80579] = { | |
460 | .name = "EP80579", | |
887c8ec7 | 461 | .iTCO_version = 2, |
4630b130 AS |
462 | }, |
463 | [LPC_CPT] = { | |
464 | .name = "Cougar Point", | |
887c8ec7 | 465 | .iTCO_version = 2, |
4630b130 AS |
466 | .gpio_version = ICH_V5_GPIO, |
467 | }, | |
468 | [LPC_CPTD] = { | |
469 | .name = "Cougar Point Desktop", | |
887c8ec7 | 470 | .iTCO_version = 2, |
4630b130 AS |
471 | .gpio_version = ICH_V5_GPIO, |
472 | }, | |
473 | [LPC_CPTM] = { | |
474 | .name = "Cougar Point Mobile", | |
887c8ec7 | 475 | .iTCO_version = 2, |
4630b130 AS |
476 | .gpio_version = ICH_V5_GPIO, |
477 | }, | |
478 | [LPC_PBG] = { | |
479 | .name = "Patsburg", | |
887c8ec7 | 480 | .iTCO_version = 2, |
4630b130 AS |
481 | }, |
482 | [LPC_DH89XXCC] = { | |
483 | .name = "DH89xxCC", | |
887c8ec7 | 484 | .iTCO_version = 2, |
4630b130 AS |
485 | }, |
486 | [LPC_PPT] = { | |
487 | .name = "Panther Point", | |
887c8ec7 | 488 | .iTCO_version = 2, |
4630b130 AS |
489 | }, |
490 | [LPC_LPT] = { | |
491 | .name = "Lynx Point", | |
887c8ec7 | 492 | .iTCO_version = 2, |
4630b130 | 493 | }, |
7fb9c1a4 JR |
494 | [LPC_LPT_LP] = { |
495 | .name = "Lynx Point_LP", | |
496 | .iTCO_version = 2, | |
497 | }, | |
6e6680e3 JR |
498 | [LPC_WBG] = { |
499 | .name = "Wellsburg", | |
500 | .iTCO_version = 2, | |
501 | }, | |
8477128f JR |
502 | [LPC_AVN] = { |
503 | .name = "Avoton SoC", | |
c48cf598 | 504 | .iTCO_version = 3, |
facd9939 | 505 | .gpio_version = AVOTON_GPIO, |
8477128f | 506 | }, |
283aae8a SH |
507 | [LPC_COLETO] = { |
508 | .name = "Coleto Creek", | |
509 | .iTCO_version = 2, | |
510 | }, | |
5e90169c | 511 | [LPC_WPT_LP] = { |
a8822df9 | 512 | .name = "Wildcat Point_LP", |
5e90169c JR |
513 | .iTCO_version = 2, |
514 | }, | |
4630b130 AS |
515 | }; |
516 | ||
517 | /* | |
518 | * This data only exists for exporting the supported PCI ids | |
519 | * via MODULE_DEVICE_TABLE. We do not actually register a | |
520 | * pci_driver, because the I/O Controller Hub has also other | |
521 | * functions that probably will be registered by other drivers. | |
522 | */ | |
36fcd06c | 523 | static const struct pci_device_id lpc_ich_ids[] = { |
4630b130 AS |
524 | { PCI_VDEVICE(INTEL, 0x2410), LPC_ICH}, |
525 | { PCI_VDEVICE(INTEL, 0x2420), LPC_ICH0}, | |
526 | { PCI_VDEVICE(INTEL, 0x2440), LPC_ICH2}, | |
527 | { PCI_VDEVICE(INTEL, 0x244c), LPC_ICH2M}, | |
528 | { PCI_VDEVICE(INTEL, 0x2480), LPC_ICH3}, | |
529 | { PCI_VDEVICE(INTEL, 0x248c), LPC_ICH3M}, | |
530 | { PCI_VDEVICE(INTEL, 0x24c0), LPC_ICH4}, | |
531 | { PCI_VDEVICE(INTEL, 0x24cc), LPC_ICH4M}, | |
532 | { PCI_VDEVICE(INTEL, 0x2450), LPC_CICH}, | |
533 | { PCI_VDEVICE(INTEL, 0x24d0), LPC_ICH5}, | |
534 | { PCI_VDEVICE(INTEL, 0x25a1), LPC_6300ESB}, | |
535 | { PCI_VDEVICE(INTEL, 0x2640), LPC_ICH6}, | |
536 | { PCI_VDEVICE(INTEL, 0x2641), LPC_ICH6M}, | |
537 | { PCI_VDEVICE(INTEL, 0x2642), LPC_ICH6W}, | |
538 | { PCI_VDEVICE(INTEL, 0x2670), LPC_631XESB}, | |
539 | { PCI_VDEVICE(INTEL, 0x2671), LPC_631XESB}, | |
540 | { PCI_VDEVICE(INTEL, 0x2672), LPC_631XESB}, | |
541 | { PCI_VDEVICE(INTEL, 0x2673), LPC_631XESB}, | |
542 | { PCI_VDEVICE(INTEL, 0x2674), LPC_631XESB}, | |
543 | { PCI_VDEVICE(INTEL, 0x2675), LPC_631XESB}, | |
544 | { PCI_VDEVICE(INTEL, 0x2676), LPC_631XESB}, | |
545 | { PCI_VDEVICE(INTEL, 0x2677), LPC_631XESB}, | |
546 | { PCI_VDEVICE(INTEL, 0x2678), LPC_631XESB}, | |
547 | { PCI_VDEVICE(INTEL, 0x2679), LPC_631XESB}, | |
548 | { PCI_VDEVICE(INTEL, 0x267a), LPC_631XESB}, | |
549 | { PCI_VDEVICE(INTEL, 0x267b), LPC_631XESB}, | |
550 | { PCI_VDEVICE(INTEL, 0x267c), LPC_631XESB}, | |
551 | { PCI_VDEVICE(INTEL, 0x267d), LPC_631XESB}, | |
552 | { PCI_VDEVICE(INTEL, 0x267e), LPC_631XESB}, | |
553 | { PCI_VDEVICE(INTEL, 0x267f), LPC_631XESB}, | |
554 | { PCI_VDEVICE(INTEL, 0x27b8), LPC_ICH7}, | |
555 | { PCI_VDEVICE(INTEL, 0x27b0), LPC_ICH7DH}, | |
556 | { PCI_VDEVICE(INTEL, 0x27b9), LPC_ICH7M}, | |
557 | { PCI_VDEVICE(INTEL, 0x27bd), LPC_ICH7MDH}, | |
558 | { PCI_VDEVICE(INTEL, 0x27bc), LPC_NM10}, | |
559 | { PCI_VDEVICE(INTEL, 0x2810), LPC_ICH8}, | |
560 | { PCI_VDEVICE(INTEL, 0x2812), LPC_ICH8DH}, | |
561 | { PCI_VDEVICE(INTEL, 0x2814), LPC_ICH8DO}, | |
562 | { PCI_VDEVICE(INTEL, 0x2815), LPC_ICH8M}, | |
563 | { PCI_VDEVICE(INTEL, 0x2811), LPC_ICH8ME}, | |
564 | { PCI_VDEVICE(INTEL, 0x2918), LPC_ICH9}, | |
565 | { PCI_VDEVICE(INTEL, 0x2916), LPC_ICH9R}, | |
566 | { PCI_VDEVICE(INTEL, 0x2912), LPC_ICH9DH}, | |
567 | { PCI_VDEVICE(INTEL, 0x2914), LPC_ICH9DO}, | |
568 | { PCI_VDEVICE(INTEL, 0x2919), LPC_ICH9M}, | |
569 | { PCI_VDEVICE(INTEL, 0x2917), LPC_ICH9ME}, | |
570 | { PCI_VDEVICE(INTEL, 0x3a18), LPC_ICH10}, | |
571 | { PCI_VDEVICE(INTEL, 0x3a16), LPC_ICH10R}, | |
572 | { PCI_VDEVICE(INTEL, 0x3a1a), LPC_ICH10D}, | |
573 | { PCI_VDEVICE(INTEL, 0x3a14), LPC_ICH10DO}, | |
574 | { PCI_VDEVICE(INTEL, 0x3b00), LPC_PCH}, | |
575 | { PCI_VDEVICE(INTEL, 0x3b01), LPC_PCHM}, | |
576 | { PCI_VDEVICE(INTEL, 0x3b02), LPC_P55}, | |
577 | { PCI_VDEVICE(INTEL, 0x3b03), LPC_PM55}, | |
578 | { PCI_VDEVICE(INTEL, 0x3b06), LPC_H55}, | |
579 | { PCI_VDEVICE(INTEL, 0x3b07), LPC_QM57}, | |
580 | { PCI_VDEVICE(INTEL, 0x3b08), LPC_H57}, | |
581 | { PCI_VDEVICE(INTEL, 0x3b09), LPC_HM55}, | |
582 | { PCI_VDEVICE(INTEL, 0x3b0a), LPC_Q57}, | |
583 | { PCI_VDEVICE(INTEL, 0x3b0b), LPC_HM57}, | |
584 | { PCI_VDEVICE(INTEL, 0x3b0d), LPC_PCHMSFF}, | |
585 | { PCI_VDEVICE(INTEL, 0x3b0f), LPC_QS57}, | |
586 | { PCI_VDEVICE(INTEL, 0x3b12), LPC_3400}, | |
587 | { PCI_VDEVICE(INTEL, 0x3b14), LPC_3420}, | |
588 | { PCI_VDEVICE(INTEL, 0x3b16), LPC_3450}, | |
589 | { PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579}, | |
590 | { PCI_VDEVICE(INTEL, 0x1c41), LPC_CPT}, | |
591 | { PCI_VDEVICE(INTEL, 0x1c42), LPC_CPTD}, | |
592 | { PCI_VDEVICE(INTEL, 0x1c43), LPC_CPTM}, | |
593 | { PCI_VDEVICE(INTEL, 0x1c44), LPC_CPT}, | |
594 | { PCI_VDEVICE(INTEL, 0x1c45), LPC_CPT}, | |
595 | { PCI_VDEVICE(INTEL, 0x1c46), LPC_CPT}, | |
596 | { PCI_VDEVICE(INTEL, 0x1c47), LPC_CPT}, | |
597 | { PCI_VDEVICE(INTEL, 0x1c48), LPC_CPT}, | |
598 | { PCI_VDEVICE(INTEL, 0x1c49), LPC_CPT}, | |
599 | { PCI_VDEVICE(INTEL, 0x1c4a), LPC_CPT}, | |
600 | { PCI_VDEVICE(INTEL, 0x1c4b), LPC_CPT}, | |
601 | { PCI_VDEVICE(INTEL, 0x1c4c), LPC_CPT}, | |
602 | { PCI_VDEVICE(INTEL, 0x1c4d), LPC_CPT}, | |
603 | { PCI_VDEVICE(INTEL, 0x1c4e), LPC_CPT}, | |
604 | { PCI_VDEVICE(INTEL, 0x1c4f), LPC_CPT}, | |
605 | { PCI_VDEVICE(INTEL, 0x1c50), LPC_CPT}, | |
606 | { PCI_VDEVICE(INTEL, 0x1c51), LPC_CPT}, | |
607 | { PCI_VDEVICE(INTEL, 0x1c52), LPC_CPT}, | |
608 | { PCI_VDEVICE(INTEL, 0x1c53), LPC_CPT}, | |
609 | { PCI_VDEVICE(INTEL, 0x1c54), LPC_CPT}, | |
610 | { PCI_VDEVICE(INTEL, 0x1c55), LPC_CPT}, | |
611 | { PCI_VDEVICE(INTEL, 0x1c56), LPC_CPT}, | |
612 | { PCI_VDEVICE(INTEL, 0x1c57), LPC_CPT}, | |
613 | { PCI_VDEVICE(INTEL, 0x1c58), LPC_CPT}, | |
614 | { PCI_VDEVICE(INTEL, 0x1c59), LPC_CPT}, | |
615 | { PCI_VDEVICE(INTEL, 0x1c5a), LPC_CPT}, | |
616 | { PCI_VDEVICE(INTEL, 0x1c5b), LPC_CPT}, | |
617 | { PCI_VDEVICE(INTEL, 0x1c5c), LPC_CPT}, | |
618 | { PCI_VDEVICE(INTEL, 0x1c5d), LPC_CPT}, | |
619 | { PCI_VDEVICE(INTEL, 0x1c5e), LPC_CPT}, | |
620 | { PCI_VDEVICE(INTEL, 0x1c5f), LPC_CPT}, | |
621 | { PCI_VDEVICE(INTEL, 0x1d40), LPC_PBG}, | |
622 | { PCI_VDEVICE(INTEL, 0x1d41), LPC_PBG}, | |
623 | { PCI_VDEVICE(INTEL, 0x2310), LPC_DH89XXCC}, | |
624 | { PCI_VDEVICE(INTEL, 0x1e40), LPC_PPT}, | |
625 | { PCI_VDEVICE(INTEL, 0x1e41), LPC_PPT}, | |
626 | { PCI_VDEVICE(INTEL, 0x1e42), LPC_PPT}, | |
627 | { PCI_VDEVICE(INTEL, 0x1e43), LPC_PPT}, | |
628 | { PCI_VDEVICE(INTEL, 0x1e44), LPC_PPT}, | |
629 | { PCI_VDEVICE(INTEL, 0x1e45), LPC_PPT}, | |
630 | { PCI_VDEVICE(INTEL, 0x1e46), LPC_PPT}, | |
631 | { PCI_VDEVICE(INTEL, 0x1e47), LPC_PPT}, | |
632 | { PCI_VDEVICE(INTEL, 0x1e48), LPC_PPT}, | |
633 | { PCI_VDEVICE(INTEL, 0x1e49), LPC_PPT}, | |
634 | { PCI_VDEVICE(INTEL, 0x1e4a), LPC_PPT}, | |
635 | { PCI_VDEVICE(INTEL, 0x1e4b), LPC_PPT}, | |
636 | { PCI_VDEVICE(INTEL, 0x1e4c), LPC_PPT}, | |
637 | { PCI_VDEVICE(INTEL, 0x1e4d), LPC_PPT}, | |
638 | { PCI_VDEVICE(INTEL, 0x1e4e), LPC_PPT}, | |
639 | { PCI_VDEVICE(INTEL, 0x1e4f), LPC_PPT}, | |
640 | { PCI_VDEVICE(INTEL, 0x1e50), LPC_PPT}, | |
641 | { PCI_VDEVICE(INTEL, 0x1e51), LPC_PPT}, | |
642 | { PCI_VDEVICE(INTEL, 0x1e52), LPC_PPT}, | |
643 | { PCI_VDEVICE(INTEL, 0x1e53), LPC_PPT}, | |
644 | { PCI_VDEVICE(INTEL, 0x1e54), LPC_PPT}, | |
645 | { PCI_VDEVICE(INTEL, 0x1e55), LPC_PPT}, | |
646 | { PCI_VDEVICE(INTEL, 0x1e56), LPC_PPT}, | |
647 | { PCI_VDEVICE(INTEL, 0x1e57), LPC_PPT}, | |
648 | { PCI_VDEVICE(INTEL, 0x1e58), LPC_PPT}, | |
649 | { PCI_VDEVICE(INTEL, 0x1e59), LPC_PPT}, | |
650 | { PCI_VDEVICE(INTEL, 0x1e5a), LPC_PPT}, | |
651 | { PCI_VDEVICE(INTEL, 0x1e5b), LPC_PPT}, | |
652 | { PCI_VDEVICE(INTEL, 0x1e5c), LPC_PPT}, | |
653 | { PCI_VDEVICE(INTEL, 0x1e5d), LPC_PPT}, | |
654 | { PCI_VDEVICE(INTEL, 0x1e5e), LPC_PPT}, | |
655 | { PCI_VDEVICE(INTEL, 0x1e5f), LPC_PPT}, | |
656 | { PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT}, | |
657 | { PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT}, | |
658 | { PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT}, | |
659 | { PCI_VDEVICE(INTEL, 0x8c43), LPC_LPT}, | |
660 | { PCI_VDEVICE(INTEL, 0x8c44), LPC_LPT}, | |
661 | { PCI_VDEVICE(INTEL, 0x8c45), LPC_LPT}, | |
662 | { PCI_VDEVICE(INTEL, 0x8c46), LPC_LPT}, | |
663 | { PCI_VDEVICE(INTEL, 0x8c47), LPC_LPT}, | |
664 | { PCI_VDEVICE(INTEL, 0x8c48), LPC_LPT}, | |
665 | { PCI_VDEVICE(INTEL, 0x8c49), LPC_LPT}, | |
666 | { PCI_VDEVICE(INTEL, 0x8c4a), LPC_LPT}, | |
667 | { PCI_VDEVICE(INTEL, 0x8c4b), LPC_LPT}, | |
668 | { PCI_VDEVICE(INTEL, 0x8c4c), LPC_LPT}, | |
669 | { PCI_VDEVICE(INTEL, 0x8c4d), LPC_LPT}, | |
670 | { PCI_VDEVICE(INTEL, 0x8c4e), LPC_LPT}, | |
671 | { PCI_VDEVICE(INTEL, 0x8c4f), LPC_LPT}, | |
672 | { PCI_VDEVICE(INTEL, 0x8c50), LPC_LPT}, | |
673 | { PCI_VDEVICE(INTEL, 0x8c51), LPC_LPT}, | |
674 | { PCI_VDEVICE(INTEL, 0x8c52), LPC_LPT}, | |
675 | { PCI_VDEVICE(INTEL, 0x8c53), LPC_LPT}, | |
676 | { PCI_VDEVICE(INTEL, 0x8c54), LPC_LPT}, | |
677 | { PCI_VDEVICE(INTEL, 0x8c55), LPC_LPT}, | |
678 | { PCI_VDEVICE(INTEL, 0x8c56), LPC_LPT}, | |
679 | { PCI_VDEVICE(INTEL, 0x8c57), LPC_LPT}, | |
680 | { PCI_VDEVICE(INTEL, 0x8c58), LPC_LPT}, | |
681 | { PCI_VDEVICE(INTEL, 0x8c59), LPC_LPT}, | |
682 | { PCI_VDEVICE(INTEL, 0x8c5a), LPC_LPT}, | |
683 | { PCI_VDEVICE(INTEL, 0x8c5b), LPC_LPT}, | |
684 | { PCI_VDEVICE(INTEL, 0x8c5c), LPC_LPT}, | |
685 | { PCI_VDEVICE(INTEL, 0x8c5d), LPC_LPT}, | |
686 | { PCI_VDEVICE(INTEL, 0x8c5e), LPC_LPT}, | |
687 | { PCI_VDEVICE(INTEL, 0x8c5f), LPC_LPT}, | |
7fb9c1a4 JR |
688 | { PCI_VDEVICE(INTEL, 0x9c40), LPC_LPT_LP}, |
689 | { PCI_VDEVICE(INTEL, 0x9c41), LPC_LPT_LP}, | |
690 | { PCI_VDEVICE(INTEL, 0x9c42), LPC_LPT_LP}, | |
691 | { PCI_VDEVICE(INTEL, 0x9c43), LPC_LPT_LP}, | |
692 | { PCI_VDEVICE(INTEL, 0x9c44), LPC_LPT_LP}, | |
693 | { PCI_VDEVICE(INTEL, 0x9c45), LPC_LPT_LP}, | |
694 | { PCI_VDEVICE(INTEL, 0x9c46), LPC_LPT_LP}, | |
695 | { PCI_VDEVICE(INTEL, 0x9c47), LPC_LPT_LP}, | |
6e6680e3 JR |
696 | { PCI_VDEVICE(INTEL, 0x8d40), LPC_WBG}, |
697 | { PCI_VDEVICE(INTEL, 0x8d41), LPC_WBG}, | |
698 | { PCI_VDEVICE(INTEL, 0x8d42), LPC_WBG}, | |
699 | { PCI_VDEVICE(INTEL, 0x8d43), LPC_WBG}, | |
700 | { PCI_VDEVICE(INTEL, 0x8d44), LPC_WBG}, | |
701 | { PCI_VDEVICE(INTEL, 0x8d45), LPC_WBG}, | |
702 | { PCI_VDEVICE(INTEL, 0x8d46), LPC_WBG}, | |
703 | { PCI_VDEVICE(INTEL, 0x8d47), LPC_WBG}, | |
704 | { PCI_VDEVICE(INTEL, 0x8d48), LPC_WBG}, | |
705 | { PCI_VDEVICE(INTEL, 0x8d49), LPC_WBG}, | |
706 | { PCI_VDEVICE(INTEL, 0x8d4a), LPC_WBG}, | |
707 | { PCI_VDEVICE(INTEL, 0x8d4b), LPC_WBG}, | |
708 | { PCI_VDEVICE(INTEL, 0x8d4c), LPC_WBG}, | |
709 | { PCI_VDEVICE(INTEL, 0x8d4d), LPC_WBG}, | |
710 | { PCI_VDEVICE(INTEL, 0x8d4e), LPC_WBG}, | |
711 | { PCI_VDEVICE(INTEL, 0x8d4f), LPC_WBG}, | |
712 | { PCI_VDEVICE(INTEL, 0x8d50), LPC_WBG}, | |
713 | { PCI_VDEVICE(INTEL, 0x8d51), LPC_WBG}, | |
714 | { PCI_VDEVICE(INTEL, 0x8d52), LPC_WBG}, | |
715 | { PCI_VDEVICE(INTEL, 0x8d53), LPC_WBG}, | |
716 | { PCI_VDEVICE(INTEL, 0x8d54), LPC_WBG}, | |
717 | { PCI_VDEVICE(INTEL, 0x8d55), LPC_WBG}, | |
718 | { PCI_VDEVICE(INTEL, 0x8d56), LPC_WBG}, | |
719 | { PCI_VDEVICE(INTEL, 0x8d57), LPC_WBG}, | |
720 | { PCI_VDEVICE(INTEL, 0x8d58), LPC_WBG}, | |
721 | { PCI_VDEVICE(INTEL, 0x8d59), LPC_WBG}, | |
722 | { PCI_VDEVICE(INTEL, 0x8d5a), LPC_WBG}, | |
723 | { PCI_VDEVICE(INTEL, 0x8d5b), LPC_WBG}, | |
724 | { PCI_VDEVICE(INTEL, 0x8d5c), LPC_WBG}, | |
725 | { PCI_VDEVICE(INTEL, 0x8d5d), LPC_WBG}, | |
726 | { PCI_VDEVICE(INTEL, 0x8d5e), LPC_WBG}, | |
727 | { PCI_VDEVICE(INTEL, 0x8d5f), LPC_WBG}, | |
8477128f JR |
728 | { PCI_VDEVICE(INTEL, 0x1f38), LPC_AVN}, |
729 | { PCI_VDEVICE(INTEL, 0x1f39), LPC_AVN}, | |
730 | { PCI_VDEVICE(INTEL, 0x1f3a), LPC_AVN}, | |
731 | { PCI_VDEVICE(INTEL, 0x1f3b), LPC_AVN}, | |
283aae8a | 732 | { PCI_VDEVICE(INTEL, 0x2390), LPC_COLETO}, |
5e90169c JR |
733 | { PCI_VDEVICE(INTEL, 0x9cc1), LPC_WPT_LP}, |
734 | { PCI_VDEVICE(INTEL, 0x9cc2), LPC_WPT_LP}, | |
735 | { PCI_VDEVICE(INTEL, 0x9cc3), LPC_WPT_LP}, | |
736 | { PCI_VDEVICE(INTEL, 0x9cc5), LPC_WPT_LP}, | |
737 | { PCI_VDEVICE(INTEL, 0x9cc6), LPC_WPT_LP}, | |
738 | { PCI_VDEVICE(INTEL, 0x9cc7), LPC_WPT_LP}, | |
739 | { PCI_VDEVICE(INTEL, 0x9cc9), LPC_WPT_LP}, | |
4630b130 AS |
740 | { 0, }, /* End of list */ |
741 | }; | |
742 | MODULE_DEVICE_TABLE(pci, lpc_ich_ids); | |
743 | ||
744 | static void lpc_ich_restore_config_space(struct pci_dev *dev) | |
745 | { | |
01560f6b AS |
746 | struct lpc_ich_priv *priv = pci_get_drvdata(dev); |
747 | ||
eb71d4de PT |
748 | if (priv->abase_save >= 0) { |
749 | pci_write_config_byte(dev, priv->abase, priv->abase_save); | |
750 | priv->abase_save = -1; | |
751 | } | |
752 | ||
753 | if (priv->actrl_pbase_save >= 0) { | |
754 | pci_write_config_byte(dev, priv->actrl_pbase, | |
755 | priv->actrl_pbase_save); | |
756 | priv->actrl_pbase_save = -1; | |
4630b130 AS |
757 | } |
758 | ||
429b941a PT |
759 | if (priv->gctrl_save >= 0) { |
760 | pci_write_config_byte(dev, priv->gctrl, priv->gctrl_save); | |
761 | priv->gctrl_save = -1; | |
4630b130 AS |
762 | } |
763 | } | |
764 | ||
f791be49 | 765 | static void lpc_ich_enable_acpi_space(struct pci_dev *dev) |
4630b130 | 766 | { |
01560f6b | 767 | struct lpc_ich_priv *priv = pci_get_drvdata(dev); |
4630b130 AS |
768 | u8 reg_save; |
769 | ||
eb71d4de PT |
770 | switch (lpc_chipset_info[priv->chipset].iTCO_version) { |
771 | case 3: | |
772 | /* | |
773 | * Some chipsets (eg Avoton) enable the ACPI space in the | |
774 | * ACPI BASE register. | |
775 | */ | |
776 | pci_read_config_byte(dev, priv->abase, ®_save); | |
777 | pci_write_config_byte(dev, priv->abase, reg_save | 0x2); | |
778 | priv->abase_save = reg_save; | |
779 | break; | |
780 | default: | |
781 | /* | |
782 | * Most chipsets enable the ACPI space in the ACPI control | |
783 | * register. | |
784 | */ | |
785 | pci_read_config_byte(dev, priv->actrl_pbase, ®_save); | |
786 | pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x80); | |
787 | priv->actrl_pbase_save = reg_save; | |
788 | break; | |
789 | } | |
4630b130 AS |
790 | } |
791 | ||
f791be49 | 792 | static void lpc_ich_enable_gpio_space(struct pci_dev *dev) |
4630b130 | 793 | { |
01560f6b | 794 | struct lpc_ich_priv *priv = pci_get_drvdata(dev); |
4630b130 AS |
795 | u8 reg_save; |
796 | ||
429b941a PT |
797 | pci_read_config_byte(dev, priv->gctrl, ®_save); |
798 | pci_write_config_byte(dev, priv->gctrl, reg_save | 0x10); | |
799 | priv->gctrl_save = reg_save; | |
4630b130 AS |
800 | } |
801 | ||
eb71d4de PT |
802 | static void lpc_ich_enable_pmc_space(struct pci_dev *dev) |
803 | { | |
804 | struct lpc_ich_priv *priv = pci_get_drvdata(dev); | |
805 | u8 reg_save; | |
806 | ||
807 | pci_read_config_byte(dev, priv->actrl_pbase, ®_save); | |
808 | pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x2); | |
809 | ||
810 | priv->actrl_pbase_save = reg_save; | |
811 | } | |
812 | ||
01560f6b | 813 | static void lpc_ich_finalize_cell(struct pci_dev *dev, struct mfd_cell *cell) |
4630b130 | 814 | { |
01560f6b AS |
815 | struct lpc_ich_priv *priv = pci_get_drvdata(dev); |
816 | ||
817 | cell->platform_data = &lpc_chipset_info[priv->chipset]; | |
4630b130 AS |
818 | cell->pdata_size = sizeof(struct lpc_ich_info); |
819 | } | |
820 | ||
4f600ada JD |
821 | /* |
822 | * We don't check for resource conflict globally. There are 2 or 3 independent | |
823 | * GPIO groups and it's enough to have access to one of these to instantiate | |
824 | * the device. | |
825 | */ | |
f791be49 | 826 | static int lpc_ich_check_conflict_gpio(struct resource *res) |
4f600ada JD |
827 | { |
828 | int ret; | |
829 | u8 use_gpio = 0; | |
830 | ||
831 | if (resource_size(res) >= 0x50 && | |
832 | !acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3")) | |
833 | use_gpio |= 1 << 2; | |
834 | ||
835 | if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2")) | |
836 | use_gpio |= 1 << 1; | |
837 | ||
838 | ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1"); | |
839 | if (!ret) | |
840 | use_gpio |= 1 << 0; | |
841 | ||
842 | return use_gpio ? use_gpio : ret; | |
843 | } | |
844 | ||
01560f6b | 845 | static int lpc_ich_init_gpio(struct pci_dev *dev) |
4630b130 | 846 | { |
01560f6b | 847 | struct lpc_ich_priv *priv = pci_get_drvdata(dev); |
4630b130 AS |
848 | u32 base_addr_cfg; |
849 | u32 base_addr; | |
850 | int ret; | |
851 | bool acpi_conflict = false; | |
852 | struct resource *res; | |
853 | ||
854 | /* Setup power management base register */ | |
429b941a | 855 | pci_read_config_dword(dev, priv->abase, &base_addr_cfg); |
4630b130 AS |
856 | base_addr = base_addr_cfg & 0x0000ff80; |
857 | if (!base_addr) { | |
0c418844 | 858 | dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n"); |
4630b130 AS |
859 | lpc_ich_cells[LPC_GPIO].num_resources--; |
860 | goto gpe0_done; | |
861 | } | |
862 | ||
863 | res = &gpio_ich_res[ICH_RES_GPE0]; | |
864 | res->start = base_addr + ACPIBASE_GPE_OFF; | |
865 | res->end = base_addr + ACPIBASE_GPE_END; | |
866 | ret = acpi_check_resource_conflict(res); | |
867 | if (ret) { | |
868 | /* | |
869 | * This isn't fatal for the GPIO, but we have to make sure that | |
870 | * the platform_device subsystem doesn't see this resource | |
871 | * or it will register an invalid region. | |
872 | */ | |
873 | lpc_ich_cells[LPC_GPIO].num_resources--; | |
874 | acpi_conflict = true; | |
875 | } else { | |
876 | lpc_ich_enable_acpi_space(dev); | |
877 | } | |
878 | ||
879 | gpe0_done: | |
880 | /* Setup GPIO base register */ | |
429b941a | 881 | pci_read_config_dword(dev, priv->gbase, &base_addr_cfg); |
4630b130 AS |
882 | base_addr = base_addr_cfg & 0x0000ff80; |
883 | if (!base_addr) { | |
0c418844 | 884 | dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n"); |
4630b130 AS |
885 | ret = -ENODEV; |
886 | goto gpio_done; | |
887 | } | |
888 | ||
889 | /* Older devices provide fewer GPIO and have a smaller resource size. */ | |
890 | res = &gpio_ich_res[ICH_RES_GPIO]; | |
891 | res->start = base_addr; | |
01560f6b | 892 | switch (lpc_chipset_info[priv->chipset].gpio_version) { |
4630b130 AS |
893 | case ICH_V5_GPIO: |
894 | case ICH_V10CORP_GPIO: | |
895 | res->end = res->start + 128 - 1; | |
896 | break; | |
897 | default: | |
898 | res->end = res->start + 64 - 1; | |
899 | break; | |
900 | } | |
901 | ||
4f600ada JD |
902 | ret = lpc_ich_check_conflict_gpio(res); |
903 | if (ret < 0) { | |
4630b130 AS |
904 | /* this isn't necessarily fatal for the GPIO */ |
905 | acpi_conflict = true; | |
906 | goto gpio_done; | |
907 | } | |
01560f6b | 908 | lpc_chipset_info[priv->chipset].use_gpio = ret; |
4630b130 AS |
909 | lpc_ich_enable_gpio_space(dev); |
910 | ||
01560f6b | 911 | lpc_ich_finalize_cell(dev, &lpc_ich_cells[LPC_GPIO]); |
4630b130 | 912 | ret = mfd_add_devices(&dev->dev, -1, &lpc_ich_cells[LPC_GPIO], |
55692af5 | 913 | 1, NULL, 0, NULL); |
4630b130 AS |
914 | |
915 | gpio_done: | |
916 | if (acpi_conflict) | |
917 | pr_warn("Resource conflict(s) found affecting %s\n", | |
918 | lpc_ich_cells[LPC_GPIO].name); | |
919 | return ret; | |
920 | } | |
921 | ||
01560f6b | 922 | static int lpc_ich_init_wdt(struct pci_dev *dev) |
887c8ec7 | 923 | { |
01560f6b | 924 | struct lpc_ich_priv *priv = pci_get_drvdata(dev); |
887c8ec7 AS |
925 | u32 base_addr_cfg; |
926 | u32 base_addr; | |
927 | int ret; | |
887c8ec7 AS |
928 | struct resource *res; |
929 | ||
930 | /* Setup power management base register */ | |
429b941a | 931 | pci_read_config_dword(dev, priv->abase, &base_addr_cfg); |
887c8ec7 AS |
932 | base_addr = base_addr_cfg & 0x0000ff80; |
933 | if (!base_addr) { | |
0c418844 | 934 | dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n"); |
887c8ec7 AS |
935 | ret = -ENODEV; |
936 | goto wdt_done; | |
937 | } | |
938 | ||
939 | res = wdt_io_res(ICH_RES_IO_TCO); | |
940 | res->start = base_addr + ACPIBASE_TCO_OFF; | |
941 | res->end = base_addr + ACPIBASE_TCO_END; | |
887c8ec7 AS |
942 | |
943 | res = wdt_io_res(ICH_RES_IO_SMI); | |
944 | res->start = base_addr + ACPIBASE_SMI_OFF; | |
945 | res->end = base_addr + ACPIBASE_SMI_END; | |
092369ef | 946 | |
887c8ec7 AS |
947 | lpc_ich_enable_acpi_space(dev); |
948 | ||
949 | /* | |
eb71d4de | 950 | * iTCO v2: |
887c8ec7 AS |
951 | * Get the Memory-Mapped GCS register. To get access to it |
952 | * we have to read RCBA from PCI Config space 0xf0 and use | |
953 | * it as base. GCS = RCBA + ICH6_GCS(0x3410). | |
eb71d4de PT |
954 | * |
955 | * iTCO v3: | |
956 | * Get the Power Management Configuration register. To get access | |
957 | * to it we have to read the PMC BASE from config space and address | |
958 | * the register at offset 0x8. | |
887c8ec7 | 959 | */ |
01560f6b | 960 | if (lpc_chipset_info[priv->chipset].iTCO_version == 1) { |
e294bc91 PH |
961 | /* Don't register iomem for TCO ver 1 */ |
962 | lpc_ich_cells[LPC_WDT].num_resources--; | |
eb71d4de | 963 | } else if (lpc_chipset_info[priv->chipset].iTCO_version == 2) { |
887c8ec7 AS |
964 | pci_read_config_dword(dev, RCBABASE, &base_addr_cfg); |
965 | base_addr = base_addr_cfg & 0xffffc000; | |
966 | if (!(base_addr_cfg & 1)) { | |
0c418844 PB |
967 | dev_notice(&dev->dev, "RCBA is disabled by " |
968 | "hardware/BIOS, device disabled\n"); | |
887c8ec7 AS |
969 | ret = -ENODEV; |
970 | goto wdt_done; | |
971 | } | |
eb71d4de | 972 | res = wdt_mem_res(ICH_RES_MEM_GCS_PMC); |
887c8ec7 AS |
973 | res->start = base_addr + ACPIBASE_GCS_OFF; |
974 | res->end = base_addr + ACPIBASE_GCS_END; | |
eb71d4de PT |
975 | } else if (lpc_chipset_info[priv->chipset].iTCO_version == 3) { |
976 | lpc_ich_enable_pmc_space(dev); | |
977 | pci_read_config_dword(dev, ACPICTRL_PMCBASE, &base_addr_cfg); | |
978 | base_addr = base_addr_cfg & 0xfffffe00; | |
979 | ||
980 | res = wdt_mem_res(ICH_RES_MEM_GCS_PMC); | |
981 | res->start = base_addr + ACPIBASE_PMC_OFF; | |
982 | res->end = base_addr + ACPIBASE_PMC_END; | |
887c8ec7 AS |
983 | } |
984 | ||
01560f6b | 985 | lpc_ich_finalize_cell(dev, &lpc_ich_cells[LPC_WDT]); |
887c8ec7 | 986 | ret = mfd_add_devices(&dev->dev, -1, &lpc_ich_cells[LPC_WDT], |
55692af5 | 987 | 1, NULL, 0, NULL); |
887c8ec7 AS |
988 | |
989 | wdt_done: | |
887c8ec7 AS |
990 | return ret; |
991 | } | |
992 | ||
f791be49 | 993 | static int lpc_ich_probe(struct pci_dev *dev, |
4630b130 AS |
994 | const struct pci_device_id *id) |
995 | { | |
01560f6b | 996 | struct lpc_ich_priv *priv; |
4630b130 AS |
997 | int ret; |
998 | bool cell_added = false; | |
999 | ||
ff7109fa AS |
1000 | priv = devm_kzalloc(&dev->dev, |
1001 | sizeof(struct lpc_ich_priv), GFP_KERNEL); | |
01560f6b AS |
1002 | if (!priv) |
1003 | return -ENOMEM; | |
1004 | ||
1005 | priv->chipset = id->driver_data; | |
01560f6b | 1006 | |
eb71d4de PT |
1007 | priv->actrl_pbase_save = -1; |
1008 | priv->abase_save = -1; | |
1009 | ||
429b941a | 1010 | priv->abase = ACPIBASE; |
eb71d4de | 1011 | priv->actrl_pbase = ACPICTRL_PMCBASE; |
429b941a PT |
1012 | |
1013 | priv->gctrl_save = -1; | |
01560f6b | 1014 | if (priv->chipset <= LPC_ICH5) { |
429b941a PT |
1015 | priv->gbase = GPIOBASE_ICH0; |
1016 | priv->gctrl = GPIOCTRL_ICH0; | |
01560f6b | 1017 | } else { |
429b941a PT |
1018 | priv->gbase = GPIOBASE_ICH6; |
1019 | priv->gctrl = GPIOCTRL_ICH6; | |
01560f6b AS |
1020 | } |
1021 | ||
1022 | pci_set_drvdata(dev, priv); | |
1023 | ||
f0776b8c PT |
1024 | if (lpc_chipset_info[priv->chipset].iTCO_version) { |
1025 | ret = lpc_ich_init_wdt(dev); | |
1026 | if (!ret) | |
1027 | cell_added = true; | |
1028 | } | |
887c8ec7 | 1029 | |
f0776b8c PT |
1030 | if (lpc_chipset_info[priv->chipset].gpio_version) { |
1031 | ret = lpc_ich_init_gpio(dev); | |
1032 | if (!ret) | |
1033 | cell_added = true; | |
1034 | } | |
4630b130 AS |
1035 | |
1036 | /* | |
1037 | * We only care if at least one or none of the cells registered | |
1038 | * successfully. | |
1039 | */ | |
1040 | if (!cell_added) { | |
0c418844 | 1041 | dev_warn(&dev->dev, "No MFD cells added\n"); |
4630b130 AS |
1042 | lpc_ich_restore_config_space(dev); |
1043 | return -ENODEV; | |
1044 | } | |
1045 | ||
1046 | return 0; | |
1047 | } | |
1048 | ||
4740f73f | 1049 | static void lpc_ich_remove(struct pci_dev *dev) |
4630b130 AS |
1050 | { |
1051 | mfd_remove_devices(&dev->dev); | |
1052 | lpc_ich_restore_config_space(dev); | |
1053 | } | |
1054 | ||
1055 | static struct pci_driver lpc_ich_driver = { | |
1056 | .name = "lpc_ich", | |
1057 | .id_table = lpc_ich_ids, | |
1058 | .probe = lpc_ich_probe, | |
84449216 | 1059 | .remove = lpc_ich_remove, |
4630b130 AS |
1060 | }; |
1061 | ||
b4d0fe9c | 1062 | module_pci_driver(lpc_ich_driver); |
4630b130 AS |
1063 | |
1064 | MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>"); | |
1065 | MODULE_DESCRIPTION("LPC interface for Intel ICH"); | |
1066 | MODULE_LICENSE("GPL"); |