[deliverable/linux.git] / drivers / mfd / max77686-irq.c

/*
 * max77686-irq.c - Interrupt controller support for MAX77686
 *
 * Copyright (C) 2012 Samsung Electronics Co.Ltd
 * Chiwoong Byun <woong.byun@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 * This driver is based on max8997-irq.c
 */

#include <linux/err.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/gpio.h>
#include <linux/mfd/max77686.h>
#include <linux/mfd/max77686-private.h>
#include <linux/irqdomain.h>
#include <linux/regmap.h>

enum {
	MAX77686_DEBUG_IRQ_INFO = 1 << 0,
	MAX77686_DEBUG_IRQ_MASK = 1 << 1,
	MAX77686_DEBUG_IRQ_INT = 1 << 2,
};

static int debug_mask = 0;
module_param(debug_mask, int, 0);
MODULE_PARM_DESC(debug_mask, "Set debug_mask : 0x0=off 0x1=IRQ_INFO  0x2=IRQ_MASK 0x4=IRQ_INI)");

static const u8 max77686_mask_reg[] = {
	[PMIC_INT1] = MAX77686_REG_INT1MSK,
	[PMIC_INT2] = MAX77686_REG_INT2MSK,
	[RTC_INT] = MAX77686_RTC_INTM,
};

static struct regmap *max77686_get_regmap(struct max77686_dev *max77686,
				enum max77686_irq_source src)
{
	switch (src) {
	case PMIC_INT1 ... PMIC_INT2:
		return max77686->regmap;
	case RTC_INT:
		return max77686->rtc_regmap;
	default:
		return ERR_PTR(-EINVAL);
	}
}

struct max77686_irq_data {
	int mask;
	enum max77686_irq_source group;
};

#define DECLARE_IRQ(idx, _group, _mask)		\
	[(idx)] = { .group = (_group), .mask = (_mask) }
static const struct max77686_irq_data max77686_irqs[] = {
	DECLARE_IRQ(MAX77686_PMICIRQ_PWRONF,	PMIC_INT1, 1 << 0),
	DECLARE_IRQ(MAX77686_PMICIRQ_PWRONR,	PMIC_INT1, 1 << 1),
	DECLARE_IRQ(MAX77686_PMICIRQ_JIGONBF,	PMIC_INT1, 1 << 2),
	DECLARE_IRQ(MAX77686_PMICIRQ_JIGONBR,	PMIC_INT1, 1 << 3),
	DECLARE_IRQ(MAX77686_PMICIRQ_ACOKBF,	PMIC_INT1, 1 << 4),
	DECLARE_IRQ(MAX77686_PMICIRQ_ACOKBR,	PMIC_INT1, 1 << 5),
	DECLARE_IRQ(MAX77686_PMICIRQ_ONKEY1S,	PMIC_INT1, 1 << 6),
	DECLARE_IRQ(MAX77686_PMICIRQ_MRSTB,		PMIC_INT1, 1 << 7),
	DECLARE_IRQ(MAX77686_PMICIRQ_140C,		PMIC_INT2, 1 << 0),
	DECLARE_IRQ(MAX77686_PMICIRQ_120C,		PMIC_INT2, 1 << 1),
	DECLARE_IRQ(MAX77686_RTCIRQ_RTC60S,		RTC_INT, 1 << 0),
	DECLARE_IRQ(MAX77686_RTCIRQ_RTCA1,		RTC_INT, 1 << 1),
	DECLARE_IRQ(MAX77686_RTCIRQ_RTCA2,		RTC_INT, 1 << 2),
	DECLARE_IRQ(MAX77686_RTCIRQ_SMPL,		RTC_INT, 1 << 3),
	DECLARE_IRQ(MAX77686_RTCIRQ_RTC1S,		RTC_INT, 1 << 4),
	DECLARE_IRQ(MAX77686_RTCIRQ_WTSR,		RTC_INT, 1 << 5),
};

static void max77686_irq_lock(struct irq_data *data)
{
	struct max77686_dev *max77686 = irq_get_chip_data(data->irq);

	if (debug_mask & MAX77686_DEBUG_IRQ_MASK)
		pr_info("%s\n", __func__);

	mutex_lock(&max77686->irqlock);
}

static void max77686_irq_sync_unlock(struct irq_data *data)
{
	struct max77686_dev *max77686 = irq_get_chip_data(data->irq);
	int i;

	for (i = 0; i < MAX77686_IRQ_GROUP_NR; i++) {
		u8 mask_reg = max77686_mask_reg[i];
		struct regmap *map = max77686_get_regmap(max77686, i);

		if (debug_mask & MAX77686_DEBUG_IRQ_MASK)
			pr_debug("%s: mask_reg[%d]=0x%x, cur=0x%x\n",
			__func__, i, mask_reg, max77686->irq_masks_cur[i]);

		if (mask_reg == MAX77686_REG_INVALID ||
				IS_ERR_OR_NULL(map))
			continue;

		max77686->irq_masks_cache[i] = max77686->irq_masks_cur[i];

		regmap_write(map, max77686_mask_reg[i],
				max77686->irq_masks_cur[i]);
	}

	mutex_unlock(&max77686->irqlock);
}

static const inline struct max77686_irq_data *to_max77686_irq(int irq)
{
	struct irq_data *data = irq_get_irq_data(irq);
	return &max77686_irqs[data->hwirq];
}

static void max77686_irq_mask(struct irq_data *data)
{
	struct max77686_dev *max77686 = irq_get_chip_data(data->irq);
	const struct max77686_irq_data *irq_data = to_max77686_irq(data->irq);

	max77686->irq_masks_cur[irq_data->group] |= irq_data->mask;

	if (debug_mask & MAX77686_DEBUG_IRQ_MASK)
		pr_info("%s: group=%d, cur=0x%x\n",
			__func__, irq_data->group,
			max77686->irq_masks_cur[irq_data->group]);
}

static void max77686_irq_unmask(struct irq_data *data)
{
	struct max77686_dev *max77686 = irq_get_chip_data(data->irq);
	const struct max77686_irq_data *irq_data = to_max77686_irq(data->irq);

	max77686->irq_masks_cur[irq_data->group] &= ~irq_data->mask;

	if (debug_mask & MAX77686_DEBUG_IRQ_MASK)
		pr_info("%s: group=%d, cur=0x%x\n",
			__func__, irq_data->group,
			max77686->irq_masks_cur[irq_data->group]);
}

static struct irq_chip max77686_irq_chip = {
	.name			= "max77686",
	.irq_bus_lock		= max77686_irq_lock,
	.irq_bus_sync_unlock	= max77686_irq_sync_unlock,
	.irq_mask		= max77686_irq_mask,
	.irq_unmask		= max77686_irq_unmask,
};

static irqreturn_t max77686_irq_thread(int irq, void *data)
{
	struct max77686_dev *max77686 = data;
	unsigned int irq_reg[MAX77686_IRQ_GROUP_NR] = {};
	unsigned int irq_src;
	int ret;
	int i, cur_irq;

	ret = regmap_read(max77686->regmap,  MAX77686_REG_INTSRC, &irq_src);
	if (ret < 0) {
		dev_err(max77686->dev, "Failed to read interrupt source: %d\n",
				ret);
		return IRQ_NONE;
	}

	if (debug_mask & MAX77686_DEBUG_IRQ_INT)
		pr_info("%s: irq_src=0x%x\n", __func__, irq_src);

	if (irq_src == MAX77686_IRQSRC_PMIC) {
		ret = regmap_bulk_read(max77686->rtc_regmap,
					 MAX77686_REG_INT1, irq_reg, 2);
		if (ret < 0) {
			dev_err(max77686->dev, "Failed to read interrupt source: %d\n",
					ret);
			return IRQ_NONE;
		}

		if (debug_mask & MAX77686_DEBUG_IRQ_INT)
			pr_info("%s: int1=0x%x, int2=0x%x\n", __func__,
				 irq_reg[PMIC_INT1], irq_reg[PMIC_INT2]);
	}

	if (irq_src & MAX77686_IRQSRC_RTC) {
		ret = regmap_read(max77686->rtc_regmap,
					MAX77686_RTC_INT, &irq_reg[RTC_INT]);
		if (ret < 0) {
			dev_err(max77686->dev, "Failed to read interrupt source: %d\n",
					ret);
			return IRQ_NONE;
		}

		if (debug_mask & MAX77686_DEBUG_IRQ_INT)
			pr_info("%s: rtc int=0x%x\n", __func__,
							 irq_reg[RTC_INT]);

	}

	for (i = 0; i < MAX77686_IRQ_NR; i++) {
		if (irq_reg[max77686_irqs[i].group] & max77686_irqs[i].mask) {
			cur_irq = irq_find_mapping(max77686->irq_domain, i);
			if (cur_irq)
				handle_nested_irq(cur_irq);
		}
	}

	return IRQ_HANDLED;
}

static int max77686_irq_domain_map(struct irq_domain *d, unsigned int irq,
					irq_hw_number_t hw)
{
	struct max77686_dev *max77686 = d->host_data;

	irq_set_chip_data(irq, max77686);
	irq_set_chip_and_handler(irq, &max77686_irq_chip, handle_edge_irq);
	irq_set_nested_thread(irq, 1);
#ifdef CONFIG_ARM
	set_irq_flags(irq, IRQF_VALID);
#else
	irq_set_noprobe(irq);
#endif
	return 0;
}

static struct irq_domain_ops max77686_irq_domain_ops = {
	.map = max77686_irq_domain_map,
};

int max77686_irq_init(struct max77686_dev *max77686)
{
	struct irq_domain *domain;
	int i;
	int ret;
	int val;
	struct regmap *map;

	mutex_init(&max77686->irqlock);

	max77686->irq = gpio_to_irq(max77686->irq_gpio);

	if (debug_mask & MAX77686_DEBUG_IRQ_INT) {
		ret = gpio_request(max77686->irq_gpio, "pmic_irq");
		if (ret < 0) {
			dev_err(max77686->dev,
				"Failed to request gpio %d with ret: %d\n",
				max77686->irq_gpio, ret);
			return IRQ_NONE;
		}

		gpio_direction_input(max77686->irq_gpio);
		val = gpio_get_value(max77686->irq_gpio);
		gpio_free(max77686->irq_gpio);
		pr_info("%s: gpio_irq=%x\n", __func__, val);
	}

	/* Mask individual interrupt sources */
	for (i = 0; i < MAX77686_IRQ_GROUP_NR; i++) {
		max77686->irq_masks_cur[i] = 0xff;
		max77686->irq_masks_cache[i] = 0xff;
		map = max77686_get_regmap(max77686, i);

		if (IS_ERR_OR_NULL(map))
			continue;
		if (max77686_mask_reg[i] == MAX77686_REG_INVALID)
			continue;

		regmap_write(map, max77686_mask_reg[i], 0xff);
	}
	domain = irq_domain_add_linear(NULL, MAX77686_IRQ_NR,
					&max77686_irq_domain_ops, max77686);
	if (!domain) {
		dev_err(max77686->dev, "could not create irq domain\n");
		return -ENODEV;
	}
	max77686->irq_domain = domain;

	ret = request_threaded_irq(max77686->irq, NULL, max77686_irq_thread,
				   IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
				   "max77686-irq", max77686);

	if (ret)
		dev_err(max77686->dev, "Failed to request IRQ %d: %d\n",
			max77686->irq, ret);


	if (debug_mask & MAX77686_DEBUG_IRQ_INFO)
		pr_info("%s-\n", __func__);

	return 0;
}

void max77686_irq_exit(struct max77686_dev *max77686)
{
	if (max77686->irq)
		free_irq(max77686->irq, max77686);
}
Commit	Line	Data
dae8a969 JL	1	/*
	2	* max77686-irq.c - Interrupt controller support for MAX77686
	3	*
	4	* Copyright (C) 2012 Samsung Electronics Co.Ltd
	5	* Chiwoong Byun <woong.byun@samsung.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*
	21	* This driver is based on max8997-irq.c
	22	*/
	23
	24	#include <linux/err.h>
	25	#include <linux/irq.h>
	26	#include <linux/interrupt.h>
	27	#include <linux/gpio.h>
	28	#include <linux/mfd/max77686.h>
	29	#include <linux/mfd/max77686-private.h>
	30	#include <linux/irqdomain.h>
	31	#include <linux/regmap.h>
	32
	33	enum {
	34	MAX77686_DEBUG_IRQ_INFO = 1 << 0,
	35	MAX77686_DEBUG_IRQ_MASK = 1 << 1,
	36	MAX77686_DEBUG_IRQ_INT = 1 << 2,
	37	};
	38
	39	static int debug_mask = 0;
	40	module_param(debug_mask, int, 0);
	41	MODULE_PARM_DESC(debug_mask, "Set debug_mask : 0x0=off 0x1=IRQ_INFO 0x2=IRQ_MASK 0x4=IRQ_INI)");
	42
	43	static const u8 max77686_mask_reg[] = {
	44	[PMIC_INT1] = MAX77686_REG_INT1MSK,
	45	[PMIC_INT2] = MAX77686_REG_INT2MSK,
	46	[RTC_INT] = MAX77686_RTC_INTM,
	47	};
	48
	49	static struct regmap max77686_get_regmap(struct max77686_dev max77686,
	50	enum max77686_irq_source src)
	51	{
	52	switch (src) {
	53	case PMIC_INT1 ... PMIC_INT2:
	54	return max77686->regmap;
	55	case RTC_INT:
	56	return max77686->rtc_regmap;
	57	default:
	58	return ERR_PTR(-EINVAL);
	59	}
	60	}
	61
	62	struct max77686_irq_data {
	63	int mask;
	64	enum max77686_irq_source group;
65	};
66
67	#define DECLARE_IRQ(idx, _group, _mask) \
68	[(idx)] = { .group = (_group), .mask = (_mask) }
69	static const struct max77686_irq_data max77686_irqs[] = {
70	DECLARE_IRQ(MAX77686_PMICIRQ_PWRONF, PMIC_INT1, 1 << 0),
71	DECLARE_IRQ(MAX77686_PMICIRQ_PWRONR, PMIC_INT1, 1 << 1),
72	DECLARE_IRQ(MAX77686_PMICIRQ_JIGONBF, PMIC_INT1, 1 << 2),
73	DECLARE_IRQ(MAX77686_PMICIRQ_JIGONBR, PMIC_INT1, 1 << 3),
74	DECLARE_IRQ(MAX77686_PMICIRQ_ACOKBF, PMIC_INT1, 1 << 4),
75	DECLARE_IRQ(MAX77686_PMICIRQ_ACOKBR, PMIC_INT1, 1 << 5),
76	DECLARE_IRQ(MAX77686_PMICIRQ_ONKEY1S, PMIC_INT1, 1 << 6),
77	DECLARE_IRQ(MAX77686_PMICIRQ_MRSTB, PMIC_INT1, 1 << 7),
78	DECLARE_IRQ(MAX77686_PMICIRQ_140C, PMIC_INT2, 1 << 0),
79	DECLARE_IRQ(MAX77686_PMICIRQ_120C, PMIC_INT2, 1 << 1),
80	DECLARE_IRQ(MAX77686_RTCIRQ_RTC60S, RTC_INT, 1 << 0),
81	DECLARE_IRQ(MAX77686_RTCIRQ_RTCA1, RTC_INT, 1 << 1),
82	DECLARE_IRQ(MAX77686_RTCIRQ_RTCA2, RTC_INT, 1 << 2),
83	DECLARE_IRQ(MAX77686_RTCIRQ_SMPL, RTC_INT, 1 << 3),
84	DECLARE_IRQ(MAX77686_RTCIRQ_RTC1S, RTC_INT, 1 << 4),
85	DECLARE_IRQ(MAX77686_RTCIRQ_WTSR, RTC_INT, 1 << 5),
86	};
87
88	static void max77686_irq_lock(struct irq_data *data)
89	{
90	struct max77686_dev *max77686 = irq_get_chip_data(data->irq);
91
92	if (debug_mask & MAX77686_DEBUG_IRQ_MASK)
93	pr_info("%s\n", __func__);
94
95	mutex_lock(&max77686->irqlock);
96	}
97
98	static void max77686_irq_sync_unlock(struct irq_data *data)
99	{
100	struct max77686_dev *max77686 = irq_get_chip_data(data->irq);
101	int i;
102
103	for (i = 0; i < MAX77686_IRQ_GROUP_NR; i++) {
104	u8 mask_reg = max77686_mask_reg[i];
105	struct regmap *map = max77686_get_regmap(max77686, i);
106
107	if (debug_mask & MAX77686_DEBUG_IRQ_MASK)
108	pr_debug("%s: mask_reg[%d]=0x%x, cur=0x%x\n",
109	__func__, i, mask_reg, max77686->irq_masks_cur[i]);
110
111	if (mask_reg == MAX77686_REG_INVALID \|\|
112	IS_ERR_OR_NULL(map))
113	continue;
114
115	max77686->irq_masks_cache[i] = max77686->irq_masks_cur[i];
116
117	regmap_write(map, max77686_mask_reg[i],
118	max77686->irq_masks_cur[i]);
119	}
120
121	mutex_unlock(&max77686->irqlock);
122	}
123
124	static const inline struct max77686_irq_data *to_max77686_irq(int irq)
125	{
126	struct irq_data *data = irq_get_irq_data(irq);
127	return &max77686_irqs[data->hwirq];
128	}
129
130	static void max77686_irq_mask(struct irq_data *data)
131	{
132	struct max77686_dev *max77686 = irq_get_chip_data(data->irq);
133	const struct max77686_irq_data *irq_data = to_max77686_irq(data->irq);
134
135	max77686->irq_masks_cur[irq_data->group] \|= irq_data->mask;
136
137	if (debug_mask & MAX77686_DEBUG_IRQ_MASK)
138	pr_info("%s: group=%d, cur=0x%x\n",
139	__func__, irq_data->group,
140	max77686->irq_masks_cur[irq_data->group]);
141	}
142
143	static void max77686_irq_unmask(struct irq_data *data)
144	{
145	struct max77686_dev *max77686 = irq_get_chip_data(data->irq);
146	const struct max77686_irq_data *irq_data = to_max77686_irq(data->irq);
147
148	max77686->irq_masks_cur[irq_data->group] &= ~irq_data->mask;
149
150	if (debug_mask & MAX77686_DEBUG_IRQ_MASK)
151	pr_info("%s: group=%d, cur=0x%x\n",
152	__func__, irq_data->group,
153	max77686->irq_masks_cur[irq_data->group]);
154	}
155
156	static struct irq_chip max77686_irq_chip = {
157	.name = "max77686",
158	.irq_bus_lock = max77686_irq_lock,
159	.irq_bus_sync_unlock = max77686_irq_sync_unlock,
160	.irq_mask = max77686_irq_mask,
161	.irq_unmask = max77686_irq_unmask,
162	};
163
164	static irqreturn_t max77686_irq_thread(int irq, void *data)
165	{
166	struct max77686_dev *max77686 = data;
167	unsigned int irq_reg[MAX77686_IRQ_GROUP_NR] = {};
168	unsigned int irq_src;
169	int ret;
170	int i, cur_irq;
171
172	ret = regmap_read(max77686->regmap, MAX77686_REG_INTSRC, &irq_src);
173	if (ret < 0) {
174	dev_err(max77686->dev, "Failed to read interrupt source: %d\n",
175	ret);
176	return IRQ_NONE;
177	}
178
179	if (debug_mask & MAX77686_DEBUG_IRQ_INT)
180	pr_info("%s: irq_src=0x%x\n", __func__, irq_src);
181
182	if (irq_src == MAX77686_IRQSRC_PMIC) {
183	ret = regmap_bulk_read(max77686->rtc_regmap,
184	MAX77686_REG_INT1, irq_reg, 2);
185	if (ret < 0) {
186	dev_err(max77686->dev, "Failed to read interrupt source: %d\n",
187	ret);
188	return IRQ_NONE;
189	}
190
191	if (debug_mask & MAX77686_DEBUG_IRQ_INT)
192	pr_info("%s: int1=0x%x, int2=0x%x\n", __func__,
193	irq_reg[PMIC_INT1], irq_reg[PMIC_INT2]);
194	}
195
196	if (irq_src & MAX77686_IRQSRC_RTC) {
197	ret = regmap_read(max77686->rtc_regmap,
198	MAX77686_RTC_INT, &irq_reg[RTC_INT]);
199	if (ret < 0) {
200	dev_err(max77686->dev, "Failed to read interrupt source: %d\n",
201	ret);
202	return IRQ_NONE;
203	}
204
205	if (debug_mask & MAX77686_DEBUG_IRQ_INT)
206	pr_info("%s: rtc int=0x%x\n", __func__,
207	irq_reg[RTC_INT]);
208
209	}
210
211	for (i = 0; i < MAX77686_IRQ_NR; i++) {
212	if (irq_reg[max77686_irqs[i].group] & max77686_irqs[i].mask) {
213	cur_irq = irq_find_mapping(max77686->irq_domain, i);
214	if (cur_irq)
215	handle_nested_irq(cur_irq);
216	}
217	}
218
219	return IRQ_HANDLED;
220	}
221
222	static int max77686_irq_domain_map(struct irq_domain *d, unsigned int irq,
223	irq_hw_number_t hw)
224	{
225	struct max77686_dev *max77686 = d->host_data;
226
227	irq_set_chip_data(irq, max77686);
228	irq_set_chip_and_handler(irq, &max77686_irq_chip, handle_edge_irq);
229	irq_set_nested_thread(irq, 1);
230	#ifdef CONFIG_ARM
231	set_irq_flags(irq, IRQF_VALID);
232	#else
233	irq_set_noprobe(irq);
234	#endif
235	return 0;
236	}
237
238	static struct irq_domain_ops max77686_irq_domain_ops = {
239	.map = max77686_irq_domain_map,
240	};
241
242	int max77686_irq_init(struct max77686_dev *max77686)
243	{
244	struct irq_domain *domain;
245	int i;
246	int ret;
247	int val;
248	struct regmap *map;
249
250	mutex_init(&max77686->irqlock);
251
252	max77686->irq = gpio_to_irq(max77686->irq_gpio);
253
254	if (debug_mask & MAX77686_DEBUG_IRQ_INT) {
255	ret = gpio_request(max77686->irq_gpio, "pmic_irq");
256	if (ret < 0) {
257	dev_err(max77686->dev,
258	"Failed to request gpio %d with ret: %d\n",
259	max77686->irq_gpio, ret);
260	return IRQ_NONE;
261	}
262
263	gpio_direction_input(max77686->irq_gpio);
264	val = gpio_get_value(max77686->irq_gpio);
265	gpio_free(max77686->irq_gpio);
266	pr_info("%s: gpio_irq=%x\n", __func__, val);
267	}
268
269	/* Mask individual interrupt sources */
270	for (i = 0; i < MAX77686_IRQ_GROUP_NR; i++) {
271	max77686->irq_masks_cur[i] = 0xff;
272	max77686->irq_masks_cache[i] = 0xff;
273	map = max77686_get_regmap(max77686, i);
274
275	if (IS_ERR_OR_NULL(map))
276	continue;
277	if (max77686_mask_reg[i] == MAX77686_REG_INVALID)
278	continue;
279
280	regmap_write(map, max77686_mask_reg[i], 0xff);
281	}
282	domain = irq_domain_add_linear(NULL, MAX77686_IRQ_NR,
283	&max77686_irq_domain_ops, max77686);
284	if (!domain) {
285	dev_err(max77686->dev, "could not create irq domain\n");
286	return -ENODEV;
287	}
288	max77686->irq_domain = domain;
289
290	ret = request_threaded_irq(max77686->irq, NULL, max77686_irq_thread,
291	IRQF_TRIGGER_FALLING \| IRQF_ONESHOT,
292	"max77686-irq", max77686);
293
294	if (ret)
295	dev_err(max77686->dev, "Failed to request IRQ %d: %d\n",
296	max77686->irq, ret);
297
298
299	if (debug_mask & MAX77686_DEBUG_IRQ_INFO)
300	pr_info("%s-\n", __func__);
301
302	return 0;
303	}
304
305	void max77686_irq_exit(struct max77686_dev *max77686)
306	{
307	if (max77686->irq)
308	free_irq(max77686->irq, max77686);
309	}