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mfd: Remove obsolete mc13783 private data
[deliverable/linux.git] / drivers / mfd / mc13783-core.c
CommitLineData
8238addc 1/*
9e272677
UKK		 2 * Copyright 2009 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
8238addc 4 *
9e272677
UKK		 5 * loosely based on an earlier driver that has
6 * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
8238addc 7 *
9e272677
UKK		 8 * This program is free software; you can redistribute it and/or modify it under
9 * the terms of the GNU General Public License version 2 as published by the
10 * Free Software Foundation.
8238addc 11 */
5a0e3ad6 12#include <linux/slab.h>
8238addc 13#include <linux/module.h>
b6e6d54c
UKK		 14#include <linux/platform_device.h>
15#include <linux/mutex.h>
16#include <linux/interrupt.h>
9e272677
UKK		 17#include <linux/spi/spi.h>
18#include <linux/mfd/core.h>
b6e6d54c
UKK		 19#include <linux/mfd/mc13783.h>
20
21struct mc13783 {
22 struct spi_device *spidev;
23 struct mutex lock;
24 int irq;
7e2bb82e 25 int adcflags;
b6e6d54c
UKK		 26
27 irq_handler_t irqhandler[MC13783_NUM_IRQ];
28 void *irqdata[MC13783_NUM_IRQ];
b6e6d54c
UKK		 29};
30
31#define MC13783_REG_REVISION 7
32#define MC13783_REG_ADC_0 43
33#define MC13783_REG_ADC_1 44
34#define MC13783_REG_ADC_2 45
9e272677
UKK		 35
36#define MC13783_IRQSTAT0 0
37#define MC13783_IRQSTAT0_ADCDONEI (1 << 0)
38#define MC13783_IRQSTAT0_ADCBISDONEI (1 << 1)
39#define MC13783_IRQSTAT0_TSI (1 << 2)
40#define MC13783_IRQSTAT0_WHIGHI (1 << 3)
41#define MC13783_IRQSTAT0_WLOWI (1 << 4)
42#define MC13783_IRQSTAT0_CHGDETI (1 << 6)
43#define MC13783_IRQSTAT0_CHGOVI (1 << 7)
44#define MC13783_IRQSTAT0_CHGREVI (1 << 8)
45#define MC13783_IRQSTAT0_CHGSHORTI (1 << 9)
46#define MC13783_IRQSTAT0_CCCVI (1 << 10)
47#define MC13783_IRQSTAT0_CHGCURRI (1 << 11)
48#define MC13783_IRQSTAT0_BPONI (1 << 12)
49#define MC13783_IRQSTAT0_LOBATLI (1 << 13)
50#define MC13783_IRQSTAT0_LOBATHI (1 << 14)
51#define MC13783_IRQSTAT0_UDPI (1 << 15)
52#define MC13783_IRQSTAT0_USBI (1 << 16)
53#define MC13783_IRQSTAT0_IDI (1 << 19)
54#define MC13783_IRQSTAT0_SE1I (1 << 21)
55#define MC13783_IRQSTAT0_CKDETI (1 << 22)
56#define MC13783_IRQSTAT0_UDMI (1 << 23)
57
58#define MC13783_IRQMASK0 1
59#define MC13783_IRQMASK0_ADCDONEM MC13783_IRQSTAT0_ADCDONEI
60#define MC13783_IRQMASK0_ADCBISDONEM MC13783_IRQSTAT0_ADCBISDONEI
61#define MC13783_IRQMASK0_TSM MC13783_IRQSTAT0_TSI
62#define MC13783_IRQMASK0_WHIGHM MC13783_IRQSTAT0_WHIGHI
63#define MC13783_IRQMASK0_WLOWM MC13783_IRQSTAT0_WLOWI
64#define MC13783_IRQMASK0_CHGDETM MC13783_IRQSTAT0_CHGDETI
65#define MC13783_IRQMASK0_CHGOVM MC13783_IRQSTAT0_CHGOVI
66#define MC13783_IRQMASK0_CHGREVM MC13783_IRQSTAT0_CHGREVI
67#define MC13783_IRQMASK0_CHGSHORTM MC13783_IRQSTAT0_CHGSHORTI
68#define MC13783_IRQMASK0_CCCVM MC13783_IRQSTAT0_CCCVI
69#define MC13783_IRQMASK0_CHGCURRM MC13783_IRQSTAT0_CHGCURRI
70#define MC13783_IRQMASK0_BPONM MC13783_IRQSTAT0_BPONI
71#define MC13783_IRQMASK0_LOBATLM MC13783_IRQSTAT0_LOBATLI
72#define MC13783_IRQMASK0_LOBATHM MC13783_IRQSTAT0_LOBATHI
73#define MC13783_IRQMASK0_UDPM MC13783_IRQSTAT0_UDPI
74#define MC13783_IRQMASK0_USBM MC13783_IRQSTAT0_USBI
75#define MC13783_IRQMASK0_IDM MC13783_IRQSTAT0_IDI
76#define MC13783_IRQMASK0_SE1M MC13783_IRQSTAT0_SE1I
77#define MC13783_IRQMASK0_CKDETM MC13783_IRQSTAT0_CKDETI
78#define MC13783_IRQMASK0_UDMM MC13783_IRQSTAT0_UDMI
79
80#define MC13783_IRQSTAT1 3
81#define MC13783_IRQSTAT1_1HZI (1 << 0)
82#define MC13783_IRQSTAT1_TODAI (1 << 1)
83#define MC13783_IRQSTAT1_ONOFD1I (1 << 3)
84#define MC13783_IRQSTAT1_ONOFD2I (1 << 4)
85#define MC13783_IRQSTAT1_ONOFD3I (1 << 5)
86#define MC13783_IRQSTAT1_SYSRSTI (1 << 6)
87#define MC13783_IRQSTAT1_RTCRSTI (1 << 7)
88#define MC13783_IRQSTAT1_PCI (1 << 8)
89#define MC13783_IRQSTAT1_WARMI (1 << 9)
90#define MC13783_IRQSTAT1_MEMHLDI (1 << 10)
91#define MC13783_IRQSTAT1_PWRRDYI (1 << 11)
92#define MC13783_IRQSTAT1_THWARNLI (1 << 12)
93#define MC13783_IRQSTAT1_THWARNHI (1 << 13)
94#define MC13783_IRQSTAT1_CLKI (1 << 14)
95#define MC13783_IRQSTAT1_SEMAFI (1 << 15)
96#define MC13783_IRQSTAT1_MC2BI (1 << 17)
97#define MC13783_IRQSTAT1_HSDETI (1 << 18)
98#define MC13783_IRQSTAT1_HSLI (1 << 19)
99#define MC13783_IRQSTAT1_ALSPTHI (1 << 20)
100#define MC13783_IRQSTAT1_AHSSHORTI (1 << 21)
101
102#define MC13783_IRQMASK1 4
103#define MC13783_IRQMASK1_1HZM MC13783_IRQSTAT1_1HZI
104#define MC13783_IRQMASK1_TODAM MC13783_IRQSTAT1_TODAI
105#define MC13783_IRQMASK1_ONOFD1M MC13783_IRQSTAT1_ONOFD1I
106#define MC13783_IRQMASK1_ONOFD2M MC13783_IRQSTAT1_ONOFD2I
107#define MC13783_IRQMASK1_ONOFD3M MC13783_IRQSTAT1_ONOFD3I
108#define MC13783_IRQMASK1_SYSRSTM MC13783_IRQSTAT1_SYSRSTI
109#define MC13783_IRQMASK1_RTCRSTM MC13783_IRQSTAT1_RTCRSTI
110#define MC13783_IRQMASK1_PCM MC13783_IRQSTAT1_PCI
111#define MC13783_IRQMASK1_WARMM MC13783_IRQSTAT1_WARMI
112#define MC13783_IRQMASK1_MEMHLDM MC13783_IRQSTAT1_MEMHLDI
113#define MC13783_IRQMASK1_PWRRDYM MC13783_IRQSTAT1_PWRRDYI
114#define MC13783_IRQMASK1_THWARNLM MC13783_IRQSTAT1_THWARNLI
115#define MC13783_IRQMASK1_THWARNHM MC13783_IRQSTAT1_THWARNHI
116#define MC13783_IRQMASK1_CLKM MC13783_IRQSTAT1_CLKI
117#define MC13783_IRQMASK1_SEMAFM MC13783_IRQSTAT1_SEMAFI
118#define MC13783_IRQMASK1_MC2BM MC13783_IRQSTAT1_MC2BI
119#define MC13783_IRQMASK1_HSDETM MC13783_IRQSTAT1_HSDETI
120#define MC13783_IRQMASK1_HSLM MC13783_IRQSTAT1_HSLI
121#define MC13783_IRQMASK1_ALSPTHM MC13783_IRQSTAT1_ALSPTHI
122#define MC13783_IRQMASK1_AHSSHORTM MC13783_IRQSTAT1_AHSSHORTI
123
124#define MC13783_ADC1 44
125#define MC13783_ADC1_ADEN (1 << 0)
126#define MC13783_ADC1_RAND (1 << 1)
127#define MC13783_ADC1_ADSEL (1 << 3)
128#define MC13783_ADC1_ASC (1 << 20)
129#define MC13783_ADC1_ADTRIGIGN (1 << 21)
130
131#define MC13783_NUMREGS 0x3f
132
133void mc13783_lock(struct mc13783 *mc13783)
134{
135 if (!mutex_trylock(&mc13783->lock)) {
136 dev_dbg(&mc13783->spidev->dev, "wait for %s from %pf\n",
137 __func__, __builtin_return_address(0));
138
139 mutex_lock(&mc13783->lock);
140 }
141 dev_dbg(&mc13783->spidev->dev, "%s from %pf\n",
142 __func__, __builtin_return_address(0));
143}
144EXPORT_SYMBOL(mc13783_lock);
8238addc 145
9e272677
UKK		 146void mc13783_unlock(struct mc13783 *mc13783)
147{
148 dev_dbg(&mc13783->spidev->dev, "%s from %pf\n",
149 __func__, __builtin_return_address(0));
150 mutex_unlock(&mc13783->lock);
151}
152EXPORT_SYMBOL(mc13783_unlock);
8238addc 153
9e272677
UKK		 154#define MC13783_REGOFFSET_SHIFT 25
155int mc13783_reg_read(struct mc13783 *mc13783, unsigned int offset, u32 *val)
8238addc 156{
9e272677 157 struct spi_transfer t;
8238addc 158 struct spi_message m;
9e272677
UKK		 159 int ret;
160
161 BUG_ON(!mutex_is_locked(&mc13783->lock));
162
163 if (offset > MC13783_NUMREGS)
164 return -EINVAL;
165
166 *val = offset << MC13783_REGOFFSET_SHIFT;
167
168 memset(&t, 0, sizeof(t));
169
170 t.tx_buf = val;
171 t.rx_buf = val;
172 t.len = sizeof(u32);
8238addc
SH		 173
174 spi_message_init(&m);
175 spi_message_add_tail(&t, &m);
8238addc 176
9e272677 177 ret = spi_sync(mc13783->spidev, &m);
8238addc 178
9e272677
UKK		 179 /* error in message.status implies error return from spi_sync */
180 BUG_ON(!ret && m.status);
8238addc 181
9e272677
UKK		 182 if (ret)
183 return ret;
8238addc 184
9e272677 185 *val &= 0xffffff;
8238addc 186
9e272677 187 dev_vdbg(&mc13783->spidev->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
8238addc 188
9e272677 189 return 0;
8238addc 190}
9e272677 191EXPORT_SYMBOL(mc13783_reg_read);
8238addc 192
9e272677 193int mc13783_reg_write(struct mc13783 *mc13783, unsigned int offset, u32 val)
8238addc 194{
9e272677
UKK		 195 u32 buf;
196 struct spi_transfer t;
197 struct spi_message m;
198 int ret;
199
200 BUG_ON(!mutex_is_locked(&mc13783->lock));
8238addc 201
9e272677
UKK		 202 dev_vdbg(&mc13783->spidev->dev, "[0x%02x] <- 0x%06x\n", offset, val);
203
204 if (offset > MC13783_NUMREGS || val > 0xffffff)
8238addc
SH		 205 return -EINVAL;
206
9e272677
UKK		 207 buf = 1 << 31 | offset << MC13783_REGOFFSET_SHIFT | val;
208
209 memset(&t, 0, sizeof(t));
8238addc 210
9e272677
UKK		 211 t.tx_buf = &buf;
212 t.rx_buf = &buf;
213 t.len = sizeof(u32);
214
215 spi_message_init(&m);
216 spi_message_add_tail(&t, &m);
217
218 ret = spi_sync(mc13783->spidev, &m);
219
220 BUG_ON(!ret && m.status);
221
222 if (ret)
223 return ret;
224
225 return 0;
8238addc 226}
9e272677 227EXPORT_SYMBOL(mc13783_reg_write);
8238addc 228
9e272677
UKK		 229int mc13783_reg_rmw(struct mc13783 *mc13783, unsigned int offset,
230 u32 mask, u32 val)
8238addc
SH		 231{
232 int ret;
9e272677 233 u32 valread;
8238addc 234
9e272677 235 BUG_ON(val & ~mask);
8238addc 236
9e272677
UKK		 237 ret = mc13783_reg_read(mc13783, offset, &valread);
238 if (ret)
239 return ret;
240
241 valread = (valread & ~mask) | val;
242
243 return mc13783_reg_write(mc13783, offset, valread);
8238addc 244}
9e272677 245EXPORT_SYMBOL(mc13783_reg_rmw);
8238addc 246
3b16bb53
UKK		 247int mc13783_get_flags(struct mc13783 *mc13783)
248{
7e2bb82e
UKK		 249 struct mc13783_platform_data *pdata =
250 dev_get_platdata(&mc13783->spidev->dev);
251
252 return pdata->flags;
3b16bb53
UKK		 253}
254EXPORT_SYMBOL(mc13783_get_flags);
255
57205026 256int mc13783_irq_mask(struct mc13783 *mc13783, int irq)
8238addc
SH		 257{
258 int ret;
9e272677
UKK		 259 unsigned int offmask = irq < 24 ? MC13783_IRQMASK0 : MC13783_IRQMASK1;
260 u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
261 u32 mask;
8238addc 262
9e272677
UKK		 263 if (irq < 0 || irq >= MC13783_NUM_IRQ)
264 return -EINVAL;
8238addc 265
9e272677
UKK		 266 ret = mc13783_reg_read(mc13783, offmask, &mask);
267 if (ret)
268 return ret;
269
270 if (mask & irqbit)
271 /* already masked */
272 return 0;
273
274 return mc13783_reg_write(mc13783, offmask, mask | irqbit);
8238addc 275}
57205026 276EXPORT_SYMBOL(mc13783_irq_mask);
8238addc 277
57205026 278int mc13783_irq_unmask(struct mc13783 *mc13783, int irq)
8238addc 279{
8238addc 280 int ret;
9e272677
UKK		 281 unsigned int offmask = irq < 24 ? MC13783_IRQMASK0 : MC13783_IRQMASK1;
282 u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
283 u32 mask;
8238addc 284
9e272677
UKK		 285 if (irq < 0 || irq >= MC13783_NUM_IRQ)
286 return -EINVAL;
8238addc 287
9e272677
UKK		 288 ret = mc13783_reg_read(mc13783, offmask, &mask);
289 if (ret)
290 return ret;
8238addc 291
9e272677
UKK		 292 if (!(mask & irqbit))
293 /* already unmasked */
294 return 0;
8238addc 295
9e272677 296 return mc13783_reg_write(mc13783, offmask, mask & ~irqbit);
8238addc 297}
57205026
UKK		 298EXPORT_SYMBOL(mc13783_irq_unmask);
299
86c34008
UKK		 300int mc13783_irq_status(struct mc13783 *mc13783, int irq,
301 int *enabled, int *pending)
302{
303 int ret;
304 unsigned int offmask = irq < 24 ? MC13783_IRQMASK0 : MC13783_IRQMASK1;
305 unsigned int offstat = irq < 24 ? MC13783_IRQSTAT0 : MC13783_IRQSTAT1;
306 u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
307
308 if (irq < 0 || irq >= MC13783_NUM_IRQ)
309 return -EINVAL;
310
311 if (enabled) {
312 u32 mask;
313
314 ret = mc13783_reg_read(mc13783, offmask, &mask);
315 if (ret)
316 return ret;
317
318 *enabled = mask & irqbit;
319 }
320
321 if (pending) {
322 u32 stat;
323
324 ret = mc13783_reg_read(mc13783, offstat, &stat);
325 if (ret)
326 return ret;
327
328 *pending = stat & irqbit;
329 }
330
331 return 0;
332}
333EXPORT_SYMBOL(mc13783_irq_status);
334
57205026
UKK		 335int mc13783_irq_ack(struct mc13783 *mc13783, int irq)
336{
337 unsigned int offstat = irq < 24 ? MC13783_IRQSTAT0 : MC13783_IRQSTAT1;
338 unsigned int val = 1 << (irq < 24 ? irq : irq - 24);
339
340 BUG_ON(irq < 0 || irq >= MC13783_NUM_IRQ);
341
342 return mc13783_reg_write(mc13783, offstat, val);
343}
344EXPORT_SYMBOL(mc13783_irq_ack);
8238addc 345
9e272677
UKK		 346int mc13783_irq_request_nounmask(struct mc13783 *mc13783, int irq,
347 irq_handler_t handler, const char *name, void *dev)
8238addc 348{
9e272677
UKK		 349 BUG_ON(!mutex_is_locked(&mc13783->lock));
350 BUG_ON(!handler);
351
352 if (irq < 0 || irq >= MC13783_NUM_IRQ)
8238addc
SH		 353 return -EINVAL;
354
9e272677 355 if (mc13783->irqhandler[irq])
8238addc
SH		 356 return -EBUSY;
357
9e272677
UKK		 358 mc13783->irqhandler[irq] = handler;
359 mc13783->irqdata[irq] = dev;
8238addc
SH		 360
361 return 0;
362}
9e272677 363EXPORT_SYMBOL(mc13783_irq_request_nounmask);
8238addc 364
9e272677
UKK		 365int mc13783_irq_request(struct mc13783 *mc13783, int irq,
366 irq_handler_t handler, const char *name, void *dev)
8238addc 367{
9e272677
UKK		 368 int ret;
369
370 ret = mc13783_irq_request_nounmask(mc13783, irq, handler, name, dev);
371 if (ret)
372 return ret;
373
57205026 374 ret = mc13783_irq_unmask(mc13783, irq);
9e272677
UKK		 375 if (ret) {
376 mc13783->irqhandler[irq] = NULL;
377 mc13783->irqdata[irq] = NULL;
378 return ret;
379 }
380
381 return 0;
382}
383EXPORT_SYMBOL(mc13783_irq_request);
384
385int mc13783_irq_free(struct mc13783 *mc13783, int irq, void *dev)
386{
387 int ret;
388 BUG_ON(!mutex_is_locked(&mc13783->lock));
389
390 if (irq < 0 || irq >= MC13783_NUM_IRQ || !mc13783->irqhandler[irq] ||
391 mc13783->irqdata[irq] != dev)
8238addc
SH		 392 return -EINVAL;
393
57205026 394 ret = mc13783_irq_mask(mc13783, irq);
9e272677
UKK		 395 if (ret)
396 return ret;
397
398 mc13783->irqhandler[irq] = NULL;
399 mc13783->irqdata[irq] = NULL;
8238addc
SH		 400
401 return 0;
402}
9e272677 403EXPORT_SYMBOL(mc13783_irq_free);
8238addc 404
9e272677 405static inline irqreturn_t mc13783_irqhandler(struct mc13783 *mc13783, int irq)
8238addc 406{
9e272677 407 return mc13783->irqhandler[irq](irq, mc13783->irqdata[irq]);
8238addc
SH		 408}
409
9e272677
UKK		 410/*
411 * returns: number of handled irqs or negative error
412 * locking: holds mc13783->lock
413 */
414static int mc13783_irq_handle(struct mc13783 *mc13783,
415 unsigned int offstat, unsigned int offmask, int baseirq)
8238addc 416{
9e272677
UKK		 417 u32 stat, mask;
418 int ret = mc13783_reg_read(mc13783, offstat, &stat);
419 int num_handled = 0;
420
421 if (ret)
422 return ret;
423
424 ret = mc13783_reg_read(mc13783, offmask, &mask);
425 if (ret)
426 return ret;
427
428 while (stat & ~mask) {
429 int irq = __ffs(stat & ~mask);
430
431 stat &= ~(1 << irq);
432
433 if (likely(mc13783->irqhandler[baseirq + irq])) {
434 irqreturn_t handled;
8238addc 435
9e272677
UKK		 436 handled = mc13783_irqhandler(mc13783, baseirq + irq);
437 if (handled == IRQ_HANDLED)
438 num_handled++;
439 } else {
440 dev_err(&mc13783->spidev->dev,
441 "BUG: irq %u but no handler\n",
442 baseirq + irq);
8238addc 443
9e272677
UKK		 444 mask |= 1 << irq;
445
446 ret = mc13783_reg_write(mc13783, offmask, mask);
447 }
448 }
449
450 return num_handled;
8238addc
SH		 451}
452
9e272677
UKK		 453static irqreturn_t mc13783_irq_thread(int irq, void *data)
454{
455 struct mc13783 *mc13783 = data;
456 irqreturn_t ret;
457 int handled = 0;
458
459 mc13783_lock(mc13783);
460
461 ret = mc13783_irq_handle(mc13783, MC13783_IRQSTAT0,
462 MC13783_IRQMASK0, MC13783_IRQ_ADCDONE);
463 if (ret > 0)
464 handled = 1;
465
466 ret = mc13783_irq_handle(mc13783, MC13783_IRQSTAT1,
467 MC13783_IRQMASK1, MC13783_IRQ_1HZ);
468 if (ret > 0)
469 handled = 1;
470
471 mc13783_unlock(mc13783);
472
473 return IRQ_RETVAL(handled);
474}
475
476#define MC13783_ADC1_CHAN0_SHIFT 5
477#define MC13783_ADC1_CHAN1_SHIFT 8
478
479struct mc13783_adcdone_data {
480 struct mc13783 *mc13783;
481 struct completion done;
482};
483
484static irqreturn_t mc13783_handler_adcdone(int irq, void *data)
485{
486 struct mc13783_adcdone_data *adcdone_data = data;
487
57205026 488 mc13783_irq_ack(adcdone_data->mc13783, irq);
9e272677
UKK		 489
490 complete_all(&adcdone_data->done);
491
492 return IRQ_HANDLED;
493}
494
7e2bb82e 495#define MC13783_ADC_WORKING (1 << 0)
9e272677 496
8238addc
SH		 497int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode,
498 unsigned int channel, unsigned int *sample)
499{
9e272677
UKK		 500 u32 adc0, adc1, old_adc0;
501 int i, ret;
502 struct mc13783_adcdone_data adcdone_data = {
503 .mc13783 = mc13783,
504 };
505 init_completion(&adcdone_data.done);
506
507 dev_dbg(&mc13783->spidev->dev, "%s\n", __func__);
508
509 mc13783_lock(mc13783);
510
7e2bb82e 511 if (mc13783->adcflags & MC13783_ADC_WORKING) {
9e272677
UKK		 512 ret = -EBUSY;
513 goto out;
514 }
515
7e2bb82e 516 mc13783->adcflags |= MC13783_ADC_WORKING;
8238addc 517
9e272677 518 mc13783_reg_read(mc13783, MC13783_ADC0, &old_adc0);
8238addc 519
9e272677
UKK		 520 adc0 = MC13783_ADC0_ADINC1 | MC13783_ADC0_ADINC2;
521 adc1 = MC13783_ADC1_ADEN | MC13783_ADC1_ADTRIGIGN | MC13783_ADC1_ASC;
8238addc 522
8238addc 523 if (channel > 7)
9e272677 524 adc1 |= MC13783_ADC1_ADSEL;
8238addc
SH		 525
526 switch (mode) {
527 case MC13783_ADC_MODE_TS:
be26d664
UKK		 528 adc0 |= MC13783_ADC0_ADREFEN | MC13783_ADC0_TSMOD0 |
529 MC13783_ADC0_TSMOD1;
9e272677 530 adc1 |= 4 << MC13783_ADC1_CHAN1_SHIFT;
8238addc 531 break;
9e272677 532
8238addc 533 case MC13783_ADC_MODE_SINGLE_CHAN:
9e272677
UKK		 534 adc0 |= old_adc0 & MC13783_ADC0_TSMOD_MASK;
535 adc1 |= (channel & 0x7) << MC13783_ADC1_CHAN0_SHIFT;
536 adc1 |= MC13783_ADC1_RAND;
8238addc 537 break;
9e272677 538
8238addc 539 case MC13783_ADC_MODE_MULT_CHAN:
9e272677
UKK		 540 adc0 |= old_adc0 & MC13783_ADC0_TSMOD_MASK;
541 adc1 |= 4 << MC13783_ADC1_CHAN1_SHIFT;
8238addc 542 break;
9e272677 543
8238addc 544 default:
9e272677 545 mc13783_unlock(mc13783);
8238addc
SH		 546 return -EINVAL;
547 }
548
9e272677
UKK		 549 dev_dbg(&mc13783->spidev->dev, "%s: request irq\n", __func__);
550 mc13783_irq_request(mc13783, MC13783_IRQ_ADCDONE,
551 mc13783_handler_adcdone, __func__, &adcdone_data);
57205026 552 mc13783_irq_ack(mc13783, MC13783_IRQ_ADCDONE);
8238addc 553
9e272677
UKK		 554 mc13783_reg_write(mc13783, MC13783_REG_ADC_0, adc0);
555 mc13783_reg_write(mc13783, MC13783_REG_ADC_1, adc1);
8238addc 556
9e272677 557 mc13783_unlock(mc13783);
8238addc 558
9e272677 559 ret = wait_for_completion_interruptible_timeout(&adcdone_data.done, HZ);
8238addc 560
9e272677
UKK		 561 if (!ret)
562 ret = -ETIMEDOUT;
8238addc 563
9e272677
UKK		 564 mc13783_lock(mc13783);
565
566 mc13783_irq_free(mc13783, MC13783_IRQ_ADCDONE, &adcdone_data);
567
568 if (ret > 0)
569 for (i = 0; i < 4; ++i) {
570 ret = mc13783_reg_read(mc13783,
571 MC13783_REG_ADC_2, &sample[i]);
572 if (ret)
573 break;
574 }
575
576 if (mode == MC13783_ADC_MODE_TS)
577 /* restore TSMOD */
578 mc13783_reg_write(mc13783, MC13783_REG_ADC_0, old_adc0);
579
7e2bb82e 580 mc13783->adcflags &= ~MC13783_ADC_WORKING;
9e272677
UKK		 581out:
582 mc13783_unlock(mc13783);
583
584 return ret;
8238addc
SH		 585}
586EXPORT_SYMBOL_GPL(mc13783_adc_do_conversion);
587
9e272677
UKK		 588static int mc13783_add_subdevice_pdata(struct mc13783 *mc13783,
589 const char *name, void *pdata, size_t pdata_size)
8238addc 590{
9e272677
UKK		 591 struct mfd_cell cell = {
592 .name = name,
593 .platform_data = pdata,
594 .data_size = pdata_size,
595 };
596
597 return mfd_add_devices(&mc13783->spidev->dev, -1, &cell, 1, NULL, 0);
598}
599
600static int mc13783_add_subdevice(struct mc13783 *mc13783, const char *name)
601{
602 return mc13783_add_subdevice_pdata(mc13783, name, NULL, 0);
8238addc 603}
8238addc
SH		 604
605static int mc13783_check_revision(struct mc13783 *mc13783)
606{
607 u32 rev_id, rev1, rev2, finid, icid;
608
9e272677 609 mc13783_reg_read(mc13783, MC13783_REG_REVISION, &rev_id);
8238addc
SH		 610
611 rev1 = (rev_id & 0x018) >> 3;
612 rev2 = (rev_id & 0x007);
613 icid = (rev_id & 0x01C0) >> 6;
614 finid = (rev_id & 0x01E00) >> 9;
615
616 /* Ver 0.2 is actually 3.2a. Report as 3.2 */
617 if ((rev1 == 0) && (rev2 == 2))
618 rev1 = 3;
619
620 if (rev1 == 0 || icid != 2) {
9e272677 621 dev_err(&mc13783->spidev->dev, "No MC13783 detected.\n");
8238addc
SH		 622 return -ENODEV;
623 }
624
9e272677
UKK		 625 dev_info(&mc13783->spidev->dev,
626 "MC13783 Rev %d.%d FinVer %x detected\n",
627 rev1, rev2, finid);
8238addc
SH		 628
629 return 0;
630}
631
9e272677 632static int mc13783_probe(struct spi_device *spi)
8238addc
SH		 633{
634 struct mc13783 *mc13783;
9e272677 635 struct mc13783_platform_data *pdata = dev_get_platdata(&spi->dev);
8238addc
SH		 636 int ret;
637
9e272677 638 mc13783 = kzalloc(sizeof(*mc13783), GFP_KERNEL);
8238addc
SH		 639 if (!mc13783)
640 return -ENOMEM;
641
642 dev_set_drvdata(&spi->dev, mc13783);
643 spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
644 spi->bits_per_word = 32;
645 spi_setup(spi);
646
9e272677
UKK		 647 mc13783->spidev = spi;
648
649 mutex_init(&mc13783->lock);
650 mc13783_lock(mc13783);
651
652 ret = mc13783_check_revision(mc13783);
653 if (ret)
654 goto err_revision;
655
656 /* mask all irqs */
657 ret = mc13783_reg_write(mc13783, MC13783_IRQMASK0, 0x00ffffff);
658 if (ret)
659 goto err_mask;
8238addc 660
9e272677
UKK		 661 ret = mc13783_reg_write(mc13783, MC13783_IRQMASK1, 0x00ffffff);
662 if (ret)
663 goto err_mask;
664
665 ret = request_threaded_irq(spi->irq, NULL, mc13783_irq_thread,
666 IRQF_ONESHOT | IRQF_TRIGGER_HIGH, "mc13783", mc13783);
667
668 if (ret) {
669err_mask:
670err_revision:
671 mutex_unlock(&mc13783->lock);
672 dev_set_drvdata(&spi->dev, NULL);
673 kfree(mc13783);
674 return ret;
675 }
8238addc 676
1e02b2c3
AP		 677 mc13783_unlock(mc13783);
678
9e272677
UKK		 679 if (pdata->flags & MC13783_USE_ADC)
680 mc13783_add_subdevice(mc13783, "mc13783-adc");
681
682 if (pdata->flags & MC13783_USE_CODEC)
683 mc13783_add_subdevice(mc13783, "mc13783-codec");
684
685 if (pdata->flags & MC13783_USE_REGULATOR) {
686 struct mc13783_regulator_platform_data regulator_pdata = {
687 .num_regulators = pdata->num_regulators,
688 .regulators = pdata->regulators,
689 };
690
691 mc13783_add_subdevice_pdata(mc13783, "mc13783-regulator",
692 &regulator_pdata, sizeof(regulator_pdata));
8238addc
SH		 693 }
694
9e272677
UKK		 695 if (pdata->flags & MC13783_USE_RTC)
696 mc13783_add_subdevice(mc13783, "mc13783-rtc");
8238addc 697
9e272677
UKK		 698 if (pdata->flags & MC13783_USE_TOUCHSCREEN)
699 mc13783_add_subdevice(mc13783, "mc13783-ts");
8238addc 700
7fdcef8a
PR		 701 if (pdata->flags & MC13783_USE_LED)
702 mc13783_add_subdevice_pdata(mc13783, "mc13783-led",
703 pdata->leds, sizeof(*pdata->leds));
704
8238addc 705 return 0;
8238addc
SH		 706}
707
708static int __devexit mc13783_remove(struct spi_device *spi)
709{
9e272677 710 struct mc13783 *mc13783 = dev_get_drvdata(&spi->dev);
8238addc 711
9e272677 712 free_irq(mc13783->spidev->irq, mc13783);
8238addc
SH		 713
714 mfd_remove_devices(&spi->dev);
715
716 return 0;
717}
718
9e272677 719static struct spi_driver mc13783_driver = {
8238addc 720 .driver = {
9e272677
UKK		 721 .name = "mc13783",
722 .bus = &spi_bus_type,
723 .owner = THIS_MODULE,
8238addc
SH		 724 },
725 .probe = mc13783_probe,
726 .remove = __devexit_p(mc13783_remove),
727};
728
9e272677 729static int __init mc13783_init(void)
8238addc 730{
9e272677 731 return spi_register_driver(&mc13783_driver);
8238addc 732}
9e272677 733subsys_initcall(mc13783_init);
8238addc 734
9e272677 735static void __exit mc13783_exit(void)
8238addc 736{
9e272677 737 spi_unregister_driver(&mc13783_driver);
8238addc 738}
9e272677 739module_exit(mc13783_exit);
8238addc 740
9e272677
UKK		 741MODULE_DESCRIPTION("Core driver for Freescale MC13783 PMIC");
742MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
743MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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