[deliverable/linux.git] / drivers / mfd / mcp-sa11x0.c

/*
 *  linux/drivers/mfd/mcp-sa11x0.c
 *
 *  Copyright (C) 2001-2005 Russell King
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License.
 *
 *  SA11x0 MCP (Multimedia Communications Port) driver.
 *
 *  MCP read/write timeouts from Jordi Colomer, rehacked by rmk.
 */
#include <linux/module.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/mfd/mcp.h>

#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/system.h>
#include <mach/mcp.h>

#include <mach/assabet.h>

#define DRIVER_NAME "sa11x0-mcp"

struct mcp_sa11x0 {
	void __iomem	*base0;
	void __iomem	*base1;
	u32		mccr0;
	u32		mccr1;
};

/* Register offsets */
#define MCCR0(m)	((m)->base0 + 0x00)
#define MCDR0(m)	((m)->base0 + 0x08)
#define MCDR1(m)	((m)->base0 + 0x0c)
#define MCDR2(m)	((m)->base0 + 0x10)
#define MCSR(m)		((m)->base0 + 0x18)
#define MCCR1(m)	((m)->base1 + 0x00)

#define priv(mcp)	((struct mcp_sa11x0 *)mcp_priv(mcp))

static void
mcp_sa11x0_set_telecom_divisor(struct mcp *mcp, unsigned int divisor)
{
	struct mcp_sa11x0 *m = priv(mcp);

	divisor /= 32;

	m->mccr0 &= ~0x00007f00;
	m->mccr0 |= divisor << 8;
	writel_relaxed(m->mccr0, MCCR0(m));
}

static void
mcp_sa11x0_set_audio_divisor(struct mcp *mcp, unsigned int divisor)
{
	struct mcp_sa11x0 *m = priv(mcp);

	divisor /= 32;

	m->mccr0 &= ~0x0000007f;
	m->mccr0 |= divisor;
	writel_relaxed(m->mccr0, MCCR0(m));
}

/*
 * Write data to the device.  The bit should be set after 3 subframe
 * times (each frame is 64 clocks).  We wait a maximum of 6 subframes.
 * We really should try doing something more productive while we
 * wait.
 */
static void
mcp_sa11x0_write(struct mcp *mcp, unsigned int reg, unsigned int val)
{
	struct mcp_sa11x0 *m = priv(mcp);
	int ret = -ETIME;
	int i;

	writel_relaxed(reg << 17 | MCDR2_Wr | (val & 0xffff), MCDR2(m));

	for (i = 0; i < 2; i++) {
		udelay(mcp->rw_timeout);
		if (readl_relaxed(MCSR(m)) & MCSR_CWC) {
			ret = 0;
			break;
		}
	}

	if (ret < 0)
		printk(KERN_WARNING "mcp: write timed out\n");
}

/*
 * Read data from the device.  The bit should be set after 3 subframe
 * times (each frame is 64 clocks).  We wait a maximum of 6 subframes.
 * We really should try doing something more productive while we
 * wait.
 */
static unsigned int
mcp_sa11x0_read(struct mcp *mcp, unsigned int reg)
{
	struct mcp_sa11x0 *m = priv(mcp);
	int ret = -ETIME;
	int i;

	writel_relaxed(reg << 17 | MCDR2_Rd, MCDR2(m));

	for (i = 0; i < 2; i++) {
		udelay(mcp->rw_timeout);
		if (readl_relaxed(MCSR(m)) & MCSR_CRC) {
			ret = readl_relaxed(MCDR2(m)) & 0xffff;
			break;
		}
	}

	if (ret < 0)
		printk(KERN_WARNING "mcp: read timed out\n");

	return ret;
}

static void mcp_sa11x0_enable(struct mcp *mcp)
{
	struct mcp_sa11x0 *m = priv(mcp);

	writel(-1, MCSR(m));
	m->mccr0 |= MCCR0_MCE;
	writel_relaxed(m->mccr0, MCCR0(m));
}

static void mcp_sa11x0_disable(struct mcp *mcp)
{
	struct mcp_sa11x0 *m = priv(mcp);

	m->mccr0 &= ~MCCR0_MCE;
	writel_relaxed(m->mccr0, MCCR0(m));
}

/*
 * Our methods.
 */
static struct mcp_ops mcp_sa11x0 = {
	.set_telecom_divisor	= mcp_sa11x0_set_telecom_divisor,
	.set_audio_divisor	= mcp_sa11x0_set_audio_divisor,
	.reg_write		= mcp_sa11x0_write,
	.reg_read		= mcp_sa11x0_read,
	.enable			= mcp_sa11x0_enable,
	.disable		= mcp_sa11x0_disable,
};

static int mcp_sa11x0_probe(struct platform_device *dev)
{
	struct mcp_plat_data *data = dev->dev.platform_data;
	struct resource *mem0, *mem1;
	struct mcp_sa11x0 *m;
	struct mcp *mcp;
	int ret;

	if (!data)
		return -ENODEV;

	mem0 = platform_get_resource(dev, IORESOURCE_MEM, 0);
	mem1 = platform_get_resource(dev, IORESOURCE_MEM, 1);
	if (!mem0 || !mem1)
		return -ENXIO;

	if (!request_mem_region(mem0->start, resource_size(mem0),
				DRIVER_NAME)) {
		ret = -EBUSY;
		goto err_mem0;
	}

	if (!request_mem_region(mem1->start, resource_size(mem1),
				DRIVER_NAME)) {
		ret = -EBUSY;
		goto err_mem1;
	}

	mcp = mcp_host_alloc(&dev->dev, sizeof(struct mcp_sa11x0));
	if (!mcp) {
		ret = -ENOMEM;
		goto err_alloc;
	}

	mcp->owner		= THIS_MODULE;
	mcp->ops		= &mcp_sa11x0;
	mcp->sclk_rate		= data->sclk_rate;

	m = priv(mcp);
	m->mccr0 = data->mccr0 | 0x7f7f;
	m->mccr1 = data->mccr1;

	m->base0 = ioremap(mem0->start, resource_size(mem0));
	m->base1 = ioremap(mem1->start, resource_size(mem1));
	if (!m->base0 || !m->base1) {
		ret = -ENOMEM;
		goto err_ioremap;
	}

	platform_set_drvdata(dev, mcp);

	if (machine_is_assabet()) {
		ASSABET_BCR_set(ASSABET_BCR_CODEC_RST);
	}

	/*
	 * Initialise device.  Note that we initially
	 * set the sampling rate to minimum.
	 */
	writel_relaxed(-1, MCSR(m));
	writel_relaxed(m->mccr1, MCCR1(m));
	writel_relaxed(m->mccr0, MCCR0(m));

	/*
	 * Calculate the read/write timeout (us) from the bit clock
	 * rate.  This is the period for 3 64-bit frames.  Always
	 * round this time up.
	 */
	mcp->rw_timeout = (64 * 3 * 1000000 + mcp->sclk_rate - 1) /
			  mcp->sclk_rate;

	ret = mcp_host_add(mcp, data->codec_pdata);
	if (ret == 0)
		return 0;

	platform_set_drvdata(dev, NULL);

 err_ioremap:
	iounmap(m->base1);
	iounmap(m->base0);
	mcp_host_free(mcp);
 err_alloc:
	release_mem_region(mem1->start, resource_size(mem1));
 err_mem1:
	release_mem_region(mem0->start, resource_size(mem0));
 err_mem0:
	return ret;
}

static int mcp_sa11x0_remove(struct platform_device *dev)
{
	struct mcp *mcp = platform_get_drvdata(dev);
	struct mcp_sa11x0 *m = priv(mcp);
	struct resource *mem0, *mem1;

	mem0 = platform_get_resource(dev, IORESOURCE_MEM, 0);
	mem1 = platform_get_resource(dev, IORESOURCE_MEM, 1);

	platform_set_drvdata(dev, NULL);
	mcp_host_del(mcp);
	iounmap(m->base1);
	iounmap(m->base0);
	mcp_host_free(mcp);
	release_mem_region(mem1->start, resource_size(mem1));
	release_mem_region(mem0->start, resource_size(mem0));

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int mcp_sa11x0_suspend(struct device *dev)
{
	struct mcp_sa11x0 *m = priv(dev_get_drvdata(dev));

	writel(m->mccr0 & ~MCCR0_MCE, MCCR0(m));

	return 0;
}

static int mcp_sa11x0_resume(struct device *dev)
{
	struct mcp_sa11x0 *m = priv(dev_get_drvdata(dev));

	writel_relaxed(m->mccr1, MCCR1(m));
	writel_relaxed(m->mccr0, MCCR0(m));

	return 0;
}
#endif

static const struct dev_pm_ops mcp_sa11x0_pm_ops = {
#ifdef CONFIG_PM_SLEEP
	.suspend = mcp_sa11x0_suspend,
	.freeze = mcp_sa11x0_suspend,
	.poweroff = mcp_sa11x0_suspend,
	.resume_noirq = mcp_sa11x0_resume,
	.thaw_noirq = mcp_sa11x0_resume,
	.restore_noirq = mcp_sa11x0_resume,
#endif
};

static struct platform_driver mcp_sa11x0_driver = {
	.probe		= mcp_sa11x0_probe,
	.remove		= mcp_sa11x0_remove,
	.driver		= {
		.name	= DRIVER_NAME,
		.owner	= THIS_MODULE,
		.pm	= &mcp_sa11x0_pm_ops,
	},
};

/*
 * This needs re-working
 */
module_platform_driver(mcp_sa11x0_driver);

MODULE_ALIAS("platform:" DRIVER_NAME);
MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
MODULE_DESCRIPTION("SA11x0 multimedia communications port driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
5e742ad6 RK	1	/*
	2	* linux/drivers/mfd/mcp-sa11x0.c
	3	*
	4	* Copyright (C) 2001-2005 Russell King
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License.
	9	*
	10	* SA11x0 MCP (Multimedia Communications Port) driver.
	11	*
	12	* MCP read/write timeouts from Jordi Colomer, rehacked by rmk.
	13	*/
	14	#include <linux/module.h>
	15	#include <linux/init.h>
45c7f75f	16	#include <linux/io.h>
5e742ad6 RK	17	#include <linux/errno.h>
	18	#include <linux/kernel.h>
	19	#include <linux/delay.h>
	20	#include <linux/spinlock.h>
d052d1be	21	#include <linux/platform_device.h>
2796e397	22	#include <linux/pm.h>
c8602edf	23	#include <linux/mfd/mcp.h>
5e742ad6	24
a09e64fb	25	#include <mach/hardware.h>
5e742ad6 RK	26	#include <asm/mach-types.h>
5e742ad6 RK	27	#include <asm/system.h>
a09e64fb	28	#include <mach/mcp.h>
5e742ad6	29
216f63c4 RK	30	#include <mach/assabet.h>
216f63c4 RK	31
c4592ce4	32	#define DRIVER_NAME "sa11x0-mcp"
5e742ad6 RK	33
5e742ad6 RK	34	struct mcp_sa11x0 {
45c7f75f RK	35	void __iomem *base0;
	36	void __iomem *base1;
	37	u32 mccr0;
	38	u32 mccr1;
5e742ad6 RK	39	};
5e742ad6 RK	40
45c7f75f RK	41	/* Register offsets */
	42	#define MCCR0(m) ((m)->base0 + 0x00)
	43	#define MCDR0(m) ((m)->base0 + 0x08)
	44	#define MCDR1(m) ((m)->base0 + 0x0c)
	45	#define MCDR2(m) ((m)->base0 + 0x10)
	46	#define MCSR(m) ((m)->base0 + 0x18)
	47	#define MCCR1(m) ((m)->base1 + 0x00)
	48
5e742ad6 RK	49	#define priv(mcp) ((struct mcp_sa11x0 *)mcp_priv(mcp))
	50
	51	static void
	52	mcp_sa11x0_set_telecom_divisor(struct mcp *mcp, unsigned int divisor)
	53	{
45c7f75f	54	struct mcp_sa11x0 *m = priv(mcp);
5e742ad6 RK	55
	56	divisor /= 32;
	57
45c7f75f RK	58	m->mccr0 &= ~0x00007f00;
	59	m->mccr0 \|= divisor << 8;
	60	writel_relaxed(m->mccr0, MCCR0(m));
5e742ad6 RK	61	}
	62
	63	static void
	64	mcp_sa11x0_set_audio_divisor(struct mcp *mcp, unsigned int divisor)
	65	{
45c7f75f	66	struct mcp_sa11x0 *m = priv(mcp);
5e742ad6 RK	67
	68	divisor /= 32;
	69
45c7f75f RK	70	m->mccr0 &= ~0x0000007f;
	71	m->mccr0 \|= divisor;
	72	writel_relaxed(m->mccr0, MCCR0(m));
5e742ad6 RK	73	}
	74
	75	/*
	76	* Write data to the device. The bit should be set after 3 subframe
	77	* times (each frame is 64 clocks). We wait a maximum of 6 subframes.
	78	* We really should try doing something more productive while we
	79	* wait.
	80	*/
	81	static void
	82	mcp_sa11x0_write(struct mcp *mcp, unsigned int reg, unsigned int val)
	83	{
45c7f75f	84	struct mcp_sa11x0 *m = priv(mcp);
5e742ad6 RK	85	int ret = -ETIME;
	86	int i;
	87
45c7f75f	88	writel_relaxed(reg << 17 \| MCDR2_Wr \| (val & 0xffff), MCDR2(m));
5e742ad6 RK	89
	90	for (i = 0; i < 2; i++) {
	91	udelay(mcp->rw_timeout);
45c7f75f	92	if (readl_relaxed(MCSR(m)) & MCSR_CWC) {
5e742ad6 RK	93	ret = 0;
	94	break;
	95	}
	96	}
	97
	98	if (ret < 0)
	99	printk(KERN_WARNING "mcp: write timed out\n");
	100	}
	101
	102	/*
	103	* Read data from the device. The bit should be set after 3 subframe
	104	* times (each frame is 64 clocks). We wait a maximum of 6 subframes.
	105	* We really should try doing something more productive while we
	106	* wait.
	107	*/
	108	static unsigned int
	109	mcp_sa11x0_read(struct mcp *mcp, unsigned int reg)
	110	{
45c7f75f	111	struct mcp_sa11x0 *m = priv(mcp);
5e742ad6 RK	112	int ret = -ETIME;
	113	int i;
	114
45c7f75f	115	writel_relaxed(reg << 17 \| MCDR2_Rd, MCDR2(m));
5e742ad6 RK	116
	117	for (i = 0; i < 2; i++) {
	118	udelay(mcp->rw_timeout);
45c7f75f RK	119	if (readl_relaxed(MCSR(m)) & MCSR_CRC) {
45c7f75f RK	120	ret = readl_relaxed(MCDR2(m)) & 0xffff;
5e742ad6 RK	121	break;
	122	}
	123	}
	124
	125	if (ret < 0)
	126	printk(KERN_WARNING "mcp: read timed out\n");
	127
	128	return ret;
	129	}
	130
	131	static void mcp_sa11x0_enable(struct mcp *mcp)
	132	{
45c7f75f RK	133	struct mcp_sa11x0 *m = priv(mcp);
	134
	135	writel(-1, MCSR(m));
	136	m->mccr0 \|= MCCR0_MCE;
	137	writel_relaxed(m->mccr0, MCCR0(m));
5e742ad6 RK	138	}
	139
	140	static void mcp_sa11x0_disable(struct mcp *mcp)
	141	{
45c7f75f RK	142	struct mcp_sa11x0 *m = priv(mcp);
	143
	144	m->mccr0 &= ~MCCR0_MCE;
	145	writel_relaxed(m->mccr0, MCCR0(m));
5e742ad6 RK	146	}
	147
	148	/*
	149	* Our methods.
	150	*/
	151	static struct mcp_ops mcp_sa11x0 = {
	152	.set_telecom_divisor = mcp_sa11x0_set_telecom_divisor,
	153	.set_audio_divisor = mcp_sa11x0_set_audio_divisor,
	154	.reg_write = mcp_sa11x0_write,
	155	.reg_read = mcp_sa11x0_read,
	156	.enable = mcp_sa11x0_enable,
	157	.disable = mcp_sa11x0_disable,
	158	};
	159
45c7f75f	160	static int mcp_sa11x0_probe(struct platform_device *dev)
5e742ad6	161	{
45c7f75f RK	162	struct mcp_plat_data *data = dev->dev.platform_data;
	163	struct resource mem0, mem1;
	164	struct mcp_sa11x0 *m;
5e742ad6 RK	165	struct mcp *mcp;
	166	int ret;
	167
323cdfc1	168	if (!data)
5e742ad6 RK	169	return -ENODEV;
5e742ad6 RK	170
45c7f75f RK	171	mem0 = platform_get_resource(dev, IORESOURCE_MEM, 0);
	172	mem1 = platform_get_resource(dev, IORESOURCE_MEM, 1);
	173	if (!mem0 \|\| !mem1)
	174	return -ENXIO;
	175
	176	if (!request_mem_region(mem0->start, resource_size(mem0),
	177	DRIVER_NAME)) {
	178	ret = -EBUSY;
	179	goto err_mem0;
	180	}
5e742ad6	181
45c7f75f RK	182	if (!request_mem_region(mem1->start, resource_size(mem1),
	183	DRIVER_NAME)) {
	184	ret = -EBUSY;
	185	goto err_mem1;
	186	}
	187
	188	mcp = mcp_host_alloc(&dev->dev, sizeof(struct mcp_sa11x0));
5e742ad6 RK	189	if (!mcp) {
5e742ad6 RK	190	ret = -ENOMEM;
45c7f75f	191	goto err_alloc;
5e742ad6 RK	192	}
	193
	194	mcp->owner = THIS_MODULE;
	195	mcp->ops = &mcp_sa11x0;
323cdfc1	196	mcp->sclk_rate = data->sclk_rate;
5e742ad6	197
45c7f75f RK	198	m = priv(mcp);
	199	m->mccr0 = data->mccr0 \| 0x7f7f;
	200	m->mccr1 = data->mccr1;
	201
	202	m->base0 = ioremap(mem0->start, resource_size(mem0));
	203	m->base1 = ioremap(mem1->start, resource_size(mem1));
	204	if (!m->base0 \|\| !m->base1) {
	205	ret = -ENOMEM;
	206	goto err_ioremap;
	207	}
	208
	209	platform_set_drvdata(dev, mcp);
5e742ad6	210
216f63c4 RK	211	if (machine_is_assabet()) {
	212	ASSABET_BCR_set(ASSABET_BCR_CODEC_RST);
	213	}
	214
323cdfc1 RK	215	/*
	216	* Initialise device. Note that we initially
	217	* set the sampling rate to minimum.
	218	*/
45c7f75f RK	219	writel_relaxed(-1, MCSR(m));
	220	writel_relaxed(m->mccr1, MCCR1(m));
	221	writel_relaxed(m->mccr0, MCCR0(m));
5e742ad6 RK	222
	223	/*
	224	* Calculate the read/write timeout (us) from the bit clock
	225	* rate. This is the period for 3 64-bit frames. Always
	226	* round this time up.
	227	*/
	228	mcp->rw_timeout = (64 * 3 * 1000000 + mcp->sclk_rate - 1) /
	229	mcp->sclk_rate;
	230
abe06082	231	ret = mcp_host_add(mcp, data->codec_pdata);
5e742ad6	232	if (ret == 0)
45c7f75f	233	return 0;
5e742ad6	234
45c7f75f	235	platform_set_drvdata(dev, NULL);
5e742ad6	236
45c7f75f RK	237	err_ioremap:
	238	iounmap(m->base1);
	239	iounmap(m->base0);
	240	mcp_host_free(mcp);
	241	err_alloc:
	242	release_mem_region(mem1->start, resource_size(mem1));
	243	err_mem1:
	244	release_mem_region(mem0->start, resource_size(mem0));
	245	err_mem0:
5e742ad6 RK	246	return ret;
	247	}
	248
216f63c4	249	static int mcp_sa11x0_remove(struct platform_device *dev)
5e742ad6	250	{
216f63c4	251	struct mcp *mcp = platform_get_drvdata(dev);
45c7f75f RK	252	struct mcp_sa11x0 *m = priv(mcp);
	253	struct resource mem0, mem1;
	254
	255	mem0 = platform_get_resource(dev, IORESOURCE_MEM, 0);
	256	mem1 = platform_get_resource(dev, IORESOURCE_MEM, 1);
5e742ad6	257
216f63c4	258	platform_set_drvdata(dev, NULL);
30816ac0	259	mcp_host_del(mcp);
45c7f75f RK	260	iounmap(m->base1);
45c7f75f RK	261	iounmap(m->base0);
30816ac0	262	mcp_host_free(mcp);
45c7f75f RK	263	release_mem_region(mem1->start, resource_size(mem1));
45c7f75f RK	264	release_mem_region(mem0->start, resource_size(mem0));
5e742ad6 RK	265
	266	return 0;
	267	}
	268
2796e397 RK	269	#ifdef CONFIG_PM_SLEEP
2796e397 RK	270	static int mcp_sa11x0_suspend(struct device *dev)
5e742ad6	271	{
2796e397	272	struct mcp_sa11x0 *m = priv(dev_get_drvdata(dev));
5e742ad6	273
45c7f75f	274	writel(m->mccr0 & ~MCCR0_MCE, MCCR0(m));
9480e307	275
5e742ad6 RK	276	return 0;
	277	}
	278
2796e397	279	static int mcp_sa11x0_resume(struct device *dev)
5e742ad6	280	{
2796e397	281	struct mcp_sa11x0 *m = priv(dev_get_drvdata(dev));
5e742ad6	282
45c7f75f RK	283	writel_relaxed(m->mccr1, MCCR1(m));
45c7f75f RK	284	writel_relaxed(m->mccr0, MCCR0(m));
9480e307	285
5e742ad6 RK	286	return 0;
5e742ad6 RK	287	}
2796e397 RK	288	#endif
	289
	290	static const struct dev_pm_ops mcp_sa11x0_pm_ops = {
a6aecae2 RK	291	#ifdef CONFIG_PM_SLEEP
	292	.suspend = mcp_sa11x0_suspend,
	293	.freeze = mcp_sa11x0_suspend,
	294	.poweroff = mcp_sa11x0_suspend,
	295	.resume_noirq = mcp_sa11x0_resume,
	296	.thaw_noirq = mcp_sa11x0_resume,
	297	.restore_noirq = mcp_sa11x0_resume,
	298	#endif
2796e397	299	};
5e742ad6	300
3ae5eaec	301	static struct platform_driver mcp_sa11x0_driver = {
5e742ad6 RK	302	.probe = mcp_sa11x0_probe,
5e742ad6 RK	303	.remove = mcp_sa11x0_remove,
3ae5eaec	304	.driver = {
c4592ce4 RK	305	.name = DRIVER_NAME,
c4592ce4 RK	306	.owner = THIS_MODULE,
2796e397	307	.pm = &mcp_sa11x0_pm_ops,
3ae5eaec	308	},
5e742ad6 RK	309	};
	310
	311	/*
	312	* This needs re-working
	313	*/
65349d60	314	module_platform_driver(mcp_sa11x0_driver);
5e742ad6	315
c4592ce4	316	MODULE_ALIAS("platform:" DRIVER_NAME);
5e742ad6 RK	317	MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
	318	MODULE_DESCRIPTION("SA11x0 multimedia communications port driver");
	319	MODULE_LICENSE("GPL");