[deliverable/linux.git] / drivers / mfd / mcp-sa11x0.c

/*
 *  linux/drivers/mfd/mcp-sa11x0.c
 *
 *  Copyright (C) 2001-2005 Russell King
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License.
 *
 *  SA11x0 MCP (Multimedia Communications Port) driver.
 *
 *  MCP read/write timeouts from Jordi Colomer, rehacked by rmk.
 */
#include <linux/module.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/mfd/mcp.h>
#include <linux/io.h>

#include <mach/dma.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/system.h>
#include <mach/mcp.h>

/* Register offsets */
#define MCCR0	0x00
#define MCDR0	0x08
#define MCDR1	0x0C
#define MCDR2	0x10
#define MCSR	0x18
#define MCCR1	0x00

struct mcp_sa11x0 {
	u32		mccr0;
	u32		mccr1;
	unsigned char	*mccr0_base;
	unsigned char	*mccr1_base;
};

#define priv(mcp)	((struct mcp_sa11x0 *)mcp_priv(mcp))

static void
mcp_sa11x0_set_telecom_divisor(struct mcp *mcp, unsigned int divisor)
{
	struct mcp_sa11x0 *priv = priv(mcp);

	divisor /= 32;

	priv->mccr0 &= ~0x00007f00;
	priv->mccr0 |= divisor << 8;
	__raw_writel(priv->mccr0, priv->mccr0_base + MCCR0);
}

static void
mcp_sa11x0_set_audio_divisor(struct mcp *mcp, unsigned int divisor)
{
	struct mcp_sa11x0 *priv = priv(mcp);

	divisor /= 32;

	priv->mccr0 &= ~0x0000007f;
	priv->mccr0 |= divisor;
	__raw_writel(priv->mccr0, priv->mccr0_base + MCCR0);
}

/*
 * Write data to the device.  The bit should be set after 3 subframe
 * times (each frame is 64 clocks).  We wait a maximum of 6 subframes.
 * We really should try doing something more productive while we
 * wait.
 */
static void
mcp_sa11x0_write(struct mcp *mcp, unsigned int reg, unsigned int val)
{
	int ret = -ETIME;
	int i;
	u32 mcpreg;
	struct mcp_sa11x0 *priv = priv(mcp);

	mcpreg = reg << 17 | MCDR2_Wr | (val & 0xffff);
	__raw_writel(mcpreg, priv->mccr0_base + MCDR2);

	for (i = 0; i < 2; i++) {
		udelay(mcp->rw_timeout);
		mcpreg = __raw_readl(priv->mccr0_base + MCSR);
		if (mcpreg & MCSR_CWC) {
			ret = 0;
			break;
		}
	}

	if (ret < 0)
		printk(KERN_WARNING "mcp: write timed out\n");
}

/*
 * Read data from the device.  The bit should be set after 3 subframe
 * times (each frame is 64 clocks).  We wait a maximum of 6 subframes.
 * We really should try doing something more productive while we
 * wait.
 */
static unsigned int
mcp_sa11x0_read(struct mcp *mcp, unsigned int reg)
{
	int ret = -ETIME;
	int i;
	u32 mcpreg;
	struct mcp_sa11x0 *priv = priv(mcp);

	mcpreg = reg << 17 | MCDR2_Rd;
	__raw_writel(mcpreg, priv->mccr0_base + MCDR2);

	for (i = 0; i < 2; i++) {
		udelay(mcp->rw_timeout);
		mcpreg = __raw_readl(priv->mccr0_base + MCSR);
		if (mcpreg & MCSR_CRC) {
			ret = __raw_readl(priv->mccr0_base + MCDR2)
				& 0xffff;
			break;
		}
	}

	if (ret < 0)
		printk(KERN_WARNING "mcp: read timed out\n");

	return ret;
}

static void mcp_sa11x0_enable(struct mcp *mcp)
{
	struct mcp_sa11x0 *priv = priv(mcp);

	__raw_writel(-1, priv->mccr0_base + MCSR);
	priv->mccr0 |= MCCR0_MCE;
	__raw_writel(priv->mccr0, priv->mccr0_base + MCCR0);
}

static void mcp_sa11x0_disable(struct mcp *mcp)
{
	struct mcp_sa11x0 *priv = priv(mcp);

	priv->mccr0 &= ~MCCR0_MCE;
	__raw_writel(priv->mccr0, priv->mccr0_base + MCCR0);
}

/*
 * Our methods.
 */
static struct mcp_ops mcp_sa11x0 = {
	.set_telecom_divisor	= mcp_sa11x0_set_telecom_divisor,
	.set_audio_divisor	= mcp_sa11x0_set_audio_divisor,
	.reg_write		= mcp_sa11x0_write,
	.reg_read		= mcp_sa11x0_read,
	.enable			= mcp_sa11x0_enable,
	.disable		= mcp_sa11x0_disable,
};

static int mcp_sa11x0_probe(struct platform_device *pdev)
{
	struct mcp_plat_data *data = pdev->dev.platform_data;
	struct mcp *mcp;
	int ret;
	struct mcp_sa11x0 *priv;
	struct resource *res_mem0, *res_mem1;
	u32 size0, size1;

	if (!data)
		return -ENODEV;

	if (!data->codec)
		return -ENODEV;

	res_mem0 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res_mem0)
		return -ENODEV;
	size0 = res_mem0->end - res_mem0->start + 1;

	res_mem1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (!res_mem1)
		return -ENODEV;
	size1 = res_mem1->end - res_mem1->start + 1;

	if (!request_mem_region(res_mem0->start, size0, "sa11x0-mcp"))
		return -EBUSY;

	if (!request_mem_region(res_mem1->start, size1, "sa11x0-mcp")) {
		ret = -EBUSY;
		goto release;
	}

	mcp = mcp_host_alloc(&pdev->dev, sizeof(struct mcp_sa11x0));
	if (!mcp) {
		ret = -ENOMEM;
		goto release2;
	}

	priv = priv(mcp);

	mcp->owner		= THIS_MODULE;
	mcp->ops		= &mcp_sa11x0;
	mcp->sclk_rate		= data->sclk_rate;
	mcp->dma_audio_rd	= DDAR_DevAdd(res_mem0->start + MCDR0)
				+ DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev;
	mcp->dma_audio_wr	= DDAR_DevAdd(res_mem0->start + MCDR0)
				+ DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev;
	mcp->dma_telco_rd	= DDAR_DevAdd(res_mem0->start + MCDR1)
				+ DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev;
	mcp->dma_telco_wr	= DDAR_DevAdd(res_mem0->start + MCDR1)
				+ DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev;
	mcp->codec		= data->codec;

	platform_set_drvdata(pdev, mcp);

	/*
	 * Initialise device.  Note that we initially
	 * set the sampling rate to minimum.
	 */
	priv->mccr0_base = ioremap(res_mem0->start, size0);
	priv->mccr1_base = ioremap(res_mem1->start, size1);

	__raw_writel(-1, priv->mccr0_base + MCSR);
	priv->mccr1 = data->mccr1;
	priv->mccr0 = data->mccr0 | 0x7f7f;
	__raw_writel(priv->mccr0, priv->mccr0_base + MCCR0);
	__raw_writel(priv->mccr1, priv->mccr1_base + MCCR1);

	/*
	 * Calculate the read/write timeout (us) from the bit clock
	 * rate.  This is the period for 3 64-bit frames.  Always
	 * round this time up.
	 */
	mcp->rw_timeout = (64 * 3 * 1000000 + mcp->sclk_rate - 1) /
			  mcp->sclk_rate;

	ret = mcp_host_register(mcp, data->codec_pdata);
	if (ret == 0)
		goto out;

 release2:
	release_mem_region(res_mem1->start, size1);
 release:
	release_mem_region(res_mem0->start, size0);
	platform_set_drvdata(pdev, NULL);

 out:
	return ret;
}

static int mcp_sa11x0_remove(struct platform_device *pdev)
{
	struct mcp *mcp = platform_get_drvdata(pdev);
	struct mcp_sa11x0 *priv = priv(mcp);
	struct resource *res_mem;
	u32 size;

	platform_set_drvdata(pdev, NULL);
	mcp_host_unregister(mcp);

	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (res_mem) {
		size = res_mem->end - res_mem->start + 1;
		release_mem_region(res_mem->start, size);
	}
	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (res_mem) {
		size = res_mem->end - res_mem->start + 1;
		release_mem_region(res_mem->start, size);
	}
	iounmap(priv->mccr0_base);
	iounmap(priv->mccr1_base);
	return 0;
}

static int mcp_sa11x0_suspend(struct platform_device *dev, pm_message_t state)
{
	struct mcp *mcp = platform_get_drvdata(dev);
	struct mcp_sa11x0 *priv = priv(mcp);
	u32 mccr0;

	mccr0 = priv->mccr0 & ~MCCR0_MCE;
	__raw_writel(mccr0, priv->mccr0_base + MCCR0);

	return 0;
}

static int mcp_sa11x0_resume(struct platform_device *dev)
{
	struct mcp *mcp = platform_get_drvdata(dev);
	struct mcp_sa11x0 *priv = priv(mcp);

	__raw_writel(priv->mccr0, priv->mccr0_base + MCCR0);
	__raw_writel(priv->mccr1, priv->mccr1_base + MCCR1);

	return 0;
}

/*
 * The driver for the SA11x0 MCP port.
 */
MODULE_ALIAS("platform:sa11x0-mcp");

static struct platform_driver mcp_sa11x0_driver = {
	.probe		= mcp_sa11x0_probe,
	.remove		= mcp_sa11x0_remove,
	.suspend	= mcp_sa11x0_suspend,
	.resume		= mcp_sa11x0_resume,
	.driver		= {
		.name	= "sa11x0-mcp",
		.owner  = THIS_MODULE,
	},
};

/*
 * This needs re-working
 */
module_platform_driver(mcp_sa11x0_driver);

MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
MODULE_DESCRIPTION("SA11x0 multimedia communications port driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
5e742ad6 RK	1	/*
	2	* linux/drivers/mfd/mcp-sa11x0.c
	3	*
	4	* Copyright (C) 2001-2005 Russell King
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License.
	9	*
	10	* SA11x0 MCP (Multimedia Communications Port) driver.
	11	*
	12	* MCP read/write timeouts from Jordi Colomer, rehacked by rmk.
	13	*/
	14	#include <linux/module.h>
	15	#include <linux/init.h>
	16	#include <linux/errno.h>
	17	#include <linux/kernel.h>
	18	#include <linux/delay.h>
	19	#include <linux/spinlock.h>
d052d1be	20	#include <linux/platform_device.h>
c8602edf	21	#include <linux/mfd/mcp.h>
af9081ae	22	#include <linux/io.h>
5e742ad6	23
dcea83ad	24	#include <mach/dma.h>
a09e64fb	25	#include <mach/hardware.h>
5e742ad6 RK	26	#include <asm/mach-types.h>
5e742ad6 RK	27	#include <asm/system.h>
a09e64fb	28	#include <mach/mcp.h>
5e742ad6	29
af9081ae JF	30	/* Register offsets */
	31	#define MCCR0 0x00
	32	#define MCDR0 0x08
	33	#define MCDR1 0x0C
	34	#define MCDR2 0x10
	35	#define MCSR 0x18
	36	#define MCCR1 0x00
5e742ad6 RK	37
5e742ad6 RK	38	struct mcp_sa11x0 {
af9081ae JF	39	u32 mccr0;
	40	u32 mccr1;
	41	unsigned char *mccr0_base;
	42	unsigned char *mccr1_base;
5e742ad6 RK	43	};
	44
	45	#define priv(mcp) ((struct mcp_sa11x0 *)mcp_priv(mcp))
	46
	47	static void
	48	mcp_sa11x0_set_telecom_divisor(struct mcp *mcp, unsigned int divisor)
	49	{
af9081ae	50	struct mcp_sa11x0 *priv = priv(mcp);
5e742ad6 RK	51
	52	divisor /= 32;
	53
af9081ae JF	54	priv->mccr0 &= ~0x00007f00;
	55	priv->mccr0 \|= divisor << 8;
	56	__raw_writel(priv->mccr0, priv->mccr0_base + MCCR0);
5e742ad6 RK	57	}
	58
	59	static void
	60	mcp_sa11x0_set_audio_divisor(struct mcp *mcp, unsigned int divisor)
	61	{
af9081ae	62	struct mcp_sa11x0 *priv = priv(mcp);
5e742ad6 RK	63
	64	divisor /= 32;
	65
af9081ae JF	66	priv->mccr0 &= ~0x0000007f;
	67	priv->mccr0 \|= divisor;
	68	__raw_writel(priv->mccr0, priv->mccr0_base + MCCR0);
5e742ad6 RK	69	}
	70
	71	/*
	72	* Write data to the device. The bit should be set after 3 subframe
	73	* times (each frame is 64 clocks). We wait a maximum of 6 subframes.
	74	* We really should try doing something more productive while we
	75	* wait.
	76	*/
	77	static void
	78	mcp_sa11x0_write(struct mcp *mcp, unsigned int reg, unsigned int val)
	79	{
	80	int ret = -ETIME;
	81	int i;
af9081ae JF	82	u32 mcpreg;
af9081ae JF	83	struct mcp_sa11x0 *priv = priv(mcp);
5e742ad6	84
af9081ae JF	85	mcpreg = reg << 17 \| MCDR2_Wr \| (val & 0xffff);
af9081ae JF	86	__raw_writel(mcpreg, priv->mccr0_base + MCDR2);
5e742ad6 RK	87
	88	for (i = 0; i < 2; i++) {
	89	udelay(mcp->rw_timeout);
af9081ae JF	90	mcpreg = __raw_readl(priv->mccr0_base + MCSR);
af9081ae JF	91	if (mcpreg & MCSR_CWC) {
5e742ad6 RK	92	ret = 0;
	93	break;
	94	}
	95	}
	96
	97	if (ret < 0)
	98	printk(KERN_WARNING "mcp: write timed out\n");
	99	}
	100
	101	/*
	102	* Read data from the device. The bit should be set after 3 subframe
	103	* times (each frame is 64 clocks). We wait a maximum of 6 subframes.
	104	* We really should try doing something more productive while we
	105	* wait.
	106	*/
	107	static unsigned int
	108	mcp_sa11x0_read(struct mcp *mcp, unsigned int reg)
	109	{
	110	int ret = -ETIME;
	111	int i;
af9081ae JF	112	u32 mcpreg;
af9081ae JF	113	struct mcp_sa11x0 *priv = priv(mcp);
5e742ad6	114
af9081ae JF	115	mcpreg = reg << 17 \| MCDR2_Rd;
af9081ae JF	116	__raw_writel(mcpreg, priv->mccr0_base + MCDR2);
5e742ad6 RK	117
	118	for (i = 0; i < 2; i++) {
	119	udelay(mcp->rw_timeout);
af9081ae JF	120	mcpreg = __raw_readl(priv->mccr0_base + MCSR);
	121	if (mcpreg & MCSR_CRC) {
	122	ret = __raw_readl(priv->mccr0_base + MCDR2)
	123	& 0xffff;
5e742ad6 RK	124	break;
	125	}
	126	}
	127
	128	if (ret < 0)
	129	printk(KERN_WARNING "mcp: read timed out\n");
	130
	131	return ret;
	132	}
	133
	134	static void mcp_sa11x0_enable(struct mcp *mcp)
	135	{
af9081ae JF	136	struct mcp_sa11x0 *priv = priv(mcp);
	137
	138	__raw_writel(-1, priv->mccr0_base + MCSR);
	139	priv->mccr0 \|= MCCR0_MCE;
	140	__raw_writel(priv->mccr0, priv->mccr0_base + MCCR0);
5e742ad6 RK	141	}
	142
	143	static void mcp_sa11x0_disable(struct mcp *mcp)
	144	{
af9081ae JF	145	struct mcp_sa11x0 *priv = priv(mcp);
	146
	147	priv->mccr0 &= ~MCCR0_MCE;
	148	__raw_writel(priv->mccr0, priv->mccr0_base + MCCR0);
5e742ad6 RK	149	}
	150
	151	/*
	152	* Our methods.
	153	*/
	154	static struct mcp_ops mcp_sa11x0 = {
	155	.set_telecom_divisor = mcp_sa11x0_set_telecom_divisor,
	156	.set_audio_divisor = mcp_sa11x0_set_audio_divisor,
	157	.reg_write = mcp_sa11x0_write,
	158	.reg_read = mcp_sa11x0_read,
	159	.enable = mcp_sa11x0_enable,
	160	.disable = mcp_sa11x0_disable,
	161	};
	162
3ae5eaec	163	static int mcp_sa11x0_probe(struct platform_device *pdev)
5e742ad6	164	{
323cdfc1	165	struct mcp_plat_data *data = pdev->dev.platform_data;
5e742ad6 RK	166	struct mcp *mcp;
5e742ad6 RK	167	int ret;
af9081ae JF	168	struct mcp_sa11x0 *priv;
	169	struct resource res_mem0, res_mem1;
	170	u32 size0, size1;
5e742ad6	171
323cdfc1	172	if (!data)
5e742ad6 RK	173	return -ENODEV;
5e742ad6 RK	174
5dd7bf59 JF	175	if (!data->codec)
	176	return -ENODEV;
	177
af9081ae JF	178	res_mem0 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	179	if (!res_mem0)
	180	return -ENODEV;
	181	size0 = res_mem0->end - res_mem0->start + 1;
	182
	183	res_mem1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	184	if (!res_mem1)
	185	return -ENODEV;
	186	size1 = res_mem1->end - res_mem1->start + 1;
	187
	188	if (!request_mem_region(res_mem0->start, size0, "sa11x0-mcp"))
5e742ad6 RK	189	return -EBUSY;
5e742ad6 RK	190
af9081ae JF	191	if (!request_mem_region(res_mem1->start, size1, "sa11x0-mcp")) {
	192	ret = -EBUSY;
	193	goto release;
	194	}
	195
5e742ad6 RK	196	mcp = mcp_host_alloc(&pdev->dev, sizeof(struct mcp_sa11x0));
	197	if (!mcp) {
	198	ret = -ENOMEM;
af9081ae	199	goto release2;
5e742ad6 RK	200	}
5e742ad6 RK	201
af9081ae JF	202	priv = priv(mcp);
af9081ae JF	203
5e742ad6 RK	204	mcp->owner = THIS_MODULE;
5e742ad6 RK	205	mcp->ops = &mcp_sa11x0;
323cdfc1	206	mcp->sclk_rate = data->sclk_rate;
af9081ae JF	207	mcp->dma_audio_rd = DDAR_DevAdd(res_mem0->start + MCDR0)
	208	+ DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev;
	209	mcp->dma_audio_wr = DDAR_DevAdd(res_mem0->start + MCDR0)
	210	+ DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev;
	211	mcp->dma_telco_rd = DDAR_DevAdd(res_mem0->start + MCDR1)
	212	+ DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev;
	213	mcp->dma_telco_wr = DDAR_DevAdd(res_mem0->start + MCDR1)
	214	+ DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev;
5dd7bf59	215	mcp->codec = data->codec;
5e742ad6	216
3ae5eaec	217	platform_set_drvdata(pdev, mcp);
5e742ad6	218
323cdfc1 RK	219	/*
	220	* Initialise device. Note that we initially
	221	* set the sampling rate to minimum.
	222	*/
af9081ae JF	223	priv->mccr0_base = ioremap(res_mem0->start, size0);
	224	priv->mccr1_base = ioremap(res_mem1->start, size1);
	225
	226	__raw_writel(-1, priv->mccr0_base + MCSR);
	227	priv->mccr1 = data->mccr1;
	228	priv->mccr0 = data->mccr0 \| 0x7f7f;
	229	__raw_writel(priv->mccr0, priv->mccr0_base + MCCR0);
	230	__raw_writel(priv->mccr1, priv->mccr1_base + MCCR1);
5e742ad6 RK	231
	232	/*
	233	* Calculate the read/write timeout (us) from the bit clock
	234	* rate. This is the period for 3 64-bit frames. Always
	235	* round this time up.
	236	*/
	237	mcp->rw_timeout = (64 * 3 * 1000000 + mcp->sclk_rate - 1) /
	238	mcp->sclk_rate;
	239
5dd7bf59	240	ret = mcp_host_register(mcp, data->codec_pdata);
5e742ad6 RK	241	if (ret == 0)
	242	goto out;
	243
af9081ae JF	244	release2:
af9081ae JF	245	release_mem_region(res_mem1->start, size1);
5e742ad6	246	release:
af9081ae	247	release_mem_region(res_mem0->start, size0);
3ae5eaec	248	platform_set_drvdata(pdev, NULL);
5e742ad6 RK	249
	250	out:
	251	return ret;
	252	}
	253
af9081ae	254	static int mcp_sa11x0_remove(struct platform_device *pdev)
5e742ad6	255	{
af9081ae JF	256	struct mcp *mcp = platform_get_drvdata(pdev);
	257	struct mcp_sa11x0 *priv = priv(mcp);
	258	struct resource *res_mem;
	259	u32 size;
5e742ad6	260
af9081ae	261	platform_set_drvdata(pdev, NULL);
5e742ad6	262	mcp_host_unregister(mcp);
5e742ad6	263
af9081ae JF	264	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	265	if (res_mem) {
	266	size = res_mem->end - res_mem->start + 1;
	267	release_mem_region(res_mem->start, size);
	268	}
	269	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	270	if (res_mem) {
	271	size = res_mem->end - res_mem->start + 1;
	272	release_mem_region(res_mem->start, size);
	273	}
	274	iounmap(priv->mccr0_base);
	275	iounmap(priv->mccr1_base);
5e742ad6 RK	276	return 0;
	277	}
	278
3ae5eaec	279	static int mcp_sa11x0_suspend(struct platform_device *dev, pm_message_t state)
5e742ad6	280	{
3ae5eaec	281	struct mcp *mcp = platform_get_drvdata(dev);
af9081ae JF	282	struct mcp_sa11x0 *priv = priv(mcp);
af9081ae JF	283	u32 mccr0;
5e742ad6	284
af9081ae JF	285	mccr0 = priv->mccr0 & ~MCCR0_MCE;
af9081ae JF	286	__raw_writel(mccr0, priv->mccr0_base + MCCR0);
9480e307	287
5e742ad6 RK	288	return 0;
	289	}
	290
3ae5eaec	291	static int mcp_sa11x0_resume(struct platform_device *dev)
5e742ad6	292	{
3ae5eaec	293	struct mcp *mcp = platform_get_drvdata(dev);
af9081ae	294	struct mcp_sa11x0 *priv = priv(mcp);
5e742ad6	295
af9081ae JF	296	__raw_writel(priv->mccr0, priv->mccr0_base + MCCR0);
af9081ae JF	297	__raw_writel(priv->mccr1, priv->mccr1_base + MCCR1);
9480e307	298
5e742ad6 RK	299	return 0;
	300	}
	301
	302	/*
	303	* The driver for the SA11x0 MCP port.
	304	*/
4f46d6e7 KS	305	MODULE_ALIAS("platform:sa11x0-mcp");
4f46d6e7 KS	306
3ae5eaec	307	static struct platform_driver mcp_sa11x0_driver = {
5e742ad6 RK	308	.probe = mcp_sa11x0_probe,
	309	.remove = mcp_sa11x0_remove,
	310	.suspend = mcp_sa11x0_suspend,
	311	.resume = mcp_sa11x0_resume,
3ae5eaec RK	312	.driver = {
3ae5eaec RK	313	.name = "sa11x0-mcp",
af9081ae	314	.owner = THIS_MODULE,
3ae5eaec	315	},
5e742ad6 RK	316	};
	317
	318	/*
	319	* This needs re-working
	320	*/
65349d60	321	module_platform_driver(mcp_sa11x0_driver);
5e742ad6 RK	322
	323	MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
	324	MODULE_DESCRIPTION("SA11x0 multimedia communications port driver");
	325	MODULE_LICENSE("GPL");