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17cdd29d KM |
1 | /** |
2 | * omap-usb-host.c - The USBHS core driver for OMAP EHCI & OHCI | |
3 | * | |
4 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com | |
5 | * Author: Keshava Munegowda <keshava_mgowda@ti.com> | |
6 | * | |
7 | * This program is free software: you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 of | |
9 | * the License as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | #include <linux/kernel.h> | |
417e206b | 20 | #include <linux/module.h> |
17cdd29d KM |
21 | #include <linux/types.h> |
22 | #include <linux/slab.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/clk.h> | |
26 | #include <linux/dma-mapping.h> | |
27 | #include <linux/spinlock.h> | |
28 | #include <linux/gpio.h> | |
17cdd29d KM |
29 | #include <plat/usb.h> |
30 | ||
31 | #define USBHS_DRIVER_NAME "usbhs-omap" | |
32 | #define OMAP_EHCI_DEVICE "ehci-omap" | |
33 | #define OMAP_OHCI_DEVICE "ohci-omap3" | |
34 | ||
35 | /* OMAP USBHOST Register addresses */ | |
36 | ||
37 | /* TLL Register Set */ | |
38 | #define OMAP_USBTLL_REVISION (0x00) | |
39 | #define OMAP_USBTLL_SYSCONFIG (0x10) | |
40 | #define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8) | |
41 | #define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3) | |
42 | #define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2) | |
43 | #define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1) | |
44 | #define OMAP_USBTLL_SYSCONFIG_AUTOIDLE (1 << 0) | |
45 | ||
46 | #define OMAP_USBTLL_SYSSTATUS (0x14) | |
47 | #define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0) | |
48 | ||
49 | #define OMAP_USBTLL_IRQSTATUS (0x18) | |
50 | #define OMAP_USBTLL_IRQENABLE (0x1C) | |
51 | ||
52 | #define OMAP_TLL_SHARED_CONF (0x30) | |
53 | #define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN (1 << 6) | |
54 | #define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN (1 << 5) | |
55 | #define OMAP_TLL_SHARED_CONF_USB_DIVRATION (1 << 2) | |
56 | #define OMAP_TLL_SHARED_CONF_FCLK_REQ (1 << 1) | |
57 | #define OMAP_TLL_SHARED_CONF_FCLK_IS_ON (1 << 0) | |
58 | ||
59 | #define OMAP_TLL_CHANNEL_CONF(num) (0x040 + 0x004 * num) | |
60 | #define OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT 24 | |
61 | #define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11) | |
62 | #define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE (1 << 10) | |
63 | #define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE (1 << 9) | |
64 | #define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE (1 << 8) | |
65 | #define OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS (1 << 1) | |
66 | #define OMAP_TLL_CHANNEL_CONF_CHANEN (1 << 0) | |
67 | ||
68 | #define OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0 0x0 | |
69 | #define OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM 0x1 | |
70 | #define OMAP_TLL_FSLSMODE_3PIN_PHY 0x2 | |
71 | #define OMAP_TLL_FSLSMODE_4PIN_PHY 0x3 | |
72 | #define OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0 0x4 | |
73 | #define OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM 0x5 | |
74 | #define OMAP_TLL_FSLSMODE_3PIN_TLL 0x6 | |
75 | #define OMAP_TLL_FSLSMODE_4PIN_TLL 0x7 | |
76 | #define OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0 0xA | |
77 | #define OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM 0xB | |
78 | ||
79 | #define OMAP_TLL_ULPI_FUNCTION_CTRL(num) (0x804 + 0x100 * num) | |
80 | #define OMAP_TLL_ULPI_INTERFACE_CTRL(num) (0x807 + 0x100 * num) | |
81 | #define OMAP_TLL_ULPI_OTG_CTRL(num) (0x80A + 0x100 * num) | |
82 | #define OMAP_TLL_ULPI_INT_EN_RISE(num) (0x80D + 0x100 * num) | |
83 | #define OMAP_TLL_ULPI_INT_EN_FALL(num) (0x810 + 0x100 * num) | |
84 | #define OMAP_TLL_ULPI_INT_STATUS(num) (0x813 + 0x100 * num) | |
85 | #define OMAP_TLL_ULPI_INT_LATCH(num) (0x814 + 0x100 * num) | |
86 | #define OMAP_TLL_ULPI_DEBUG(num) (0x815 + 0x100 * num) | |
87 | #define OMAP_TLL_ULPI_SCRATCH_REGISTER(num) (0x816 + 0x100 * num) | |
88 | ||
89 | #define OMAP_TLL_CHANNEL_COUNT 3 | |
90 | #define OMAP_TLL_CHANNEL_1_EN_MASK (1 << 0) | |
91 | #define OMAP_TLL_CHANNEL_2_EN_MASK (1 << 1) | |
92 | #define OMAP_TLL_CHANNEL_3_EN_MASK (1 << 2) | |
93 | ||
94 | /* UHH Register Set */ | |
95 | #define OMAP_UHH_REVISION (0x00) | |
96 | #define OMAP_UHH_SYSCONFIG (0x10) | |
97 | #define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12) | |
98 | #define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8) | |
99 | #define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3) | |
100 | #define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2) | |
101 | #define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1) | |
102 | #define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0) | |
103 | ||
104 | #define OMAP_UHH_SYSSTATUS (0x14) | |
105 | #define OMAP_UHH_HOSTCONFIG (0x40) | |
106 | #define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0) | |
107 | #define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0) | |
108 | #define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11) | |
109 | #define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12) | |
110 | #define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2) | |
111 | #define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3) | |
112 | #define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4) | |
113 | #define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5) | |
114 | #define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8) | |
115 | #define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9) | |
116 | #define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10) | |
117 | #define OMAP4_UHH_HOSTCONFIG_APP_START_CLK (1 << 31) | |
118 | ||
119 | /* OMAP4-specific defines */ | |
120 | #define OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR (3 << 2) | |
121 | #define OMAP4_UHH_SYSCONFIG_NOIDLE (1 << 2) | |
122 | #define OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR (3 << 4) | |
123 | #define OMAP4_UHH_SYSCONFIG_NOSTDBY (1 << 4) | |
124 | #define OMAP4_UHH_SYSCONFIG_SOFTRESET (1 << 0) | |
125 | ||
126 | #define OMAP4_P1_MODE_CLEAR (3 << 16) | |
127 | #define OMAP4_P1_MODE_TLL (1 << 16) | |
128 | #define OMAP4_P1_MODE_HSIC (3 << 16) | |
129 | #define OMAP4_P2_MODE_CLEAR (3 << 18) | |
130 | #define OMAP4_P2_MODE_TLL (1 << 18) | |
131 | #define OMAP4_P2_MODE_HSIC (3 << 18) | |
132 | ||
133 | #define OMAP_REV2_TLL_CHANNEL_COUNT 2 | |
134 | ||
135 | #define OMAP_UHH_DEBUG_CSR (0x44) | |
136 | ||
137 | /* Values of UHH_REVISION - Note: these are not given in the TRM */ | |
138 | #define OMAP_USBHS_REV1 0x00000010 /* OMAP3 */ | |
139 | #define OMAP_USBHS_REV2 0x50700100 /* OMAP4 */ | |
140 | ||
141 | #define is_omap_usbhs_rev1(x) (x->usbhs_rev == OMAP_USBHS_REV1) | |
142 | #define is_omap_usbhs_rev2(x) (x->usbhs_rev == OMAP_USBHS_REV2) | |
143 | ||
144 | #define is_ehci_phy_mode(x) (x == OMAP_EHCI_PORT_MODE_PHY) | |
145 | #define is_ehci_tll_mode(x) (x == OMAP_EHCI_PORT_MODE_TLL) | |
146 | #define is_ehci_hsic_mode(x) (x == OMAP_EHCI_PORT_MODE_HSIC) | |
147 | ||
148 | ||
149 | struct usbhs_hcd_omap { | |
8f2df014 KM |
150 | struct clk *usbhost_ick; |
151 | struct clk *usbhost_hs_fck; | |
152 | struct clk *usbhost_fs_fck; | |
17cdd29d KM |
153 | struct clk *xclk60mhsp1_ck; |
154 | struct clk *xclk60mhsp2_ck; | |
155 | struct clk *utmi_p1_fck; | |
156 | struct clk *usbhost_p1_fck; | |
157 | struct clk *usbtll_p1_fck; | |
158 | struct clk *utmi_p2_fck; | |
159 | struct clk *usbhost_p2_fck; | |
160 | struct clk *usbtll_p2_fck; | |
161 | struct clk *init_60m_fclk; | |
8f2df014 KM |
162 | struct clk *usbtll_fck; |
163 | struct clk *usbtll_ick; | |
17cdd29d KM |
164 | |
165 | void __iomem *uhh_base; | |
166 | void __iomem *tll_base; | |
167 | ||
168 | struct usbhs_omap_platform_data platdata; | |
169 | ||
170 | u32 usbhs_rev; | |
171 | spinlock_t lock; | |
172 | int count; | |
173 | }; | |
174 | /*-------------------------------------------------------------------------*/ | |
175 | ||
176 | const char usbhs_driver_name[] = USBHS_DRIVER_NAME; | |
177 | static u64 usbhs_dmamask = ~(u32)0; | |
178 | ||
179 | /*-------------------------------------------------------------------------*/ | |
180 | ||
181 | static inline void usbhs_write(void __iomem *base, u32 reg, u32 val) | |
182 | { | |
183 | __raw_writel(val, base + reg); | |
184 | } | |
185 | ||
186 | static inline u32 usbhs_read(void __iomem *base, u32 reg) | |
187 | { | |
188 | return __raw_readl(base + reg); | |
189 | } | |
190 | ||
191 | static inline void usbhs_writeb(void __iomem *base, u8 reg, u8 val) | |
192 | { | |
193 | __raw_writeb(val, base + reg); | |
194 | } | |
195 | ||
196 | static inline u8 usbhs_readb(void __iomem *base, u8 reg) | |
197 | { | |
198 | return __raw_readb(base + reg); | |
199 | } | |
200 | ||
201 | /*-------------------------------------------------------------------------*/ | |
202 | ||
203 | static struct platform_device *omap_usbhs_alloc_child(const char *name, | |
204 | struct resource *res, int num_resources, void *pdata, | |
205 | size_t pdata_size, struct device *dev) | |
206 | { | |
207 | struct platform_device *child; | |
208 | int ret; | |
209 | ||
210 | child = platform_device_alloc(name, 0); | |
211 | ||
212 | if (!child) { | |
213 | dev_err(dev, "platform_device_alloc %s failed\n", name); | |
214 | goto err_end; | |
215 | } | |
216 | ||
217 | ret = platform_device_add_resources(child, res, num_resources); | |
218 | if (ret) { | |
219 | dev_err(dev, "platform_device_add_resources failed\n"); | |
220 | goto err_alloc; | |
221 | } | |
222 | ||
223 | ret = platform_device_add_data(child, pdata, pdata_size); | |
224 | if (ret) { | |
225 | dev_err(dev, "platform_device_add_data failed\n"); | |
226 | goto err_alloc; | |
227 | } | |
228 | ||
229 | child->dev.dma_mask = &usbhs_dmamask; | |
230 | child->dev.coherent_dma_mask = 0xffffffff; | |
231 | child->dev.parent = dev; | |
232 | ||
233 | ret = platform_device_add(child); | |
234 | if (ret) { | |
235 | dev_err(dev, "platform_device_add failed\n"); | |
236 | goto err_alloc; | |
237 | } | |
238 | ||
239 | return child; | |
240 | ||
241 | err_alloc: | |
242 | platform_device_put(child); | |
243 | ||
244 | err_end: | |
245 | return NULL; | |
246 | } | |
247 | ||
248 | static int omap_usbhs_alloc_children(struct platform_device *pdev) | |
249 | { | |
250 | struct device *dev = &pdev->dev; | |
251 | struct usbhs_hcd_omap *omap; | |
252 | struct ehci_hcd_omap_platform_data *ehci_data; | |
253 | struct ohci_hcd_omap_platform_data *ohci_data; | |
254 | struct platform_device *ehci; | |
255 | struct platform_device *ohci; | |
256 | struct resource *res; | |
257 | struct resource resources[2]; | |
258 | int ret; | |
259 | ||
260 | omap = platform_get_drvdata(pdev); | |
261 | ehci_data = omap->platdata.ehci_data; | |
262 | ohci_data = omap->platdata.ohci_data; | |
263 | ||
264 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ehci"); | |
265 | if (!res) { | |
266 | dev_err(dev, "EHCI get resource IORESOURCE_MEM failed\n"); | |
267 | ret = -ENODEV; | |
268 | goto err_end; | |
269 | } | |
270 | resources[0] = *res; | |
271 | ||
272 | res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ehci-irq"); | |
273 | if (!res) { | |
274 | dev_err(dev, " EHCI get resource IORESOURCE_IRQ failed\n"); | |
275 | ret = -ENODEV; | |
276 | goto err_end; | |
277 | } | |
278 | resources[1] = *res; | |
279 | ||
280 | ehci = omap_usbhs_alloc_child(OMAP_EHCI_DEVICE, resources, 2, ehci_data, | |
281 | sizeof(*ehci_data), dev); | |
282 | ||
283 | if (!ehci) { | |
284 | dev_err(dev, "omap_usbhs_alloc_child failed\n"); | |
d910774f | 285 | ret = -ENOMEM; |
17cdd29d KM |
286 | goto err_end; |
287 | } | |
288 | ||
289 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ohci"); | |
290 | if (!res) { | |
291 | dev_err(dev, "OHCI get resource IORESOURCE_MEM failed\n"); | |
292 | ret = -ENODEV; | |
293 | goto err_ehci; | |
294 | } | |
295 | resources[0] = *res; | |
296 | ||
297 | res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ohci-irq"); | |
298 | if (!res) { | |
299 | dev_err(dev, "OHCI get resource IORESOURCE_IRQ failed\n"); | |
300 | ret = -ENODEV; | |
301 | goto err_ehci; | |
302 | } | |
303 | resources[1] = *res; | |
304 | ||
305 | ohci = omap_usbhs_alloc_child(OMAP_OHCI_DEVICE, resources, 2, ohci_data, | |
306 | sizeof(*ohci_data), dev); | |
307 | if (!ohci) { | |
308 | dev_err(dev, "omap_usbhs_alloc_child failed\n"); | |
d910774f | 309 | ret = -ENOMEM; |
17cdd29d KM |
310 | goto err_ehci; |
311 | } | |
312 | ||
313 | return 0; | |
314 | ||
315 | err_ehci: | |
d910774f | 316 | platform_device_unregister(ehci); |
17cdd29d KM |
317 | |
318 | err_end: | |
319 | return ret; | |
320 | } | |
321 | ||
322 | /** | |
323 | * usbhs_omap_probe - initialize TI-based HCDs | |
324 | * | |
325 | * Allocates basic resources for this USB host controller. | |
326 | */ | |
327 | static int __devinit usbhs_omap_probe(struct platform_device *pdev) | |
328 | { | |
329 | struct device *dev = &pdev->dev; | |
330 | struct usbhs_omap_platform_data *pdata = dev->platform_data; | |
331 | struct usbhs_hcd_omap *omap; | |
332 | struct resource *res; | |
333 | int ret = 0; | |
334 | int i; | |
335 | ||
336 | if (!pdata) { | |
25985edc | 337 | dev_err(dev, "Missing platform data\n"); |
17cdd29d KM |
338 | ret = -ENOMEM; |
339 | goto end_probe; | |
340 | } | |
341 | ||
342 | omap = kzalloc(sizeof(*omap), GFP_KERNEL); | |
343 | if (!omap) { | |
344 | dev_err(dev, "Memory allocation failed\n"); | |
345 | ret = -ENOMEM; | |
346 | goto end_probe; | |
347 | } | |
348 | ||
349 | spin_lock_init(&omap->lock); | |
350 | ||
351 | for (i = 0; i < OMAP3_HS_USB_PORTS; i++) | |
352 | omap->platdata.port_mode[i] = pdata->port_mode[i]; | |
353 | ||
354 | omap->platdata.ehci_data = pdata->ehci_data; | |
355 | omap->platdata.ohci_data = pdata->ohci_data; | |
356 | ||
8f2df014 KM |
357 | omap->usbhost_ick = clk_get(dev, "usbhost_ick"); |
358 | if (IS_ERR(omap->usbhost_ick)) { | |
359 | ret = PTR_ERR(omap->usbhost_ick); | |
360 | dev_err(dev, "usbhost_ick failed error:%d\n", ret); | |
361 | goto err_end; | |
362 | } | |
363 | ||
364 | omap->usbhost_hs_fck = clk_get(dev, "hs_fck"); | |
365 | if (IS_ERR(omap->usbhost_hs_fck)) { | |
366 | ret = PTR_ERR(omap->usbhost_hs_fck); | |
367 | dev_err(dev, "usbhost_hs_fck failed error:%d\n", ret); | |
368 | goto err_usbhost_ick; | |
369 | } | |
370 | ||
371 | omap->usbhost_fs_fck = clk_get(dev, "fs_fck"); | |
372 | if (IS_ERR(omap->usbhost_fs_fck)) { | |
373 | ret = PTR_ERR(omap->usbhost_fs_fck); | |
374 | dev_err(dev, "usbhost_fs_fck failed error:%d\n", ret); | |
375 | goto err_usbhost_hs_fck; | |
376 | } | |
377 | ||
378 | omap->usbtll_fck = clk_get(dev, "usbtll_fck"); | |
379 | if (IS_ERR(omap->usbtll_fck)) { | |
380 | ret = PTR_ERR(omap->usbtll_fck); | |
381 | dev_err(dev, "usbtll_fck failed error:%d\n", ret); | |
382 | goto err_usbhost_fs_fck; | |
383 | } | |
384 | ||
385 | omap->usbtll_ick = clk_get(dev, "usbtll_ick"); | |
386 | if (IS_ERR(omap->usbtll_ick)) { | |
387 | ret = PTR_ERR(omap->usbtll_ick); | |
388 | dev_err(dev, "usbtll_ick failed error:%d\n", ret); | |
389 | goto err_usbtll_fck; | |
390 | } | |
17cdd29d KM |
391 | |
392 | omap->utmi_p1_fck = clk_get(dev, "utmi_p1_gfclk"); | |
393 | if (IS_ERR(omap->utmi_p1_fck)) { | |
394 | ret = PTR_ERR(omap->utmi_p1_fck); | |
395 | dev_err(dev, "utmi_p1_gfclk failed error:%d\n", ret); | |
8f2df014 | 396 | goto err_usbtll_ick; |
17cdd29d KM |
397 | } |
398 | ||
399 | omap->xclk60mhsp1_ck = clk_get(dev, "xclk60mhsp1_ck"); | |
400 | if (IS_ERR(omap->xclk60mhsp1_ck)) { | |
401 | ret = PTR_ERR(omap->xclk60mhsp1_ck); | |
402 | dev_err(dev, "xclk60mhsp1_ck failed error:%d\n", ret); | |
403 | goto err_utmi_p1_fck; | |
404 | } | |
405 | ||
406 | omap->utmi_p2_fck = clk_get(dev, "utmi_p2_gfclk"); | |
407 | if (IS_ERR(omap->utmi_p2_fck)) { | |
408 | ret = PTR_ERR(omap->utmi_p2_fck); | |
409 | dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret); | |
410 | goto err_xclk60mhsp1_ck; | |
411 | } | |
412 | ||
413 | omap->xclk60mhsp2_ck = clk_get(dev, "xclk60mhsp2_ck"); | |
414 | if (IS_ERR(omap->xclk60mhsp2_ck)) { | |
415 | ret = PTR_ERR(omap->xclk60mhsp2_ck); | |
416 | dev_err(dev, "xclk60mhsp2_ck failed error:%d\n", ret); | |
417 | goto err_utmi_p2_fck; | |
418 | } | |
419 | ||
420 | omap->usbhost_p1_fck = clk_get(dev, "usb_host_hs_utmi_p1_clk"); | |
421 | if (IS_ERR(omap->usbhost_p1_fck)) { | |
422 | ret = PTR_ERR(omap->usbhost_p1_fck); | |
423 | dev_err(dev, "usbhost_p1_fck failed error:%d\n", ret); | |
424 | goto err_xclk60mhsp2_ck; | |
425 | } | |
426 | ||
427 | omap->usbtll_p1_fck = clk_get(dev, "usb_tll_hs_usb_ch0_clk"); | |
428 | if (IS_ERR(omap->usbtll_p1_fck)) { | |
429 | ret = PTR_ERR(omap->usbtll_p1_fck); | |
430 | dev_err(dev, "usbtll_p1_fck failed error:%d\n", ret); | |
431 | goto err_usbhost_p1_fck; | |
432 | } | |
433 | ||
434 | omap->usbhost_p2_fck = clk_get(dev, "usb_host_hs_utmi_p2_clk"); | |
435 | if (IS_ERR(omap->usbhost_p2_fck)) { | |
436 | ret = PTR_ERR(omap->usbhost_p2_fck); | |
437 | dev_err(dev, "usbhost_p2_fck failed error:%d\n", ret); | |
438 | goto err_usbtll_p1_fck; | |
439 | } | |
440 | ||
441 | omap->usbtll_p2_fck = clk_get(dev, "usb_tll_hs_usb_ch1_clk"); | |
442 | if (IS_ERR(omap->usbtll_p2_fck)) { | |
443 | ret = PTR_ERR(omap->usbtll_p2_fck); | |
444 | dev_err(dev, "usbtll_p2_fck failed error:%d\n", ret); | |
445 | goto err_usbhost_p2_fck; | |
446 | } | |
447 | ||
448 | omap->init_60m_fclk = clk_get(dev, "init_60m_fclk"); | |
449 | if (IS_ERR(omap->init_60m_fclk)) { | |
450 | ret = PTR_ERR(omap->init_60m_fclk); | |
451 | dev_err(dev, "init_60m_fclk failed error:%d\n", ret); | |
452 | goto err_usbtll_p2_fck; | |
453 | } | |
454 | ||
455 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "uhh"); | |
456 | if (!res) { | |
457 | dev_err(dev, "UHH EHCI get resource failed\n"); | |
458 | ret = -ENODEV; | |
459 | goto err_init_60m_fclk; | |
460 | } | |
461 | ||
462 | omap->uhh_base = ioremap(res->start, resource_size(res)); | |
463 | if (!omap->uhh_base) { | |
464 | dev_err(dev, "UHH ioremap failed\n"); | |
465 | ret = -ENOMEM; | |
466 | goto err_init_60m_fclk; | |
467 | } | |
468 | ||
469 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tll"); | |
470 | if (!res) { | |
471 | dev_err(dev, "UHH EHCI get resource failed\n"); | |
472 | ret = -ENODEV; | |
473 | goto err_tll; | |
474 | } | |
475 | ||
476 | omap->tll_base = ioremap(res->start, resource_size(res)); | |
477 | if (!omap->tll_base) { | |
478 | dev_err(dev, "TLL ioremap failed\n"); | |
479 | ret = -ENOMEM; | |
480 | goto err_tll; | |
481 | } | |
482 | ||
483 | platform_set_drvdata(pdev, omap); | |
484 | ||
485 | ret = omap_usbhs_alloc_children(pdev); | |
486 | if (ret) { | |
487 | dev_err(dev, "omap_usbhs_alloc_children failed\n"); | |
488 | goto err_alloc; | |
489 | } | |
490 | ||
491 | goto end_probe; | |
492 | ||
493 | err_alloc: | |
494 | iounmap(omap->tll_base); | |
495 | ||
496 | err_tll: | |
497 | iounmap(omap->uhh_base); | |
498 | ||
499 | err_init_60m_fclk: | |
500 | clk_put(omap->init_60m_fclk); | |
501 | ||
502 | err_usbtll_p2_fck: | |
503 | clk_put(omap->usbtll_p2_fck); | |
504 | ||
505 | err_usbhost_p2_fck: | |
506 | clk_put(omap->usbhost_p2_fck); | |
507 | ||
508 | err_usbtll_p1_fck: | |
509 | clk_put(omap->usbtll_p1_fck); | |
510 | ||
511 | err_usbhost_p1_fck: | |
512 | clk_put(omap->usbhost_p1_fck); | |
513 | ||
514 | err_xclk60mhsp2_ck: | |
515 | clk_put(omap->xclk60mhsp2_ck); | |
516 | ||
517 | err_utmi_p2_fck: | |
518 | clk_put(omap->utmi_p2_fck); | |
519 | ||
520 | err_xclk60mhsp1_ck: | |
521 | clk_put(omap->xclk60mhsp1_ck); | |
522 | ||
523 | err_utmi_p1_fck: | |
524 | clk_put(omap->utmi_p1_fck); | |
525 | ||
8f2df014 KM |
526 | err_usbtll_ick: |
527 | clk_put(omap->usbtll_ick); | |
528 | ||
529 | err_usbtll_fck: | |
530 | clk_put(omap->usbtll_fck); | |
531 | ||
532 | err_usbhost_fs_fck: | |
533 | clk_put(omap->usbhost_fs_fck); | |
534 | ||
535 | err_usbhost_hs_fck: | |
536 | clk_put(omap->usbhost_hs_fck); | |
537 | ||
538 | err_usbhost_ick: | |
539 | clk_put(omap->usbhost_ick); | |
540 | ||
17cdd29d KM |
541 | err_end: |
542 | kfree(omap); | |
543 | ||
544 | end_probe: | |
545 | return ret; | |
546 | } | |
547 | ||
548 | /** | |
549 | * usbhs_omap_remove - shutdown processing for UHH & TLL HCDs | |
550 | * @pdev: USB Host Controller being removed | |
551 | * | |
552 | * Reverses the effect of usbhs_omap_probe(). | |
553 | */ | |
554 | static int __devexit usbhs_omap_remove(struct platform_device *pdev) | |
555 | { | |
556 | struct usbhs_hcd_omap *omap = platform_get_drvdata(pdev); | |
557 | ||
558 | if (omap->count != 0) { | |
559 | dev_err(&pdev->dev, | |
560 | "Either EHCI or OHCI is still using usbhs core\n"); | |
561 | return -EBUSY; | |
562 | } | |
563 | ||
564 | iounmap(omap->tll_base); | |
565 | iounmap(omap->uhh_base); | |
566 | clk_put(omap->init_60m_fclk); | |
567 | clk_put(omap->usbtll_p2_fck); | |
568 | clk_put(omap->usbhost_p2_fck); | |
569 | clk_put(omap->usbtll_p1_fck); | |
570 | clk_put(omap->usbhost_p1_fck); | |
571 | clk_put(omap->xclk60mhsp2_ck); | |
572 | clk_put(omap->utmi_p2_fck); | |
573 | clk_put(omap->xclk60mhsp1_ck); | |
574 | clk_put(omap->utmi_p1_fck); | |
8f2df014 KM |
575 | clk_put(omap->usbtll_ick); |
576 | clk_put(omap->usbtll_fck); | |
577 | clk_put(omap->usbhost_fs_fck); | |
578 | clk_put(omap->usbhost_hs_fck); | |
579 | clk_put(omap->usbhost_ick); | |
17cdd29d KM |
580 | kfree(omap); |
581 | ||
582 | return 0; | |
583 | } | |
584 | ||
585 | static bool is_ohci_port(enum usbhs_omap_port_mode pmode) | |
586 | { | |
587 | switch (pmode) { | |
588 | case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0: | |
589 | case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM: | |
590 | case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0: | |
591 | case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM: | |
592 | case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0: | |
593 | case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM: | |
594 | case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0: | |
595 | case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM: | |
596 | case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0: | |
597 | case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM: | |
598 | return true; | |
599 | ||
600 | default: | |
601 | return false; | |
602 | } | |
603 | } | |
604 | ||
605 | /* | |
606 | * convert the port-mode enum to a value we can use in the FSLSMODE | |
607 | * field of USBTLL_CHANNEL_CONF | |
608 | */ | |
609 | static unsigned ohci_omap3_fslsmode(enum usbhs_omap_port_mode mode) | |
610 | { | |
611 | switch (mode) { | |
612 | case OMAP_USBHS_PORT_MODE_UNUSED: | |
613 | case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0: | |
614 | return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0; | |
615 | ||
616 | case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM: | |
617 | return OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM; | |
618 | ||
619 | case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0: | |
620 | return OMAP_TLL_FSLSMODE_3PIN_PHY; | |
621 | ||
622 | case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM: | |
623 | return OMAP_TLL_FSLSMODE_4PIN_PHY; | |
624 | ||
625 | case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0: | |
626 | return OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0; | |
627 | ||
628 | case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM: | |
629 | return OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM; | |
630 | ||
631 | case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0: | |
632 | return OMAP_TLL_FSLSMODE_3PIN_TLL; | |
633 | ||
634 | case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM: | |
635 | return OMAP_TLL_FSLSMODE_4PIN_TLL; | |
636 | ||
637 | case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0: | |
638 | return OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0; | |
639 | ||
640 | case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM: | |
641 | return OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM; | |
642 | default: | |
643 | pr_warning("Invalid port mode, using default\n"); | |
644 | return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0; | |
645 | } | |
646 | } | |
647 | ||
648 | static void usbhs_omap_tll_init(struct device *dev, u8 tll_channel_count) | |
649 | { | |
650 | struct usbhs_hcd_omap *omap = dev_get_drvdata(dev); | |
651 | struct usbhs_omap_platform_data *pdata = dev->platform_data; | |
652 | unsigned reg; | |
653 | int i; | |
654 | ||
655 | /* Program Common TLL register */ | |
656 | reg = usbhs_read(omap->tll_base, OMAP_TLL_SHARED_CONF); | |
657 | reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON | |
658 | | OMAP_TLL_SHARED_CONF_USB_DIVRATION); | |
659 | reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN; | |
660 | reg &= ~OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN; | |
661 | ||
662 | usbhs_write(omap->tll_base, OMAP_TLL_SHARED_CONF, reg); | |
663 | ||
664 | /* Enable channels now */ | |
665 | for (i = 0; i < tll_channel_count; i++) { | |
666 | reg = usbhs_read(omap->tll_base, | |
667 | OMAP_TLL_CHANNEL_CONF(i)); | |
668 | ||
669 | if (is_ohci_port(pdata->port_mode[i])) { | |
670 | reg |= ohci_omap3_fslsmode(pdata->port_mode[i]) | |
671 | << OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT; | |
672 | reg |= OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS; | |
673 | } else if (pdata->port_mode[i] == OMAP_EHCI_PORT_MODE_TLL) { | |
674 | ||
675 | /* Disable AutoIdle, BitStuffing and use SDR Mode */ | |
676 | reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE | |
677 | | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF | |
678 | | OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE); | |
679 | ||
17cdd29d KM |
680 | } else |
681 | continue; | |
682 | ||
683 | reg |= OMAP_TLL_CHANNEL_CONF_CHANEN; | |
684 | usbhs_write(omap->tll_base, | |
685 | OMAP_TLL_CHANNEL_CONF(i), reg); | |
686 | ||
687 | usbhs_writeb(omap->tll_base, | |
688 | OMAP_TLL_ULPI_SCRATCH_REGISTER(i), 0xbe); | |
689 | } | |
690 | } | |
691 | ||
692 | static int usbhs_enable(struct device *dev) | |
693 | { | |
694 | struct usbhs_hcd_omap *omap = dev_get_drvdata(dev); | |
695 | struct usbhs_omap_platform_data *pdata = &omap->platdata; | |
696 | unsigned long flags = 0; | |
697 | int ret = 0; | |
8f2df014 | 698 | unsigned long timeout; |
17cdd29d KM |
699 | unsigned reg; |
700 | ||
701 | dev_dbg(dev, "starting TI HSUSB Controller\n"); | |
702 | if (!pdata) { | |
703 | dev_dbg(dev, "missing platform_data\n"); | |
d11536e4 | 704 | return -ENODEV; |
17cdd29d KM |
705 | } |
706 | ||
707 | spin_lock_irqsave(&omap->lock, flags); | |
708 | if (omap->count > 0) | |
709 | goto end_count; | |
710 | ||
8f2df014 KM |
711 | clk_enable(omap->usbhost_ick); |
712 | clk_enable(omap->usbhost_hs_fck); | |
713 | clk_enable(omap->usbhost_fs_fck); | |
714 | clk_enable(omap->usbtll_fck); | |
715 | clk_enable(omap->usbtll_ick); | |
17cdd29d KM |
716 | |
717 | if (pdata->ehci_data->phy_reset) { | |
718 | if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) { | |
719 | gpio_request(pdata->ehci_data->reset_gpio_port[0], | |
720 | "USB1 PHY reset"); | |
721 | gpio_direction_output | |
557f447f | 722 | (pdata->ehci_data->reset_gpio_port[0], 0); |
17cdd29d KM |
723 | } |
724 | ||
725 | if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) { | |
726 | gpio_request(pdata->ehci_data->reset_gpio_port[1], | |
727 | "USB2 PHY reset"); | |
728 | gpio_direction_output | |
557f447f | 729 | (pdata->ehci_data->reset_gpio_port[1], 0); |
17cdd29d KM |
730 | } |
731 | ||
732 | /* Hold the PHY in RESET for enough time till DIR is high */ | |
733 | udelay(10); | |
734 | } | |
735 | ||
736 | omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION); | |
737 | dev_dbg(dev, "OMAP UHH_REVISION 0x%x\n", omap->usbhs_rev); | |
738 | ||
8f2df014 KM |
739 | /* perform TLL soft reset, and wait until reset is complete */ |
740 | usbhs_write(omap->tll_base, OMAP_USBTLL_SYSCONFIG, | |
741 | OMAP_USBTLL_SYSCONFIG_SOFTRESET); | |
742 | ||
743 | /* Wait for TLL reset to complete */ | |
744 | timeout = jiffies + msecs_to_jiffies(1000); | |
745 | while (!(usbhs_read(omap->tll_base, OMAP_USBTLL_SYSSTATUS) | |
746 | & OMAP_USBTLL_SYSSTATUS_RESETDONE)) { | |
747 | cpu_relax(); | |
748 | ||
749 | if (time_after(jiffies, timeout)) { | |
750 | dev_dbg(dev, "operation timed out\n"); | |
751 | ret = -EINVAL; | |
752 | goto err_tll; | |
753 | } | |
754 | } | |
755 | ||
756 | dev_dbg(dev, "TLL RESET DONE\n"); | |
757 | ||
758 | /* (1<<3) = no idle mode only for initial debugging */ | |
759 | usbhs_write(omap->tll_base, OMAP_USBTLL_SYSCONFIG, | |
760 | OMAP_USBTLL_SYSCONFIG_ENAWAKEUP | | |
761 | OMAP_USBTLL_SYSCONFIG_SIDLEMODE | | |
762 | OMAP_USBTLL_SYSCONFIG_AUTOIDLE); | |
763 | ||
764 | /* Put UHH in NoIdle/NoStandby mode */ | |
765 | reg = usbhs_read(omap->uhh_base, OMAP_UHH_SYSCONFIG); | |
766 | if (is_omap_usbhs_rev1(omap)) { | |
767 | reg |= (OMAP_UHH_SYSCONFIG_ENAWAKEUP | |
768 | | OMAP_UHH_SYSCONFIG_SIDLEMODE | |
769 | | OMAP_UHH_SYSCONFIG_CACTIVITY | |
770 | | OMAP_UHH_SYSCONFIG_MIDLEMODE); | |
771 | reg &= ~OMAP_UHH_SYSCONFIG_AUTOIDLE; | |
772 | ||
773 | ||
774 | } else if (is_omap_usbhs_rev2(omap)) { | |
775 | reg &= ~OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR; | |
776 | reg |= OMAP4_UHH_SYSCONFIG_NOIDLE; | |
777 | reg &= ~OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR; | |
778 | reg |= OMAP4_UHH_SYSCONFIG_NOSTDBY; | |
779 | } | |
780 | ||
781 | usbhs_write(omap->uhh_base, OMAP_UHH_SYSCONFIG, reg); | |
782 | ||
17cdd29d KM |
783 | reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG); |
784 | /* setup ULPI bypass and burst configurations */ | |
785 | reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN | |
786 | | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN | |
787 | | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN); | |
788 | reg |= OMAP4_UHH_HOSTCONFIG_APP_START_CLK; | |
789 | reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN; | |
790 | ||
791 | if (is_omap_usbhs_rev1(omap)) { | |
792 | if (pdata->port_mode[0] == OMAP_USBHS_PORT_MODE_UNUSED) | |
793 | reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS; | |
794 | if (pdata->port_mode[1] == OMAP_USBHS_PORT_MODE_UNUSED) | |
795 | reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS; | |
796 | if (pdata->port_mode[2] == OMAP_USBHS_PORT_MODE_UNUSED) | |
797 | reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS; | |
798 | ||
799 | /* Bypass the TLL module for PHY mode operation */ | |
800 | if (cpu_is_omap3430() && (omap_rev() <= OMAP3430_REV_ES2_1)) { | |
801 | dev_dbg(dev, "OMAP3 ES version <= ES2.1\n"); | |
802 | if (is_ehci_phy_mode(pdata->port_mode[0]) || | |
803 | is_ehci_phy_mode(pdata->port_mode[1]) || | |
804 | is_ehci_phy_mode(pdata->port_mode[2])) | |
805 | reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; | |
806 | else | |
807 | reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; | |
808 | } else { | |
809 | dev_dbg(dev, "OMAP3 ES version > ES2.1\n"); | |
810 | if (is_ehci_phy_mode(pdata->port_mode[0])) | |
811 | reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; | |
812 | else | |
813 | reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; | |
814 | if (is_ehci_phy_mode(pdata->port_mode[1])) | |
815 | reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS; | |
816 | else | |
817 | reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS; | |
818 | if (is_ehci_phy_mode(pdata->port_mode[2])) | |
819 | reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS; | |
820 | else | |
821 | reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS; | |
822 | } | |
823 | } else if (is_omap_usbhs_rev2(omap)) { | |
824 | /* Clear port mode fields for PHY mode*/ | |
825 | reg &= ~OMAP4_P1_MODE_CLEAR; | |
826 | reg &= ~OMAP4_P2_MODE_CLEAR; | |
827 | ||
828 | if (is_ehci_phy_mode(pdata->port_mode[0])) { | |
829 | ret = clk_set_parent(omap->utmi_p1_fck, | |
830 | omap->xclk60mhsp1_ck); | |
831 | if (ret != 0) { | |
832 | dev_err(dev, "xclk60mhsp1_ck set parent" | |
833 | "failed error:%d\n", ret); | |
834 | goto err_tll; | |
835 | } | |
836 | } else if (is_ehci_tll_mode(pdata->port_mode[0])) { | |
837 | ret = clk_set_parent(omap->utmi_p1_fck, | |
838 | omap->init_60m_fclk); | |
839 | if (ret != 0) { | |
840 | dev_err(dev, "init_60m_fclk set parent" | |
841 | "failed error:%d\n", ret); | |
842 | goto err_tll; | |
843 | } | |
844 | clk_enable(omap->usbhost_p1_fck); | |
845 | clk_enable(omap->usbtll_p1_fck); | |
846 | } | |
847 | ||
848 | if (is_ehci_phy_mode(pdata->port_mode[1])) { | |
849 | ret = clk_set_parent(omap->utmi_p2_fck, | |
850 | omap->xclk60mhsp2_ck); | |
851 | if (ret != 0) { | |
852 | dev_err(dev, "xclk60mhsp1_ck set parent" | |
853 | "failed error:%d\n", ret); | |
854 | goto err_tll; | |
855 | } | |
856 | } else if (is_ehci_tll_mode(pdata->port_mode[1])) { | |
857 | ret = clk_set_parent(omap->utmi_p2_fck, | |
858 | omap->init_60m_fclk); | |
859 | if (ret != 0) { | |
860 | dev_err(dev, "init_60m_fclk set parent" | |
861 | "failed error:%d\n", ret); | |
862 | goto err_tll; | |
863 | } | |
864 | clk_enable(omap->usbhost_p2_fck); | |
865 | clk_enable(omap->usbtll_p2_fck); | |
866 | } | |
867 | ||
868 | clk_enable(omap->utmi_p1_fck); | |
869 | clk_enable(omap->utmi_p2_fck); | |
870 | ||
871 | if (is_ehci_tll_mode(pdata->port_mode[0]) || | |
872 | (is_ohci_port(pdata->port_mode[0]))) | |
873 | reg |= OMAP4_P1_MODE_TLL; | |
874 | else if (is_ehci_hsic_mode(pdata->port_mode[0])) | |
875 | reg |= OMAP4_P1_MODE_HSIC; | |
876 | ||
877 | if (is_ehci_tll_mode(pdata->port_mode[1]) || | |
878 | (is_ohci_port(pdata->port_mode[1]))) | |
879 | reg |= OMAP4_P2_MODE_TLL; | |
880 | else if (is_ehci_hsic_mode(pdata->port_mode[1])) | |
881 | reg |= OMAP4_P2_MODE_HSIC; | |
882 | } | |
883 | ||
884 | usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg); | |
885 | dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg); | |
886 | ||
887 | if (is_ehci_tll_mode(pdata->port_mode[0]) || | |
888 | is_ehci_tll_mode(pdata->port_mode[1]) || | |
889 | is_ehci_tll_mode(pdata->port_mode[2]) || | |
890 | (is_ohci_port(pdata->port_mode[0])) || | |
891 | (is_ohci_port(pdata->port_mode[1])) || | |
892 | (is_ohci_port(pdata->port_mode[2]))) { | |
893 | ||
894 | /* Enable UTMI mode for required TLL channels */ | |
895 | if (is_omap_usbhs_rev2(omap)) | |
896 | usbhs_omap_tll_init(dev, OMAP_REV2_TLL_CHANNEL_COUNT); | |
897 | else | |
898 | usbhs_omap_tll_init(dev, OMAP_TLL_CHANNEL_COUNT); | |
899 | } | |
900 | ||
901 | if (pdata->ehci_data->phy_reset) { | |
902 | /* Hold the PHY in RESET for enough time till | |
903 | * PHY is settled and ready | |
904 | */ | |
905 | udelay(10); | |
906 | ||
907 | if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) | |
908 | gpio_set_value | |
557f447f | 909 | (pdata->ehci_data->reset_gpio_port[0], 1); |
17cdd29d KM |
910 | |
911 | if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) | |
912 | gpio_set_value | |
557f447f | 913 | (pdata->ehci_data->reset_gpio_port[1], 1); |
17cdd29d KM |
914 | } |
915 | ||
916 | end_count: | |
917 | omap->count++; | |
d11536e4 AL |
918 | spin_unlock_irqrestore(&omap->lock, flags); |
919 | return 0; | |
17cdd29d KM |
920 | |
921 | err_tll: | |
922 | if (pdata->ehci_data->phy_reset) { | |
923 | if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) | |
924 | gpio_free(pdata->ehci_data->reset_gpio_port[0]); | |
925 | ||
926 | if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) | |
927 | gpio_free(pdata->ehci_data->reset_gpio_port[1]); | |
928 | } | |
8f2df014 KM |
929 | |
930 | clk_disable(omap->usbtll_ick); | |
931 | clk_disable(omap->usbtll_fck); | |
932 | clk_disable(omap->usbhost_fs_fck); | |
933 | clk_disable(omap->usbhost_hs_fck); | |
934 | clk_disable(omap->usbhost_ick); | |
935 | spin_unlock_irqrestore(&omap->lock, flags); | |
17cdd29d KM |
936 | return ret; |
937 | } | |
938 | ||
939 | static void usbhs_disable(struct device *dev) | |
940 | { | |
941 | struct usbhs_hcd_omap *omap = dev_get_drvdata(dev); | |
942 | struct usbhs_omap_platform_data *pdata = &omap->platdata; | |
943 | unsigned long flags = 0; | |
944 | unsigned long timeout; | |
945 | ||
946 | dev_dbg(dev, "stopping TI HSUSB Controller\n"); | |
947 | ||
948 | spin_lock_irqsave(&omap->lock, flags); | |
949 | ||
950 | if (omap->count == 0) | |
951 | goto end_disble; | |
952 | ||
953 | omap->count--; | |
954 | ||
955 | if (omap->count != 0) | |
956 | goto end_disble; | |
957 | ||
958 | /* Reset OMAP modules for insmod/rmmod to work */ | |
959 | usbhs_write(omap->uhh_base, OMAP_UHH_SYSCONFIG, | |
960 | is_omap_usbhs_rev2(omap) ? | |
961 | OMAP4_UHH_SYSCONFIG_SOFTRESET : | |
962 | OMAP_UHH_SYSCONFIG_SOFTRESET); | |
963 | ||
964 | timeout = jiffies + msecs_to_jiffies(100); | |
965 | while (!(usbhs_read(omap->uhh_base, OMAP_UHH_SYSSTATUS) | |
966 | & (1 << 0))) { | |
967 | cpu_relax(); | |
968 | ||
969 | if (time_after(jiffies, timeout)) | |
970 | dev_dbg(dev, "operation timed out\n"); | |
971 | } | |
972 | ||
973 | while (!(usbhs_read(omap->uhh_base, OMAP_UHH_SYSSTATUS) | |
974 | & (1 << 1))) { | |
975 | cpu_relax(); | |
976 | ||
977 | if (time_after(jiffies, timeout)) | |
978 | dev_dbg(dev, "operation timed out\n"); | |
979 | } | |
980 | ||
981 | while (!(usbhs_read(omap->uhh_base, OMAP_UHH_SYSSTATUS) | |
982 | & (1 << 2))) { | |
983 | cpu_relax(); | |
984 | ||
985 | if (time_after(jiffies, timeout)) | |
986 | dev_dbg(dev, "operation timed out\n"); | |
987 | } | |
988 | ||
989 | usbhs_write(omap->tll_base, OMAP_USBTLL_SYSCONFIG, (1 << 1)); | |
990 | ||
991 | while (!(usbhs_read(omap->tll_base, OMAP_USBTLL_SYSSTATUS) | |
992 | & (1 << 0))) { | |
993 | cpu_relax(); | |
994 | ||
995 | if (time_after(jiffies, timeout)) | |
996 | dev_dbg(dev, "operation timed out\n"); | |
997 | } | |
998 | ||
6eb6fbbf KM |
999 | if (is_omap_usbhs_rev2(omap)) { |
1000 | if (is_ehci_tll_mode(pdata->port_mode[0])) | |
e2e49d57 | 1001 | clk_disable(omap->usbtll_p1_fck); |
6eb6fbbf | 1002 | if (is_ehci_tll_mode(pdata->port_mode[1])) |
e2e49d57 | 1003 | clk_disable(omap->usbtll_p2_fck); |
6eb6fbbf KM |
1004 | clk_disable(omap->utmi_p2_fck); |
1005 | clk_disable(omap->utmi_p1_fck); | |
17cdd29d KM |
1006 | } |
1007 | ||
8f2df014 KM |
1008 | clk_disable(omap->usbtll_ick); |
1009 | clk_disable(omap->usbtll_fck); | |
1010 | clk_disable(omap->usbhost_fs_fck); | |
1011 | clk_disable(omap->usbhost_hs_fck); | |
1012 | clk_disable(omap->usbhost_ick); | |
17cdd29d | 1013 | |
6eb6fbbf KM |
1014 | /* The gpio_free migh sleep; so unlock the spinlock */ |
1015 | spin_unlock_irqrestore(&omap->lock, flags); | |
1016 | ||
1017 | if (pdata->ehci_data->phy_reset) { | |
1018 | if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) | |
1019 | gpio_free(pdata->ehci_data->reset_gpio_port[0]); | |
1020 | ||
1021 | if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) | |
1022 | gpio_free(pdata->ehci_data->reset_gpio_port[1]); | |
1023 | } | |
1024 | return; | |
1025 | ||
17cdd29d KM |
1026 | end_disble: |
1027 | spin_unlock_irqrestore(&omap->lock, flags); | |
1028 | } | |
1029 | ||
1030 | int omap_usbhs_enable(struct device *dev) | |
1031 | { | |
1032 | return usbhs_enable(dev->parent); | |
1033 | } | |
1034 | EXPORT_SYMBOL_GPL(omap_usbhs_enable); | |
1035 | ||
1036 | void omap_usbhs_disable(struct device *dev) | |
1037 | { | |
1038 | usbhs_disable(dev->parent); | |
1039 | } | |
1040 | EXPORT_SYMBOL_GPL(omap_usbhs_disable); | |
1041 | ||
1042 | static struct platform_driver usbhs_omap_driver = { | |
1043 | .driver = { | |
1044 | .name = (char *)usbhs_driver_name, | |
1045 | .owner = THIS_MODULE, | |
1046 | }, | |
1047 | .remove = __exit_p(usbhs_omap_remove), | |
1048 | }; | |
1049 | ||
1050 | MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>"); | |
1051 | MODULE_ALIAS("platform:" USBHS_DRIVER_NAME); | |
1052 | MODULE_LICENSE("GPL v2"); | |
1053 | MODULE_DESCRIPTION("usb host common core driver for omap EHCI and OHCI"); | |
1054 | ||
1055 | static int __init omap_usbhs_drvinit(void) | |
1056 | { | |
1057 | return platform_driver_probe(&usbhs_omap_driver, usbhs_omap_probe); | |
1058 | } | |
1059 | ||
1060 | /* | |
1061 | * init before ehci and ohci drivers; | |
1062 | * The usbhs core driver should be initialized much before | |
1063 | * the omap ehci and ohci probe functions are called. | |
1064 | */ | |
1065 | fs_initcall(omap_usbhs_drvinit); | |
1066 | ||
1067 | static void __exit omap_usbhs_drvexit(void) | |
1068 | { | |
1069 | platform_driver_unregister(&usbhs_omap_driver); | |
1070 | } | |
1071 | module_exit(omap_usbhs_drvexit); |