Commit | Line | Data |
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cbdb53e1 AD |
1 | /* |
2 | * Copyright (c) 2011, Code Aurora Forum. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 and | |
6 | * only version 2 as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | #define pr_fmt(fmt) "%s: " fmt, __func__ | |
15 | ||
16 | #include <linux/kernel.h> | |
bc866fc7 | 17 | #include <linux/interrupt.h> |
cced3548 | 18 | #include <linux/irqchip/chained_irq.h> |
bc866fc7 | 19 | #include <linux/irq.h> |
dc1a95cc | 20 | #include <linux/irqdomain.h> |
ef310f4b | 21 | #include <linux/module.h> |
cbdb53e1 AD |
22 | #include <linux/platform_device.h> |
23 | #include <linux/slab.h> | |
c013f0a5 | 24 | #include <linux/err.h> |
ce44bf5b | 25 | #include <linux/ssbi.h> |
e7b81fca | 26 | #include <linux/regmap.h> |
dc1a95cc | 27 | #include <linux/of_platform.h> |
cbdb53e1 | 28 | #include <linux/mfd/core.h> |
bc866fc7 SB |
29 | |
30 | #define SSBI_REG_ADDR_IRQ_BASE 0x1BB | |
31 | ||
32 | #define SSBI_REG_ADDR_IRQ_ROOT (SSBI_REG_ADDR_IRQ_BASE + 0) | |
33 | #define SSBI_REG_ADDR_IRQ_M_STATUS1 (SSBI_REG_ADDR_IRQ_BASE + 1) | |
34 | #define SSBI_REG_ADDR_IRQ_M_STATUS2 (SSBI_REG_ADDR_IRQ_BASE + 2) | |
35 | #define SSBI_REG_ADDR_IRQ_M_STATUS3 (SSBI_REG_ADDR_IRQ_BASE + 3) | |
36 | #define SSBI_REG_ADDR_IRQ_M_STATUS4 (SSBI_REG_ADDR_IRQ_BASE + 4) | |
37 | #define SSBI_REG_ADDR_IRQ_BLK_SEL (SSBI_REG_ADDR_IRQ_BASE + 5) | |
38 | #define SSBI_REG_ADDR_IRQ_IT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 6) | |
39 | #define SSBI_REG_ADDR_IRQ_CONFIG (SSBI_REG_ADDR_IRQ_BASE + 7) | |
40 | #define SSBI_REG_ADDR_IRQ_RT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 8) | |
41 | ||
42 | #define PM_IRQF_LVL_SEL 0x01 /* level select */ | |
43 | #define PM_IRQF_MASK_FE 0x02 /* mask falling edge */ | |
44 | #define PM_IRQF_MASK_RE 0x04 /* mask rising edge */ | |
45 | #define PM_IRQF_CLR 0x08 /* clear interrupt */ | |
46 | #define PM_IRQF_BITS_MASK 0x70 | |
47 | #define PM_IRQF_BITS_SHIFT 4 | |
48 | #define PM_IRQF_WRITE 0x80 | |
49 | ||
50 | #define PM_IRQF_MASK_ALL (PM_IRQF_MASK_FE | \ | |
51 | PM_IRQF_MASK_RE) | |
cbdb53e1 AD |
52 | |
53 | #define REG_HWREV 0x002 /* PMIC4 revision */ | |
54 | #define REG_HWREV_2 0x0E8 /* PMIC4 revision 2 */ | |
55 | ||
dc1a95cc SB |
56 | #define PM8921_NR_IRQS 256 |
57 | ||
bc866fc7 | 58 | struct pm_irq_chip { |
e7b81fca | 59 | struct regmap *regmap; |
bc866fc7 | 60 | spinlock_t pm_irq_lock; |
dc1a95cc | 61 | struct irq_domain *irqdomain; |
bc866fc7 SB |
62 | unsigned int num_irqs; |
63 | unsigned int num_blocks; | |
64 | unsigned int num_masters; | |
65 | u8 config[0]; | |
66 | }; | |
67 | ||
e7b81fca SB |
68 | static int pm8xxx_read_block_irq(struct pm_irq_chip *chip, unsigned int bp, |
69 | unsigned int *ip) | |
bc866fc7 SB |
70 | { |
71 | int rc; | |
72 | ||
73 | spin_lock(&chip->pm_irq_lock); | |
e7b81fca | 74 | rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp); |
bc866fc7 SB |
75 | if (rc) { |
76 | pr_err("Failed Selecting Block %d rc=%d\n", bp, rc); | |
77 | goto bail; | |
78 | } | |
79 | ||
e7b81fca | 80 | rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_IT_STATUS, ip); |
bc866fc7 SB |
81 | if (rc) |
82 | pr_err("Failed Reading Status rc=%d\n", rc); | |
83 | bail: | |
84 | spin_unlock(&chip->pm_irq_lock); | |
85 | return rc; | |
86 | } | |
87 | ||
e7b81fca SB |
88 | static int |
89 | pm8xxx_config_irq(struct pm_irq_chip *chip, unsigned int bp, unsigned int cp) | |
bc866fc7 SB |
90 | { |
91 | int rc; | |
92 | ||
93 | spin_lock(&chip->pm_irq_lock); | |
e7b81fca | 94 | rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp); |
bc866fc7 SB |
95 | if (rc) { |
96 | pr_err("Failed Selecting Block %d rc=%d\n", bp, rc); | |
97 | goto bail; | |
98 | } | |
99 | ||
100 | cp |= PM_IRQF_WRITE; | |
e7b81fca | 101 | rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_CONFIG, cp); |
bc866fc7 SB |
102 | if (rc) |
103 | pr_err("Failed Configuring IRQ rc=%d\n", rc); | |
104 | bail: | |
105 | spin_unlock(&chip->pm_irq_lock); | |
106 | return rc; | |
107 | } | |
108 | ||
109 | static int pm8xxx_irq_block_handler(struct pm_irq_chip *chip, int block) | |
110 | { | |
111 | int pmirq, irq, i, ret = 0; | |
e7b81fca | 112 | unsigned int bits; |
bc866fc7 SB |
113 | |
114 | ret = pm8xxx_read_block_irq(chip, block, &bits); | |
115 | if (ret) { | |
116 | pr_err("Failed reading %d block ret=%d", block, ret); | |
117 | return ret; | |
118 | } | |
119 | if (!bits) { | |
120 | pr_err("block bit set in master but no irqs: %d", block); | |
121 | return 0; | |
122 | } | |
123 | ||
124 | /* Check IRQ bits */ | |
125 | for (i = 0; i < 8; i++) { | |
126 | if (bits & (1 << i)) { | |
127 | pmirq = block * 8 + i; | |
dc1a95cc | 128 | irq = irq_find_mapping(chip->irqdomain, pmirq); |
bc866fc7 SB |
129 | generic_handle_irq(irq); |
130 | } | |
131 | } | |
132 | return 0; | |
133 | } | |
134 | ||
135 | static int pm8xxx_irq_master_handler(struct pm_irq_chip *chip, int master) | |
136 | { | |
e7b81fca | 137 | unsigned int blockbits; |
bc866fc7 SB |
138 | int block_number, i, ret = 0; |
139 | ||
e7b81fca SB |
140 | ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_M_STATUS1 + master, |
141 | &blockbits); | |
bc866fc7 SB |
142 | if (ret) { |
143 | pr_err("Failed to read master %d ret=%d\n", master, ret); | |
144 | return ret; | |
145 | } | |
146 | if (!blockbits) { | |
147 | pr_err("master bit set in root but no blocks: %d", master); | |
148 | return 0; | |
149 | } | |
150 | ||
151 | for (i = 0; i < 8; i++) | |
152 | if (blockbits & (1 << i)) { | |
153 | block_number = master * 8 + i; /* block # */ | |
154 | ret |= pm8xxx_irq_block_handler(chip, block_number); | |
155 | } | |
156 | return ret; | |
157 | } | |
158 | ||
159 | static void pm8xxx_irq_handler(unsigned int irq, struct irq_desc *desc) | |
160 | { | |
161 | struct pm_irq_chip *chip = irq_desc_get_handler_data(desc); | |
162 | struct irq_chip *irq_chip = irq_desc_get_chip(desc); | |
e7b81fca | 163 | unsigned int root; |
bc866fc7 SB |
164 | int i, ret, masters = 0; |
165 | ||
cced3548 SB |
166 | chained_irq_enter(irq_chip, desc); |
167 | ||
e7b81fca | 168 | ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_ROOT, &root); |
bc866fc7 SB |
169 | if (ret) { |
170 | pr_err("Can't read root status ret=%d\n", ret); | |
171 | return; | |
172 | } | |
173 | ||
174 | /* on pm8xxx series masters start from bit 1 of the root */ | |
175 | masters = root >> 1; | |
176 | ||
177 | /* Read allowed masters for blocks. */ | |
178 | for (i = 0; i < chip->num_masters; i++) | |
179 | if (masters & (1 << i)) | |
180 | pm8xxx_irq_master_handler(chip, i); | |
181 | ||
cced3548 | 182 | chained_irq_exit(irq_chip, desc); |
bc866fc7 SB |
183 | } |
184 | ||
185 | static void pm8xxx_irq_mask_ack(struct irq_data *d) | |
186 | { | |
187 | struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d); | |
dc1a95cc SB |
188 | unsigned int pmirq = irqd_to_hwirq(d); |
189 | int irq_bit; | |
bc866fc7 SB |
190 | u8 block, config; |
191 | ||
192 | block = pmirq / 8; | |
bc866fc7 SB |
193 | irq_bit = pmirq % 8; |
194 | ||
195 | config = chip->config[pmirq] | PM_IRQF_MASK_ALL | PM_IRQF_CLR; | |
196 | pm8xxx_config_irq(chip, block, config); | |
197 | } | |
198 | ||
199 | static void pm8xxx_irq_unmask(struct irq_data *d) | |
200 | { | |
201 | struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d); | |
dc1a95cc SB |
202 | unsigned int pmirq = irqd_to_hwirq(d); |
203 | int irq_bit; | |
bc866fc7 SB |
204 | u8 block, config; |
205 | ||
206 | block = pmirq / 8; | |
bc866fc7 SB |
207 | irq_bit = pmirq % 8; |
208 | ||
209 | config = chip->config[pmirq]; | |
210 | pm8xxx_config_irq(chip, block, config); | |
211 | } | |
212 | ||
213 | static int pm8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type) | |
214 | { | |
215 | struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d); | |
dc1a95cc SB |
216 | unsigned int pmirq = irqd_to_hwirq(d); |
217 | int irq_bit; | |
bc866fc7 SB |
218 | u8 block, config; |
219 | ||
220 | block = pmirq / 8; | |
bc866fc7 SB |
221 | irq_bit = pmirq % 8; |
222 | ||
223 | chip->config[pmirq] = (irq_bit << PM_IRQF_BITS_SHIFT) | |
224 | | PM_IRQF_MASK_ALL; | |
225 | if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { | |
226 | if (flow_type & IRQF_TRIGGER_RISING) | |
227 | chip->config[pmirq] &= ~PM_IRQF_MASK_RE; | |
228 | if (flow_type & IRQF_TRIGGER_FALLING) | |
229 | chip->config[pmirq] &= ~PM_IRQF_MASK_FE; | |
230 | } else { | |
231 | chip->config[pmirq] |= PM_IRQF_LVL_SEL; | |
232 | ||
233 | if (flow_type & IRQF_TRIGGER_HIGH) | |
234 | chip->config[pmirq] &= ~PM_IRQF_MASK_RE; | |
235 | else | |
236 | chip->config[pmirq] &= ~PM_IRQF_MASK_FE; | |
237 | } | |
238 | ||
239 | config = chip->config[pmirq] | PM_IRQF_CLR; | |
240 | return pm8xxx_config_irq(chip, block, config); | |
241 | } | |
242 | ||
bc866fc7 SB |
243 | static struct irq_chip pm8xxx_irq_chip = { |
244 | .name = "pm8xxx", | |
245 | .irq_mask_ack = pm8xxx_irq_mask_ack, | |
246 | .irq_unmask = pm8xxx_irq_unmask, | |
247 | .irq_set_type = pm8xxx_irq_set_type, | |
d2d24ad1 | 248 | .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE, |
bc866fc7 SB |
249 | }; |
250 | ||
dc1a95cc SB |
251 | static int pm8xxx_irq_domain_map(struct irq_domain *d, unsigned int irq, |
252 | irq_hw_number_t hwirq) | |
253 | { | |
254 | struct pm_irq_chip *chip = d->host_data; | |
bc866fc7 | 255 | |
dc1a95cc SB |
256 | irq_set_chip_and_handler(irq, &pm8xxx_irq_chip, handle_level_irq); |
257 | irq_set_chip_data(irq, chip); | |
bc866fc7 | 258 | #ifdef CONFIG_ARM |
dc1a95cc | 259 | set_irq_flags(irq, IRQF_VALID); |
bc866fc7 | 260 | #else |
dc1a95cc | 261 | irq_set_noprobe(irq); |
bc866fc7 | 262 | #endif |
bc866fc7 SB |
263 | return 0; |
264 | } | |
265 | ||
dc1a95cc SB |
266 | static const struct irq_domain_ops pm8xxx_irq_domain_ops = { |
267 | .xlate = irq_domain_xlate_twocell, | |
268 | .map = pm8xxx_irq_domain_map, | |
269 | }; | |
270 | ||
e7b81fca SB |
271 | static const struct regmap_config ssbi_regmap_config = { |
272 | .reg_bits = 16, | |
273 | .val_bits = 8, | |
274 | .max_register = 0x3ff, | |
275 | .fast_io = true, | |
276 | .reg_read = ssbi_reg_read, | |
277 | .reg_write = ssbi_reg_write | |
278 | }; | |
279 | ||
c5865a53 SB |
280 | static const struct of_device_id pm8921_id_table[] = { |
281 | { .compatible = "qcom,pm8058", }, | |
282 | { .compatible = "qcom,pm8921", }, | |
283 | { } | |
284 | }; | |
285 | MODULE_DEVICE_TABLE(of, pm8921_id_table); | |
286 | ||
f791be49 | 287 | static int pm8921_probe(struct platform_device *pdev) |
cbdb53e1 | 288 | { |
e7b81fca | 289 | struct regmap *regmap; |
202f7680 | 290 | int irq, rc; |
e7b81fca | 291 | unsigned int val; |
c013f0a5 | 292 | u32 rev; |
dc1a95cc SB |
293 | struct pm_irq_chip *chip; |
294 | unsigned int nirqs = PM8921_NR_IRQS; | |
cbdb53e1 | 295 | |
dc1a95cc SB |
296 | irq = platform_get_irq(pdev, 0); |
297 | if (irq < 0) | |
298 | return irq; | |
cbdb53e1 | 299 | |
e7b81fca SB |
300 | regmap = devm_regmap_init(&pdev->dev, NULL, pdev->dev.parent, |
301 | &ssbi_regmap_config); | |
302 | if (IS_ERR(regmap)) | |
303 | return PTR_ERR(regmap); | |
304 | ||
cbdb53e1 | 305 | /* Read PMIC chip revision */ |
e7b81fca | 306 | rc = regmap_read(regmap, REG_HWREV, &val); |
cbdb53e1 AD |
307 | if (rc) { |
308 | pr_err("Failed to read hw rev reg %d:rc=%d\n", REG_HWREV, rc); | |
b2cdcfac | 309 | return rc; |
cbdb53e1 AD |
310 | } |
311 | pr_info("PMIC revision 1: %02X\n", val); | |
c013f0a5 | 312 | rev = val; |
cbdb53e1 AD |
313 | |
314 | /* Read PMIC chip revision 2 */ | |
e7b81fca | 315 | rc = regmap_read(regmap, REG_HWREV_2, &val); |
cbdb53e1 AD |
316 | if (rc) { |
317 | pr_err("Failed to read hw rev 2 reg %d:rc=%d\n", | |
318 | REG_HWREV_2, rc); | |
b2cdcfac | 319 | return rc; |
cbdb53e1 AD |
320 | } |
321 | pr_info("PMIC revision 2: %02X\n", val); | |
c013f0a5 | 322 | rev |= val << BITS_PER_BYTE; |
cbdb53e1 | 323 | |
dc1a95cc SB |
324 | chip = devm_kzalloc(&pdev->dev, sizeof(*chip) + |
325 | sizeof(chip->config[0]) * nirqs, | |
326 | GFP_KERNEL); | |
327 | if (!chip) | |
328 | return -ENOMEM; | |
329 | ||
3e87933a | 330 | platform_set_drvdata(pdev, chip); |
e7b81fca | 331 | chip->regmap = regmap; |
dc1a95cc SB |
332 | chip->num_irqs = nirqs; |
333 | chip->num_blocks = DIV_ROUND_UP(chip->num_irqs, 8); | |
334 | chip->num_masters = DIV_ROUND_UP(chip->num_blocks, 8); | |
335 | spin_lock_init(&chip->pm_irq_lock); | |
336 | ||
337 | chip->irqdomain = irq_domain_add_linear(pdev->dev.of_node, nirqs, | |
338 | &pm8xxx_irq_domain_ops, | |
339 | chip); | |
340 | if (!chip->irqdomain) | |
341 | return -ENODEV; | |
342 | ||
343 | irq_set_handler_data(irq, chip); | |
344 | irq_set_chained_handler(irq, pm8xxx_irq_handler); | |
345 | irq_set_irq_wake(irq, 1); | |
346 | ||
347 | rc = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); | |
c013f0a5 | 348 | if (rc) { |
dc1a95cc SB |
349 | irq_set_chained_handler(irq, NULL); |
350 | irq_set_handler_data(irq, NULL); | |
351 | irq_domain_remove(chip->irqdomain); | |
c013f0a5 AD |
352 | } |
353 | ||
dc1a95cc SB |
354 | return rc; |
355 | } | |
c013f0a5 | 356 | |
dc1a95cc SB |
357 | static int pm8921_remove_child(struct device *dev, void *unused) |
358 | { | |
359 | platform_device_unregister(to_platform_device(dev)); | |
cbdb53e1 | 360 | return 0; |
cbdb53e1 AD |
361 | } |
362 | ||
4740f73f | 363 | static int pm8921_remove(struct platform_device *pdev) |
cbdb53e1 | 364 | { |
dc1a95cc | 365 | int irq = platform_get_irq(pdev, 0); |
3e87933a | 366 | struct pm_irq_chip *chip = platform_get_drvdata(pdev); |
dc1a95cc SB |
367 | |
368 | device_for_each_child(&pdev->dev, NULL, pm8921_remove_child); | |
369 | irq_set_chained_handler(irq, NULL); | |
370 | irq_set_handler_data(irq, NULL); | |
371 | irq_domain_remove(chip->irqdomain); | |
cbdb53e1 AD |
372 | |
373 | return 0; | |
374 | } | |
375 | ||
376 | static struct platform_driver pm8921_driver = { | |
377 | .probe = pm8921_probe, | |
84449216 | 378 | .remove = pm8921_remove, |
cbdb53e1 AD |
379 | .driver = { |
380 | .name = "pm8921-core", | |
381 | .owner = THIS_MODULE, | |
c5865a53 | 382 | .of_match_table = pm8921_id_table, |
cbdb53e1 AD |
383 | }, |
384 | }; | |
385 | ||
386 | static int __init pm8921_init(void) | |
387 | { | |
388 | return platform_driver_register(&pm8921_driver); | |
389 | } | |
390 | subsys_initcall(pm8921_init); | |
391 | ||
392 | static void __exit pm8921_exit(void) | |
393 | { | |
394 | platform_driver_unregister(&pm8921_driver); | |
395 | } | |
396 | module_exit(pm8921_exit); | |
397 | ||
398 | MODULE_LICENSE("GPL v2"); | |
399 | MODULE_DESCRIPTION("PMIC 8921 core driver"); | |
400 | MODULE_VERSION("1.0"); | |
401 | MODULE_ALIAS("platform:pm8921-core"); |