Commit | Line | Data |
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ada8a8a1 WW |
1 | /* Driver for Realtek PCI-Express card reader |
2 | * | |
09fd8678 | 3 | * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. |
ada8a8a1 WW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2, or (at your option) any | |
8 | * later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along | |
16 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
17 | * | |
18 | * Author: | |
19 | * Wei WANG <wei_wang@realsil.com.cn> | |
ada8a8a1 WW |
20 | */ |
21 | ||
22 | #include <linux/pci.h> | |
23 | #include <linux/module.h> | |
aec17ea1 | 24 | #include <linux/slab.h> |
ada8a8a1 WW |
25 | #include <linux/dma-mapping.h> |
26 | #include <linux/highmem.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/idr.h> | |
30 | #include <linux/platform_device.h> | |
31 | #include <linux/mfd/core.h> | |
32 | #include <linux/mfd/rtsx_pci.h> | |
33 | #include <asm/unaligned.h> | |
34 | ||
35 | #include "rtsx_pcr.h" | |
36 | ||
37 | static bool msi_en = true; | |
38 | module_param(msi_en, bool, S_IRUGO | S_IWUSR); | |
39 | MODULE_PARM_DESC(msi_en, "Enable MSI"); | |
40 | ||
41 | static DEFINE_IDR(rtsx_pci_idr); | |
42 | static DEFINE_SPINLOCK(rtsx_pci_lock); | |
43 | ||
44 | static struct mfd_cell rtsx_pcr_cells[] = { | |
45 | [RTSX_SD_CARD] = { | |
46 | .name = DRV_NAME_RTSX_PCI_SDMMC, | |
47 | }, | |
48 | [RTSX_MS_CARD] = { | |
49 | .name = DRV_NAME_RTSX_PCI_MS, | |
50 | }, | |
51 | }; | |
52 | ||
36fcd06c | 53 | static const struct pci_device_id rtsx_pci_ids[] = { |
ada8a8a1 WW |
54 | { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 }, |
55 | { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 }, | |
56 | { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 }, | |
e1237932 | 57 | { PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS << 16, 0xFF0000 }, |
4c4b8c10 | 58 | { PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 }, |
9032eabd | 59 | { PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 }, |
56cb3cc1 | 60 | { PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS << 16, 0xFF0000 }, |
663c425f | 61 | { PCI_DEVICE(0x10EC, 0x524A), PCI_CLASS_OTHERS << 16, 0xFF0000 }, |
41bc2334 | 62 | { PCI_DEVICE(0x10EC, 0x525A), PCI_CLASS_OTHERS << 16, 0xFF0000 }, |
ada8a8a1 WW |
63 | { 0, } |
64 | }; | |
65 | ||
66 | MODULE_DEVICE_TABLE(pci, rtsx_pci_ids); | |
67 | ||
19f3bd54 MC |
68 | static inline void rtsx_pci_enable_aspm(struct rtsx_pcr *pcr) |
69 | { | |
70 | rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL, | |
71 | 0xFC, pcr->aspm_en); | |
72 | } | |
73 | ||
74 | static inline void rtsx_pci_disable_aspm(struct rtsx_pcr *pcr) | |
75 | { | |
76 | rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL, | |
77 | 0xFC, 0); | |
78 | } | |
79 | ||
ada8a8a1 WW |
80 | void rtsx_pci_start_run(struct rtsx_pcr *pcr) |
81 | { | |
82 | /* If pci device removed, don't queue idle work any more */ | |
83 | if (pcr->remove_pci) | |
84 | return; | |
85 | ||
86 | if (pcr->state != PDEV_STAT_RUN) { | |
87 | pcr->state = PDEV_STAT_RUN; | |
88 | if (pcr->ops->enable_auto_blink) | |
89 | pcr->ops->enable_auto_blink(pcr); | |
773ccdfd WW |
90 | |
91 | if (pcr->aspm_en) | |
19f3bd54 | 92 | rtsx_pci_disable_aspm(pcr); |
ada8a8a1 WW |
93 | } |
94 | ||
95 | mod_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200)); | |
96 | } | |
97 | EXPORT_SYMBOL_GPL(rtsx_pci_start_run); | |
98 | ||
99 | int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data) | |
100 | { | |
101 | int i; | |
102 | u32 val = HAIMR_WRITE_START; | |
103 | ||
104 | val |= (u32)(addr & 0x3FFF) << 16; | |
105 | val |= (u32)mask << 8; | |
106 | val |= (u32)data; | |
107 | ||
108 | rtsx_pci_writel(pcr, RTSX_HAIMR, val); | |
109 | ||
110 | for (i = 0; i < MAX_RW_REG_CNT; i++) { | |
111 | val = rtsx_pci_readl(pcr, RTSX_HAIMR); | |
112 | if ((val & HAIMR_TRANS_END) == 0) { | |
113 | if (data != (u8)val) | |
114 | return -EIO; | |
115 | return 0; | |
116 | } | |
117 | } | |
118 | ||
119 | return -ETIMEDOUT; | |
120 | } | |
121 | EXPORT_SYMBOL_GPL(rtsx_pci_write_register); | |
122 | ||
123 | int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data) | |
124 | { | |
125 | u32 val = HAIMR_READ_START; | |
126 | int i; | |
127 | ||
128 | val |= (u32)(addr & 0x3FFF) << 16; | |
129 | rtsx_pci_writel(pcr, RTSX_HAIMR, val); | |
130 | ||
131 | for (i = 0; i < MAX_RW_REG_CNT; i++) { | |
132 | val = rtsx_pci_readl(pcr, RTSX_HAIMR); | |
133 | if ((val & HAIMR_TRANS_END) == 0) | |
134 | break; | |
135 | } | |
136 | ||
137 | if (i >= MAX_RW_REG_CNT) | |
138 | return -ETIMEDOUT; | |
139 | ||
140 | if (data) | |
141 | *data = (u8)(val & 0xFF); | |
142 | ||
143 | return 0; | |
144 | } | |
145 | EXPORT_SYMBOL_GPL(rtsx_pci_read_register); | |
146 | ||
663c425f | 147 | int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val) |
ada8a8a1 WW |
148 | { |
149 | int err, i, finished = 0; | |
150 | u8 tmp; | |
151 | ||
152 | rtsx_pci_init_cmd(pcr); | |
153 | ||
154 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA0, 0xFF, (u8)val); | |
155 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA1, 0xFF, (u8)(val >> 8)); | |
156 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr); | |
157 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x81); | |
158 | ||
159 | err = rtsx_pci_send_cmd(pcr, 100); | |
160 | if (err < 0) | |
161 | return err; | |
162 | ||
163 | for (i = 0; i < 100000; i++) { | |
164 | err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp); | |
165 | if (err < 0) | |
166 | return err; | |
167 | ||
168 | if (!(tmp & 0x80)) { | |
169 | finished = 1; | |
170 | break; | |
171 | } | |
172 | } | |
173 | ||
174 | if (!finished) | |
175 | return -ETIMEDOUT; | |
176 | ||
177 | return 0; | |
178 | } | |
663c425f MC |
179 | |
180 | int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val) | |
181 | { | |
182 | if (pcr->ops->write_phy) | |
183 | return pcr->ops->write_phy(pcr, addr, val); | |
184 | ||
185 | return __rtsx_pci_write_phy_register(pcr, addr, val); | |
186 | } | |
ada8a8a1 WW |
187 | EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register); |
188 | ||
663c425f | 189 | int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val) |
ada8a8a1 WW |
190 | { |
191 | int err, i, finished = 0; | |
192 | u16 data; | |
193 | u8 *ptr, tmp; | |
194 | ||
195 | rtsx_pci_init_cmd(pcr); | |
196 | ||
197 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr); | |
198 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x80); | |
199 | ||
200 | err = rtsx_pci_send_cmd(pcr, 100); | |
201 | if (err < 0) | |
202 | return err; | |
203 | ||
204 | for (i = 0; i < 100000; i++) { | |
205 | err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp); | |
206 | if (err < 0) | |
207 | return err; | |
208 | ||
209 | if (!(tmp & 0x80)) { | |
210 | finished = 1; | |
211 | break; | |
212 | } | |
213 | } | |
214 | ||
215 | if (!finished) | |
216 | return -ETIMEDOUT; | |
217 | ||
218 | rtsx_pci_init_cmd(pcr); | |
219 | ||
220 | rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA0, 0, 0); | |
221 | rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA1, 0, 0); | |
222 | ||
223 | err = rtsx_pci_send_cmd(pcr, 100); | |
224 | if (err < 0) | |
225 | return err; | |
226 | ||
227 | ptr = rtsx_pci_get_cmd_data(pcr); | |
228 | data = ((u16)ptr[1] << 8) | ptr[0]; | |
229 | ||
230 | if (val) | |
231 | *val = data; | |
232 | ||
233 | return 0; | |
234 | } | |
663c425f MC |
235 | |
236 | int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val) | |
237 | { | |
238 | if (pcr->ops->read_phy) | |
239 | return pcr->ops->read_phy(pcr, addr, val); | |
240 | ||
241 | return __rtsx_pci_read_phy_register(pcr, addr, val); | |
242 | } | |
ada8a8a1 WW |
243 | EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register); |
244 | ||
245 | void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr) | |
246 | { | |
247 | rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD); | |
248 | rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA); | |
249 | ||
250 | rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80); | |
251 | rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80); | |
252 | } | |
253 | EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd); | |
254 | ||
255 | void rtsx_pci_add_cmd(struct rtsx_pcr *pcr, | |
256 | u8 cmd_type, u16 reg_addr, u8 mask, u8 data) | |
257 | { | |
258 | unsigned long flags; | |
259 | u32 val = 0; | |
260 | u32 *ptr = (u32 *)(pcr->host_cmds_ptr); | |
261 | ||
262 | val |= (u32)(cmd_type & 0x03) << 30; | |
263 | val |= (u32)(reg_addr & 0x3FFF) << 16; | |
264 | val |= (u32)mask << 8; | |
265 | val |= (u32)data; | |
266 | ||
267 | spin_lock_irqsave(&pcr->lock, flags); | |
268 | ptr += pcr->ci; | |
269 | if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) { | |
270 | put_unaligned_le32(val, ptr); | |
271 | ptr++; | |
272 | pcr->ci++; | |
273 | } | |
274 | spin_unlock_irqrestore(&pcr->lock, flags); | |
275 | } | |
276 | EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd); | |
277 | ||
278 | void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr) | |
279 | { | |
280 | u32 val = 1 << 31; | |
281 | ||
282 | rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr); | |
283 | ||
284 | val |= (u32)(pcr->ci * 4) & 0x00FFFFFF; | |
285 | /* Hardware Auto Response */ | |
286 | val |= 0x40000000; | |
287 | rtsx_pci_writel(pcr, RTSX_HCBCTLR, val); | |
288 | } | |
289 | EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait); | |
290 | ||
291 | int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout) | |
292 | { | |
293 | struct completion trans_done; | |
294 | u32 val = 1 << 31; | |
295 | long timeleft; | |
296 | unsigned long flags; | |
297 | int err = 0; | |
298 | ||
299 | spin_lock_irqsave(&pcr->lock, flags); | |
300 | ||
301 | /* set up data structures for the wakeup system */ | |
302 | pcr->done = &trans_done; | |
303 | pcr->trans_result = TRANS_NOT_READY; | |
304 | init_completion(&trans_done); | |
305 | ||
306 | rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr); | |
307 | ||
308 | val |= (u32)(pcr->ci * 4) & 0x00FFFFFF; | |
309 | /* Hardware Auto Response */ | |
310 | val |= 0x40000000; | |
311 | rtsx_pci_writel(pcr, RTSX_HCBCTLR, val); | |
312 | ||
313 | spin_unlock_irqrestore(&pcr->lock, flags); | |
314 | ||
315 | /* Wait for TRANS_OK_INT */ | |
316 | timeleft = wait_for_completion_interruptible_timeout( | |
317 | &trans_done, msecs_to_jiffies(timeout)); | |
318 | if (timeleft <= 0) { | |
0523b8f4 | 319 | pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__); |
ada8a8a1 WW |
320 | err = -ETIMEDOUT; |
321 | goto finish_send_cmd; | |
322 | } | |
323 | ||
324 | spin_lock_irqsave(&pcr->lock, flags); | |
325 | if (pcr->trans_result == TRANS_RESULT_FAIL) | |
326 | err = -EINVAL; | |
327 | else if (pcr->trans_result == TRANS_RESULT_OK) | |
328 | err = 0; | |
329 | else if (pcr->trans_result == TRANS_NO_DEVICE) | |
330 | err = -ENODEV; | |
331 | spin_unlock_irqrestore(&pcr->lock, flags); | |
332 | ||
333 | finish_send_cmd: | |
334 | spin_lock_irqsave(&pcr->lock, flags); | |
335 | pcr->done = NULL; | |
336 | spin_unlock_irqrestore(&pcr->lock, flags); | |
337 | ||
338 | if ((err < 0) && (err != -ENODEV)) | |
339 | rtsx_pci_stop_cmd(pcr); | |
340 | ||
341 | if (pcr->finish_me) | |
342 | complete(pcr->finish_me); | |
343 | ||
344 | return err; | |
345 | } | |
346 | EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd); | |
347 | ||
348 | static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr, | |
349 | dma_addr_t addr, unsigned int len, int end) | |
350 | { | |
351 | u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi; | |
352 | u64 val; | |
353 | u8 option = SG_VALID | SG_TRANS_DATA; | |
354 | ||
0523b8f4 | 355 | pcr_dbg(pcr, "DMA addr: 0x%x, Len: 0x%x\n", (unsigned int)addr, len); |
ada8a8a1 WW |
356 | |
357 | if (end) | |
358 | option |= SG_END; | |
359 | val = ((u64)addr << 32) | ((u64)len << 12) | option; | |
360 | ||
361 | put_unaligned_le64(val, ptr); | |
ada8a8a1 WW |
362 | pcr->sgi++; |
363 | } | |
364 | ||
365 | int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist, | |
366 | int num_sg, bool read, int timeout) | |
367 | { | |
8cd11830 | 368 | int err = 0, count; |
98fcc576 | 369 | |
0523b8f4 | 370 | pcr_dbg(pcr, "--> %s: num_sg = %d\n", __func__, num_sg); |
8cd11830 MC |
371 | count = rtsx_pci_dma_map_sg(pcr, sglist, num_sg, read); |
372 | if (count < 1) | |
373 | return -EINVAL; | |
0523b8f4 | 374 | pcr_dbg(pcr, "DMA mapping count: %d\n", count); |
8cd11830 MC |
375 | |
376 | err = rtsx_pci_dma_transfer(pcr, sglist, count, read, timeout); | |
377 | ||
378 | rtsx_pci_dma_unmap_sg(pcr, sglist, num_sg, read); | |
379 | ||
380 | return err; | |
381 | } | |
382 | EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data); | |
383 | ||
384 | int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist, | |
385 | int num_sg, bool read) | |
386 | { | |
387 | enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; | |
98fcc576 | 388 | |
98fcc576 MC |
389 | if (pcr->remove_pci) |
390 | return -EINVAL; | |
391 | ||
392 | if ((sglist == NULL) || (num_sg <= 0)) | |
393 | return -EINVAL; | |
ada8a8a1 | 394 | |
8cd11830 MC |
395 | return dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dir); |
396 | } | |
397 | EXPORT_SYMBOL_GPL(rtsx_pci_dma_map_sg); | |
398 | ||
399 | void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist, | |
400 | int num_sg, bool read) | |
401 | { | |
402 | enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; | |
403 | ||
404 | dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dir); | |
405 | } | |
406 | EXPORT_SYMBOL_GPL(rtsx_pci_dma_unmap_sg); | |
407 | ||
408 | int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist, | |
409 | int count, bool read, int timeout) | |
410 | { | |
411 | struct completion trans_done; | |
412 | struct scatterlist *sg; | |
413 | dma_addr_t addr; | |
414 | long timeleft; | |
415 | unsigned long flags; | |
416 | unsigned int len; | |
417 | int i, err = 0; | |
418 | u32 val; | |
419 | u8 dir = read ? DEVICE_TO_HOST : HOST_TO_DEVICE; | |
98fcc576 | 420 | |
8cd11830 MC |
421 | if (pcr->remove_pci) |
422 | return -ENODEV; | |
423 | ||
424 | if ((sglist == NULL) || (count < 1)) | |
ada8a8a1 | 425 | return -EINVAL; |
ada8a8a1 | 426 | |
98fcc576 MC |
427 | val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE; |
428 | pcr->sgi = 0; | |
429 | for_each_sg(sglist, sg, count, i) { | |
430 | addr = sg_dma_address(sg); | |
431 | len = sg_dma_len(sg); | |
432 | rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1); | |
433 | } | |
ada8a8a1 WW |
434 | |
435 | spin_lock_irqsave(&pcr->lock, flags); | |
436 | ||
437 | pcr->done = &trans_done; | |
438 | pcr->trans_result = TRANS_NOT_READY; | |
439 | init_completion(&trans_done); | |
98fcc576 MC |
440 | rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr); |
441 | rtsx_pci_writel(pcr, RTSX_HDBCTLR, val); | |
ada8a8a1 WW |
442 | |
443 | spin_unlock_irqrestore(&pcr->lock, flags); | |
444 | ||
445 | timeleft = wait_for_completion_interruptible_timeout( | |
446 | &trans_done, msecs_to_jiffies(timeout)); | |
447 | if (timeleft <= 0) { | |
0523b8f4 | 448 | pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__); |
ada8a8a1 WW |
449 | err = -ETIMEDOUT; |
450 | goto out; | |
451 | } | |
452 | ||
453 | spin_lock_irqsave(&pcr->lock, flags); | |
ada8a8a1 WW |
454 | if (pcr->trans_result == TRANS_RESULT_FAIL) |
455 | err = -EINVAL; | |
456 | else if (pcr->trans_result == TRANS_NO_DEVICE) | |
457 | err = -ENODEV; | |
ada8a8a1 WW |
458 | spin_unlock_irqrestore(&pcr->lock, flags); |
459 | ||
460 | out: | |
461 | spin_lock_irqsave(&pcr->lock, flags); | |
462 | pcr->done = NULL; | |
463 | spin_unlock_irqrestore(&pcr->lock, flags); | |
464 | ||
ada8a8a1 WW |
465 | if ((err < 0) && (err != -ENODEV)) |
466 | rtsx_pci_stop_cmd(pcr); | |
467 | ||
468 | if (pcr->finish_me) | |
469 | complete(pcr->finish_me); | |
470 | ||
471 | return err; | |
472 | } | |
8cd11830 | 473 | EXPORT_SYMBOL_GPL(rtsx_pci_dma_transfer); |
ada8a8a1 WW |
474 | |
475 | int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len) | |
476 | { | |
477 | int err; | |
478 | int i, j; | |
479 | u16 reg; | |
480 | u8 *ptr; | |
481 | ||
482 | if (buf_len > 512) | |
483 | buf_len = 512; | |
484 | ||
485 | ptr = buf; | |
486 | reg = PPBUF_BASE2; | |
487 | for (i = 0; i < buf_len / 256; i++) { | |
488 | rtsx_pci_init_cmd(pcr); | |
489 | ||
490 | for (j = 0; j < 256; j++) | |
491 | rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0); | |
492 | ||
493 | err = rtsx_pci_send_cmd(pcr, 250); | |
494 | if (err < 0) | |
495 | return err; | |
496 | ||
497 | memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256); | |
498 | ptr += 256; | |
499 | } | |
500 | ||
501 | if (buf_len % 256) { | |
502 | rtsx_pci_init_cmd(pcr); | |
503 | ||
504 | for (j = 0; j < buf_len % 256; j++) | |
505 | rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0); | |
506 | ||
507 | err = rtsx_pci_send_cmd(pcr, 250); | |
508 | if (err < 0) | |
509 | return err; | |
510 | } | |
511 | ||
512 | memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256); | |
513 | ||
514 | return 0; | |
515 | } | |
516 | EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf); | |
517 | ||
518 | int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len) | |
519 | { | |
520 | int err; | |
521 | int i, j; | |
522 | u16 reg; | |
523 | u8 *ptr; | |
524 | ||
525 | if (buf_len > 512) | |
526 | buf_len = 512; | |
527 | ||
528 | ptr = buf; | |
529 | reg = PPBUF_BASE2; | |
530 | for (i = 0; i < buf_len / 256; i++) { | |
531 | rtsx_pci_init_cmd(pcr); | |
532 | ||
533 | for (j = 0; j < 256; j++) { | |
534 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, | |
535 | reg++, 0xFF, *ptr); | |
536 | ptr++; | |
537 | } | |
538 | ||
539 | err = rtsx_pci_send_cmd(pcr, 250); | |
540 | if (err < 0) | |
541 | return err; | |
542 | } | |
543 | ||
544 | if (buf_len % 256) { | |
545 | rtsx_pci_init_cmd(pcr); | |
546 | ||
547 | for (j = 0; j < buf_len % 256; j++) { | |
548 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, | |
549 | reg++, 0xFF, *ptr); | |
550 | ptr++; | |
551 | } | |
552 | ||
553 | err = rtsx_pci_send_cmd(pcr, 250); | |
554 | if (err < 0) | |
555 | return err; | |
556 | } | |
557 | ||
558 | return 0; | |
559 | } | |
560 | EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf); | |
561 | ||
562 | static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl) | |
563 | { | |
564 | int err; | |
565 | ||
566 | rtsx_pci_init_cmd(pcr); | |
567 | ||
568 | while (*tbl & 0xFFFF0000) { | |
569 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, | |
570 | (u16)(*tbl >> 16), 0xFF, (u8)(*tbl)); | |
571 | tbl++; | |
572 | } | |
573 | ||
574 | err = rtsx_pci_send_cmd(pcr, 100); | |
575 | if (err < 0) | |
576 | return err; | |
577 | ||
578 | return 0; | |
579 | } | |
580 | ||
581 | int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card) | |
582 | { | |
583 | const u32 *tbl; | |
584 | ||
585 | if (card == RTSX_SD_CARD) | |
586 | tbl = pcr->sd_pull_ctl_enable_tbl; | |
587 | else if (card == RTSX_MS_CARD) | |
588 | tbl = pcr->ms_pull_ctl_enable_tbl; | |
589 | else | |
590 | return -EINVAL; | |
591 | ||
592 | return rtsx_pci_set_pull_ctl(pcr, tbl); | |
593 | } | |
594 | EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable); | |
595 | ||
596 | int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card) | |
597 | { | |
598 | const u32 *tbl; | |
599 | ||
600 | if (card == RTSX_SD_CARD) | |
601 | tbl = pcr->sd_pull_ctl_disable_tbl; | |
602 | else if (card == RTSX_MS_CARD) | |
603 | tbl = pcr->ms_pull_ctl_disable_tbl; | |
604 | else | |
605 | return -EINVAL; | |
606 | ||
607 | ||
608 | return rtsx_pci_set_pull_ctl(pcr, tbl); | |
609 | } | |
610 | EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable); | |
611 | ||
612 | static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr) | |
613 | { | |
614 | pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN; | |
615 | ||
616 | if (pcr->num_slots > 1) | |
617 | pcr->bier |= MS_INT_EN; | |
618 | ||
619 | /* Enable Bus Interrupt */ | |
620 | rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier); | |
621 | ||
0523b8f4 | 622 | pcr_dbg(pcr, "RTSX_BIER: 0x%08x\n", pcr->bier); |
ada8a8a1 WW |
623 | } |
624 | ||
625 | static inline u8 double_ssc_depth(u8 depth) | |
626 | { | |
627 | return ((depth > 1) ? (depth - 1) : depth); | |
628 | } | |
629 | ||
630 | static u8 revise_ssc_depth(u8 ssc_depth, u8 div) | |
631 | { | |
632 | if (div > CLK_DIV_1) { | |
633 | if (ssc_depth > (div - 1)) | |
634 | ssc_depth -= (div - 1); | |
635 | else | |
636 | ssc_depth = SSC_DEPTH_4M; | |
637 | } | |
638 | ||
639 | return ssc_depth; | |
640 | } | |
641 | ||
642 | int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, | |
643 | u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk) | |
644 | { | |
645 | int err, clk; | |
eebbe254 | 646 | u8 n, clk_divider, mcu_cnt, div; |
ada8a8a1 WW |
647 | u8 depth[] = { |
648 | [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M, | |
649 | [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M, | |
650 | [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M, | |
651 | [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K, | |
652 | [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K, | |
653 | }; | |
654 | ||
655 | if (initial_mode) { | |
656 | /* We use 250k(around) here, in initial stage */ | |
657 | clk_divider = SD_CLK_DIVIDE_128; | |
658 | card_clock = 30000000; | |
659 | } else { | |
660 | clk_divider = SD_CLK_DIVIDE_0; | |
661 | } | |
662 | err = rtsx_pci_write_register(pcr, SD_CFG1, | |
663 | SD_CLK_DIVIDE_MASK, clk_divider); | |
664 | if (err < 0) | |
665 | return err; | |
666 | ||
667 | card_clock /= 1000000; | |
0523b8f4 | 668 | pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock); |
ada8a8a1 | 669 | |
ada8a8a1 WW |
670 | clk = card_clock; |
671 | if (!initial_mode && double_clk) | |
672 | clk = card_clock * 2; | |
0523b8f4 MC |
673 | pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n", |
674 | clk, pcr->cur_clock); | |
ada8a8a1 WW |
675 | |
676 | if (clk == pcr->cur_clock) | |
677 | return 0; | |
678 | ||
ab4e8f8b | 679 | if (pcr->ops->conv_clk_and_div_n) |
678cacdf | 680 | n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N); |
ab4e8f8b | 681 | else |
678cacdf | 682 | n = (u8)(clk - 2); |
eebbe254 | 683 | if ((clk <= 2) || (n > MAX_DIV_N_PCR)) |
ada8a8a1 WW |
684 | return -EINVAL; |
685 | ||
686 | mcu_cnt = (u8)(125/clk + 3); | |
687 | if (mcu_cnt > 15) | |
688 | mcu_cnt = 15; | |
689 | ||
eebbe254 | 690 | /* Make sure that the SSC clock div_n is not less than MIN_DIV_N_PCR */ |
ada8a8a1 | 691 | div = CLK_DIV_1; |
eebbe254 | 692 | while ((n < MIN_DIV_N_PCR) && (div < CLK_DIV_8)) { |
ab4e8f8b | 693 | if (pcr->ops->conv_clk_and_div_n) { |
678cacdf | 694 | int dbl_clk = pcr->ops->conv_clk_and_div_n(n, |
ab4e8f8b | 695 | DIV_N_TO_CLK) * 2; |
678cacdf | 696 | n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk, |
ab4e8f8b WW |
697 | CLK_TO_DIV_N); |
698 | } else { | |
678cacdf | 699 | n = (n + 2) * 2 - 2; |
ab4e8f8b | 700 | } |
ada8a8a1 WW |
701 | div++; |
702 | } | |
0523b8f4 | 703 | pcr_dbg(pcr, "n = %d, div = %d\n", n, div); |
ada8a8a1 WW |
704 | |
705 | ssc_depth = depth[ssc_depth]; | |
706 | if (double_clk) | |
707 | ssc_depth = double_ssc_depth(ssc_depth); | |
708 | ||
709 | ssc_depth = revise_ssc_depth(ssc_depth, div); | |
0523b8f4 | 710 | pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth); |
ada8a8a1 WW |
711 | |
712 | rtsx_pci_init_cmd(pcr); | |
713 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, | |
714 | CLK_LOW_FREQ, CLK_LOW_FREQ); | |
715 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, | |
716 | 0xFF, (div << 4) | mcu_cnt); | |
717 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0); | |
718 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, | |
719 | SSC_DEPTH_MASK, ssc_depth); | |
678cacdf | 720 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n); |
ada8a8a1 WW |
721 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB); |
722 | if (vpclk) { | |
723 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, | |
724 | PHASE_NOT_RESET, 0); | |
725 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, | |
726 | PHASE_NOT_RESET, PHASE_NOT_RESET); | |
727 | } | |
728 | ||
729 | err = rtsx_pci_send_cmd(pcr, 2000); | |
730 | if (err < 0) | |
731 | return err; | |
732 | ||
733 | /* Wait SSC clock stable */ | |
734 | udelay(10); | |
735 | err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); | |
736 | if (err < 0) | |
737 | return err; | |
738 | ||
739 | pcr->cur_clock = clk; | |
740 | return 0; | |
741 | } | |
742 | EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock); | |
743 | ||
744 | int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card) | |
745 | { | |
746 | if (pcr->ops->card_power_on) | |
747 | return pcr->ops->card_power_on(pcr, card); | |
748 | ||
749 | return 0; | |
750 | } | |
751 | EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on); | |
752 | ||
753 | int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card) | |
754 | { | |
755 | if (pcr->ops->card_power_off) | |
756 | return pcr->ops->card_power_off(pcr, card); | |
757 | ||
758 | return 0; | |
759 | } | |
760 | EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off); | |
761 | ||
c3481955 WW |
762 | int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card) |
763 | { | |
764 | unsigned int cd_mask[] = { | |
765 | [RTSX_SD_CARD] = SD_EXIST, | |
766 | [RTSX_MS_CARD] = MS_EXIST | |
767 | }; | |
768 | ||
773ccdfd | 769 | if (!(pcr->flags & PCR_MS_PMOS)) { |
c3481955 WW |
770 | /* When using single PMOS, accessing card is not permitted |
771 | * if the existing card is not the designated one. | |
772 | */ | |
773 | if (pcr->card_exist & (~cd_mask[card])) | |
774 | return -EIO; | |
775 | } | |
776 | ||
777 | return 0; | |
778 | } | |
779 | EXPORT_SYMBOL_GPL(rtsx_pci_card_exclusive_check); | |
780 | ||
d817ac4e WW |
781 | int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) |
782 | { | |
783 | if (pcr->ops->switch_output_voltage) | |
784 | return pcr->ops->switch_output_voltage(pcr, voltage); | |
785 | ||
786 | return 0; | |
787 | } | |
788 | EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage); | |
789 | ||
ada8a8a1 WW |
790 | unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr) |
791 | { | |
792 | unsigned int val; | |
793 | ||
794 | val = rtsx_pci_readl(pcr, RTSX_BIPR); | |
795 | if (pcr->ops->cd_deglitch) | |
796 | val = pcr->ops->cd_deglitch(pcr); | |
797 | ||
798 | return val; | |
799 | } | |
800 | EXPORT_SYMBOL_GPL(rtsx_pci_card_exist); | |
801 | ||
802 | void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr) | |
803 | { | |
804 | struct completion finish; | |
805 | ||
806 | pcr->finish_me = &finish; | |
807 | init_completion(&finish); | |
808 | ||
809 | if (pcr->done) | |
810 | complete(pcr->done); | |
811 | ||
812 | if (!pcr->remove_pci) | |
813 | rtsx_pci_stop_cmd(pcr); | |
814 | ||
815 | wait_for_completion_interruptible_timeout(&finish, | |
816 | msecs_to_jiffies(2)); | |
817 | pcr->finish_me = NULL; | |
818 | } | |
819 | EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer); | |
820 | ||
821 | static void rtsx_pci_card_detect(struct work_struct *work) | |
822 | { | |
823 | struct delayed_work *dwork; | |
824 | struct rtsx_pcr *pcr; | |
825 | unsigned long flags; | |
504decc0 | 826 | unsigned int card_detect = 0, card_inserted, card_removed; |
ada8a8a1 WW |
827 | u32 irq_status; |
828 | ||
829 | dwork = to_delayed_work(work); | |
830 | pcr = container_of(dwork, struct rtsx_pcr, carddet_work); | |
831 | ||
0523b8f4 | 832 | pcr_dbg(pcr, "--> %s\n", __func__); |
ada8a8a1 | 833 | |
504decc0 | 834 | mutex_lock(&pcr->pcr_mutex); |
ada8a8a1 WW |
835 | spin_lock_irqsave(&pcr->lock, flags); |
836 | ||
837 | irq_status = rtsx_pci_readl(pcr, RTSX_BIPR); | |
0523b8f4 | 838 | pcr_dbg(pcr, "irq_status: 0x%08x\n", irq_status); |
ada8a8a1 | 839 | |
504decc0 WW |
840 | irq_status &= CARD_EXIST; |
841 | card_inserted = pcr->card_inserted & irq_status; | |
842 | card_removed = pcr->card_removed; | |
843 | pcr->card_inserted = 0; | |
844 | pcr->card_removed = 0; | |
845 | ||
846 | spin_unlock_irqrestore(&pcr->lock, flags); | |
847 | ||
848 | if (card_inserted || card_removed) { | |
0523b8f4 MC |
849 | pcr_dbg(pcr, "card_inserted: 0x%x, card_removed: 0x%x\n", |
850 | card_inserted, card_removed); | |
ada8a8a1 WW |
851 | |
852 | if (pcr->ops->cd_deglitch) | |
504decc0 | 853 | card_inserted = pcr->ops->cd_deglitch(pcr); |
ada8a8a1 | 854 | |
504decc0 | 855 | card_detect = card_inserted | card_removed; |
c3481955 WW |
856 | |
857 | pcr->card_exist |= card_inserted; | |
858 | pcr->card_exist &= ~card_removed; | |
ada8a8a1 WW |
859 | } |
860 | ||
504decc0 | 861 | mutex_unlock(&pcr->pcr_mutex); |
ada8a8a1 | 862 | |
2d1484f5 | 863 | if ((card_detect & SD_EXIST) && pcr->slots[RTSX_SD_CARD].card_event) |
ada8a8a1 WW |
864 | pcr->slots[RTSX_SD_CARD].card_event( |
865 | pcr->slots[RTSX_SD_CARD].p_dev); | |
2d1484f5 | 866 | if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event) |
ada8a8a1 WW |
867 | pcr->slots[RTSX_MS_CARD].card_event( |
868 | pcr->slots[RTSX_MS_CARD].p_dev); | |
869 | } | |
870 | ||
871 | static irqreturn_t rtsx_pci_isr(int irq, void *dev_id) | |
872 | { | |
873 | struct rtsx_pcr *pcr = dev_id; | |
874 | u32 int_reg; | |
875 | ||
876 | if (!pcr) | |
877 | return IRQ_NONE; | |
878 | ||
879 | spin_lock(&pcr->lock); | |
880 | ||
881 | int_reg = rtsx_pci_readl(pcr, RTSX_BIPR); | |
882 | /* Clear interrupt flag */ | |
883 | rtsx_pci_writel(pcr, RTSX_BIPR, int_reg); | |
884 | if ((int_reg & pcr->bier) == 0) { | |
885 | spin_unlock(&pcr->lock); | |
886 | return IRQ_NONE; | |
887 | } | |
888 | if (int_reg == 0xFFFFFFFF) { | |
889 | spin_unlock(&pcr->lock); | |
890 | return IRQ_HANDLED; | |
891 | } | |
892 | ||
893 | int_reg &= (pcr->bier | 0x7FFFFF); | |
894 | ||
895 | if (int_reg & SD_INT) { | |
896 | if (int_reg & SD_EXIST) { | |
897 | pcr->card_inserted |= SD_EXIST; | |
898 | } else { | |
899 | pcr->card_removed |= SD_EXIST; | |
900 | pcr->card_inserted &= ~SD_EXIST; | |
901 | } | |
902 | } | |
903 | ||
904 | if (int_reg & MS_INT) { | |
905 | if (int_reg & MS_EXIST) { | |
906 | pcr->card_inserted |= MS_EXIST; | |
907 | } else { | |
908 | pcr->card_removed |= MS_EXIST; | |
909 | pcr->card_inserted &= ~MS_EXIST; | |
910 | } | |
911 | } | |
912 | ||
ada8a8a1 | 913 | if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) { |
98fcc576 | 914 | if (int_reg & (TRANS_FAIL_INT | DELINK_INT)) { |
ada8a8a1 | 915 | pcr->trans_result = TRANS_RESULT_FAIL; |
98fcc576 MC |
916 | if (pcr->done) |
917 | complete(pcr->done); | |
918 | } else if (int_reg & TRANS_OK_INT) { | |
ada8a8a1 | 919 | pcr->trans_result = TRANS_RESULT_OK; |
98fcc576 MC |
920 | if (pcr->done) |
921 | complete(pcr->done); | |
ada8a8a1 WW |
922 | } |
923 | } | |
924 | ||
504decc0 WW |
925 | if (pcr->card_inserted || pcr->card_removed) |
926 | schedule_delayed_work(&pcr->carddet_work, | |
927 | msecs_to_jiffies(200)); | |
928 | ||
ada8a8a1 WW |
929 | spin_unlock(&pcr->lock); |
930 | return IRQ_HANDLED; | |
931 | } | |
932 | ||
933 | static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr) | |
934 | { | |
935 | dev_info(&(pcr->pci->dev), "%s: pcr->msi_en = %d, pci->irq = %d\n", | |
936 | __func__, pcr->msi_en, pcr->pci->irq); | |
937 | ||
938 | if (request_irq(pcr->pci->irq, rtsx_pci_isr, | |
939 | pcr->msi_en ? 0 : IRQF_SHARED, | |
940 | DRV_NAME_RTSX_PCI, pcr)) { | |
941 | dev_err(&(pcr->pci->dev), | |
942 | "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n", | |
943 | pcr->pci->irq); | |
944 | return -1; | |
945 | } | |
946 | ||
947 | pcr->irq = pcr->pci->irq; | |
948 | pci_intx(pcr->pci, !pcr->msi_en); | |
949 | ||
950 | return 0; | |
951 | } | |
952 | ||
953 | static void rtsx_pci_idle_work(struct work_struct *work) | |
954 | { | |
955 | struct delayed_work *dwork = to_delayed_work(work); | |
956 | struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, idle_work); | |
957 | ||
0523b8f4 | 958 | pcr_dbg(pcr, "--> %s\n", __func__); |
ada8a8a1 WW |
959 | |
960 | mutex_lock(&pcr->pcr_mutex); | |
961 | ||
962 | pcr->state = PDEV_STAT_IDLE; | |
963 | ||
964 | if (pcr->ops->disable_auto_blink) | |
965 | pcr->ops->disable_auto_blink(pcr); | |
966 | if (pcr->ops->turn_off_led) | |
967 | pcr->ops->turn_off_led(pcr); | |
968 | ||
773ccdfd | 969 | if (pcr->aspm_en) |
19f3bd54 | 970 | rtsx_pci_enable_aspm(pcr); |
773ccdfd | 971 | |
ada8a8a1 WW |
972 | mutex_unlock(&pcr->pcr_mutex); |
973 | } | |
974 | ||
451be648 | 975 | #ifdef CONFIG_PM |
5947c167 WW |
976 | static void rtsx_pci_power_off(struct rtsx_pcr *pcr, u8 pm_state) |
977 | { | |
978 | if (pcr->ops->turn_off_led) | |
979 | pcr->ops->turn_off_led(pcr); | |
980 | ||
981 | rtsx_pci_writel(pcr, RTSX_BIER, 0); | |
982 | pcr->bier = 0; | |
983 | ||
984 | rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08); | |
985 | rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, pm_state); | |
986 | ||
987 | if (pcr->ops->force_power_down) | |
eb891c65 | 988 | pcr->ops->force_power_down(pcr, pm_state); |
5947c167 | 989 | } |
451be648 | 990 | #endif |
5947c167 | 991 | |
ada8a8a1 WW |
992 | static int rtsx_pci_init_hw(struct rtsx_pcr *pcr) |
993 | { | |
994 | int err; | |
995 | ||
19f3bd54 | 996 | pcr->pcie_cap = pci_find_capability(pcr->pci, PCI_CAP_ID_EXP); |
ada8a8a1 WW |
997 | rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr); |
998 | ||
999 | rtsx_pci_enable_bus_int(pcr); | |
1000 | ||
1001 | /* Power on SSC */ | |
1002 | err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0); | |
1003 | if (err < 0) | |
1004 | return err; | |
1005 | ||
1006 | /* Wait SSC power stable */ | |
1007 | udelay(200); | |
1008 | ||
19f3bd54 | 1009 | rtsx_pci_disable_aspm(pcr); |
ada8a8a1 WW |
1010 | if (pcr->ops->optimize_phy) { |
1011 | err = pcr->ops->optimize_phy(pcr); | |
1012 | if (err < 0) | |
1013 | return err; | |
1014 | } | |
1015 | ||
1016 | rtsx_pci_init_cmd(pcr); | |
1017 | ||
1018 | /* Set mcu_cnt to 7 to ensure data can be sampled properly */ | |
1019 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07); | |
1020 | ||
1021 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00); | |
1022 | /* Disable card clock */ | |
1023 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0); | |
ada8a8a1 WW |
1024 | /* Reset delink mode */ |
1025 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0); | |
1026 | /* Card driving select */ | |
773ccdfd WW |
1027 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL, |
1028 | 0xFF, pcr->card_drive_sel); | |
ada8a8a1 WW |
1029 | /* Enable SSC Clock */ |
1030 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, | |
1031 | 0xFF, SSC_8X_EN | SSC_SEL_4M); | |
1032 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12); | |
1033 | /* Disable cd_pwr_save */ | |
1034 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10); | |
1035 | /* Clear Link Ready Interrupt */ | |
1036 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, | |
1037 | LINK_RDY_INT, LINK_RDY_INT); | |
1038 | /* Enlarge the estimation window of PERST# glitch | |
1039 | * to reduce the chance of invalid card interrupt | |
1040 | */ | |
1041 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80); | |
1042 | /* Update RC oscillator to 400k | |
1043 | * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1 | |
1044 | * 1: 2M 0: 400k | |
1045 | */ | |
1046 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00); | |
1047 | /* Set interrupt write clear | |
1048 | * bit 1: U_elbi_if_rd_clr_en | |
1049 | * 1: Enable ELBI interrupt[31:22] & [7:0] flag read clear | |
1050 | * 0: ELBI interrupt flag[31:22] & [7:0] only can be write clear | |
1051 | */ | |
1052 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0); | |
ada8a8a1 WW |
1053 | |
1054 | err = rtsx_pci_send_cmd(pcr, 100); | |
1055 | if (err < 0) | |
1056 | return err; | |
1057 | ||
1058 | /* Enable clk_request_n to enable clock power management */ | |
19f3bd54 | 1059 | rtsx_pci_write_config_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL + 1, 1); |
ada8a8a1 WW |
1060 | /* Enter L1 when host tx idle */ |
1061 | rtsx_pci_write_config_byte(pcr, 0x70F, 0x5B); | |
1062 | ||
1063 | if (pcr->ops->extra_init_hw) { | |
1064 | err = pcr->ops->extra_init_hw(pcr); | |
1065 | if (err < 0) | |
1066 | return err; | |
1067 | } | |
1068 | ||
c3481955 WW |
1069 | /* No CD interrupt if probing driver with card inserted. |
1070 | * So we need to initialize pcr->card_exist here. | |
1071 | */ | |
1072 | if (pcr->ops->cd_deglitch) | |
1073 | pcr->card_exist = pcr->ops->cd_deglitch(pcr); | |
1074 | else | |
1075 | pcr->card_exist = rtsx_pci_readl(pcr, RTSX_BIPR) & CARD_EXIST; | |
1076 | ||
ada8a8a1 WW |
1077 | return 0; |
1078 | } | |
1079 | ||
1080 | static int rtsx_pci_init_chip(struct rtsx_pcr *pcr) | |
1081 | { | |
1082 | int err; | |
1083 | ||
1084 | spin_lock_init(&pcr->lock); | |
1085 | mutex_init(&pcr->pcr_mutex); | |
1086 | ||
1087 | switch (PCI_PID(pcr)) { | |
1088 | default: | |
1089 | case 0x5209: | |
1090 | rts5209_init_params(pcr); | |
1091 | break; | |
1092 | ||
1093 | case 0x5229: | |
1094 | rts5229_init_params(pcr); | |
1095 | break; | |
1096 | ||
1097 | case 0x5289: | |
1098 | rtl8411_init_params(pcr); | |
1099 | break; | |
e1237932 RT |
1100 | |
1101 | case 0x5227: | |
1102 | rts5227_init_params(pcr); | |
1103 | break; | |
4c4b8c10 WW |
1104 | |
1105 | case 0x5249: | |
1106 | rts5249_init_params(pcr); | |
1107 | break; | |
9032eabd | 1108 | |
663c425f MC |
1109 | case 0x524A: |
1110 | rts524a_init_params(pcr); | |
1111 | break; | |
1112 | ||
41bc2334 MC |
1113 | case 0x525A: |
1114 | rts525a_init_params(pcr); | |
1115 | break; | |
1116 | ||
9032eabd RT |
1117 | case 0x5287: |
1118 | rtl8411b_init_params(pcr); | |
1119 | break; | |
56cb3cc1 MC |
1120 | |
1121 | case 0x5286: | |
1122 | rtl8402_init_params(pcr); | |
1123 | break; | |
ada8a8a1 WW |
1124 | } |
1125 | ||
0523b8f4 | 1126 | pcr_dbg(pcr, "PID: 0x%04x, IC version: 0x%02x\n", |
ada8a8a1 WW |
1127 | PCI_PID(pcr), pcr->ic_version); |
1128 | ||
1129 | pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot), | |
1130 | GFP_KERNEL); | |
1131 | if (!pcr->slots) | |
1132 | return -ENOMEM; | |
1133 | ||
773ccdfd WW |
1134 | if (pcr->ops->fetch_vendor_settings) |
1135 | pcr->ops->fetch_vendor_settings(pcr); | |
1136 | ||
0523b8f4 MC |
1137 | pcr_dbg(pcr, "pcr->aspm_en = 0x%x\n", pcr->aspm_en); |
1138 | pcr_dbg(pcr, "pcr->sd30_drive_sel_1v8 = 0x%x\n", | |
773ccdfd | 1139 | pcr->sd30_drive_sel_1v8); |
0523b8f4 | 1140 | pcr_dbg(pcr, "pcr->sd30_drive_sel_3v3 = 0x%x\n", |
773ccdfd | 1141 | pcr->sd30_drive_sel_3v3); |
0523b8f4 | 1142 | pcr_dbg(pcr, "pcr->card_drive_sel = 0x%x\n", |
773ccdfd | 1143 | pcr->card_drive_sel); |
0523b8f4 | 1144 | pcr_dbg(pcr, "pcr->flags = 0x%x\n", pcr->flags); |
773ccdfd | 1145 | |
ada8a8a1 WW |
1146 | pcr->state = PDEV_STAT_IDLE; |
1147 | err = rtsx_pci_init_hw(pcr); | |
1148 | if (err < 0) { | |
1149 | kfree(pcr->slots); | |
1150 | return err; | |
1151 | } | |
1152 | ||
1153 | return 0; | |
1154 | } | |
1155 | ||
612b95cd GKH |
1156 | static int rtsx_pci_probe(struct pci_dev *pcidev, |
1157 | const struct pci_device_id *id) | |
ada8a8a1 WW |
1158 | { |
1159 | struct rtsx_pcr *pcr; | |
1160 | struct pcr_handle *handle; | |
1161 | u32 base, len; | |
41bc2334 | 1162 | int ret, i, bar = 0; |
ada8a8a1 WW |
1163 | |
1164 | dev_dbg(&(pcidev->dev), | |
1165 | ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n", | |
1166 | pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device, | |
1167 | (int)pcidev->revision); | |
1168 | ||
f84ef042 WW |
1169 | ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32)); |
1170 | if (ret < 0) | |
1171 | return ret; | |
1172 | ||
ada8a8a1 WW |
1173 | ret = pci_enable_device(pcidev); |
1174 | if (ret) | |
1175 | return ret; | |
1176 | ||
1177 | ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCI); | |
1178 | if (ret) | |
1179 | goto disable; | |
1180 | ||
1181 | pcr = kzalloc(sizeof(*pcr), GFP_KERNEL); | |
1182 | if (!pcr) { | |
1183 | ret = -ENOMEM; | |
1184 | goto release_pci; | |
1185 | } | |
1186 | ||
1187 | handle = kzalloc(sizeof(*handle), GFP_KERNEL); | |
1188 | if (!handle) { | |
1189 | ret = -ENOMEM; | |
1190 | goto free_pcr; | |
1191 | } | |
1192 | handle->pcr = pcr; | |
1193 | ||
9f12563d | 1194 | idr_preload(GFP_KERNEL); |
ada8a8a1 | 1195 | spin_lock(&rtsx_pci_lock); |
9f12563d TH |
1196 | ret = idr_alloc(&rtsx_pci_idr, pcr, 0, 0, GFP_NOWAIT); |
1197 | if (ret >= 0) | |
1198 | pcr->id = ret; | |
ada8a8a1 | 1199 | spin_unlock(&rtsx_pci_lock); |
9f12563d TH |
1200 | idr_preload_end(); |
1201 | if (ret < 0) | |
ada8a8a1 WW |
1202 | goto free_handle; |
1203 | ||
1204 | pcr->pci = pcidev; | |
1205 | dev_set_drvdata(&pcidev->dev, handle); | |
1206 | ||
41bc2334 MC |
1207 | if (CHK_PCI_PID(pcr, 0x525A)) |
1208 | bar = 1; | |
1209 | len = pci_resource_len(pcidev, bar); | |
1210 | base = pci_resource_start(pcidev, bar); | |
ada8a8a1 WW |
1211 | pcr->remap_addr = ioremap_nocache(base, len); |
1212 | if (!pcr->remap_addr) { | |
1213 | ret = -ENOMEM; | |
af1192d7 | 1214 | goto free_handle; |
ada8a8a1 WW |
1215 | } |
1216 | ||
1217 | pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev), | |
1218 | RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr), | |
1219 | GFP_KERNEL); | |
1220 | if (pcr->rtsx_resv_buf == NULL) { | |
1221 | ret = -ENXIO; | |
1222 | goto unmap; | |
1223 | } | |
1224 | pcr->host_cmds_ptr = pcr->rtsx_resv_buf; | |
1225 | pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr; | |
1226 | pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN; | |
1227 | pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN; | |
1228 | ||
1229 | pcr->card_inserted = 0; | |
1230 | pcr->card_removed = 0; | |
1231 | INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect); | |
1232 | INIT_DELAYED_WORK(&pcr->idle_work, rtsx_pci_idle_work); | |
1233 | ||
1234 | pcr->msi_en = msi_en; | |
1235 | if (pcr->msi_en) { | |
1236 | ret = pci_enable_msi(pcidev); | |
51529705 | 1237 | if (ret) |
ada8a8a1 WW |
1238 | pcr->msi_en = false; |
1239 | } | |
1240 | ||
1241 | ret = rtsx_pci_acquire_irq(pcr); | |
1242 | if (ret < 0) | |
9d66b568 | 1243 | goto disable_msi; |
ada8a8a1 WW |
1244 | |
1245 | pci_set_master(pcidev); | |
1246 | synchronize_irq(pcr->irq); | |
1247 | ||
1248 | ret = rtsx_pci_init_chip(pcr); | |
1249 | if (ret < 0) | |
1250 | goto disable_irq; | |
1251 | ||
1252 | for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) { | |
1253 | rtsx_pcr_cells[i].platform_data = handle; | |
1254 | rtsx_pcr_cells[i].pdata_size = sizeof(*handle); | |
1255 | } | |
1256 | ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells, | |
1257 | ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL); | |
1258 | if (ret < 0) | |
1259 | goto disable_irq; | |
1260 | ||
1261 | schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200)); | |
1262 | ||
1263 | return 0; | |
1264 | ||
1265 | disable_irq: | |
1266 | free_irq(pcr->irq, (void *)pcr); | |
9d66b568 JS |
1267 | disable_msi: |
1268 | if (pcr->msi_en) | |
1269 | pci_disable_msi(pcr->pci); | |
ada8a8a1 WW |
1270 | dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN, |
1271 | pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr); | |
1272 | unmap: | |
1273 | iounmap(pcr->remap_addr); | |
ada8a8a1 WW |
1274 | free_handle: |
1275 | kfree(handle); | |
1276 | free_pcr: | |
1277 | kfree(pcr); | |
1278 | release_pci: | |
1279 | pci_release_regions(pcidev); | |
1280 | disable: | |
1281 | pci_disable_device(pcidev); | |
1282 | ||
1283 | return ret; | |
1284 | } | |
1285 | ||
612b95cd | 1286 | static void rtsx_pci_remove(struct pci_dev *pcidev) |
ada8a8a1 WW |
1287 | { |
1288 | struct pcr_handle *handle = pci_get_drvdata(pcidev); | |
1289 | struct rtsx_pcr *pcr = handle->pcr; | |
1290 | ||
1291 | pcr->remove_pci = true; | |
1292 | ||
73beb63d TG |
1293 | /* Disable interrupts at the pcr level */ |
1294 | spin_lock_irq(&pcr->lock); | |
1295 | rtsx_pci_writel(pcr, RTSX_BIER, 0); | |
1296 | pcr->bier = 0; | |
1297 | spin_unlock_irq(&pcr->lock); | |
1298 | ||
1299 | cancel_delayed_work_sync(&pcr->carddet_work); | |
1300 | cancel_delayed_work_sync(&pcr->idle_work); | |
ada8a8a1 WW |
1301 | |
1302 | mfd_remove_devices(&pcidev->dev); | |
1303 | ||
1304 | dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN, | |
1305 | pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr); | |
1306 | free_irq(pcr->irq, (void *)pcr); | |
1307 | if (pcr->msi_en) | |
1308 | pci_disable_msi(pcr->pci); | |
1309 | iounmap(pcr->remap_addr); | |
1310 | ||
ada8a8a1 WW |
1311 | pci_release_regions(pcidev); |
1312 | pci_disable_device(pcidev); | |
1313 | ||
1314 | spin_lock(&rtsx_pci_lock); | |
1315 | idr_remove(&rtsx_pci_idr, pcr->id); | |
1316 | spin_unlock(&rtsx_pci_lock); | |
1317 | ||
1318 | kfree(pcr->slots); | |
1319 | kfree(pcr); | |
1320 | kfree(handle); | |
1321 | ||
1322 | dev_dbg(&(pcidev->dev), | |
1323 | ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n", | |
1324 | pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device); | |
1325 | } | |
1326 | ||
1327 | #ifdef CONFIG_PM | |
1328 | ||
1329 | static int rtsx_pci_suspend(struct pci_dev *pcidev, pm_message_t state) | |
1330 | { | |
1331 | struct pcr_handle *handle; | |
1332 | struct rtsx_pcr *pcr; | |
ada8a8a1 WW |
1333 | |
1334 | dev_dbg(&(pcidev->dev), "--> %s\n", __func__); | |
1335 | ||
1336 | handle = pci_get_drvdata(pcidev); | |
1337 | pcr = handle->pcr; | |
1338 | ||
1339 | cancel_delayed_work(&pcr->carddet_work); | |
1340 | cancel_delayed_work(&pcr->idle_work); | |
1341 | ||
1342 | mutex_lock(&pcr->pcr_mutex); | |
1343 | ||
5947c167 | 1344 | rtsx_pci_power_off(pcr, HOST_ENTER_S3); |
ada8a8a1 WW |
1345 | |
1346 | pci_save_state(pcidev); | |
1347 | pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0); | |
1348 | pci_disable_device(pcidev); | |
1349 | pci_set_power_state(pcidev, pci_choose_state(pcidev, state)); | |
1350 | ||
1351 | mutex_unlock(&pcr->pcr_mutex); | |
5947c167 | 1352 | return 0; |
ada8a8a1 WW |
1353 | } |
1354 | ||
1355 | static int rtsx_pci_resume(struct pci_dev *pcidev) | |
1356 | { | |
1357 | struct pcr_handle *handle; | |
1358 | struct rtsx_pcr *pcr; | |
1359 | int ret = 0; | |
1360 | ||
1361 | dev_dbg(&(pcidev->dev), "--> %s\n", __func__); | |
1362 | ||
1363 | handle = pci_get_drvdata(pcidev); | |
1364 | pcr = handle->pcr; | |
1365 | ||
1366 | mutex_lock(&pcr->pcr_mutex); | |
1367 | ||
1368 | pci_set_power_state(pcidev, PCI_D0); | |
1369 | pci_restore_state(pcidev); | |
1370 | ret = pci_enable_device(pcidev); | |
1371 | if (ret) | |
1372 | goto out; | |
1373 | pci_set_master(pcidev); | |
1374 | ||
1375 | ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00); | |
1376 | if (ret) | |
1377 | goto out; | |
1378 | ||
1379 | ret = rtsx_pci_init_hw(pcr); | |
1380 | if (ret) | |
1381 | goto out; | |
1382 | ||
1383 | schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200)); | |
1384 | ||
1385 | out: | |
1386 | mutex_unlock(&pcr->pcr_mutex); | |
1387 | return ret; | |
1388 | } | |
1389 | ||
5947c167 WW |
1390 | static void rtsx_pci_shutdown(struct pci_dev *pcidev) |
1391 | { | |
1392 | struct pcr_handle *handle; | |
1393 | struct rtsx_pcr *pcr; | |
1394 | ||
1395 | dev_dbg(&(pcidev->dev), "--> %s\n", __func__); | |
1396 | ||
1397 | handle = pci_get_drvdata(pcidev); | |
1398 | pcr = handle->pcr; | |
1399 | rtsx_pci_power_off(pcr, HOST_ENTER_S1); | |
1400 | ||
1401 | pci_disable_device(pcidev); | |
1402 | } | |
1403 | ||
ada8a8a1 WW |
1404 | #else /* CONFIG_PM */ |
1405 | ||
1406 | #define rtsx_pci_suspend NULL | |
1407 | #define rtsx_pci_resume NULL | |
5947c167 | 1408 | #define rtsx_pci_shutdown NULL |
ada8a8a1 WW |
1409 | |
1410 | #endif /* CONFIG_PM */ | |
1411 | ||
1412 | static struct pci_driver rtsx_pci_driver = { | |
1413 | .name = DRV_NAME_RTSX_PCI, | |
1414 | .id_table = rtsx_pci_ids, | |
1415 | .probe = rtsx_pci_probe, | |
612b95cd | 1416 | .remove = rtsx_pci_remove, |
ada8a8a1 WW |
1417 | .suspend = rtsx_pci_suspend, |
1418 | .resume = rtsx_pci_resume, | |
5947c167 | 1419 | .shutdown = rtsx_pci_shutdown, |
ada8a8a1 WW |
1420 | }; |
1421 | module_pci_driver(rtsx_pci_driver); | |
1422 | ||
1423 | MODULE_LICENSE("GPL"); | |
1424 | MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>"); | |
1425 | MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver"); |