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video: bf54x-lq043fb: fix build error
[deliverable/linux.git] / drivers / mfd / rtsx_pcr.c
CommitLineData
ada8a8a1
WW		 1/* Driver for Realtek PCI-Express card reader
2 *
09fd8678 3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
ada8a8a1
WW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
ada8a8a1
WW		 20 */
21
22#include <linux/pci.h>
23#include <linux/module.h>
aec17ea1 24#include <linux/slab.h>
ada8a8a1
WW		 25#include <linux/dma-mapping.h>
26#include <linux/highmem.h>
27#include <linux/interrupt.h>
28#include <linux/delay.h>
29#include <linux/idr.h>
30#include <linux/platform_device.h>
31#include <linux/mfd/core.h>
32#include <linux/mfd/rtsx_pci.h>
33#include <asm/unaligned.h>
34
35#include "rtsx_pcr.h"
36
37static bool msi_en = true;
38module_param(msi_en, bool, S_IRUGO | S_IWUSR);
39MODULE_PARM_DESC(msi_en, "Enable MSI");
40
41static DEFINE_IDR(rtsx_pci_idr);
42static DEFINE_SPINLOCK(rtsx_pci_lock);
43
44static struct mfd_cell rtsx_pcr_cells[] = {
45 [RTSX_SD_CARD] = {
46 .name = DRV_NAME_RTSX_PCI_SDMMC,
47 },
48 [RTSX_MS_CARD] = {
49 .name = DRV_NAME_RTSX_PCI_MS,
50 },
51};
52
36fcd06c 53static const struct pci_device_id rtsx_pci_ids[] = {
ada8a8a1
WW		 54 { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 },
55 { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 },
56 { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 },
e1237932 57 { PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS << 16, 0xFF0000 },
4c4b8c10 58 { PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 },
9032eabd 59 { PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 },
56cb3cc1 60 { PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS << 16, 0xFF0000 },
ada8a8a1
WW		 61 { 0, }
62};
63
64MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
65
66void rtsx_pci_start_run(struct rtsx_pcr *pcr)
67{
68 /* If pci device removed, don't queue idle work any more */
69 if (pcr->remove_pci)
70 return;
71
72 if (pcr->state != PDEV_STAT_RUN) {
73 pcr->state = PDEV_STAT_RUN;
74 if (pcr->ops->enable_auto_blink)
75 pcr->ops->enable_auto_blink(pcr);
773ccdfd
WW		 76
77 if (pcr->aspm_en)
78 rtsx_pci_write_config_byte(pcr, LCTLR, 0);
ada8a8a1
WW		 79 }
80
81 mod_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200));
82}
83EXPORT_SYMBOL_GPL(rtsx_pci_start_run);
84
85int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data)
86{
87 int i;
88 u32 val = HAIMR_WRITE_START;
89
90 val |= (u32)(addr & 0x3FFF) << 16;
91 val |= (u32)mask << 8;
92 val |= (u32)data;
93
94 rtsx_pci_writel(pcr, RTSX_HAIMR, val);
95
96 for (i = 0; i < MAX_RW_REG_CNT; i++) {
97 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
98 if ((val & HAIMR_TRANS_END) == 0) {
99 if (data != (u8)val)
100 return -EIO;
101 return 0;
102 }
103 }
104
105 return -ETIMEDOUT;
106}
107EXPORT_SYMBOL_GPL(rtsx_pci_write_register);
108
109int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
110{
111 u32 val = HAIMR_READ_START;
112 int i;
113
114 val |= (u32)(addr & 0x3FFF) << 16;
115 rtsx_pci_writel(pcr, RTSX_HAIMR, val);
116
117 for (i = 0; i < MAX_RW_REG_CNT; i++) {
118 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
119 if ((val & HAIMR_TRANS_END) == 0)
120 break;
121 }
122
123 if (i >= MAX_RW_REG_CNT)
124 return -ETIMEDOUT;
125
126 if (data)
127 *data = (u8)(val & 0xFF);
128
129 return 0;
130}
131EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
132
133int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
134{
135 int err, i, finished = 0;
136 u8 tmp;
137
138 rtsx_pci_init_cmd(pcr);
139
140 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA0, 0xFF, (u8)val);
141 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA1, 0xFF, (u8)(val >> 8));
142 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
143 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x81);
144
145 err = rtsx_pci_send_cmd(pcr, 100);
146 if (err < 0)
147 return err;
148
149 for (i = 0; i < 100000; i++) {
150 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
151 if (err < 0)
152 return err;
153
154 if (!(tmp & 0x80)) {
155 finished = 1;
156 break;
157 }
158 }
159
160 if (!finished)
161 return -ETIMEDOUT;
162
163 return 0;
164}
165EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
166
167int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
168{
169 int err, i, finished = 0;
170 u16 data;
171 u8 *ptr, tmp;
172
173 rtsx_pci_init_cmd(pcr);
174
175 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
176 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x80);
177
178 err = rtsx_pci_send_cmd(pcr, 100);
179 if (err < 0)
180 return err;
181
182 for (i = 0; i < 100000; i++) {
183 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
184 if (err < 0)
185 return err;
186
187 if (!(tmp & 0x80)) {
188 finished = 1;
189 break;
190 }
191 }
192
193 if (!finished)
194 return -ETIMEDOUT;
195
196 rtsx_pci_init_cmd(pcr);
197
198 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA0, 0, 0);
199 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA1, 0, 0);
200
201 err = rtsx_pci_send_cmd(pcr, 100);
202 if (err < 0)
203 return err;
204
205 ptr = rtsx_pci_get_cmd_data(pcr);
206 data = ((u16)ptr[1] << 8) | ptr[0];
207
208 if (val)
209 *val = data;
210
211 return 0;
212}
213EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register);
214
215void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
216{
217 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
218 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
219
220 rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80);
221 rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80);
222}
223EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd);
224
225void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
226 u8 cmd_type, u16 reg_addr, u8 mask, u8 data)
227{
228 unsigned long flags;
229 u32 val = 0;
230 u32 *ptr = (u32 *)(pcr->host_cmds_ptr);
231
232 val |= (u32)(cmd_type & 0x03) << 30;
233 val |= (u32)(reg_addr & 0x3FFF) << 16;
234 val |= (u32)mask << 8;
235 val |= (u32)data;
236
237 spin_lock_irqsave(&pcr->lock, flags);
238 ptr += pcr->ci;
239 if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) {
240 put_unaligned_le32(val, ptr);
241 ptr++;
242 pcr->ci++;
243 }
244 spin_unlock_irqrestore(&pcr->lock, flags);
245}
246EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd);
247
248void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr)
249{
250 u32 val = 1 << 31;
251
252 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
253
254 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
255 /* Hardware Auto Response */
256 val |= 0x40000000;
257 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
258}
259EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait);
260
261int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout)
262{
263 struct completion trans_done;
264 u32 val = 1 << 31;
265 long timeleft;
266 unsigned long flags;
267 int err = 0;
268
269 spin_lock_irqsave(&pcr->lock, flags);
270
271 /* set up data structures for the wakeup system */
272 pcr->done = &trans_done;
273 pcr->trans_result = TRANS_NOT_READY;
274 init_completion(&trans_done);
275
276 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
277
278 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
279 /* Hardware Auto Response */
280 val |= 0x40000000;
281 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
282
283 spin_unlock_irqrestore(&pcr->lock, flags);
284
285 /* Wait for TRANS_OK_INT */
286 timeleft = wait_for_completion_interruptible_timeout(
287 &trans_done, msecs_to_jiffies(timeout));
288 if (timeleft <= 0) {
289 dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
290 __func__, __LINE__);
291 err = -ETIMEDOUT;
292 goto finish_send_cmd;
293 }
294
295 spin_lock_irqsave(&pcr->lock, flags);
296 if (pcr->trans_result == TRANS_RESULT_FAIL)
297 err = -EINVAL;
298 else if (pcr->trans_result == TRANS_RESULT_OK)
299 err = 0;
300 else if (pcr->trans_result == TRANS_NO_DEVICE)
301 err = -ENODEV;
302 spin_unlock_irqrestore(&pcr->lock, flags);
303
304finish_send_cmd:
305 spin_lock_irqsave(&pcr->lock, flags);
306 pcr->done = NULL;
307 spin_unlock_irqrestore(&pcr->lock, flags);
308
309 if ((err < 0) && (err != -ENODEV))
310 rtsx_pci_stop_cmd(pcr);
311
312 if (pcr->finish_me)
313 complete(pcr->finish_me);
314
315 return err;
316}
317EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd);
318
319static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr,
320 dma_addr_t addr, unsigned int len, int end)
321{
322 u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi;
323 u64 val;
324 u8 option = SG_VALID | SG_TRANS_DATA;
325
326 dev_dbg(&(pcr->pci->dev), "DMA addr: 0x%x, Len: 0x%x\n",
327 (unsigned int)addr, len);
328
329 if (end)
330 option |= SG_END;
331 val = ((u64)addr << 32) | ((u64)len << 12) | option;
332
333 put_unaligned_le64(val, ptr);
ada8a8a1
WW		 334 pcr->sgi++;
335}
336
337int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
338 int num_sg, bool read, int timeout)
339{
340 struct completion trans_done;
c42deffd 341 int err = 0, count;
ada8a8a1
WW		 342 long timeleft;
343 unsigned long flags;
ada8a8a1 344
c42deffd 345 count = rtsx_pci_dma_map_sg(pcr, sglist, num_sg, read);
ada8a8a1
WW		 346 if (count < 1) {
347 dev_err(&(pcr->pci->dev), "scatterlist map failed\n");
348 return -EINVAL;
349 }
350 dev_dbg(&(pcr->pci->dev), "DMA mapping count: %d\n", count);
351
ada8a8a1
WW		 352
353 spin_lock_irqsave(&pcr->lock, flags);
354
355 pcr->done = &trans_done;
356 pcr->trans_result = TRANS_NOT_READY;
357 init_completion(&trans_done);
ada8a8a1
WW		 358
359 spin_unlock_irqrestore(&pcr->lock, flags);
360
c42deffd
MC		 361 rtsx_pci_dma_transfer(pcr, sglist, count, read);
362
ada8a8a1
WW		 363 timeleft = wait_for_completion_interruptible_timeout(
364 &trans_done, msecs_to_jiffies(timeout));
365 if (timeleft <= 0) {
366 dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
367 __func__, __LINE__);
368 err = -ETIMEDOUT;
369 goto out;
370 }
371
372 spin_lock_irqsave(&pcr->lock, flags);
373
374 if (pcr->trans_result == TRANS_RESULT_FAIL)
375 err = -EINVAL;
376 else if (pcr->trans_result == TRANS_NO_DEVICE)
377 err = -ENODEV;
378
379 spin_unlock_irqrestore(&pcr->lock, flags);
380
381out:
382 spin_lock_irqsave(&pcr->lock, flags);
383 pcr->done = NULL;
384 spin_unlock_irqrestore(&pcr->lock, flags);
385
c42deffd 386 rtsx_pci_dma_unmap_sg(pcr, sglist, num_sg, read);
ada8a8a1
WW		 387
388 if ((err < 0) && (err != -ENODEV))
389 rtsx_pci_stop_cmd(pcr);
390
391 if (pcr->finish_me)
392 complete(pcr->finish_me);
393
394 return err;
395}
396EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data);
397
c42deffd
MC		 398int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
399 int num_sg, bool read)
400{
401 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
402
403 if (pcr->remove_pci)
404 return -EINVAL;
405
406 if ((sglist == NULL) || num_sg < 1)
407 return -EINVAL;
408
409 return dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dir);
410}
411EXPORT_SYMBOL_GPL(rtsx_pci_dma_map_sg);
412
413int rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
414 int num_sg, bool read)
415{
416 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
417
418 if (pcr->remove_pci)
419 return -EINVAL;
420
421 if (sglist == NULL || num_sg < 1)
422 return -EINVAL;
423
424 dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dir);
425 return num_sg;
426}
427EXPORT_SYMBOL_GPL(rtsx_pci_dma_unmap_sg);
428
429int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist,
430 int sg_count, bool read)
431{
432 struct scatterlist *sg;
433 dma_addr_t addr;
434 unsigned int len;
435 int i;
436 u32 val;
437 u8 dir = read ? DEVICE_TO_HOST : HOST_TO_DEVICE;
438 unsigned long flags;
439
440 if (pcr->remove_pci)
441 return -EINVAL;
442
443 if ((sglist == NULL) || (sg_count < 1))
444 return -EINVAL;
445
446 val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE;
447 pcr->sgi = 0;
448 for_each_sg(sglist, sg, sg_count, i) {
449 addr = sg_dma_address(sg);
450 len = sg_dma_len(sg);
451 rtsx_pci_add_sg_tbl(pcr, addr, len, i == sg_count - 1);
452 }
453
454 spin_lock_irqsave(&pcr->lock, flags);
455
456 rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr);
457 rtsx_pci_writel(pcr, RTSX_HDBCTLR, val);
458
459 spin_unlock_irqrestore(&pcr->lock, flags);
460
461 return 0;
462}
463EXPORT_SYMBOL_GPL(rtsx_pci_dma_transfer);
464
ada8a8a1
WW		 465int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
466{
467 int err;
468 int i, j;
469 u16 reg;
470 u8 *ptr;
471
472 if (buf_len > 512)
473 buf_len = 512;
474
475 ptr = buf;
476 reg = PPBUF_BASE2;
477 for (i = 0; i < buf_len / 256; i++) {
478 rtsx_pci_init_cmd(pcr);
479
480 for (j = 0; j < 256; j++)
481 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
482
483 err = rtsx_pci_send_cmd(pcr, 250);
484 if (err < 0)
485 return err;
486
487 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256);
488 ptr += 256;
489 }
490
491 if (buf_len % 256) {
492 rtsx_pci_init_cmd(pcr);
493
494 for (j = 0; j < buf_len % 256; j++)
495 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
496
497 err = rtsx_pci_send_cmd(pcr, 250);
498 if (err < 0)
499 return err;
500 }
501
502 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256);
503
504 return 0;
505}
506EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf);
507
508int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
509{
510 int err;
511 int i, j;
512 u16 reg;
513 u8 *ptr;
514
515 if (buf_len > 512)
516 buf_len = 512;
517
518 ptr = buf;
519 reg = PPBUF_BASE2;
520 for (i = 0; i < buf_len / 256; i++) {
521 rtsx_pci_init_cmd(pcr);
522
523 for (j = 0; j < 256; j++) {
524 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
525 reg++, 0xFF, *ptr);
526 ptr++;
527 }
528
529 err = rtsx_pci_send_cmd(pcr, 250);
530 if (err < 0)
531 return err;
532 }
533
534 if (buf_len % 256) {
535 rtsx_pci_init_cmd(pcr);
536
537 for (j = 0; j < buf_len % 256; j++) {
538 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
539 reg++, 0xFF, *ptr);
540 ptr++;
541 }
542
543 err = rtsx_pci_send_cmd(pcr, 250);
544 if (err < 0)
545 return err;
546 }
547
548 return 0;
549}
550EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf);
551
552static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl)
553{
554 int err;
555
556 rtsx_pci_init_cmd(pcr);
557
558 while (*tbl & 0xFFFF0000) {
559 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
560 (u16)(*tbl >> 16), 0xFF, (u8)(*tbl));
561 tbl++;
562 }
563
564 err = rtsx_pci_send_cmd(pcr, 100);
565 if (err < 0)
566 return err;
567
568 return 0;
569}
570
571int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card)
572{
573 const u32 *tbl;
574
575 if (card == RTSX_SD_CARD)
576 tbl = pcr->sd_pull_ctl_enable_tbl;
577 else if (card == RTSX_MS_CARD)
578 tbl = pcr->ms_pull_ctl_enable_tbl;
579 else
580 return -EINVAL;
581
582 return rtsx_pci_set_pull_ctl(pcr, tbl);
583}
584EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable);
585
586int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card)
587{
588 const u32 *tbl;
589
590 if (card == RTSX_SD_CARD)
591 tbl = pcr->sd_pull_ctl_disable_tbl;
592 else if (card == RTSX_MS_CARD)
593 tbl = pcr->ms_pull_ctl_disable_tbl;
594 else
595 return -EINVAL;
596
597
598 return rtsx_pci_set_pull_ctl(pcr, tbl);
599}
600EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable);
601
602static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
603{
604 pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN;
605
606 if (pcr->num_slots > 1)
607 pcr->bier |= MS_INT_EN;
608
609 /* Enable Bus Interrupt */
610 rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
611
612 dev_dbg(&(pcr->pci->dev), "RTSX_BIER: 0x%08x\n", pcr->bier);
613}
614
615static inline u8 double_ssc_depth(u8 depth)
616{
617 return ((depth > 1) ? (depth - 1) : depth);
618}
619
620static u8 revise_ssc_depth(u8 ssc_depth, u8 div)
621{
622 if (div > CLK_DIV_1) {
623 if (ssc_depth > (div - 1))
624 ssc_depth -= (div - 1);
625 else
626 ssc_depth = SSC_DEPTH_4M;
627 }
628
629 return ssc_depth;
630}
631
632int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
633 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
634{
635 int err, clk;
eebbe254 636 u8 n, clk_divider, mcu_cnt, div;
ada8a8a1
WW		 637 u8 depth[] = {
638 [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M,
639 [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M,
640 [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M,
641 [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K,
642 [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K,
643 };
644
645 if (initial_mode) {
646 /* We use 250k(around) here, in initial stage */
647 clk_divider = SD_CLK_DIVIDE_128;
648 card_clock = 30000000;
649 } else {
650 clk_divider = SD_CLK_DIVIDE_0;
651 }
652 err = rtsx_pci_write_register(pcr, SD_CFG1,
653 SD_CLK_DIVIDE_MASK, clk_divider);
654 if (err < 0)
655 return err;
656
657 card_clock /= 1000000;
658 dev_dbg(&(pcr->pci->dev), "Switch card clock to %dMHz\n", card_clock);
659
ada8a8a1
WW		 660 clk = card_clock;
661 if (!initial_mode && double_clk)
662 clk = card_clock * 2;
663 dev_dbg(&(pcr->pci->dev),
664 "Internal SSC clock: %dMHz (cur_clock = %d)\n",
665 clk, pcr->cur_clock);
666
667 if (clk == pcr->cur_clock)
668 return 0;
669
ab4e8f8b 670 if (pcr->ops->conv_clk_and_div_n)
678cacdf 671 n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
ab4e8f8b 672 else
678cacdf 673 n = (u8)(clk - 2);
eebbe254 674 if ((clk <= 2) || (n > MAX_DIV_N_PCR))
ada8a8a1
WW		 675 return -EINVAL;
676
677 mcu_cnt = (u8)(125/clk + 3);
678 if (mcu_cnt > 15)
679 mcu_cnt = 15;
680
eebbe254 681 /* Make sure that the SSC clock div_n is not less than MIN_DIV_N_PCR */
ada8a8a1 682 div = CLK_DIV_1;
eebbe254 683 while ((n < MIN_DIV_N_PCR) && (div < CLK_DIV_8)) {
ab4e8f8b 684 if (pcr->ops->conv_clk_and_div_n) {
678cacdf 685 int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
ab4e8f8b 686 DIV_N_TO_CLK) * 2;
678cacdf 687 n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk,
ab4e8f8b
WW		 688 CLK_TO_DIV_N);
689 } else {
678cacdf 690 n = (n + 2) * 2 - 2;
ab4e8f8b 691 }
ada8a8a1
WW		 692 div++;
693 }
678cacdf 694 dev_dbg(&(pcr->pci->dev), "n = %d, div = %d\n", n, div);
ada8a8a1
WW		 695
696 ssc_depth = depth[ssc_depth];
697 if (double_clk)
698 ssc_depth = double_ssc_depth(ssc_depth);
699
700 ssc_depth = revise_ssc_depth(ssc_depth, div);
701 dev_dbg(&(pcr->pci->dev), "ssc_depth = %d\n", ssc_depth);
702
703 rtsx_pci_init_cmd(pcr);
704 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
705 CLK_LOW_FREQ, CLK_LOW_FREQ);
706 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
707 0xFF, (div << 4) | mcu_cnt);
708 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
709 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
710 SSC_DEPTH_MASK, ssc_depth);
678cacdf 711 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
ada8a8a1
WW		 712 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
713 if (vpclk) {
714 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
715 PHASE_NOT_RESET, 0);
716 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
717 PHASE_NOT_RESET, PHASE_NOT_RESET);
718 }
719
720 err = rtsx_pci_send_cmd(pcr, 2000);
721 if (err < 0)
722 return err;
723
724 /* Wait SSC clock stable */
725 udelay(10);
726 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
727 if (err < 0)
728 return err;
729
730 pcr->cur_clock = clk;
731 return 0;
732}
733EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock);
734
735int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card)
736{
737 if (pcr->ops->card_power_on)
738 return pcr->ops->card_power_on(pcr, card);
739
740 return 0;
741}
742EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on);
743
744int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card)
745{
746 if (pcr->ops->card_power_off)
747 return pcr->ops->card_power_off(pcr, card);
748
749 return 0;
750}
751EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off);
752
c3481955
WW		 753int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card)
754{
755 unsigned int cd_mask[] = {
756 [RTSX_SD_CARD] = SD_EXIST,
757 [RTSX_MS_CARD] = MS_EXIST
758 };
759
773ccdfd 760 if (!(pcr->flags & PCR_MS_PMOS)) {
c3481955
WW		 761 /* When using single PMOS, accessing card is not permitted
762 * if the existing card is not the designated one.
763 */
764 if (pcr->card_exist & (~cd_mask[card]))
765 return -EIO;
766 }
767
768 return 0;
769}
770EXPORT_SYMBOL_GPL(rtsx_pci_card_exclusive_check);
771
d817ac4e
WW		 772int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
773{
774 if (pcr->ops->switch_output_voltage)
775 return pcr->ops->switch_output_voltage(pcr, voltage);
776
777 return 0;
778}
779EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage);
780
ada8a8a1
WW		 781unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr)
782{
783 unsigned int val;
784
785 val = rtsx_pci_readl(pcr, RTSX_BIPR);
786 if (pcr->ops->cd_deglitch)
787 val = pcr->ops->cd_deglitch(pcr);
788
789 return val;
790}
791EXPORT_SYMBOL_GPL(rtsx_pci_card_exist);
792
793void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr)
794{
795 struct completion finish;
796
797 pcr->finish_me = &finish;
798 init_completion(&finish);
799
800 if (pcr->done)
801 complete(pcr->done);
802
803 if (!pcr->remove_pci)
804 rtsx_pci_stop_cmd(pcr);
805
806 wait_for_completion_interruptible_timeout(&finish,
807 msecs_to_jiffies(2));
808 pcr->finish_me = NULL;
809}
810EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer);
811
812static void rtsx_pci_card_detect(struct work_struct *work)
813{
814 struct delayed_work *dwork;
815 struct rtsx_pcr *pcr;
816 unsigned long flags;
504decc0 817 unsigned int card_detect = 0, card_inserted, card_removed;
ada8a8a1
WW		 818 u32 irq_status;
819
820 dwork = to_delayed_work(work);
821 pcr = container_of(dwork, struct rtsx_pcr, carddet_work);
822
823 dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
824
504decc0 825 mutex_lock(&pcr->pcr_mutex);
ada8a8a1
WW		 826 spin_lock_irqsave(&pcr->lock, flags);
827
828 irq_status = rtsx_pci_readl(pcr, RTSX_BIPR);
829 dev_dbg(&(pcr->pci->dev), "irq_status: 0x%08x\n", irq_status);
830
504decc0
WW		 831 irq_status &= CARD_EXIST;
832 card_inserted = pcr->card_inserted & irq_status;
833 card_removed = pcr->card_removed;
834 pcr->card_inserted = 0;
835 pcr->card_removed = 0;
836
837 spin_unlock_irqrestore(&pcr->lock, flags);
838
839 if (card_inserted || card_removed) {
ada8a8a1
WW		 840 dev_dbg(&(pcr->pci->dev),
841 "card_inserted: 0x%x, card_removed: 0x%x\n",
504decc0 842 card_inserted, card_removed);
ada8a8a1
WW		 843
844 if (pcr->ops->cd_deglitch)
504decc0 845 card_inserted = pcr->ops->cd_deglitch(pcr);
ada8a8a1 846
504decc0 847 card_detect = card_inserted | card_removed;
c3481955
WW		 848
849 pcr->card_exist |= card_inserted;
850 pcr->card_exist &= ~card_removed;
ada8a8a1
WW		 851 }
852
504decc0 853 mutex_unlock(&pcr->pcr_mutex);
ada8a8a1 854
2d1484f5 855 if ((card_detect & SD_EXIST) && pcr->slots[RTSX_SD_CARD].card_event)
ada8a8a1
WW		 856 pcr->slots[RTSX_SD_CARD].card_event(
857 pcr->slots[RTSX_SD_CARD].p_dev);
2d1484f5 858 if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event)
ada8a8a1
WW		 859 pcr->slots[RTSX_MS_CARD].card_event(
860 pcr->slots[RTSX_MS_CARD].p_dev);
861}
862
863static irqreturn_t rtsx_pci_isr(int irq, void *dev_id)
864{
865 struct rtsx_pcr *pcr = dev_id;
866 u32 int_reg;
867
868 if (!pcr)
869 return IRQ_NONE;
870
871 spin_lock(&pcr->lock);
872
873 int_reg = rtsx_pci_readl(pcr, RTSX_BIPR);
874 /* Clear interrupt flag */
875 rtsx_pci_writel(pcr, RTSX_BIPR, int_reg);
c42deffd
MC		 876 dev_dbg(&pcr->pci->dev, "=========== BIPR 0x%8x ==========\n", int_reg);
877
ada8a8a1
WW		 878 if ((int_reg & pcr->bier) == 0) {
879 spin_unlock(&pcr->lock);
880 return IRQ_NONE;
881 }
882 if (int_reg == 0xFFFFFFFF) {
883 spin_unlock(&pcr->lock);
884 return IRQ_HANDLED;
885 }
886
887 int_reg &= (pcr->bier | 0x7FFFFF);
888
889 if (int_reg & SD_INT) {
890 if (int_reg & SD_EXIST) {
891 pcr->card_inserted |= SD_EXIST;
892 } else {
893 pcr->card_removed |= SD_EXIST;
894 pcr->card_inserted &= ~SD_EXIST;
895 }
896 }
897
898 if (int_reg & MS_INT) {
899 if (int_reg & MS_EXIST) {
900 pcr->card_inserted |= MS_EXIST;
901 } else {
902 pcr->card_removed |= MS_EXIST;
903 pcr->card_inserted &= ~MS_EXIST;
904 }
905 }
906
ada8a8a1 907 if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) {
c42deffd 908 if (int_reg & (TRANS_FAIL_INT | DELINK_INT))
ada8a8a1 909 pcr->trans_result = TRANS_RESULT_FAIL;
c42deffd 910 else if (int_reg & TRANS_OK_INT)
ada8a8a1 911 pcr->trans_result = TRANS_RESULT_OK;
c42deffd
MC		 912
913 if (pcr->done)
914 complete(pcr->done);
915
916 if (int_reg & SD_EXIST) {
917 struct rtsx_slot *slot = &pcr->slots[RTSX_SD_CARD];
918 if (slot && slot->done_transfer)
919 slot->done_transfer(slot->p_dev);
920 }
921
922 if (int_reg & MS_EXIST) {
923 struct rtsx_slot *slot = &pcr->slots[RTSX_SD_CARD];
924 if (slot && slot->done_transfer)
925 slot->done_transfer(slot->p_dev);
ada8a8a1
WW		 926 }
927 }
928
c42deffd 929
504decc0
WW		 930 if (pcr->card_inserted || pcr->card_removed)
931 schedule_delayed_work(&pcr->carddet_work,
932 msecs_to_jiffies(200));
933
ada8a8a1
WW		 934 spin_unlock(&pcr->lock);
935 return IRQ_HANDLED;
936}
937
938static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr)
939{
940 dev_info(&(pcr->pci->dev), "%s: pcr->msi_en = %d, pci->irq = %d\n",
941 __func__, pcr->msi_en, pcr->pci->irq);
942
943 if (request_irq(pcr->pci->irq, rtsx_pci_isr,
944 pcr->msi_en ? 0 : IRQF_SHARED,
945 DRV_NAME_RTSX_PCI, pcr)) {
946 dev_err(&(pcr->pci->dev),
947 "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
948 pcr->pci->irq);
949 return -1;
950 }
951
952 pcr->irq = pcr->pci->irq;
953 pci_intx(pcr->pci, !pcr->msi_en);
954
955 return 0;
956}
957
958static void rtsx_pci_idle_work(struct work_struct *work)
959{
960 struct delayed_work *dwork = to_delayed_work(work);
961 struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, idle_work);
962
963 dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
964
965 mutex_lock(&pcr->pcr_mutex);
966
967 pcr->state = PDEV_STAT_IDLE;
968
969 if (pcr->ops->disable_auto_blink)
970 pcr->ops->disable_auto_blink(pcr);
971 if (pcr->ops->turn_off_led)
972 pcr->ops->turn_off_led(pcr);
973
773ccdfd
WW		 974 if (pcr->aspm_en)
975 rtsx_pci_write_config_byte(pcr, LCTLR, pcr->aspm_en);
976
ada8a8a1
WW		 977 mutex_unlock(&pcr->pcr_mutex);
978}
979
5947c167
WW		 980static void rtsx_pci_power_off(struct rtsx_pcr *pcr, u8 pm_state)
981{
982 if (pcr->ops->turn_off_led)
983 pcr->ops->turn_off_led(pcr);
984
985 rtsx_pci_writel(pcr, RTSX_BIER, 0);
986 pcr->bier = 0;
987
988 rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08);
989 rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, pm_state);
990
991 if (pcr->ops->force_power_down)
eb891c65 992 pcr->ops->force_power_down(pcr, pm_state);
5947c167
WW		 993}
994
ada8a8a1
WW		 995static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
996{
997 int err;
998
999 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
1000
1001 rtsx_pci_enable_bus_int(pcr);
1002
1003 /* Power on SSC */
1004 err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0);
1005 if (err < 0)
1006 return err;
1007
1008 /* Wait SSC power stable */
1009 udelay(200);
1010
1011 if (pcr->ops->optimize_phy) {
1012 err = pcr->ops->optimize_phy(pcr);
1013 if (err < 0)
1014 return err;
1015 }
1016
1017 rtsx_pci_init_cmd(pcr);
1018
1019 /* Set mcu_cnt to 7 to ensure data can be sampled properly */
1020 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);
1021
1022 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);
1023 /* Disable card clock */
1024 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);
ada8a8a1
WW		 1025 /* Reset delink mode */
1026 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);
1027 /* Card driving select */
773ccdfd
WW		 1028 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL,
1029 0xFF, pcr->card_drive_sel);
ada8a8a1
WW		 1030 /* Enable SSC Clock */
1031 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,
1032 0xFF, SSC_8X_EN | SSC_SEL_4M);
1033 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
1034 /* Disable cd_pwr_save */
1035 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);
1036 /* Clear Link Ready Interrupt */
1037 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
1038 LINK_RDY_INT, LINK_RDY_INT);
1039 /* Enlarge the estimation window of PERST# glitch
1040 * to reduce the chance of invalid card interrupt
1041 */
1042 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);
1043 /* Update RC oscillator to 400k
1044 * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
1045 * 1: 2M 0: 400k
1046 */
1047 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);
1048 /* Set interrupt write clear
1049 * bit 1: U_elbi_if_rd_clr_en
1050 * 1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
1051 * 0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
1052 */
1053 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);
ada8a8a1
WW		 1054
1055 err = rtsx_pci_send_cmd(pcr, 100);
1056 if (err < 0)
1057 return err;
1058
773ccdfd
WW		 1059 rtsx_pci_write_config_byte(pcr, LCTLR, 0);
1060
ada8a8a1
WW		 1061 /* Enable clk_request_n to enable clock power management */
1062 rtsx_pci_write_config_byte(pcr, 0x81, 1);
1063 /* Enter L1 when host tx idle */
1064 rtsx_pci_write_config_byte(pcr, 0x70F, 0x5B);
1065
1066 if (pcr->ops->extra_init_hw) {
1067 err = pcr->ops->extra_init_hw(pcr);
1068 if (err < 0)
1069 return err;
1070 }
1071
c3481955
WW		 1072 /* No CD interrupt if probing driver with card inserted.
1073 * So we need to initialize pcr->card_exist here.
1074 */
1075 if (pcr->ops->cd_deglitch)
1076 pcr->card_exist = pcr->ops->cd_deglitch(pcr);
1077 else
1078 pcr->card_exist = rtsx_pci_readl(pcr, RTSX_BIPR) & CARD_EXIST;
1079
ada8a8a1
WW		 1080 return 0;
1081}
1082
1083static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
1084{
1085 int err;
1086
1087 spin_lock_init(&pcr->lock);
1088 mutex_init(&pcr->pcr_mutex);
1089
1090 switch (PCI_PID(pcr)) {
1091 default:
1092 case 0x5209:
1093 rts5209_init_params(pcr);
1094 break;
1095
1096 case 0x5229:
1097 rts5229_init_params(pcr);
1098 break;
1099
1100 case 0x5289:
1101 rtl8411_init_params(pcr);
1102 break;
e1237932
RT		 1103
1104 case 0x5227:
1105 rts5227_init_params(pcr);
1106 break;
4c4b8c10
WW		 1107
1108 case 0x5249:
1109 rts5249_init_params(pcr);
1110 break;
9032eabd
RT		 1111
1112 case 0x5287:
1113 rtl8411b_init_params(pcr);
1114 break;
56cb3cc1
MC		 1115
1116 case 0x5286:
1117 rtl8402_init_params(pcr);
1118 break;
ada8a8a1
WW		 1119 }
1120
1121 dev_dbg(&(pcr->pci->dev), "PID: 0x%04x, IC version: 0x%02x\n",
1122 PCI_PID(pcr), pcr->ic_version);
1123
1124 pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot),
1125 GFP_KERNEL);
1126 if (!pcr->slots)
1127 return -ENOMEM;
1128
773ccdfd
WW		 1129 if (pcr->ops->fetch_vendor_settings)
1130 pcr->ops->fetch_vendor_settings(pcr);
1131
1132 dev_dbg(&(pcr->pci->dev), "pcr->aspm_en = 0x%x\n", pcr->aspm_en);
1133 dev_dbg(&(pcr->pci->dev), "pcr->sd30_drive_sel_1v8 = 0x%x\n",
1134 pcr->sd30_drive_sel_1v8);
1135 dev_dbg(&(pcr->pci->dev), "pcr->sd30_drive_sel_3v3 = 0x%x\n",
1136 pcr->sd30_drive_sel_3v3);
1137 dev_dbg(&(pcr->pci->dev), "pcr->card_drive_sel = 0x%x\n",
1138 pcr->card_drive_sel);
1139 dev_dbg(&(pcr->pci->dev), "pcr->flags = 0x%x\n", pcr->flags);
1140
ada8a8a1
WW		 1141 pcr->state = PDEV_STAT_IDLE;
1142 err = rtsx_pci_init_hw(pcr);
1143 if (err < 0) {
1144 kfree(pcr->slots);
1145 return err;
1146 }
1147
1148 return 0;
1149}
1150
612b95cd
GKH		 1151static int rtsx_pci_probe(struct pci_dev *pcidev,
1152 const struct pci_device_id *id)
ada8a8a1
WW		 1153{
1154 struct rtsx_pcr *pcr;
1155 struct pcr_handle *handle;
1156 u32 base, len;
1157 int ret, i;
1158
1159 dev_dbg(&(pcidev->dev),
1160 ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
1161 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1162 (int)pcidev->revision);
1163
f84ef042
WW		 1164 ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32));
1165 if (ret < 0)
1166 return ret;
1167
ada8a8a1
WW		 1168 ret = pci_enable_device(pcidev);
1169 if (ret)
1170 return ret;
1171
1172 ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCI);
1173 if (ret)
1174 goto disable;
1175
1176 pcr = kzalloc(sizeof(*pcr), GFP_KERNEL);
1177 if (!pcr) {
1178 ret = -ENOMEM;
1179 goto release_pci;
1180 }
1181
1182 handle = kzalloc(sizeof(*handle), GFP_KERNEL);
1183 if (!handle) {
1184 ret = -ENOMEM;
1185 goto free_pcr;
1186 }
1187 handle->pcr = pcr;
1188
9f12563d 1189 idr_preload(GFP_KERNEL);
ada8a8a1 1190 spin_lock(&rtsx_pci_lock);
9f12563d
TH		 1191 ret = idr_alloc(&rtsx_pci_idr, pcr, 0, 0, GFP_NOWAIT);
1192 if (ret >= 0)
1193 pcr->id = ret;
ada8a8a1 1194 spin_unlock(&rtsx_pci_lock);
9f12563d
TH		 1195 idr_preload_end();
1196 if (ret < 0)
ada8a8a1
WW		 1197 goto free_handle;
1198
1199 pcr->pci = pcidev;
1200 dev_set_drvdata(&pcidev->dev, handle);
1201
1202 len = pci_resource_len(pcidev, 0);
1203 base = pci_resource_start(pcidev, 0);
1204 pcr->remap_addr = ioremap_nocache(base, len);
1205 if (!pcr->remap_addr) {
1206 ret = -ENOMEM;
af1192d7 1207 goto free_handle;
ada8a8a1
WW		 1208 }
1209
1210 pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev),
1211 RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr),
1212 GFP_KERNEL);
1213 if (pcr->rtsx_resv_buf == NULL) {
1214 ret = -ENXIO;
1215 goto unmap;
1216 }
1217 pcr->host_cmds_ptr = pcr->rtsx_resv_buf;
1218 pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr;
1219 pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN;
1220 pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN;
1221
1222 pcr->card_inserted = 0;
1223 pcr->card_removed = 0;
1224 INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);
1225 INIT_DELAYED_WORK(&pcr->idle_work, rtsx_pci_idle_work);
1226
1227 pcr->msi_en = msi_en;
1228 if (pcr->msi_en) {
1229 ret = pci_enable_msi(pcidev);
1230 if (ret < 0)
1231 pcr->msi_en = false;
1232 }
1233
1234 ret = rtsx_pci_acquire_irq(pcr);
1235 if (ret < 0)
9d66b568 1236 goto disable_msi;
ada8a8a1
WW		 1237
1238 pci_set_master(pcidev);
1239 synchronize_irq(pcr->irq);
1240
1241 ret = rtsx_pci_init_chip(pcr);
1242 if (ret < 0)
1243 goto disable_irq;
1244
1245 for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) {
1246 rtsx_pcr_cells[i].platform_data = handle;
1247 rtsx_pcr_cells[i].pdata_size = sizeof(*handle);
1248 }
1249 ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells,
1250 ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL);
1251 if (ret < 0)
1252 goto disable_irq;
1253
1254 schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1255
1256 return 0;
1257
1258disable_irq:
1259 free_irq(pcr->irq, (void *)pcr);
9d66b568
JS		 1260disable_msi:
1261 if (pcr->msi_en)
1262 pci_disable_msi(pcr->pci);
ada8a8a1
WW		 1263 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1264 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1265unmap:
1266 iounmap(pcr->remap_addr);
ada8a8a1
WW		 1267free_handle:
1268 kfree(handle);
1269free_pcr:
1270 kfree(pcr);
1271release_pci:
1272 pci_release_regions(pcidev);
1273disable:
1274 pci_disable_device(pcidev);
1275
1276 return ret;
1277}
1278
612b95cd 1279static void rtsx_pci_remove(struct pci_dev *pcidev)
ada8a8a1
WW		 1280{
1281 struct pcr_handle *handle = pci_get_drvdata(pcidev);
1282 struct rtsx_pcr *pcr = handle->pcr;
1283
1284 pcr->remove_pci = true;
1285
73beb63d
TG		 1286 /* Disable interrupts at the pcr level */
1287 spin_lock_irq(&pcr->lock);
1288 rtsx_pci_writel(pcr, RTSX_BIER, 0);
1289 pcr->bier = 0;
1290 spin_unlock_irq(&pcr->lock);
1291
1292 cancel_delayed_work_sync(&pcr->carddet_work);
1293 cancel_delayed_work_sync(&pcr->idle_work);
ada8a8a1
WW		 1294
1295 mfd_remove_devices(&pcidev->dev);
1296
1297 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1298 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1299 free_irq(pcr->irq, (void *)pcr);
1300 if (pcr->msi_en)
1301 pci_disable_msi(pcr->pci);
1302 iounmap(pcr->remap_addr);
1303
ada8a8a1
WW		 1304 pci_release_regions(pcidev);
1305 pci_disable_device(pcidev);
1306
1307 spin_lock(&rtsx_pci_lock);
1308 idr_remove(&rtsx_pci_idr, pcr->id);
1309 spin_unlock(&rtsx_pci_lock);
1310
1311 kfree(pcr->slots);
1312 kfree(pcr);
1313 kfree(handle);
1314
1315 dev_dbg(&(pcidev->dev),
1316 ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
1317 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1318}
1319
1320#ifdef CONFIG_PM
1321
1322static int rtsx_pci_suspend(struct pci_dev *pcidev, pm_message_t state)
1323{
1324 struct pcr_handle *handle;
1325 struct rtsx_pcr *pcr;
ada8a8a1
WW		 1326
1327 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1328
1329 handle = pci_get_drvdata(pcidev);
1330 pcr = handle->pcr;
1331
1332 cancel_delayed_work(&pcr->carddet_work);
1333 cancel_delayed_work(&pcr->idle_work);
1334
1335 mutex_lock(&pcr->pcr_mutex);
1336
5947c167 1337 rtsx_pci_power_off(pcr, HOST_ENTER_S3);
ada8a8a1
WW		 1338
1339 pci_save_state(pcidev);
1340 pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0);
1341 pci_disable_device(pcidev);
1342 pci_set_power_state(pcidev, pci_choose_state(pcidev, state));
1343
1344 mutex_unlock(&pcr->pcr_mutex);
5947c167 1345 return 0;
ada8a8a1
WW		 1346}
1347
1348static int rtsx_pci_resume(struct pci_dev *pcidev)
1349{
1350 struct pcr_handle *handle;
1351 struct rtsx_pcr *pcr;
1352 int ret = 0;
1353
1354 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1355
1356 handle = pci_get_drvdata(pcidev);
1357 pcr = handle->pcr;
1358
1359 mutex_lock(&pcr->pcr_mutex);
1360
1361 pci_set_power_state(pcidev, PCI_D0);
1362 pci_restore_state(pcidev);
1363 ret = pci_enable_device(pcidev);
1364 if (ret)
1365 goto out;
1366 pci_set_master(pcidev);
1367
1368 ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
1369 if (ret)
1370 goto out;
1371
1372 ret = rtsx_pci_init_hw(pcr);
1373 if (ret)
1374 goto out;
1375
1376 schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1377
1378out:
1379 mutex_unlock(&pcr->pcr_mutex);
1380 return ret;
1381}
1382
5947c167
WW		 1383static void rtsx_pci_shutdown(struct pci_dev *pcidev)
1384{
1385 struct pcr_handle *handle;
1386 struct rtsx_pcr *pcr;
1387
1388 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1389
1390 handle = pci_get_drvdata(pcidev);
1391 pcr = handle->pcr;
1392 rtsx_pci_power_off(pcr, HOST_ENTER_S1);
1393
1394 pci_disable_device(pcidev);
1395}
1396
ada8a8a1
WW		 1397#else /* CONFIG_PM */
1398
1399#define rtsx_pci_suspend NULL
1400#define rtsx_pci_resume NULL
5947c167 1401#define rtsx_pci_shutdown NULL
ada8a8a1
WW		 1402
1403#endif /* CONFIG_PM */
1404
1405static struct pci_driver rtsx_pci_driver = {
1406 .name = DRV_NAME_RTSX_PCI,
1407 .id_table = rtsx_pci_ids,
1408 .probe = rtsx_pci_probe,
612b95cd 1409 .remove = rtsx_pci_remove,
ada8a8a1
WW		 1410 .suspend = rtsx_pci_suspend,
1411 .resume = rtsx_pci_resume,
5947c167 1412 .shutdown = rtsx_pci_shutdown,
ada8a8a1
WW		 1413};
1414module_pci_driver(rtsx_pci_driver);
1415
1416MODULE_LICENSE("GPL");
1417MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1418MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver");
Linux kernel - Deliverables
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