Commit | Line | Data |
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27e34995 | 1 | /* |
1a6e4b74 VK |
2 | * ST Microelectronics MFD: stmpe's driver |
3 | * | |
27e34995 RV |
4 | * Copyright (C) ST-Ericsson SA 2010 |
5 | * | |
6 | * License Terms: GNU General Public License, version 2 | |
7 | * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson | |
8 | */ | |
9 | ||
73de16db | 10 | #include <linux/gpio.h> |
dba61c8f | 11 | #include <linux/export.h> |
27e34995 | 12 | #include <linux/kernel.h> |
27e34995 RV |
13 | #include <linux/interrupt.h> |
14 | #include <linux/irq.h> | |
76f93992 | 15 | #include <linux/irqdomain.h> |
20d5c7de | 16 | #include <linux/of.h> |
1a6e4b74 | 17 | #include <linux/pm.h> |
27e34995 | 18 | #include <linux/slab.h> |
27e34995 | 19 | #include <linux/mfd/core.h> |
27e34995 RV |
20 | #include "stmpe.h" |
21 | ||
22 | static int __stmpe_enable(struct stmpe *stmpe, unsigned int blocks) | |
23 | { | |
24 | return stmpe->variant->enable(stmpe, blocks, true); | |
25 | } | |
26 | ||
27 | static int __stmpe_disable(struct stmpe *stmpe, unsigned int blocks) | |
28 | { | |
29 | return stmpe->variant->enable(stmpe, blocks, false); | |
30 | } | |
31 | ||
32 | static int __stmpe_reg_read(struct stmpe *stmpe, u8 reg) | |
33 | { | |
34 | int ret; | |
35 | ||
1a6e4b74 | 36 | ret = stmpe->ci->read_byte(stmpe, reg); |
27e34995 | 37 | if (ret < 0) |
1a6e4b74 | 38 | dev_err(stmpe->dev, "failed to read reg %#x: %d\n", reg, ret); |
27e34995 RV |
39 | |
40 | dev_vdbg(stmpe->dev, "rd: reg %#x => data %#x\n", reg, ret); | |
41 | ||
42 | return ret; | |
43 | } | |
44 | ||
45 | static int __stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 val) | |
46 | { | |
47 | int ret; | |
48 | ||
49 | dev_vdbg(stmpe->dev, "wr: reg %#x <= %#x\n", reg, val); | |
50 | ||
1a6e4b74 | 51 | ret = stmpe->ci->write_byte(stmpe, reg, val); |
27e34995 | 52 | if (ret < 0) |
1a6e4b74 | 53 | dev_err(stmpe->dev, "failed to write reg %#x: %d\n", reg, ret); |
27e34995 RV |
54 | |
55 | return ret; | |
56 | } | |
57 | ||
58 | static int __stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val) | |
59 | { | |
60 | int ret; | |
61 | ||
62 | ret = __stmpe_reg_read(stmpe, reg); | |
63 | if (ret < 0) | |
64 | return ret; | |
65 | ||
66 | ret &= ~mask; | |
67 | ret |= val; | |
68 | ||
69 | return __stmpe_reg_write(stmpe, reg, ret); | |
70 | } | |
71 | ||
72 | static int __stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length, | |
73 | u8 *values) | |
74 | { | |
75 | int ret; | |
76 | ||
1a6e4b74 | 77 | ret = stmpe->ci->read_block(stmpe, reg, length, values); |
27e34995 | 78 | if (ret < 0) |
1a6e4b74 | 79 | dev_err(stmpe->dev, "failed to read regs %#x: %d\n", reg, ret); |
27e34995 RV |
80 | |
81 | dev_vdbg(stmpe->dev, "rd: reg %#x (%d) => ret %#x\n", reg, length, ret); | |
82 | stmpe_dump_bytes("stmpe rd: ", values, length); | |
83 | ||
84 | return ret; | |
85 | } | |
86 | ||
87 | static int __stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length, | |
88 | const u8 *values) | |
89 | { | |
90 | int ret; | |
91 | ||
92 | dev_vdbg(stmpe->dev, "wr: regs %#x (%d)\n", reg, length); | |
93 | stmpe_dump_bytes("stmpe wr: ", values, length); | |
94 | ||
1a6e4b74 | 95 | ret = stmpe->ci->write_block(stmpe, reg, length, values); |
27e34995 | 96 | if (ret < 0) |
1a6e4b74 | 97 | dev_err(stmpe->dev, "failed to write regs %#x: %d\n", reg, ret); |
27e34995 RV |
98 | |
99 | return ret; | |
100 | } | |
101 | ||
102 | /** | |
103 | * stmpe_enable - enable blocks on an STMPE device | |
104 | * @stmpe: Device to work on | |
105 | * @blocks: Mask of blocks (enum stmpe_block values) to enable | |
106 | */ | |
107 | int stmpe_enable(struct stmpe *stmpe, unsigned int blocks) | |
108 | { | |
109 | int ret; | |
110 | ||
111 | mutex_lock(&stmpe->lock); | |
112 | ret = __stmpe_enable(stmpe, blocks); | |
113 | mutex_unlock(&stmpe->lock); | |
114 | ||
115 | return ret; | |
116 | } | |
117 | EXPORT_SYMBOL_GPL(stmpe_enable); | |
118 | ||
119 | /** | |
120 | * stmpe_disable - disable blocks on an STMPE device | |
121 | * @stmpe: Device to work on | |
122 | * @blocks: Mask of blocks (enum stmpe_block values) to enable | |
123 | */ | |
124 | int stmpe_disable(struct stmpe *stmpe, unsigned int blocks) | |
125 | { | |
126 | int ret; | |
127 | ||
128 | mutex_lock(&stmpe->lock); | |
129 | ret = __stmpe_disable(stmpe, blocks); | |
130 | mutex_unlock(&stmpe->lock); | |
131 | ||
132 | return ret; | |
133 | } | |
134 | EXPORT_SYMBOL_GPL(stmpe_disable); | |
135 | ||
136 | /** | |
137 | * stmpe_reg_read() - read a single STMPE register | |
138 | * @stmpe: Device to read from | |
139 | * @reg: Register to read | |
140 | */ | |
141 | int stmpe_reg_read(struct stmpe *stmpe, u8 reg) | |
142 | { | |
143 | int ret; | |
144 | ||
145 | mutex_lock(&stmpe->lock); | |
146 | ret = __stmpe_reg_read(stmpe, reg); | |
147 | mutex_unlock(&stmpe->lock); | |
148 | ||
149 | return ret; | |
150 | } | |
151 | EXPORT_SYMBOL_GPL(stmpe_reg_read); | |
152 | ||
153 | /** | |
154 | * stmpe_reg_write() - write a single STMPE register | |
155 | * @stmpe: Device to write to | |
156 | * @reg: Register to write | |
157 | * @val: Value to write | |
158 | */ | |
159 | int stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 val) | |
160 | { | |
161 | int ret; | |
162 | ||
163 | mutex_lock(&stmpe->lock); | |
164 | ret = __stmpe_reg_write(stmpe, reg, val); | |
165 | mutex_unlock(&stmpe->lock); | |
166 | ||
167 | return ret; | |
168 | } | |
169 | EXPORT_SYMBOL_GPL(stmpe_reg_write); | |
170 | ||
171 | /** | |
172 | * stmpe_set_bits() - set the value of a bitfield in a STMPE register | |
173 | * @stmpe: Device to write to | |
174 | * @reg: Register to write | |
175 | * @mask: Mask of bits to set | |
176 | * @val: Value to set | |
177 | */ | |
178 | int stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val) | |
179 | { | |
180 | int ret; | |
181 | ||
182 | mutex_lock(&stmpe->lock); | |
183 | ret = __stmpe_set_bits(stmpe, reg, mask, val); | |
184 | mutex_unlock(&stmpe->lock); | |
185 | ||
186 | return ret; | |
187 | } | |
188 | EXPORT_SYMBOL_GPL(stmpe_set_bits); | |
189 | ||
190 | /** | |
191 | * stmpe_block_read() - read multiple STMPE registers | |
192 | * @stmpe: Device to read from | |
193 | * @reg: First register | |
194 | * @length: Number of registers | |
195 | * @values: Buffer to write to | |
196 | */ | |
197 | int stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length, u8 *values) | |
198 | { | |
199 | int ret; | |
200 | ||
201 | mutex_lock(&stmpe->lock); | |
202 | ret = __stmpe_block_read(stmpe, reg, length, values); | |
203 | mutex_unlock(&stmpe->lock); | |
204 | ||
205 | return ret; | |
206 | } | |
207 | EXPORT_SYMBOL_GPL(stmpe_block_read); | |
208 | ||
209 | /** | |
210 | * stmpe_block_write() - write multiple STMPE registers | |
211 | * @stmpe: Device to write to | |
212 | * @reg: First register | |
213 | * @length: Number of registers | |
214 | * @values: Values to write | |
215 | */ | |
216 | int stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length, | |
217 | const u8 *values) | |
218 | { | |
219 | int ret; | |
220 | ||
221 | mutex_lock(&stmpe->lock); | |
222 | ret = __stmpe_block_write(stmpe, reg, length, values); | |
223 | mutex_unlock(&stmpe->lock); | |
224 | ||
225 | return ret; | |
226 | } | |
227 | EXPORT_SYMBOL_GPL(stmpe_block_write); | |
228 | ||
229 | /** | |
4dcaa6b6 | 230 | * stmpe_set_altfunc()- set the alternate function for STMPE pins |
27e34995 RV |
231 | * @stmpe: Device to configure |
232 | * @pins: Bitmask of pins to affect | |
233 | * @block: block to enable alternate functions for | |
234 | * | |
235 | * @pins is assumed to have a bit set for each of the bits whose alternate | |
236 | * function is to be changed, numbered according to the GPIOXY numbers. | |
237 | * | |
238 | * If the GPIO module is not enabled, this function automatically enables it in | |
239 | * order to perform the change. | |
240 | */ | |
241 | int stmpe_set_altfunc(struct stmpe *stmpe, u32 pins, enum stmpe_block block) | |
242 | { | |
243 | struct stmpe_variant_info *variant = stmpe->variant; | |
244 | u8 regaddr = stmpe->regs[STMPE_IDX_GPAFR_U_MSB]; | |
245 | int af_bits = variant->af_bits; | |
246 | int numregs = DIV_ROUND_UP(stmpe->num_gpios * af_bits, 8); | |
27e34995 RV |
247 | int mask = (1 << af_bits) - 1; |
248 | u8 regs[numregs]; | |
7f7f4ea1 VK |
249 | int af, afperreg, ret; |
250 | ||
251 | if (!variant->get_altfunc) | |
252 | return 0; | |
27e34995 | 253 | |
7f7f4ea1 | 254 | afperreg = 8 / af_bits; |
27e34995 RV |
255 | mutex_lock(&stmpe->lock); |
256 | ||
257 | ret = __stmpe_enable(stmpe, STMPE_BLOCK_GPIO); | |
258 | if (ret < 0) | |
259 | goto out; | |
260 | ||
261 | ret = __stmpe_block_read(stmpe, regaddr, numregs, regs); | |
262 | if (ret < 0) | |
263 | goto out; | |
264 | ||
265 | af = variant->get_altfunc(stmpe, block); | |
266 | ||
267 | while (pins) { | |
268 | int pin = __ffs(pins); | |
269 | int regoffset = numregs - (pin / afperreg) - 1; | |
270 | int pos = (pin % afperreg) * (8 / afperreg); | |
271 | ||
272 | regs[regoffset] &= ~(mask << pos); | |
273 | regs[regoffset] |= af << pos; | |
274 | ||
275 | pins &= ~(1 << pin); | |
276 | } | |
277 | ||
278 | ret = __stmpe_block_write(stmpe, regaddr, numregs, regs); | |
279 | ||
280 | out: | |
281 | mutex_unlock(&stmpe->lock); | |
282 | return ret; | |
283 | } | |
284 | EXPORT_SYMBOL_GPL(stmpe_set_altfunc); | |
285 | ||
286 | /* | |
287 | * GPIO (all variants) | |
288 | */ | |
289 | ||
290 | static struct resource stmpe_gpio_resources[] = { | |
291 | /* Start and end filled dynamically */ | |
292 | { | |
293 | .flags = IORESOURCE_IRQ, | |
294 | }, | |
295 | }; | |
296 | ||
297 | static struct mfd_cell stmpe_gpio_cell = { | |
298 | .name = "stmpe-gpio", | |
299 | .resources = stmpe_gpio_resources, | |
300 | .num_resources = ARRAY_SIZE(stmpe_gpio_resources), | |
301 | }; | |
302 | ||
e31f9b82 CB |
303 | static struct mfd_cell stmpe_gpio_cell_noirq = { |
304 | .name = "stmpe-gpio", | |
305 | /* gpio cell resources consist of an irq only so no resources here */ | |
306 | }; | |
307 | ||
27e34995 RV |
308 | /* |
309 | * Keypad (1601, 2401, 2403) | |
310 | */ | |
311 | ||
312 | static struct resource stmpe_keypad_resources[] = { | |
313 | { | |
314 | .name = "KEYPAD", | |
27e34995 RV |
315 | .flags = IORESOURCE_IRQ, |
316 | }, | |
317 | { | |
318 | .name = "KEYPAD_OVER", | |
27e34995 RV |
319 | .flags = IORESOURCE_IRQ, |
320 | }, | |
321 | }; | |
322 | ||
323 | static struct mfd_cell stmpe_keypad_cell = { | |
324 | .name = "stmpe-keypad", | |
325 | .resources = stmpe_keypad_resources, | |
326 | .num_resources = ARRAY_SIZE(stmpe_keypad_resources), | |
327 | }; | |
328 | ||
7f7f4ea1 VK |
329 | /* |
330 | * STMPE801 | |
331 | */ | |
332 | static const u8 stmpe801_regs[] = { | |
333 | [STMPE_IDX_CHIP_ID] = STMPE801_REG_CHIP_ID, | |
334 | [STMPE_IDX_ICR_LSB] = STMPE801_REG_SYS_CTRL, | |
335 | [STMPE_IDX_GPMR_LSB] = STMPE801_REG_GPIO_MP_STA, | |
336 | [STMPE_IDX_GPSR_LSB] = STMPE801_REG_GPIO_SET_PIN, | |
337 | [STMPE_IDX_GPCR_LSB] = STMPE801_REG_GPIO_SET_PIN, | |
338 | [STMPE_IDX_GPDR_LSB] = STMPE801_REG_GPIO_DIR, | |
339 | [STMPE_IDX_IEGPIOR_LSB] = STMPE801_REG_GPIO_INT_EN, | |
340 | [STMPE_IDX_ISGPIOR_MSB] = STMPE801_REG_GPIO_INT_STA, | |
341 | ||
342 | }; | |
343 | ||
344 | static struct stmpe_variant_block stmpe801_blocks[] = { | |
345 | { | |
346 | .cell = &stmpe_gpio_cell, | |
347 | .irq = 0, | |
348 | .block = STMPE_BLOCK_GPIO, | |
349 | }, | |
350 | }; | |
351 | ||
e31f9b82 CB |
352 | static struct stmpe_variant_block stmpe801_blocks_noirq[] = { |
353 | { | |
354 | .cell = &stmpe_gpio_cell_noirq, | |
355 | .block = STMPE_BLOCK_GPIO, | |
356 | }, | |
357 | }; | |
358 | ||
7f7f4ea1 VK |
359 | static int stmpe801_enable(struct stmpe *stmpe, unsigned int blocks, |
360 | bool enable) | |
361 | { | |
362 | if (blocks & STMPE_BLOCK_GPIO) | |
363 | return 0; | |
364 | else | |
365 | return -EINVAL; | |
366 | } | |
367 | ||
368 | static struct stmpe_variant_info stmpe801 = { | |
369 | .name = "stmpe801", | |
370 | .id_val = STMPE801_ID, | |
371 | .id_mask = 0xffff, | |
372 | .num_gpios = 8, | |
373 | .regs = stmpe801_regs, | |
374 | .blocks = stmpe801_blocks, | |
375 | .num_blocks = ARRAY_SIZE(stmpe801_blocks), | |
376 | .num_irqs = STMPE801_NR_INTERNAL_IRQS, | |
377 | .enable = stmpe801_enable, | |
378 | }; | |
379 | ||
e31f9b82 CB |
380 | static struct stmpe_variant_info stmpe801_noirq = { |
381 | .name = "stmpe801", | |
382 | .id_val = STMPE801_ID, | |
383 | .id_mask = 0xffff, | |
384 | .num_gpios = 8, | |
385 | .regs = stmpe801_regs, | |
386 | .blocks = stmpe801_blocks_noirq, | |
387 | .num_blocks = ARRAY_SIZE(stmpe801_blocks_noirq), | |
388 | .enable = stmpe801_enable, | |
389 | }; | |
390 | ||
27e34995 | 391 | /* |
1cda2394 | 392 | * Touchscreen (STMPE811 or STMPE610) |
27e34995 RV |
393 | */ |
394 | ||
395 | static struct resource stmpe_ts_resources[] = { | |
396 | { | |
397 | .name = "TOUCH_DET", | |
27e34995 RV |
398 | .flags = IORESOURCE_IRQ, |
399 | }, | |
400 | { | |
401 | .name = "FIFO_TH", | |
27e34995 RV |
402 | .flags = IORESOURCE_IRQ, |
403 | }, | |
404 | }; | |
405 | ||
406 | static struct mfd_cell stmpe_ts_cell = { | |
407 | .name = "stmpe-ts", | |
408 | .resources = stmpe_ts_resources, | |
409 | .num_resources = ARRAY_SIZE(stmpe_ts_resources), | |
410 | }; | |
411 | ||
412 | /* | |
1cda2394 | 413 | * STMPE811 or STMPE610 |
27e34995 RV |
414 | */ |
415 | ||
416 | static const u8 stmpe811_regs[] = { | |
417 | [STMPE_IDX_CHIP_ID] = STMPE811_REG_CHIP_ID, | |
418 | [STMPE_IDX_ICR_LSB] = STMPE811_REG_INT_CTRL, | |
419 | [STMPE_IDX_IER_LSB] = STMPE811_REG_INT_EN, | |
420 | [STMPE_IDX_ISR_MSB] = STMPE811_REG_INT_STA, | |
421 | [STMPE_IDX_GPMR_LSB] = STMPE811_REG_GPIO_MP_STA, | |
422 | [STMPE_IDX_GPSR_LSB] = STMPE811_REG_GPIO_SET_PIN, | |
423 | [STMPE_IDX_GPCR_LSB] = STMPE811_REG_GPIO_CLR_PIN, | |
424 | [STMPE_IDX_GPDR_LSB] = STMPE811_REG_GPIO_DIR, | |
425 | [STMPE_IDX_GPRER_LSB] = STMPE811_REG_GPIO_RE, | |
426 | [STMPE_IDX_GPFER_LSB] = STMPE811_REG_GPIO_FE, | |
427 | [STMPE_IDX_GPAFR_U_MSB] = STMPE811_REG_GPIO_AF, | |
428 | [STMPE_IDX_IEGPIOR_LSB] = STMPE811_REG_GPIO_INT_EN, | |
429 | [STMPE_IDX_ISGPIOR_MSB] = STMPE811_REG_GPIO_INT_STA, | |
430 | [STMPE_IDX_GPEDR_MSB] = STMPE811_REG_GPIO_ED, | |
431 | }; | |
432 | ||
433 | static struct stmpe_variant_block stmpe811_blocks[] = { | |
434 | { | |
435 | .cell = &stmpe_gpio_cell, | |
436 | .irq = STMPE811_IRQ_GPIOC, | |
437 | .block = STMPE_BLOCK_GPIO, | |
438 | }, | |
439 | { | |
440 | .cell = &stmpe_ts_cell, | |
441 | .irq = STMPE811_IRQ_TOUCH_DET, | |
442 | .block = STMPE_BLOCK_TOUCHSCREEN, | |
443 | }, | |
444 | }; | |
445 | ||
446 | static int stmpe811_enable(struct stmpe *stmpe, unsigned int blocks, | |
447 | bool enable) | |
448 | { | |
449 | unsigned int mask = 0; | |
450 | ||
451 | if (blocks & STMPE_BLOCK_GPIO) | |
452 | mask |= STMPE811_SYS_CTRL2_GPIO_OFF; | |
453 | ||
454 | if (blocks & STMPE_BLOCK_ADC) | |
455 | mask |= STMPE811_SYS_CTRL2_ADC_OFF; | |
456 | ||
457 | if (blocks & STMPE_BLOCK_TOUCHSCREEN) | |
458 | mask |= STMPE811_SYS_CTRL2_TSC_OFF; | |
459 | ||
460 | return __stmpe_set_bits(stmpe, STMPE811_REG_SYS_CTRL2, mask, | |
461 | enable ? 0 : mask); | |
462 | } | |
463 | ||
464 | static int stmpe811_get_altfunc(struct stmpe *stmpe, enum stmpe_block block) | |
465 | { | |
466 | /* 0 for touchscreen, 1 for GPIO */ | |
467 | return block != STMPE_BLOCK_TOUCHSCREEN; | |
468 | } | |
469 | ||
470 | static struct stmpe_variant_info stmpe811 = { | |
471 | .name = "stmpe811", | |
472 | .id_val = 0x0811, | |
473 | .id_mask = 0xffff, | |
474 | .num_gpios = 8, | |
475 | .af_bits = 1, | |
476 | .regs = stmpe811_regs, | |
477 | .blocks = stmpe811_blocks, | |
478 | .num_blocks = ARRAY_SIZE(stmpe811_blocks), | |
479 | .num_irqs = STMPE811_NR_INTERNAL_IRQS, | |
480 | .enable = stmpe811_enable, | |
481 | .get_altfunc = stmpe811_get_altfunc, | |
482 | }; | |
483 | ||
1cda2394 VK |
484 | /* Similar to 811, except number of gpios */ |
485 | static struct stmpe_variant_info stmpe610 = { | |
486 | .name = "stmpe610", | |
487 | .id_val = 0x0811, | |
488 | .id_mask = 0xffff, | |
489 | .num_gpios = 6, | |
490 | .af_bits = 1, | |
491 | .regs = stmpe811_regs, | |
492 | .blocks = stmpe811_blocks, | |
493 | .num_blocks = ARRAY_SIZE(stmpe811_blocks), | |
494 | .num_irqs = STMPE811_NR_INTERNAL_IRQS, | |
495 | .enable = stmpe811_enable, | |
496 | .get_altfunc = stmpe811_get_altfunc, | |
497 | }; | |
498 | ||
27e34995 RV |
499 | /* |
500 | * STMPE1601 | |
501 | */ | |
502 | ||
503 | static const u8 stmpe1601_regs[] = { | |
504 | [STMPE_IDX_CHIP_ID] = STMPE1601_REG_CHIP_ID, | |
505 | [STMPE_IDX_ICR_LSB] = STMPE1601_REG_ICR_LSB, | |
506 | [STMPE_IDX_IER_LSB] = STMPE1601_REG_IER_LSB, | |
507 | [STMPE_IDX_ISR_MSB] = STMPE1601_REG_ISR_MSB, | |
508 | [STMPE_IDX_GPMR_LSB] = STMPE1601_REG_GPIO_MP_LSB, | |
509 | [STMPE_IDX_GPSR_LSB] = STMPE1601_REG_GPIO_SET_LSB, | |
510 | [STMPE_IDX_GPCR_LSB] = STMPE1601_REG_GPIO_CLR_LSB, | |
511 | [STMPE_IDX_GPDR_LSB] = STMPE1601_REG_GPIO_SET_DIR_LSB, | |
512 | [STMPE_IDX_GPRER_LSB] = STMPE1601_REG_GPIO_RE_LSB, | |
513 | [STMPE_IDX_GPFER_LSB] = STMPE1601_REG_GPIO_FE_LSB, | |
514 | [STMPE_IDX_GPAFR_U_MSB] = STMPE1601_REG_GPIO_AF_U_MSB, | |
515 | [STMPE_IDX_IEGPIOR_LSB] = STMPE1601_REG_INT_EN_GPIO_MASK_LSB, | |
516 | [STMPE_IDX_ISGPIOR_MSB] = STMPE1601_REG_INT_STA_GPIO_MSB, | |
517 | [STMPE_IDX_GPEDR_MSB] = STMPE1601_REG_GPIO_ED_MSB, | |
518 | }; | |
519 | ||
520 | static struct stmpe_variant_block stmpe1601_blocks[] = { | |
521 | { | |
522 | .cell = &stmpe_gpio_cell, | |
5204e51d | 523 | .irq = STMPE1601_IRQ_GPIOC, |
27e34995 RV |
524 | .block = STMPE_BLOCK_GPIO, |
525 | }, | |
526 | { | |
527 | .cell = &stmpe_keypad_cell, | |
5204e51d | 528 | .irq = STMPE1601_IRQ_KEYPAD, |
27e34995 RV |
529 | .block = STMPE_BLOCK_KEYPAD, |
530 | }, | |
531 | }; | |
532 | ||
5981f4e6 SI |
533 | /* supported autosleep timeout delay (in msecs) */ |
534 | static const int stmpe_autosleep_delay[] = { | |
535 | 4, 16, 32, 64, 128, 256, 512, 1024, | |
536 | }; | |
537 | ||
538 | static int stmpe_round_timeout(int timeout) | |
539 | { | |
540 | int i; | |
541 | ||
542 | for (i = 0; i < ARRAY_SIZE(stmpe_autosleep_delay); i++) { | |
543 | if (stmpe_autosleep_delay[i] >= timeout) | |
544 | return i; | |
545 | } | |
546 | ||
547 | /* | |
548 | * requests for delays longer than supported should not return the | |
549 | * longest supported delay | |
550 | */ | |
551 | return -EINVAL; | |
552 | } | |
553 | ||
554 | static int stmpe_autosleep(struct stmpe *stmpe, int autosleep_timeout) | |
555 | { | |
556 | int ret; | |
557 | ||
558 | if (!stmpe->variant->enable_autosleep) | |
559 | return -ENOSYS; | |
560 | ||
561 | mutex_lock(&stmpe->lock); | |
562 | ret = stmpe->variant->enable_autosleep(stmpe, autosleep_timeout); | |
563 | mutex_unlock(&stmpe->lock); | |
564 | ||
565 | return ret; | |
566 | } | |
567 | ||
568 | /* | |
569 | * Both stmpe 1601/2403 support same layout for autosleep | |
570 | */ | |
571 | static int stmpe1601_autosleep(struct stmpe *stmpe, | |
572 | int autosleep_timeout) | |
573 | { | |
574 | int ret, timeout; | |
575 | ||
576 | /* choose the best available timeout */ | |
577 | timeout = stmpe_round_timeout(autosleep_timeout); | |
578 | if (timeout < 0) { | |
579 | dev_err(stmpe->dev, "invalid timeout\n"); | |
580 | return timeout; | |
581 | } | |
582 | ||
583 | ret = __stmpe_set_bits(stmpe, STMPE1601_REG_SYS_CTRL2, | |
584 | STMPE1601_AUTOSLEEP_TIMEOUT_MASK, | |
585 | timeout); | |
586 | if (ret < 0) | |
587 | return ret; | |
588 | ||
589 | return __stmpe_set_bits(stmpe, STMPE1601_REG_SYS_CTRL2, | |
590 | STPME1601_AUTOSLEEP_ENABLE, | |
591 | STPME1601_AUTOSLEEP_ENABLE); | |
592 | } | |
593 | ||
27e34995 RV |
594 | static int stmpe1601_enable(struct stmpe *stmpe, unsigned int blocks, |
595 | bool enable) | |
596 | { | |
597 | unsigned int mask = 0; | |
598 | ||
599 | if (blocks & STMPE_BLOCK_GPIO) | |
600 | mask |= STMPE1601_SYS_CTRL_ENABLE_GPIO; | |
601 | ||
602 | if (blocks & STMPE_BLOCK_KEYPAD) | |
603 | mask |= STMPE1601_SYS_CTRL_ENABLE_KPC; | |
604 | ||
605 | return __stmpe_set_bits(stmpe, STMPE1601_REG_SYS_CTRL, mask, | |
606 | enable ? mask : 0); | |
607 | } | |
608 | ||
609 | static int stmpe1601_get_altfunc(struct stmpe *stmpe, enum stmpe_block block) | |
610 | { | |
611 | switch (block) { | |
612 | case STMPE_BLOCK_PWM: | |
613 | return 2; | |
614 | ||
615 | case STMPE_BLOCK_KEYPAD: | |
616 | return 1; | |
617 | ||
618 | case STMPE_BLOCK_GPIO: | |
619 | default: | |
620 | return 0; | |
621 | } | |
622 | } | |
623 | ||
624 | static struct stmpe_variant_info stmpe1601 = { | |
625 | .name = "stmpe1601", | |
626 | .id_val = 0x0210, | |
627 | .id_mask = 0xfff0, /* at least 0x0210 and 0x0212 */ | |
628 | .num_gpios = 16, | |
629 | .af_bits = 2, | |
630 | .regs = stmpe1601_regs, | |
631 | .blocks = stmpe1601_blocks, | |
632 | .num_blocks = ARRAY_SIZE(stmpe1601_blocks), | |
633 | .num_irqs = STMPE1601_NR_INTERNAL_IRQS, | |
634 | .enable = stmpe1601_enable, | |
635 | .get_altfunc = stmpe1601_get_altfunc, | |
5981f4e6 | 636 | .enable_autosleep = stmpe1601_autosleep, |
27e34995 RV |
637 | }; |
638 | ||
639 | /* | |
640 | * STMPE24XX | |
641 | */ | |
642 | ||
643 | static const u8 stmpe24xx_regs[] = { | |
644 | [STMPE_IDX_CHIP_ID] = STMPE24XX_REG_CHIP_ID, | |
645 | [STMPE_IDX_ICR_LSB] = STMPE24XX_REG_ICR_LSB, | |
646 | [STMPE_IDX_IER_LSB] = STMPE24XX_REG_IER_LSB, | |
647 | [STMPE_IDX_ISR_MSB] = STMPE24XX_REG_ISR_MSB, | |
648 | [STMPE_IDX_GPMR_LSB] = STMPE24XX_REG_GPMR_LSB, | |
649 | [STMPE_IDX_GPSR_LSB] = STMPE24XX_REG_GPSR_LSB, | |
650 | [STMPE_IDX_GPCR_LSB] = STMPE24XX_REG_GPCR_LSB, | |
651 | [STMPE_IDX_GPDR_LSB] = STMPE24XX_REG_GPDR_LSB, | |
652 | [STMPE_IDX_GPRER_LSB] = STMPE24XX_REG_GPRER_LSB, | |
653 | [STMPE_IDX_GPFER_LSB] = STMPE24XX_REG_GPFER_LSB, | |
654 | [STMPE_IDX_GPAFR_U_MSB] = STMPE24XX_REG_GPAFR_U_MSB, | |
655 | [STMPE_IDX_IEGPIOR_LSB] = STMPE24XX_REG_IEGPIOR_LSB, | |
656 | [STMPE_IDX_ISGPIOR_MSB] = STMPE24XX_REG_ISGPIOR_MSB, | |
657 | [STMPE_IDX_GPEDR_MSB] = STMPE24XX_REG_GPEDR_MSB, | |
658 | }; | |
659 | ||
660 | static struct stmpe_variant_block stmpe24xx_blocks[] = { | |
661 | { | |
662 | .cell = &stmpe_gpio_cell, | |
663 | .irq = STMPE24XX_IRQ_GPIOC, | |
664 | .block = STMPE_BLOCK_GPIO, | |
665 | }, | |
666 | { | |
667 | .cell = &stmpe_keypad_cell, | |
668 | .irq = STMPE24XX_IRQ_KEYPAD, | |
669 | .block = STMPE_BLOCK_KEYPAD, | |
670 | }, | |
671 | }; | |
672 | ||
673 | static int stmpe24xx_enable(struct stmpe *stmpe, unsigned int blocks, | |
674 | bool enable) | |
675 | { | |
676 | unsigned int mask = 0; | |
677 | ||
678 | if (blocks & STMPE_BLOCK_GPIO) | |
679 | mask |= STMPE24XX_SYS_CTRL_ENABLE_GPIO; | |
680 | ||
681 | if (blocks & STMPE_BLOCK_KEYPAD) | |
682 | mask |= STMPE24XX_SYS_CTRL_ENABLE_KPC; | |
683 | ||
684 | return __stmpe_set_bits(stmpe, STMPE24XX_REG_SYS_CTRL, mask, | |
685 | enable ? mask : 0); | |
686 | } | |
687 | ||
688 | static int stmpe24xx_get_altfunc(struct stmpe *stmpe, enum stmpe_block block) | |
689 | { | |
690 | switch (block) { | |
691 | case STMPE_BLOCK_ROTATOR: | |
692 | return 2; | |
693 | ||
694 | case STMPE_BLOCK_KEYPAD: | |
695 | return 1; | |
696 | ||
697 | case STMPE_BLOCK_GPIO: | |
698 | default: | |
699 | return 0; | |
700 | } | |
701 | } | |
702 | ||
703 | static struct stmpe_variant_info stmpe2401 = { | |
704 | .name = "stmpe2401", | |
705 | .id_val = 0x0101, | |
706 | .id_mask = 0xffff, | |
707 | .num_gpios = 24, | |
708 | .af_bits = 2, | |
709 | .regs = stmpe24xx_regs, | |
710 | .blocks = stmpe24xx_blocks, | |
711 | .num_blocks = ARRAY_SIZE(stmpe24xx_blocks), | |
712 | .num_irqs = STMPE24XX_NR_INTERNAL_IRQS, | |
713 | .enable = stmpe24xx_enable, | |
714 | .get_altfunc = stmpe24xx_get_altfunc, | |
715 | }; | |
716 | ||
717 | static struct stmpe_variant_info stmpe2403 = { | |
718 | .name = "stmpe2403", | |
719 | .id_val = 0x0120, | |
720 | .id_mask = 0xffff, | |
721 | .num_gpios = 24, | |
722 | .af_bits = 2, | |
723 | .regs = stmpe24xx_regs, | |
724 | .blocks = stmpe24xx_blocks, | |
725 | .num_blocks = ARRAY_SIZE(stmpe24xx_blocks), | |
726 | .num_irqs = STMPE24XX_NR_INTERNAL_IRQS, | |
727 | .enable = stmpe24xx_enable, | |
728 | .get_altfunc = stmpe24xx_get_altfunc, | |
5981f4e6 | 729 | .enable_autosleep = stmpe1601_autosleep, /* same as stmpe1601 */ |
27e34995 RV |
730 | }; |
731 | ||
e31f9b82 | 732 | static struct stmpe_variant_info *stmpe_variant_info[STMPE_NBR_PARTS] = { |
1cda2394 | 733 | [STMPE610] = &stmpe610, |
7f7f4ea1 | 734 | [STMPE801] = &stmpe801, |
27e34995 RV |
735 | [STMPE811] = &stmpe811, |
736 | [STMPE1601] = &stmpe1601, | |
737 | [STMPE2401] = &stmpe2401, | |
738 | [STMPE2403] = &stmpe2403, | |
739 | }; | |
740 | ||
e31f9b82 CB |
741 | /* |
742 | * These devices can be connected in a 'no-irq' configuration - the irq pin | |
743 | * is not used and the device cannot interrupt the CPU. Here we only list | |
744 | * devices which support this configuration - the driver will fail probing | |
745 | * for any devices not listed here which are configured in this way. | |
746 | */ | |
747 | static struct stmpe_variant_info *stmpe_noirq_variant_info[STMPE_NBR_PARTS] = { | |
748 | [STMPE801] = &stmpe801_noirq, | |
749 | }; | |
750 | ||
27e34995 RV |
751 | static irqreturn_t stmpe_irq(int irq, void *data) |
752 | { | |
753 | struct stmpe *stmpe = data; | |
754 | struct stmpe_variant_info *variant = stmpe->variant; | |
755 | int num = DIV_ROUND_UP(variant->num_irqs, 8); | |
756 | u8 israddr = stmpe->regs[STMPE_IDX_ISR_MSB]; | |
757 | u8 isr[num]; | |
758 | int ret; | |
759 | int i; | |
760 | ||
7f7f4ea1 | 761 | if (variant->id_val == STMPE801_ID) { |
76f93992 LJ |
762 | int base = irq_create_mapping(stmpe->domain, 0); |
763 | ||
764 | handle_nested_irq(base); | |
7f7f4ea1 VK |
765 | return IRQ_HANDLED; |
766 | } | |
767 | ||
27e34995 RV |
768 | ret = stmpe_block_read(stmpe, israddr, num, isr); |
769 | if (ret < 0) | |
770 | return IRQ_NONE; | |
771 | ||
772 | for (i = 0; i < num; i++) { | |
773 | int bank = num - i - 1; | |
774 | u8 status = isr[i]; | |
775 | u8 clear; | |
776 | ||
777 | status &= stmpe->ier[bank]; | |
778 | if (!status) | |
779 | continue; | |
780 | ||
781 | clear = status; | |
782 | while (status) { | |
783 | int bit = __ffs(status); | |
784 | int line = bank * 8 + bit; | |
76f93992 | 785 | int nestedirq = irq_create_mapping(stmpe->domain, line); |
27e34995 | 786 | |
76f93992 | 787 | handle_nested_irq(nestedirq); |
27e34995 RV |
788 | status &= ~(1 << bit); |
789 | } | |
790 | ||
791 | stmpe_reg_write(stmpe, israddr + i, clear); | |
792 | } | |
793 | ||
794 | return IRQ_HANDLED; | |
795 | } | |
796 | ||
43b8c084 | 797 | static void stmpe_irq_lock(struct irq_data *data) |
27e34995 | 798 | { |
43b8c084 | 799 | struct stmpe *stmpe = irq_data_get_irq_chip_data(data); |
27e34995 RV |
800 | |
801 | mutex_lock(&stmpe->irq_lock); | |
802 | } | |
803 | ||
43b8c084 | 804 | static void stmpe_irq_sync_unlock(struct irq_data *data) |
27e34995 | 805 | { |
43b8c084 | 806 | struct stmpe *stmpe = irq_data_get_irq_chip_data(data); |
27e34995 RV |
807 | struct stmpe_variant_info *variant = stmpe->variant; |
808 | int num = DIV_ROUND_UP(variant->num_irqs, 8); | |
809 | int i; | |
810 | ||
811 | for (i = 0; i < num; i++) { | |
812 | u8 new = stmpe->ier[i]; | |
813 | u8 old = stmpe->oldier[i]; | |
814 | ||
815 | if (new == old) | |
816 | continue; | |
817 | ||
818 | stmpe->oldier[i] = new; | |
819 | stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_IER_LSB] - i, new); | |
820 | } | |
821 | ||
822 | mutex_unlock(&stmpe->irq_lock); | |
823 | } | |
824 | ||
43b8c084 | 825 | static void stmpe_irq_mask(struct irq_data *data) |
27e34995 | 826 | { |
43b8c084 | 827 | struct stmpe *stmpe = irq_data_get_irq_chip_data(data); |
76f93992 | 828 | int offset = data->hwirq; |
27e34995 RV |
829 | int regoffset = offset / 8; |
830 | int mask = 1 << (offset % 8); | |
831 | ||
832 | stmpe->ier[regoffset] &= ~mask; | |
833 | } | |
834 | ||
43b8c084 | 835 | static void stmpe_irq_unmask(struct irq_data *data) |
27e34995 | 836 | { |
43b8c084 | 837 | struct stmpe *stmpe = irq_data_get_irq_chip_data(data); |
76f93992 | 838 | int offset = data->hwirq; |
27e34995 RV |
839 | int regoffset = offset / 8; |
840 | int mask = 1 << (offset % 8); | |
841 | ||
842 | stmpe->ier[regoffset] |= mask; | |
843 | } | |
844 | ||
845 | static struct irq_chip stmpe_irq_chip = { | |
846 | .name = "stmpe", | |
43b8c084 MB |
847 | .irq_bus_lock = stmpe_irq_lock, |
848 | .irq_bus_sync_unlock = stmpe_irq_sync_unlock, | |
849 | .irq_mask = stmpe_irq_mask, | |
850 | .irq_unmask = stmpe_irq_unmask, | |
27e34995 RV |
851 | }; |
852 | ||
76f93992 LJ |
853 | static int stmpe_irq_map(struct irq_domain *d, unsigned int virq, |
854 | irq_hw_number_t hwirq) | |
27e34995 | 855 | { |
76f93992 | 856 | struct stmpe *stmpe = d->host_data; |
7f7f4ea1 | 857 | struct irq_chip *chip = NULL; |
27e34995 | 858 | |
7f7f4ea1 VK |
859 | if (stmpe->variant->id_val != STMPE801_ID) |
860 | chip = &stmpe_irq_chip; | |
861 | ||
76f93992 LJ |
862 | irq_set_chip_data(virq, stmpe); |
863 | irq_set_chip_and_handler(virq, chip, handle_edge_irq); | |
864 | irq_set_nested_thread(virq, 1); | |
27e34995 | 865 | #ifdef CONFIG_ARM |
76f93992 | 866 | set_irq_flags(virq, IRQF_VALID); |
27e34995 | 867 | #else |
76f93992 | 868 | irq_set_noprobe(virq); |
27e34995 | 869 | #endif |
27e34995 RV |
870 | |
871 | return 0; | |
872 | } | |
873 | ||
76f93992 | 874 | static void stmpe_irq_unmap(struct irq_domain *d, unsigned int virq) |
27e34995 | 875 | { |
27e34995 | 876 | #ifdef CONFIG_ARM |
76f93992 | 877 | set_irq_flags(virq, 0); |
27e34995 | 878 | #endif |
76f93992 LJ |
879 | irq_set_chip_and_handler(virq, NULL, NULL); |
880 | irq_set_chip_data(virq, NULL); | |
881 | } | |
882 | ||
883 | static struct irq_domain_ops stmpe_irq_ops = { | |
884 | .map = stmpe_irq_map, | |
885 | .unmap = stmpe_irq_unmap, | |
886 | .xlate = irq_domain_xlate_twocell, | |
887 | }; | |
888 | ||
909582ca LJ |
889 | static int __devinit stmpe_irq_init(struct stmpe *stmpe, |
890 | struct device_node *np) | |
76f93992 | 891 | { |
b20a4371 | 892 | int base = 0; |
76f93992 LJ |
893 | int num_irqs = stmpe->variant->num_irqs; |
894 | ||
b20a4371 LJ |
895 | if (!np) |
896 | base = stmpe->irq_base; | |
76f93992 | 897 | |
b20a4371 LJ |
898 | stmpe->domain = irq_domain_add_simple(np, num_irqs, base, |
899 | &stmpe_irq_ops, stmpe); | |
76f93992 LJ |
900 | if (!stmpe->domain) { |
901 | dev_err(stmpe->dev, "Failed to create irqdomain\n"); | |
902 | return -ENOSYS; | |
27e34995 | 903 | } |
76f93992 LJ |
904 | |
905 | return 0; | |
27e34995 RV |
906 | } |
907 | ||
908 | static int __devinit stmpe_chip_init(struct stmpe *stmpe) | |
909 | { | |
910 | unsigned int irq_trigger = stmpe->pdata->irq_trigger; | |
5981f4e6 | 911 | int autosleep_timeout = stmpe->pdata->autosleep_timeout; |
27e34995 | 912 | struct stmpe_variant_info *variant = stmpe->variant; |
e31f9b82 | 913 | u8 icr = 0; |
27e34995 RV |
914 | unsigned int id; |
915 | u8 data[2]; | |
916 | int ret; | |
917 | ||
918 | ret = stmpe_block_read(stmpe, stmpe->regs[STMPE_IDX_CHIP_ID], | |
919 | ARRAY_SIZE(data), data); | |
920 | if (ret < 0) | |
921 | return ret; | |
922 | ||
923 | id = (data[0] << 8) | data[1]; | |
924 | if ((id & variant->id_mask) != variant->id_val) { | |
925 | dev_err(stmpe->dev, "unknown chip id: %#x\n", id); | |
926 | return -EINVAL; | |
927 | } | |
928 | ||
929 | dev_info(stmpe->dev, "%s detected, chip id: %#x\n", variant->name, id); | |
930 | ||
931 | /* Disable all modules -- subdrivers should enable what they need. */ | |
932 | ret = stmpe_disable(stmpe, ~0); | |
933 | if (ret) | |
934 | return ret; | |
935 | ||
e31f9b82 | 936 | if (stmpe->irq >= 0) { |
7f7f4ea1 | 937 | if (id == STMPE801_ID) |
e31f9b82 | 938 | icr = STMPE801_REG_SYS_CTRL_INT_EN; |
7f7f4ea1 | 939 | else |
e31f9b82 | 940 | icr = STMPE_ICR_LSB_GIM; |
27e34995 | 941 | |
e31f9b82 CB |
942 | /* STMPE801 doesn't support Edge interrupts */ |
943 | if (id != STMPE801_ID) { | |
944 | if (irq_trigger == IRQF_TRIGGER_FALLING || | |
945 | irq_trigger == IRQF_TRIGGER_RISING) | |
946 | icr |= STMPE_ICR_LSB_EDGE; | |
947 | } | |
948 | ||
949 | if (irq_trigger == IRQF_TRIGGER_RISING || | |
950 | irq_trigger == IRQF_TRIGGER_HIGH) { | |
951 | if (id == STMPE801_ID) | |
952 | icr |= STMPE801_REG_SYS_CTRL_INT_HI; | |
953 | else | |
954 | icr |= STMPE_ICR_LSB_HIGH; | |
955 | } | |
7f7f4ea1 | 956 | } |
27e34995 | 957 | |
5981f4e6 SI |
958 | if (stmpe->pdata->autosleep) { |
959 | ret = stmpe_autosleep(stmpe, autosleep_timeout); | |
960 | if (ret) | |
961 | return ret; | |
962 | } | |
963 | ||
27e34995 RV |
964 | return stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_ICR_LSB], icr); |
965 | } | |
966 | ||
967 | static int __devinit stmpe_add_device(struct stmpe *stmpe, | |
7da0cbfc | 968 | struct mfd_cell *cell) |
27e34995 RV |
969 | { |
970 | return mfd_add_devices(stmpe->dev, stmpe->pdata->id, cell, 1, | |
76f93992 | 971 | NULL, stmpe->irq_base, stmpe->domain); |
27e34995 RV |
972 | } |
973 | ||
974 | static int __devinit stmpe_devices_init(struct stmpe *stmpe) | |
975 | { | |
976 | struct stmpe_variant_info *variant = stmpe->variant; | |
977 | unsigned int platform_blocks = stmpe->pdata->blocks; | |
978 | int ret = -EINVAL; | |
7da0cbfc | 979 | int i, j; |
27e34995 RV |
980 | |
981 | for (i = 0; i < variant->num_blocks; i++) { | |
982 | struct stmpe_variant_block *block = &variant->blocks[i]; | |
983 | ||
984 | if (!(platform_blocks & block->block)) | |
985 | continue; | |
986 | ||
7da0cbfc LJ |
987 | for (j = 0; j < block->cell->num_resources; j++) { |
988 | struct resource *res = | |
989 | (struct resource *) &block->cell->resources[j]; | |
990 | ||
991 | /* Dynamically fill in a variant's IRQ. */ | |
992 | if (res->flags & IORESOURCE_IRQ) | |
993 | res->start = res->end = block->irq + j; | |
994 | } | |
995 | ||
27e34995 | 996 | platform_blocks &= ~block->block; |
7da0cbfc | 997 | ret = stmpe_add_device(stmpe, block->cell); |
27e34995 RV |
998 | if (ret) |
999 | return ret; | |
1000 | } | |
1001 | ||
1002 | if (platform_blocks) | |
1003 | dev_warn(stmpe->dev, | |
1004 | "platform wants blocks (%#x) not present on variant", | |
1005 | platform_blocks); | |
1006 | ||
1007 | return ret; | |
1008 | } | |
1009 | ||
909582ca LJ |
1010 | void __devinit stmpe_of_probe(struct stmpe_platform_data *pdata, |
1011 | struct device_node *np) | |
1012 | { | |
1013 | struct device_node *child; | |
1014 | ||
1015 | of_property_read_u32(np, "st,autosleep-timeout", | |
1016 | &pdata->autosleep_timeout); | |
1017 | ||
1018 | pdata->autosleep = (pdata->autosleep_timeout) ? true : false; | |
1019 | ||
1020 | for_each_child_of_node(np, child) { | |
1021 | if (!strcmp(child->name, "stmpe_gpio")) { | |
1022 | pdata->blocks |= STMPE_BLOCK_GPIO; | |
1023 | } | |
1024 | if (!strcmp(child->name, "stmpe_keypad")) { | |
1025 | pdata->blocks |= STMPE_BLOCK_KEYPAD; | |
1026 | } | |
1027 | if (!strcmp(child->name, "stmpe_touchscreen")) { | |
1028 | pdata->blocks |= STMPE_BLOCK_TOUCHSCREEN; | |
1029 | } | |
1030 | if (!strcmp(child->name, "stmpe_adc")) { | |
1031 | pdata->blocks |= STMPE_BLOCK_ADC; | |
1032 | } | |
1033 | } | |
1034 | } | |
1035 | ||
1a6e4b74 | 1036 | /* Called from client specific probe routines */ |
8ad1a973 | 1037 | int __devinit stmpe_probe(struct stmpe_client_info *ci, int partnum) |
208c4343 | 1038 | { |
1a6e4b74 | 1039 | struct stmpe_platform_data *pdata = dev_get_platdata(ci->dev); |
909582ca | 1040 | struct device_node *np = ci->dev->of_node; |
27e34995 RV |
1041 | struct stmpe *stmpe; |
1042 | int ret; | |
1043 | ||
909582ca | 1044 | if (!pdata) { |
cb5faba9 | 1045 | if (!np) |
909582ca | 1046 | return -EINVAL; |
cb5faba9 VK |
1047 | |
1048 | pdata = devm_kzalloc(ci->dev, sizeof(*pdata), GFP_KERNEL); | |
1049 | if (!pdata) | |
1050 | return -ENOMEM; | |
1051 | ||
1052 | stmpe_of_probe(pdata, np); | |
909582ca | 1053 | } |
27e34995 | 1054 | |
cb5faba9 | 1055 | stmpe = devm_kzalloc(ci->dev, sizeof(struct stmpe), GFP_KERNEL); |
27e34995 RV |
1056 | if (!stmpe) |
1057 | return -ENOMEM; | |
1058 | ||
1059 | mutex_init(&stmpe->irq_lock); | |
1060 | mutex_init(&stmpe->lock); | |
1061 | ||
1a6e4b74 VK |
1062 | stmpe->dev = ci->dev; |
1063 | stmpe->client = ci->client; | |
27e34995 RV |
1064 | stmpe->pdata = pdata; |
1065 | stmpe->irq_base = pdata->irq_base; | |
1a6e4b74 VK |
1066 | stmpe->ci = ci; |
1067 | stmpe->partnum = partnum; | |
1068 | stmpe->variant = stmpe_variant_info[partnum]; | |
27e34995 RV |
1069 | stmpe->regs = stmpe->variant->regs; |
1070 | stmpe->num_gpios = stmpe->variant->num_gpios; | |
1a6e4b74 | 1071 | dev_set_drvdata(stmpe->dev, stmpe); |
27e34995 | 1072 | |
1a6e4b74 VK |
1073 | if (ci->init) |
1074 | ci->init(stmpe); | |
27e34995 | 1075 | |
73de16db | 1076 | if (pdata->irq_over_gpio) { |
cb5faba9 VK |
1077 | ret = devm_gpio_request_one(ci->dev, pdata->irq_gpio, |
1078 | GPIOF_DIR_IN, "stmpe"); | |
73de16db VK |
1079 | if (ret) { |
1080 | dev_err(stmpe->dev, "failed to request IRQ GPIO: %d\n", | |
1081 | ret); | |
cb5faba9 | 1082 | return ret; |
73de16db VK |
1083 | } |
1084 | ||
1085 | stmpe->irq = gpio_to_irq(pdata->irq_gpio); | |
1086 | } else { | |
1a6e4b74 | 1087 | stmpe->irq = ci->irq; |
73de16db VK |
1088 | } |
1089 | ||
e31f9b82 CB |
1090 | if (stmpe->irq < 0) { |
1091 | /* use alternate variant info for no-irq mode, if supported */ | |
1092 | dev_info(stmpe->dev, | |
1093 | "%s configured in no-irq mode by platform data\n", | |
1094 | stmpe->variant->name); | |
1095 | if (!stmpe_noirq_variant_info[stmpe->partnum]) { | |
1096 | dev_err(stmpe->dev, | |
1097 | "%s does not support no-irq mode!\n", | |
1098 | stmpe->variant->name); | |
cb5faba9 | 1099 | return -ENODEV; |
e31f9b82 CB |
1100 | } |
1101 | stmpe->variant = stmpe_noirq_variant_info[stmpe->partnum]; | |
1102 | } | |
1103 | ||
27e34995 RV |
1104 | ret = stmpe_chip_init(stmpe); |
1105 | if (ret) | |
cb5faba9 | 1106 | return ret; |
27e34995 | 1107 | |
e31f9b82 | 1108 | if (stmpe->irq >= 0) { |
909582ca | 1109 | ret = stmpe_irq_init(stmpe, np); |
e31f9b82 | 1110 | if (ret) |
cb5faba9 | 1111 | return ret; |
27e34995 | 1112 | |
cb5faba9 VK |
1113 | ret = devm_request_threaded_irq(ci->dev, stmpe->irq, NULL, |
1114 | stmpe_irq, pdata->irq_trigger | IRQF_ONESHOT, | |
e31f9b82 CB |
1115 | "stmpe", stmpe); |
1116 | if (ret) { | |
1117 | dev_err(stmpe->dev, "failed to request IRQ: %d\n", | |
1118 | ret); | |
cb5faba9 | 1119 | return ret; |
e31f9b82 | 1120 | } |
27e34995 RV |
1121 | } |
1122 | ||
1123 | ret = stmpe_devices_init(stmpe); | |
cb5faba9 VK |
1124 | if (!ret) |
1125 | return 0; | |
27e34995 | 1126 | |
cb5faba9 | 1127 | dev_err(stmpe->dev, "failed to add children\n"); |
27e34995 | 1128 | mfd_remove_devices(stmpe->dev); |
cb5faba9 | 1129 | |
27e34995 RV |
1130 | return ret; |
1131 | } | |
1132 | ||
1a6e4b74 | 1133 | int stmpe_remove(struct stmpe *stmpe) |
27e34995 | 1134 | { |
27e34995 RV |
1135 | mfd_remove_devices(stmpe->dev); |
1136 | ||
27e34995 RV |
1137 | return 0; |
1138 | } | |
1139 | ||
208c4343 | 1140 | #ifdef CONFIG_PM |
1a6e4b74 VK |
1141 | static int stmpe_suspend(struct device *dev) |
1142 | { | |
1143 | struct stmpe *stmpe = dev_get_drvdata(dev); | |
208c4343 | 1144 | |
e31f9b82 | 1145 | if (stmpe->irq >= 0 && device_may_wakeup(dev)) |
1a6e4b74 | 1146 | enable_irq_wake(stmpe->irq); |
27e34995 | 1147 | |
1a6e4b74 | 1148 | return 0; |
27e34995 | 1149 | } |
27e34995 | 1150 | |
1a6e4b74 | 1151 | static int stmpe_resume(struct device *dev) |
27e34995 | 1152 | { |
1a6e4b74 VK |
1153 | struct stmpe *stmpe = dev_get_drvdata(dev); |
1154 | ||
e31f9b82 | 1155 | if (stmpe->irq >= 0 && device_may_wakeup(dev)) |
1a6e4b74 VK |
1156 | disable_irq_wake(stmpe->irq); |
1157 | ||
1158 | return 0; | |
27e34995 | 1159 | } |
27e34995 | 1160 | |
1a6e4b74 VK |
1161 | const struct dev_pm_ops stmpe_dev_pm_ops = { |
1162 | .suspend = stmpe_suspend, | |
1163 | .resume = stmpe_resume, | |
1164 | }; | |
1165 | #endif |