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a30d46c0 DB |
1 | /* |
2 | * twl4030-irq.c - TWL4030/TPS659x0 irq support | |
3 | * | |
4 | * Copyright (C) 2005-2006 Texas Instruments, Inc. | |
5 | * | |
6 | * Modifications to defer interrupt handling to a kernel thread: | |
7 | * Copyright (C) 2006 MontaVista Software, Inc. | |
8 | * | |
9 | * Based on tlv320aic23.c: | |
10 | * Copyright (c) by Kai Svahn <kai.svahn@nokia.com> | |
11 | * | |
12 | * Code cleanup and modifications to IRQ handler. | |
13 | * by syed khasim <x0khasim@ti.com> | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License as published by | |
17 | * the Free Software Foundation; either version 2 of the License, or | |
18 | * (at your option) any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License | |
26 | * along with this program; if not, write to the Free Software | |
27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
28 | */ | |
29 | ||
30 | #include <linux/init.h> | |
78518ffa | 31 | #include <linux/export.h> |
a30d46c0 DB |
32 | #include <linux/interrupt.h> |
33 | #include <linux/irq.h> | |
5a0e3ad6 | 34 | #include <linux/slab.h> |
78518ffa BC |
35 | #include <linux/of.h> |
36 | #include <linux/irqdomain.h> | |
b07682b6 | 37 | #include <linux/i2c/twl.h> |
a30d46c0 | 38 | |
b0b4a7c2 | 39 | #include "twl-core.h" |
a30d46c0 DB |
40 | |
41 | /* | |
42 | * TWL4030 IRQ handling has two stages in hardware, and thus in software. | |
43 | * The Primary Interrupt Handler (PIH) stage exposes status bits saying | |
44 | * which Secondary Interrupt Handler (SIH) stage is raising an interrupt. | |
45 | * SIH modules are more traditional IRQ components, which support per-IRQ | |
46 | * enable/disable and trigger controls; they do most of the work. | |
47 | * | |
48 | * These chips are designed to support IRQ handling from two different | |
49 | * I2C masters. Each has a dedicated IRQ line, and dedicated IRQ status | |
50 | * and mask registers in the PIH and SIH modules. | |
51 | * | |
52 | * We set up IRQs starting at a platform-specified base, always starting | |
53 | * with PIH and the SIH for PWR_INT and then usually adding GPIO: | |
54 | * base + 0 .. base + 7 PIH | |
55 | * base + 8 .. base + 15 SIH for PWR_INT | |
56 | * base + 16 .. base + 33 SIH for GPIO | |
57 | */ | |
78518ffa BC |
58 | #define TWL4030_CORE_NR_IRQS 8 |
59 | #define TWL4030_PWR_NR_IRQS 8 | |
a30d46c0 DB |
60 | |
61 | /* PIH register offsets */ | |
62 | #define REG_PIH_ISR_P1 0x01 | |
63 | #define REG_PIH_ISR_P2 0x02 | |
64 | #define REG_PIH_SIR 0x03 /* for testing */ | |
65 | ||
a30d46c0 DB |
66 | /* Linux could (eventually) use either IRQ line */ |
67 | static int irq_line; | |
68 | ||
69 | struct sih { | |
70 | char name[8]; | |
71 | u8 module; /* module id */ | |
72 | u8 control_offset; /* for SIH_CTRL */ | |
73 | bool set_cor; | |
74 | ||
75 | u8 bits; /* valid in isr/imr */ | |
76 | u8 bytes_ixr; /* bytelen of ISR/IMR/SIR */ | |
77 | ||
78 | u8 edr_offset; | |
79 | u8 bytes_edr; /* bytelen of EDR */ | |
80 | ||
1920a61e IK |
81 | u8 irq_lines; /* number of supported irq lines */ |
82 | ||
a30d46c0 | 83 | /* SIR ignored -- set interrupt, for testing only */ |
35a27e8e | 84 | struct sih_irq_data { |
a30d46c0 DB |
85 | u8 isr_offset; |
86 | u8 imr_offset; | |
87 | } mask[2]; | |
88 | /* + 2 bytes padding */ | |
89 | }; | |
90 | ||
1920a61e IK |
91 | static const struct sih *sih_modules; |
92 | static int nr_sih_modules; | |
93 | ||
a30d46c0 DB |
94 | #define SIH_INITIALIZER(modname, nbits) \ |
95 | .module = TWL4030_MODULE_ ## modname, \ | |
96 | .control_offset = TWL4030_ ## modname ## _SIH_CTRL, \ | |
97 | .bits = nbits, \ | |
98 | .bytes_ixr = DIV_ROUND_UP(nbits, 8), \ | |
99 | .edr_offset = TWL4030_ ## modname ## _EDR, \ | |
100 | .bytes_edr = DIV_ROUND_UP((2*(nbits)), 8), \ | |
1920a61e | 101 | .irq_lines = 2, \ |
a30d46c0 DB |
102 | .mask = { { \ |
103 | .isr_offset = TWL4030_ ## modname ## _ISR1, \ | |
104 | .imr_offset = TWL4030_ ## modname ## _IMR1, \ | |
105 | }, \ | |
106 | { \ | |
107 | .isr_offset = TWL4030_ ## modname ## _ISR2, \ | |
108 | .imr_offset = TWL4030_ ## modname ## _IMR2, \ | |
109 | }, }, | |
110 | ||
111 | /* register naming policies are inconsistent ... */ | |
112 | #define TWL4030_INT_PWR_EDR TWL4030_INT_PWR_EDR1 | |
113 | #define TWL4030_MODULE_KEYPAD_KEYP TWL4030_MODULE_KEYPAD | |
114 | #define TWL4030_MODULE_INT_PWR TWL4030_MODULE_INT | |
115 | ||
116 | ||
cbcde05e FC |
117 | /* |
118 | * Order in this table matches order in PIH_ISR. That is, | |
a30d46c0 DB |
119 | * BIT(n) in PIH_ISR is sih_modules[n]. |
120 | */ | |
1920a61e IK |
121 | /* sih_modules_twl4030 is used both in twl4030 and twl5030 */ |
122 | static const struct sih sih_modules_twl4030[6] = { | |
a30d46c0 DB |
123 | [0] = { |
124 | .name = "gpio", | |
125 | .module = TWL4030_MODULE_GPIO, | |
126 | .control_offset = REG_GPIO_SIH_CTRL, | |
127 | .set_cor = true, | |
128 | .bits = TWL4030_GPIO_MAX, | |
129 | .bytes_ixr = 3, | |
130 | /* Note: *all* of these IRQs default to no-trigger */ | |
131 | .edr_offset = REG_GPIO_EDR1, | |
132 | .bytes_edr = 5, | |
1920a61e | 133 | .irq_lines = 2, |
a30d46c0 DB |
134 | .mask = { { |
135 | .isr_offset = REG_GPIO_ISR1A, | |
136 | .imr_offset = REG_GPIO_IMR1A, | |
137 | }, { | |
138 | .isr_offset = REG_GPIO_ISR1B, | |
139 | .imr_offset = REG_GPIO_IMR1B, | |
140 | }, }, | |
141 | }, | |
142 | [1] = { | |
143 | .name = "keypad", | |
144 | .set_cor = true, | |
145 | SIH_INITIALIZER(KEYPAD_KEYP, 4) | |
146 | }, | |
147 | [2] = { | |
148 | .name = "bci", | |
149 | .module = TWL4030_MODULE_INTERRUPTS, | |
150 | .control_offset = TWL4030_INTERRUPTS_BCISIHCTRL, | |
8e52e279 | 151 | .set_cor = true, |
a30d46c0 DB |
152 | .bits = 12, |
153 | .bytes_ixr = 2, | |
154 | .edr_offset = TWL4030_INTERRUPTS_BCIEDR1, | |
155 | /* Note: most of these IRQs default to no-trigger */ | |
156 | .bytes_edr = 3, | |
1920a61e | 157 | .irq_lines = 2, |
a30d46c0 DB |
158 | .mask = { { |
159 | .isr_offset = TWL4030_INTERRUPTS_BCIISR1A, | |
160 | .imr_offset = TWL4030_INTERRUPTS_BCIIMR1A, | |
161 | }, { | |
162 | .isr_offset = TWL4030_INTERRUPTS_BCIISR1B, | |
163 | .imr_offset = TWL4030_INTERRUPTS_BCIIMR1B, | |
164 | }, }, | |
165 | }, | |
166 | [3] = { | |
167 | .name = "madc", | |
168 | SIH_INITIALIZER(MADC, 4) | |
169 | }, | |
170 | [4] = { | |
171 | /* USB doesn't use the same SIH organization */ | |
172 | .name = "usb", | |
173 | }, | |
174 | [5] = { | |
175 | .name = "power", | |
176 | .set_cor = true, | |
177 | SIH_INITIALIZER(INT_PWR, 8) | |
178 | }, | |
179 | /* there are no SIH modules #6 or #7 ... */ | |
180 | }; | |
181 | ||
1920a61e IK |
182 | static const struct sih sih_modules_twl5031[8] = { |
183 | [0] = { | |
184 | .name = "gpio", | |
185 | .module = TWL4030_MODULE_GPIO, | |
186 | .control_offset = REG_GPIO_SIH_CTRL, | |
187 | .set_cor = true, | |
188 | .bits = TWL4030_GPIO_MAX, | |
189 | .bytes_ixr = 3, | |
190 | /* Note: *all* of these IRQs default to no-trigger */ | |
191 | .edr_offset = REG_GPIO_EDR1, | |
192 | .bytes_edr = 5, | |
193 | .irq_lines = 2, | |
194 | .mask = { { | |
195 | .isr_offset = REG_GPIO_ISR1A, | |
196 | .imr_offset = REG_GPIO_IMR1A, | |
197 | }, { | |
198 | .isr_offset = REG_GPIO_ISR1B, | |
199 | .imr_offset = REG_GPIO_IMR1B, | |
200 | }, }, | |
201 | }, | |
202 | [1] = { | |
203 | .name = "keypad", | |
204 | .set_cor = true, | |
205 | SIH_INITIALIZER(KEYPAD_KEYP, 4) | |
206 | }, | |
207 | [2] = { | |
208 | .name = "bci", | |
209 | .module = TWL5031_MODULE_INTERRUPTS, | |
210 | .control_offset = TWL5031_INTERRUPTS_BCISIHCTRL, | |
211 | .bits = 7, | |
212 | .bytes_ixr = 1, | |
213 | .edr_offset = TWL5031_INTERRUPTS_BCIEDR1, | |
214 | /* Note: most of these IRQs default to no-trigger */ | |
215 | .bytes_edr = 2, | |
216 | .irq_lines = 2, | |
217 | .mask = { { | |
218 | .isr_offset = TWL5031_INTERRUPTS_BCIISR1, | |
219 | .imr_offset = TWL5031_INTERRUPTS_BCIIMR1, | |
220 | }, { | |
221 | .isr_offset = TWL5031_INTERRUPTS_BCIISR2, | |
222 | .imr_offset = TWL5031_INTERRUPTS_BCIIMR2, | |
223 | }, }, | |
224 | }, | |
225 | [3] = { | |
226 | .name = "madc", | |
227 | SIH_INITIALIZER(MADC, 4) | |
228 | }, | |
229 | [4] = { | |
230 | /* USB doesn't use the same SIH organization */ | |
231 | .name = "usb", | |
232 | }, | |
233 | [5] = { | |
234 | .name = "power", | |
235 | .set_cor = true, | |
236 | SIH_INITIALIZER(INT_PWR, 8) | |
237 | }, | |
238 | [6] = { | |
239 | /* | |
191211f5 IK |
240 | * ECI/DBI doesn't use the same SIH organization. |
241 | * For example, it supports only one interrupt output line. | |
242 | * That is, the interrupts are seen on both INT1 and INT2 lines. | |
1920a61e | 243 | */ |
191211f5 | 244 | .name = "eci_dbi", |
1920a61e IK |
245 | .module = TWL5031_MODULE_ACCESSORY, |
246 | .bits = 9, | |
247 | .bytes_ixr = 2, | |
248 | .irq_lines = 1, | |
249 | .mask = { { | |
250 | .isr_offset = TWL5031_ACIIDR_LSB, | |
251 | .imr_offset = TWL5031_ACIIMR_LSB, | |
252 | }, }, | |
253 | ||
254 | }, | |
255 | [7] = { | |
191211f5 IK |
256 | /* Audio accessory */ |
257 | .name = "audio", | |
1920a61e IK |
258 | .module = TWL5031_MODULE_ACCESSORY, |
259 | .control_offset = TWL5031_ACCSIHCTRL, | |
260 | .bits = 2, | |
261 | .bytes_ixr = 1, | |
262 | .edr_offset = TWL5031_ACCEDR1, | |
263 | /* Note: most of these IRQs default to no-trigger */ | |
264 | .bytes_edr = 1, | |
265 | .irq_lines = 2, | |
266 | .mask = { { | |
267 | .isr_offset = TWL5031_ACCISR1, | |
268 | .imr_offset = TWL5031_ACCIMR1, | |
269 | }, { | |
270 | .isr_offset = TWL5031_ACCISR2, | |
271 | .imr_offset = TWL5031_ACCIMR2, | |
272 | }, }, | |
273 | }, | |
274 | }; | |
275 | ||
a30d46c0 DB |
276 | #undef TWL4030_MODULE_KEYPAD_KEYP |
277 | #undef TWL4030_MODULE_INT_PWR | |
278 | #undef TWL4030_INT_PWR_EDR | |
279 | ||
280 | /*----------------------------------------------------------------------*/ | |
281 | ||
282 | static unsigned twl4030_irq_base; | |
283 | ||
a30d46c0 DB |
284 | /* |
285 | * handle_twl4030_pih() is the desc->handle method for the twl4030 interrupt. | |
286 | * This is a chained interrupt, so there is no desc->action method for it. | |
287 | * Now we need to query the interrupt controller in the twl4030 to determine | |
288 | * which module is generating the interrupt request. However, we can't do i2c | |
289 | * transactions in interrupt context, so we must defer that work to a kernel | |
290 | * thread. All we do here is acknowledge and mask the interrupt and wakeup | |
291 | * the kernel thread. | |
292 | */ | |
1cef8e41 | 293 | static irqreturn_t handle_twl4030_pih(int irq, void *devid) |
a30d46c0 | 294 | { |
7750c9b0 FB |
295 | irqreturn_t ret; |
296 | u8 pih_isr; | |
297 | ||
6fbc6420 PU |
298 | ret = twl_i2c_read_u8(TWL_MODULE_PIH, &pih_isr, |
299 | REG_PIH_ISR_P1); | |
7750c9b0 FB |
300 | if (ret) { |
301 | pr_warning("twl4030: I2C error %d reading PIH ISR\n", ret); | |
302 | return IRQ_NONE; | |
303 | } | |
304 | ||
5a903090 FB |
305 | while (pih_isr) { |
306 | unsigned long pending = __ffs(pih_isr); | |
307 | unsigned int irq; | |
308 | ||
309 | pih_isr &= ~BIT(pending); | |
310 | irq = pending + twl4030_irq_base; | |
311 | handle_nested_irq(irq); | |
7750c9b0 FB |
312 | } |
313 | ||
1cef8e41 | 314 | return IRQ_HANDLED; |
a30d46c0 | 315 | } |
cbcde05e | 316 | |
a30d46c0 DB |
317 | /*----------------------------------------------------------------------*/ |
318 | ||
319 | /* | |
320 | * twl4030_init_sih_modules() ... start from a known state where no | |
321 | * IRQs will be coming in, and where we can quickly enable them then | |
322 | * handle them as they arrive. Mask all IRQs: maybe init SIH_CTRL. | |
323 | * | |
324 | * NOTE: we don't touch EDR registers here; they stay with hardware | |
325 | * defaults or whatever the last value was. Note that when both EDR | |
326 | * bits for an IRQ are clear, that's as if its IMR bit is set... | |
327 | */ | |
328 | static int twl4030_init_sih_modules(unsigned line) | |
329 | { | |
330 | const struct sih *sih; | |
331 | u8 buf[4]; | |
332 | int i; | |
333 | int status; | |
334 | ||
335 | /* line 0 == int1_n signal; line 1 == int2_n signal */ | |
336 | if (line > 1) | |
337 | return -EINVAL; | |
338 | ||
339 | irq_line = line; | |
340 | ||
341 | /* disable all interrupts on our line */ | |
342 | memset(buf, 0xff, sizeof buf); | |
343 | sih = sih_modules; | |
1920a61e | 344 | for (i = 0; i < nr_sih_modules; i++, sih++) { |
a30d46c0 DB |
345 | /* skip USB -- it's funky */ |
346 | if (!sih->bytes_ixr) | |
347 | continue; | |
348 | ||
1920a61e IK |
349 | /* Not all the SIH modules support multiple interrupt lines */ |
350 | if (sih->irq_lines <= line) | |
351 | continue; | |
352 | ||
fc7b92fc | 353 | status = twl_i2c_write(sih->module, buf, |
a30d46c0 DB |
354 | sih->mask[line].imr_offset, sih->bytes_ixr); |
355 | if (status < 0) | |
356 | pr_err("twl4030: err %d initializing %s %s\n", | |
357 | status, sih->name, "IMR"); | |
358 | ||
cbcde05e FC |
359 | /* |
360 | * Maybe disable "exclusive" mode; buffer second pending irq; | |
a30d46c0 DB |
361 | * set Clear-On-Read (COR) bit. |
362 | * | |
363 | * NOTE that sometimes COR polarity is documented as being | |
8e52e279 | 364 | * inverted: for MADC, COR=1 means "clear on write". |
a30d46c0 DB |
365 | * And for PWR_INT it's not documented... |
366 | */ | |
367 | if (sih->set_cor) { | |
fc7b92fc | 368 | status = twl_i2c_write_u8(sih->module, |
a30d46c0 DB |
369 | TWL4030_SIH_CTRL_COR_MASK, |
370 | sih->control_offset); | |
371 | if (status < 0) | |
372 | pr_err("twl4030: err %d initializing %s %s\n", | |
373 | status, sih->name, "SIH_CTRL"); | |
374 | } | |
375 | } | |
376 | ||
377 | sih = sih_modules; | |
1920a61e | 378 | for (i = 0; i < nr_sih_modules; i++, sih++) { |
a30d46c0 DB |
379 | u8 rxbuf[4]; |
380 | int j; | |
381 | ||
382 | /* skip USB */ | |
383 | if (!sih->bytes_ixr) | |
384 | continue; | |
385 | ||
1920a61e IK |
386 | /* Not all the SIH modules support multiple interrupt lines */ |
387 | if (sih->irq_lines <= line) | |
388 | continue; | |
389 | ||
cbcde05e FC |
390 | /* |
391 | * Clear pending interrupt status. Either the read was | |
a30d46c0 DB |
392 | * enough, or we need to write those bits. Repeat, in |
393 | * case an IRQ is pending (PENDDIS=0) ... that's not | |
394 | * uncommon with PWR_INT.PWRON. | |
395 | */ | |
396 | for (j = 0; j < 2; j++) { | |
fc7b92fc | 397 | status = twl_i2c_read(sih->module, rxbuf, |
a30d46c0 DB |
398 | sih->mask[line].isr_offset, sih->bytes_ixr); |
399 | if (status < 0) | |
400 | pr_err("twl4030: err %d initializing %s %s\n", | |
401 | status, sih->name, "ISR"); | |
402 | ||
403 | if (!sih->set_cor) | |
fc7b92fc | 404 | status = twl_i2c_write(sih->module, buf, |
a30d46c0 DB |
405 | sih->mask[line].isr_offset, |
406 | sih->bytes_ixr); | |
cbcde05e FC |
407 | /* |
408 | * else COR=1 means read sufficed. | |
a30d46c0 DB |
409 | * (for most SIH modules...) |
410 | */ | |
411 | } | |
412 | } | |
413 | ||
414 | return 0; | |
415 | } | |
416 | ||
417 | static inline void activate_irq(int irq) | |
418 | { | |
419 | #ifdef CONFIG_ARM | |
cbcde05e FC |
420 | /* |
421 | * ARM requires an extra step to clear IRQ_NOREQUEST, which it | |
a30d46c0 DB |
422 | * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE. |
423 | */ | |
424 | set_irq_flags(irq, IRQF_VALID); | |
425 | #else | |
426 | /* same effect on other architectures */ | |
d5bb1221 | 427 | irq_set_noprobe(irq); |
a30d46c0 DB |
428 | #endif |
429 | } | |
430 | ||
431 | /*----------------------------------------------------------------------*/ | |
432 | ||
a30d46c0 DB |
433 | struct sih_agent { |
434 | int irq_base; | |
435 | const struct sih *sih; | |
436 | ||
437 | u32 imr; | |
438 | bool imr_change_pending; | |
a30d46c0 DB |
439 | |
440 | u32 edge_change; | |
91e3569f FB |
441 | |
442 | struct mutex irq_lock; | |
c1e61bcf | 443 | char *irq_name; |
a30d46c0 DB |
444 | }; |
445 | ||
a30d46c0 DB |
446 | /*----------------------------------------------------------------------*/ |
447 | ||
448 | /* | |
449 | * All irq_chip methods get issued from code holding irq_desc[irq].lock, | |
450 | * which can't perform the underlying I2C operations (because they sleep). | |
451 | * So we must hand them off to a thread (workqueue) and cope with asynch | |
452 | * completion, potentially including some re-ordering, of these requests. | |
453 | */ | |
454 | ||
845aeab5 | 455 | static void twl4030_sih_mask(struct irq_data *data) |
a30d46c0 | 456 | { |
84868424 | 457 | struct sih_agent *agent = irq_data_get_irq_chip_data(data); |
a30d46c0 | 458 | |
84868424 FB |
459 | agent->imr |= BIT(data->irq - agent->irq_base); |
460 | agent->imr_change_pending = true; | |
a30d46c0 DB |
461 | } |
462 | ||
845aeab5 | 463 | static void twl4030_sih_unmask(struct irq_data *data) |
a30d46c0 | 464 | { |
84868424 | 465 | struct sih_agent *agent = irq_data_get_irq_chip_data(data); |
a30d46c0 | 466 | |
84868424 FB |
467 | agent->imr &= ~BIT(data->irq - agent->irq_base); |
468 | agent->imr_change_pending = true; | |
a30d46c0 DB |
469 | } |
470 | ||
845aeab5 | 471 | static int twl4030_sih_set_type(struct irq_data *data, unsigned trigger) |
a30d46c0 | 472 | { |
84868424 | 473 | struct sih_agent *agent = irq_data_get_irq_chip_data(data); |
a30d46c0 DB |
474 | |
475 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
476 | return -EINVAL; | |
477 | ||
2f2a7d5e | 478 | if (irqd_get_trigger_type(data) != trigger) |
84868424 | 479 | agent->edge_change |= BIT(data->irq - agent->irq_base); |
91e3569f | 480 | |
a30d46c0 DB |
481 | return 0; |
482 | } | |
483 | ||
91e3569f FB |
484 | static void twl4030_sih_bus_lock(struct irq_data *data) |
485 | { | |
84868424 | 486 | struct sih_agent *agent = irq_data_get_irq_chip_data(data); |
91e3569f | 487 | |
84868424 | 488 | mutex_lock(&agent->irq_lock); |
91e3569f FB |
489 | } |
490 | ||
491 | static void twl4030_sih_bus_sync_unlock(struct irq_data *data) | |
492 | { | |
84868424 FB |
493 | struct sih_agent *agent = irq_data_get_irq_chip_data(data); |
494 | const struct sih *sih = agent->sih; | |
495 | int status; | |
496 | ||
497 | if (agent->imr_change_pending) { | |
498 | union { | |
499 | u32 word; | |
500 | u8 bytes[4]; | |
501 | } imr; | |
502 | ||
c9531227 | 503 | /* byte[0] gets overwritten as we write ... */ |
14591d88 | 504 | imr.word = cpu_to_le32(agent->imr); |
84868424 FB |
505 | agent->imr_change_pending = false; |
506 | ||
507 | /* write the whole mask ... simpler than subsetting it */ | |
508 | status = twl_i2c_write(sih->module, imr.bytes, | |
509 | sih->mask[irq_line].imr_offset, | |
510 | sih->bytes_ixr); | |
511 | if (status) | |
512 | pr_err("twl4030: %s, %s --> %d\n", __func__, | |
513 | "write", status); | |
514 | } | |
91e3569f | 515 | |
2f2a7d5e FB |
516 | if (agent->edge_change) { |
517 | u32 edge_change; | |
518 | u8 bytes[6]; | |
519 | ||
520 | edge_change = agent->edge_change; | |
521 | agent->edge_change = 0; | |
522 | ||
523 | /* | |
524 | * Read, reserving first byte for write scratch. Yes, this | |
525 | * could be cached for some speedup ... but be careful about | |
526 | * any processor on the other IRQ line, EDR registers are | |
527 | * shared. | |
528 | */ | |
14591d88 | 529 | status = twl_i2c_read(sih->module, bytes, |
2f2a7d5e FB |
530 | sih->edr_offset, sih->bytes_edr); |
531 | if (status) { | |
532 | pr_err("twl4030: %s, %s --> %d\n", __func__, | |
533 | "read", status); | |
534 | return; | |
535 | } | |
536 | ||
537 | /* Modify only the bits we know must change */ | |
538 | while (edge_change) { | |
539 | int i = fls(edge_change) - 1; | |
540 | struct irq_data *idata; | |
14591d88 | 541 | int byte = i >> 2; |
2f2a7d5e FB |
542 | int off = (i & 0x3) * 2; |
543 | unsigned int type; | |
544 | ||
545 | idata = irq_get_irq_data(i + agent->irq_base); | |
546 | ||
547 | bytes[byte] &= ~(0x03 << off); | |
548 | ||
549 | type = irqd_get_trigger_type(idata); | |
550 | if (type & IRQ_TYPE_EDGE_RISING) | |
551 | bytes[byte] |= BIT(off + 1); | |
552 | if (type & IRQ_TYPE_EDGE_FALLING) | |
553 | bytes[byte] |= BIT(off + 0); | |
554 | ||
555 | edge_change &= ~BIT(i); | |
556 | } | |
557 | ||
558 | /* Write */ | |
559 | status = twl_i2c_write(sih->module, bytes, | |
560 | sih->edr_offset, sih->bytes_edr); | |
561 | if (status) | |
562 | pr_err("twl4030: %s, %s --> %d\n", __func__, | |
563 | "write", status); | |
564 | } | |
565 | ||
84868424 | 566 | mutex_unlock(&agent->irq_lock); |
91e3569f FB |
567 | } |
568 | ||
a30d46c0 DB |
569 | static struct irq_chip twl4030_sih_irq_chip = { |
570 | .name = "twl4030", | |
8cd6af29 | 571 | .irq_mask = twl4030_sih_mask, |
845aeab5 MB |
572 | .irq_unmask = twl4030_sih_unmask, |
573 | .irq_set_type = twl4030_sih_set_type, | |
91e3569f FB |
574 | .irq_bus_lock = twl4030_sih_bus_lock, |
575 | .irq_bus_sync_unlock = twl4030_sih_bus_sync_unlock, | |
a30d46c0 DB |
576 | }; |
577 | ||
578 | /*----------------------------------------------------------------------*/ | |
579 | ||
580 | static inline int sih_read_isr(const struct sih *sih) | |
581 | { | |
582 | int status; | |
583 | union { | |
584 | u8 bytes[4]; | |
585 | u32 word; | |
586 | } isr; | |
587 | ||
588 | /* FIXME need retry-on-error ... */ | |
589 | ||
590 | isr.word = 0; | |
fc7b92fc | 591 | status = twl_i2c_read(sih->module, isr.bytes, |
a30d46c0 DB |
592 | sih->mask[irq_line].isr_offset, sih->bytes_ixr); |
593 | ||
594 | return (status < 0) ? status : le32_to_cpu(isr.word); | |
595 | } | |
596 | ||
597 | /* | |
598 | * Generic handler for SIH interrupts ... we "know" this is called | |
599 | * in task context, with IRQs enabled. | |
600 | */ | |
c1e61bcf | 601 | static irqreturn_t handle_twl4030_sih(int irq, void *data) |
a30d46c0 | 602 | { |
d5bb1221 | 603 | struct sih_agent *agent = irq_get_handler_data(irq); |
a30d46c0 DB |
604 | const struct sih *sih = agent->sih; |
605 | int isr; | |
606 | ||
607 | /* reading ISR acks the IRQs, using clear-on-read mode */ | |
a30d46c0 | 608 | isr = sih_read_isr(sih); |
a30d46c0 DB |
609 | |
610 | if (isr < 0) { | |
611 | pr_err("twl4030: %s SIH, read ISR error %d\n", | |
612 | sih->name, isr); | |
613 | /* REVISIT: recover; eventually mask it all, etc */ | |
c1e61bcf | 614 | return IRQ_HANDLED; |
a30d46c0 DB |
615 | } |
616 | ||
617 | while (isr) { | |
618 | irq = fls(isr); | |
619 | irq--; | |
620 | isr &= ~BIT(irq); | |
621 | ||
622 | if (irq < sih->bits) | |
925e853c | 623 | handle_nested_irq(agent->irq_base + irq); |
a30d46c0 DB |
624 | else |
625 | pr_err("twl4030: %s SIH, invalid ISR bit %d\n", | |
626 | sih->name, irq); | |
627 | } | |
c1e61bcf | 628 | return IRQ_HANDLED; |
a30d46c0 DB |
629 | } |
630 | ||
cbcde05e | 631 | /* returns the first IRQ used by this SIH bank, or negative errno */ |
f01b1f90 | 632 | int twl4030_sih_setup(struct device *dev, int module, int irq_base) |
a30d46c0 DB |
633 | { |
634 | int sih_mod; | |
635 | const struct sih *sih = NULL; | |
636 | struct sih_agent *agent; | |
637 | int i, irq; | |
638 | int status = -EINVAL; | |
a30d46c0 DB |
639 | |
640 | /* only support modules with standard clear-on-read for now */ | |
ec1a07b3 | 641 | for (sih_mod = 0, sih = sih_modules; sih_mod < nr_sih_modules; |
a30d46c0 DB |
642 | sih_mod++, sih++) { |
643 | if (sih->module == module && sih->set_cor) { | |
f01b1f90 | 644 | status = 0; |
a30d46c0 DB |
645 | break; |
646 | } | |
647 | } | |
ec1a07b3 | 648 | |
a30d46c0 DB |
649 | if (status < 0) |
650 | return status; | |
651 | ||
652 | agent = kzalloc(sizeof *agent, GFP_KERNEL); | |
653 | if (!agent) | |
654 | return -ENOMEM; | |
655 | ||
a30d46c0 DB |
656 | agent->irq_base = irq_base; |
657 | agent->sih = sih; | |
658 | agent->imr = ~0; | |
91e3569f | 659 | mutex_init(&agent->irq_lock); |
a30d46c0 DB |
660 | |
661 | for (i = 0; i < sih->bits; i++) { | |
662 | irq = irq_base + i; | |
663 | ||
91e3569f | 664 | irq_set_chip_data(irq, agent); |
d5bb1221 TG |
665 | irq_set_chip_and_handler(irq, &twl4030_sih_irq_chip, |
666 | handle_edge_irq); | |
b18d1f0f | 667 | irq_set_nested_thread(irq, 1); |
a30d46c0 DB |
668 | activate_irq(irq); |
669 | } | |
670 | ||
a30d46c0 DB |
671 | /* replace generic PIH handler (handle_simple_irq) */ |
672 | irq = sih_mod + twl4030_irq_base; | |
d5bb1221 | 673 | irq_set_handler_data(irq, agent); |
c1e61bcf | 674 | agent->irq_name = kasprintf(GFP_KERNEL, "twl4030_%s", sih->name); |
8b41669c KJ |
675 | status = request_threaded_irq(irq, NULL, handle_twl4030_sih, |
676 | IRQF_EARLY_RESUME, | |
c1e61bcf | 677 | agent->irq_name ?: sih->name, NULL); |
a30d46c0 | 678 | |
ec1a07b3 | 679 | dev_info(dev, "%s (irq %d) chaining IRQs %d..%d\n", sih->name, |
f01b1f90 | 680 | irq, irq_base, irq_base + i - 1); |
a30d46c0 | 681 | |
c1e61bcf | 682 | return status < 0 ? status : irq_base; |
a30d46c0 DB |
683 | } |
684 | ||
685 | /* FIXME need a call to reverse twl4030_sih_setup() ... */ | |
686 | ||
a30d46c0 DB |
687 | /*----------------------------------------------------------------------*/ |
688 | ||
689 | /* FIXME pass in which interrupt line we'll use ... */ | |
690 | #define twl_irq_line 0 | |
691 | ||
78518ffa | 692 | int twl4030_init_irq(struct device *dev, int irq_num) |
a30d46c0 DB |
693 | { |
694 | static struct irq_chip twl4030_irq_chip; | |
ec1a07b3 | 695 | int status, i; |
78518ffa BC |
696 | int irq_base, irq_end, nr_irqs; |
697 | struct device_node *node = dev->of_node; | |
a30d46c0 | 698 | |
78518ffa BC |
699 | /* |
700 | * TWL core and pwr interrupts must be contiguous because | |
701 | * the hwirqs numbers are defined contiguously from 1 to 15. | |
702 | * Create only one domain for both. | |
703 | */ | |
704 | nr_irqs = TWL4030_PWR_NR_IRQS + TWL4030_CORE_NR_IRQS; | |
705 | ||
706 | irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0); | |
707 | if (IS_ERR_VALUE(irq_base)) { | |
708 | dev_err(dev, "Fail to allocate IRQ descs\n"); | |
709 | return irq_base; | |
710 | } | |
711 | ||
712 | irq_domain_add_legacy(node, nr_irqs, irq_base, 0, | |
713 | &irq_domain_simple_ops, NULL); | |
714 | ||
715 | irq_end = irq_base + TWL4030_CORE_NR_IRQS; | |
716 | ||
a30d46c0 DB |
717 | /* |
718 | * Mask and clear all TWL4030 interrupts since initially we do | |
719 | * not have any TWL4030 module interrupt handlers present | |
720 | */ | |
721 | status = twl4030_init_sih_modules(twl_irq_line); | |
722 | if (status < 0) | |
723 | return status; | |
724 | ||
a30d46c0 DB |
725 | twl4030_irq_base = irq_base; |
726 | ||
cbcde05e | 727 | /* |
ec1a07b3 | 728 | * Install an irq handler for each of the SIH modules; |
a30d46c0 DB |
729 | * clone dummy irq_chip since PIH can't *do* anything |
730 | */ | |
731 | twl4030_irq_chip = dummy_irq_chip; | |
732 | twl4030_irq_chip.name = "twl4030"; | |
733 | ||
fe212213 | 734 | twl4030_sih_irq_chip.irq_ack = dummy_irq_chip.irq_ack; |
a30d46c0 DB |
735 | |
736 | for (i = irq_base; i < irq_end; i++) { | |
d5bb1221 TG |
737 | irq_set_chip_and_handler(i, &twl4030_irq_chip, |
738 | handle_simple_irq); | |
925e853c | 739 | irq_set_nested_thread(i, 1); |
a30d46c0 DB |
740 | activate_irq(i); |
741 | } | |
f01b1f90 | 742 | |
ec1a07b3 | 743 | dev_info(dev, "%s (irq %d) chaining IRQs %d..%d\n", "PIH", |
f01b1f90 | 744 | irq_num, irq_base, irq_end); |
a30d46c0 DB |
745 | |
746 | /* ... and the PWR_INT module ... */ | |
f01b1f90 | 747 | status = twl4030_sih_setup(dev, TWL4030_MODULE_INT, irq_end); |
a30d46c0 | 748 | if (status < 0) { |
ec1a07b3 | 749 | dev_err(dev, "sih_setup PWR INT --> %d\n", status); |
a30d46c0 DB |
750 | goto fail; |
751 | } | |
752 | ||
753 | /* install an irq handler to demultiplex the TWL4030 interrupt */ | |
286f8f3c N |
754 | status = request_threaded_irq(irq_num, NULL, handle_twl4030_pih, |
755 | IRQF_ONESHOT, | |
756 | "TWL4030-PIH", NULL); | |
1cef8e41 | 757 | if (status < 0) { |
ec1a07b3 | 758 | dev_err(dev, "could not claim irq%d: %d\n", irq_num, status); |
1cef8e41 RK |
759 | goto fail_rqirq; |
760 | } | |
5a2f1b5f | 761 | enable_irq_wake(irq_num); |
1cef8e41 | 762 | |
78518ffa | 763 | return irq_base; |
1cef8e41 RK |
764 | fail_rqirq: |
765 | /* clean up twl4030_sih_setup */ | |
a30d46c0 | 766 | fail: |
925e853c FB |
767 | for (i = irq_base; i < irq_end; i++) { |
768 | irq_set_nested_thread(i, 0); | |
d5bb1221 | 769 | irq_set_chip_and_handler(i, NULL, NULL); |
925e853c | 770 | } |
2f2a7d5e | 771 | |
a30d46c0 DB |
772 | return status; |
773 | } | |
774 | ||
e8deb28c | 775 | int twl4030_exit_irq(void) |
a30d46c0 DB |
776 | { |
777 | /* FIXME undo twl_init_irq() */ | |
778 | if (twl4030_irq_base) { | |
779 | pr_err("twl4030: can't yet clean up IRQs?\n"); | |
780 | return -ENOSYS; | |
781 | } | |
782 | return 0; | |
783 | } | |
1920a61e | 784 | |
e8deb28c | 785 | int twl4030_init_chip_irq(const char *chip) |
1920a61e IK |
786 | { |
787 | if (!strcmp(chip, "twl5031")) { | |
788 | sih_modules = sih_modules_twl5031; | |
789 | nr_sih_modules = ARRAY_SIZE(sih_modules_twl5031); | |
790 | } else { | |
791 | sih_modules = sih_modules_twl4030; | |
792 | nr_sih_modules = ARRAY_SIZE(sih_modules_twl4030); | |
793 | } | |
794 | ||
795 | return 0; | |
796 | } |