Commit | Line | Data |
---|---|---|
a30d46c0 DB |
1 | /* |
2 | * twl4030-irq.c - TWL4030/TPS659x0 irq support | |
3 | * | |
4 | * Copyright (C) 2005-2006 Texas Instruments, Inc. | |
5 | * | |
6 | * Modifications to defer interrupt handling to a kernel thread: | |
7 | * Copyright (C) 2006 MontaVista Software, Inc. | |
8 | * | |
9 | * Based on tlv320aic23.c: | |
10 | * Copyright (c) by Kai Svahn <kai.svahn@nokia.com> | |
11 | * | |
12 | * Code cleanup and modifications to IRQ handler. | |
13 | * by syed khasim <x0khasim@ti.com> | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License as published by | |
17 | * the Free Software Foundation; either version 2 of the License, or | |
18 | * (at your option) any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License | |
26 | * along with this program; if not, write to the Free Software | |
27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
28 | */ | |
29 | ||
30 | #include <linux/init.h> | |
78518ffa | 31 | #include <linux/export.h> |
a30d46c0 DB |
32 | #include <linux/interrupt.h> |
33 | #include <linux/irq.h> | |
5a0e3ad6 | 34 | #include <linux/slab.h> |
a30d46c0 | 35 | |
78518ffa BC |
36 | #include <linux/of.h> |
37 | #include <linux/irqdomain.h> | |
b07682b6 | 38 | #include <linux/i2c/twl.h> |
a30d46c0 | 39 | |
b0b4a7c2 | 40 | #include "twl-core.h" |
a30d46c0 DB |
41 | |
42 | /* | |
43 | * TWL4030 IRQ handling has two stages in hardware, and thus in software. | |
44 | * The Primary Interrupt Handler (PIH) stage exposes status bits saying | |
45 | * which Secondary Interrupt Handler (SIH) stage is raising an interrupt. | |
46 | * SIH modules are more traditional IRQ components, which support per-IRQ | |
47 | * enable/disable and trigger controls; they do most of the work. | |
48 | * | |
49 | * These chips are designed to support IRQ handling from two different | |
50 | * I2C masters. Each has a dedicated IRQ line, and dedicated IRQ status | |
51 | * and mask registers in the PIH and SIH modules. | |
52 | * | |
53 | * We set up IRQs starting at a platform-specified base, always starting | |
54 | * with PIH and the SIH for PWR_INT and then usually adding GPIO: | |
55 | * base + 0 .. base + 7 PIH | |
56 | * base + 8 .. base + 15 SIH for PWR_INT | |
57 | * base + 16 .. base + 33 SIH for GPIO | |
58 | */ | |
78518ffa BC |
59 | #define TWL4030_CORE_NR_IRQS 8 |
60 | #define TWL4030_PWR_NR_IRQS 8 | |
a30d46c0 DB |
61 | |
62 | /* PIH register offsets */ | |
63 | #define REG_PIH_ISR_P1 0x01 | |
64 | #define REG_PIH_ISR_P2 0x02 | |
65 | #define REG_PIH_SIR 0x03 /* for testing */ | |
66 | ||
a30d46c0 DB |
67 | /* Linux could (eventually) use either IRQ line */ |
68 | static int irq_line; | |
69 | ||
70 | struct sih { | |
71 | char name[8]; | |
72 | u8 module; /* module id */ | |
73 | u8 control_offset; /* for SIH_CTRL */ | |
74 | bool set_cor; | |
75 | ||
76 | u8 bits; /* valid in isr/imr */ | |
77 | u8 bytes_ixr; /* bytelen of ISR/IMR/SIR */ | |
78 | ||
79 | u8 edr_offset; | |
80 | u8 bytes_edr; /* bytelen of EDR */ | |
81 | ||
1920a61e IK |
82 | u8 irq_lines; /* number of supported irq lines */ |
83 | ||
a30d46c0 | 84 | /* SIR ignored -- set interrupt, for testing only */ |
35a27e8e | 85 | struct sih_irq_data { |
a30d46c0 DB |
86 | u8 isr_offset; |
87 | u8 imr_offset; | |
88 | } mask[2]; | |
89 | /* + 2 bytes padding */ | |
90 | }; | |
91 | ||
1920a61e IK |
92 | static const struct sih *sih_modules; |
93 | static int nr_sih_modules; | |
94 | ||
a30d46c0 DB |
95 | #define SIH_INITIALIZER(modname, nbits) \ |
96 | .module = TWL4030_MODULE_ ## modname, \ | |
97 | .control_offset = TWL4030_ ## modname ## _SIH_CTRL, \ | |
98 | .bits = nbits, \ | |
99 | .bytes_ixr = DIV_ROUND_UP(nbits, 8), \ | |
100 | .edr_offset = TWL4030_ ## modname ## _EDR, \ | |
101 | .bytes_edr = DIV_ROUND_UP((2*(nbits)), 8), \ | |
1920a61e | 102 | .irq_lines = 2, \ |
a30d46c0 DB |
103 | .mask = { { \ |
104 | .isr_offset = TWL4030_ ## modname ## _ISR1, \ | |
105 | .imr_offset = TWL4030_ ## modname ## _IMR1, \ | |
106 | }, \ | |
107 | { \ | |
108 | .isr_offset = TWL4030_ ## modname ## _ISR2, \ | |
109 | .imr_offset = TWL4030_ ## modname ## _IMR2, \ | |
110 | }, }, | |
111 | ||
112 | /* register naming policies are inconsistent ... */ | |
113 | #define TWL4030_INT_PWR_EDR TWL4030_INT_PWR_EDR1 | |
114 | #define TWL4030_MODULE_KEYPAD_KEYP TWL4030_MODULE_KEYPAD | |
115 | #define TWL4030_MODULE_INT_PWR TWL4030_MODULE_INT | |
116 | ||
117 | ||
cbcde05e FC |
118 | /* |
119 | * Order in this table matches order in PIH_ISR. That is, | |
a30d46c0 DB |
120 | * BIT(n) in PIH_ISR is sih_modules[n]. |
121 | */ | |
1920a61e IK |
122 | /* sih_modules_twl4030 is used both in twl4030 and twl5030 */ |
123 | static const struct sih sih_modules_twl4030[6] = { | |
a30d46c0 DB |
124 | [0] = { |
125 | .name = "gpio", | |
126 | .module = TWL4030_MODULE_GPIO, | |
127 | .control_offset = REG_GPIO_SIH_CTRL, | |
128 | .set_cor = true, | |
129 | .bits = TWL4030_GPIO_MAX, | |
130 | .bytes_ixr = 3, | |
131 | /* Note: *all* of these IRQs default to no-trigger */ | |
132 | .edr_offset = REG_GPIO_EDR1, | |
133 | .bytes_edr = 5, | |
1920a61e | 134 | .irq_lines = 2, |
a30d46c0 DB |
135 | .mask = { { |
136 | .isr_offset = REG_GPIO_ISR1A, | |
137 | .imr_offset = REG_GPIO_IMR1A, | |
138 | }, { | |
139 | .isr_offset = REG_GPIO_ISR1B, | |
140 | .imr_offset = REG_GPIO_IMR1B, | |
141 | }, }, | |
142 | }, | |
143 | [1] = { | |
144 | .name = "keypad", | |
145 | .set_cor = true, | |
146 | SIH_INITIALIZER(KEYPAD_KEYP, 4) | |
147 | }, | |
148 | [2] = { | |
149 | .name = "bci", | |
150 | .module = TWL4030_MODULE_INTERRUPTS, | |
151 | .control_offset = TWL4030_INTERRUPTS_BCISIHCTRL, | |
8e52e279 | 152 | .set_cor = true, |
a30d46c0 DB |
153 | .bits = 12, |
154 | .bytes_ixr = 2, | |
155 | .edr_offset = TWL4030_INTERRUPTS_BCIEDR1, | |
156 | /* Note: most of these IRQs default to no-trigger */ | |
157 | .bytes_edr = 3, | |
1920a61e | 158 | .irq_lines = 2, |
a30d46c0 DB |
159 | .mask = { { |
160 | .isr_offset = TWL4030_INTERRUPTS_BCIISR1A, | |
161 | .imr_offset = TWL4030_INTERRUPTS_BCIIMR1A, | |
162 | }, { | |
163 | .isr_offset = TWL4030_INTERRUPTS_BCIISR1B, | |
164 | .imr_offset = TWL4030_INTERRUPTS_BCIIMR1B, | |
165 | }, }, | |
166 | }, | |
167 | [3] = { | |
168 | .name = "madc", | |
169 | SIH_INITIALIZER(MADC, 4) | |
170 | }, | |
171 | [4] = { | |
172 | /* USB doesn't use the same SIH organization */ | |
173 | .name = "usb", | |
174 | }, | |
175 | [5] = { | |
176 | .name = "power", | |
177 | .set_cor = true, | |
178 | SIH_INITIALIZER(INT_PWR, 8) | |
179 | }, | |
180 | /* there are no SIH modules #6 or #7 ... */ | |
181 | }; | |
182 | ||
1920a61e IK |
183 | static const struct sih sih_modules_twl5031[8] = { |
184 | [0] = { | |
185 | .name = "gpio", | |
186 | .module = TWL4030_MODULE_GPIO, | |
187 | .control_offset = REG_GPIO_SIH_CTRL, | |
188 | .set_cor = true, | |
189 | .bits = TWL4030_GPIO_MAX, | |
190 | .bytes_ixr = 3, | |
191 | /* Note: *all* of these IRQs default to no-trigger */ | |
192 | .edr_offset = REG_GPIO_EDR1, | |
193 | .bytes_edr = 5, | |
194 | .irq_lines = 2, | |
195 | .mask = { { | |
196 | .isr_offset = REG_GPIO_ISR1A, | |
197 | .imr_offset = REG_GPIO_IMR1A, | |
198 | }, { | |
199 | .isr_offset = REG_GPIO_ISR1B, | |
200 | .imr_offset = REG_GPIO_IMR1B, | |
201 | }, }, | |
202 | }, | |
203 | [1] = { | |
204 | .name = "keypad", | |
205 | .set_cor = true, | |
206 | SIH_INITIALIZER(KEYPAD_KEYP, 4) | |
207 | }, | |
208 | [2] = { | |
209 | .name = "bci", | |
210 | .module = TWL5031_MODULE_INTERRUPTS, | |
211 | .control_offset = TWL5031_INTERRUPTS_BCISIHCTRL, | |
212 | .bits = 7, | |
213 | .bytes_ixr = 1, | |
214 | .edr_offset = TWL5031_INTERRUPTS_BCIEDR1, | |
215 | /* Note: most of these IRQs default to no-trigger */ | |
216 | .bytes_edr = 2, | |
217 | .irq_lines = 2, | |
218 | .mask = { { | |
219 | .isr_offset = TWL5031_INTERRUPTS_BCIISR1, | |
220 | .imr_offset = TWL5031_INTERRUPTS_BCIIMR1, | |
221 | }, { | |
222 | .isr_offset = TWL5031_INTERRUPTS_BCIISR2, | |
223 | .imr_offset = TWL5031_INTERRUPTS_BCIIMR2, | |
224 | }, }, | |
225 | }, | |
226 | [3] = { | |
227 | .name = "madc", | |
228 | SIH_INITIALIZER(MADC, 4) | |
229 | }, | |
230 | [4] = { | |
231 | /* USB doesn't use the same SIH organization */ | |
232 | .name = "usb", | |
233 | }, | |
234 | [5] = { | |
235 | .name = "power", | |
236 | .set_cor = true, | |
237 | SIH_INITIALIZER(INT_PWR, 8) | |
238 | }, | |
239 | [6] = { | |
240 | /* | |
191211f5 IK |
241 | * ECI/DBI doesn't use the same SIH organization. |
242 | * For example, it supports only one interrupt output line. | |
243 | * That is, the interrupts are seen on both INT1 and INT2 lines. | |
1920a61e | 244 | */ |
191211f5 | 245 | .name = "eci_dbi", |
1920a61e IK |
246 | .module = TWL5031_MODULE_ACCESSORY, |
247 | .bits = 9, | |
248 | .bytes_ixr = 2, | |
249 | .irq_lines = 1, | |
250 | .mask = { { | |
251 | .isr_offset = TWL5031_ACIIDR_LSB, | |
252 | .imr_offset = TWL5031_ACIIMR_LSB, | |
253 | }, }, | |
254 | ||
255 | }, | |
256 | [7] = { | |
191211f5 IK |
257 | /* Audio accessory */ |
258 | .name = "audio", | |
1920a61e IK |
259 | .module = TWL5031_MODULE_ACCESSORY, |
260 | .control_offset = TWL5031_ACCSIHCTRL, | |
261 | .bits = 2, | |
262 | .bytes_ixr = 1, | |
263 | .edr_offset = TWL5031_ACCEDR1, | |
264 | /* Note: most of these IRQs default to no-trigger */ | |
265 | .bytes_edr = 1, | |
266 | .irq_lines = 2, | |
267 | .mask = { { | |
268 | .isr_offset = TWL5031_ACCISR1, | |
269 | .imr_offset = TWL5031_ACCIMR1, | |
270 | }, { | |
271 | .isr_offset = TWL5031_ACCISR2, | |
272 | .imr_offset = TWL5031_ACCIMR2, | |
273 | }, }, | |
274 | }, | |
275 | }; | |
276 | ||
a30d46c0 DB |
277 | #undef TWL4030_MODULE_KEYPAD_KEYP |
278 | #undef TWL4030_MODULE_INT_PWR | |
279 | #undef TWL4030_INT_PWR_EDR | |
280 | ||
281 | /*----------------------------------------------------------------------*/ | |
282 | ||
283 | static unsigned twl4030_irq_base; | |
284 | ||
a30d46c0 DB |
285 | /* |
286 | * handle_twl4030_pih() is the desc->handle method for the twl4030 interrupt. | |
287 | * This is a chained interrupt, so there is no desc->action method for it. | |
288 | * Now we need to query the interrupt controller in the twl4030 to determine | |
289 | * which module is generating the interrupt request. However, we can't do i2c | |
290 | * transactions in interrupt context, so we must defer that work to a kernel | |
291 | * thread. All we do here is acknowledge and mask the interrupt and wakeup | |
292 | * the kernel thread. | |
293 | */ | |
1cef8e41 | 294 | static irqreturn_t handle_twl4030_pih(int irq, void *devid) |
a30d46c0 | 295 | { |
7750c9b0 FB |
296 | int module_irq; |
297 | irqreturn_t ret; | |
298 | u8 pih_isr; | |
299 | ||
300 | ret = twl_i2c_read_u8(TWL4030_MODULE_PIH, &pih_isr, | |
301 | REG_PIH_ISR_P1); | |
302 | if (ret) { | |
303 | pr_warning("twl4030: I2C error %d reading PIH ISR\n", ret); | |
304 | return IRQ_NONE; | |
305 | } | |
306 | ||
307 | /* these handlers deal with the relevant SIH irq status */ | |
308 | for (module_irq = twl4030_irq_base; | |
309 | pih_isr; | |
310 | pih_isr >>= 1, module_irq++) { | |
311 | if (pih_isr & 0x1) | |
925e853c | 312 | handle_nested_irq(module_irq); |
7750c9b0 FB |
313 | } |
314 | ||
1cef8e41 | 315 | return IRQ_HANDLED; |
a30d46c0 | 316 | } |
cbcde05e | 317 | |
a30d46c0 DB |
318 | /*----------------------------------------------------------------------*/ |
319 | ||
320 | /* | |
321 | * twl4030_init_sih_modules() ... start from a known state where no | |
322 | * IRQs will be coming in, and where we can quickly enable them then | |
323 | * handle them as they arrive. Mask all IRQs: maybe init SIH_CTRL. | |
324 | * | |
325 | * NOTE: we don't touch EDR registers here; they stay with hardware | |
326 | * defaults or whatever the last value was. Note that when both EDR | |
327 | * bits for an IRQ are clear, that's as if its IMR bit is set... | |
328 | */ | |
329 | static int twl4030_init_sih_modules(unsigned line) | |
330 | { | |
331 | const struct sih *sih; | |
332 | u8 buf[4]; | |
333 | int i; | |
334 | int status; | |
335 | ||
336 | /* line 0 == int1_n signal; line 1 == int2_n signal */ | |
337 | if (line > 1) | |
338 | return -EINVAL; | |
339 | ||
340 | irq_line = line; | |
341 | ||
342 | /* disable all interrupts on our line */ | |
343 | memset(buf, 0xff, sizeof buf); | |
344 | sih = sih_modules; | |
1920a61e | 345 | for (i = 0; i < nr_sih_modules; i++, sih++) { |
a30d46c0 DB |
346 | /* skip USB -- it's funky */ |
347 | if (!sih->bytes_ixr) | |
348 | continue; | |
349 | ||
1920a61e IK |
350 | /* Not all the SIH modules support multiple interrupt lines */ |
351 | if (sih->irq_lines <= line) | |
352 | continue; | |
353 | ||
fc7b92fc | 354 | status = twl_i2c_write(sih->module, buf, |
a30d46c0 DB |
355 | sih->mask[line].imr_offset, sih->bytes_ixr); |
356 | if (status < 0) | |
357 | pr_err("twl4030: err %d initializing %s %s\n", | |
358 | status, sih->name, "IMR"); | |
359 | ||
cbcde05e FC |
360 | /* |
361 | * Maybe disable "exclusive" mode; buffer second pending irq; | |
a30d46c0 DB |
362 | * set Clear-On-Read (COR) bit. |
363 | * | |
364 | * NOTE that sometimes COR polarity is documented as being | |
8e52e279 | 365 | * inverted: for MADC, COR=1 means "clear on write". |
a30d46c0 DB |
366 | * And for PWR_INT it's not documented... |
367 | */ | |
368 | if (sih->set_cor) { | |
fc7b92fc | 369 | status = twl_i2c_write_u8(sih->module, |
a30d46c0 DB |
370 | TWL4030_SIH_CTRL_COR_MASK, |
371 | sih->control_offset); | |
372 | if (status < 0) | |
373 | pr_err("twl4030: err %d initializing %s %s\n", | |
374 | status, sih->name, "SIH_CTRL"); | |
375 | } | |
376 | } | |
377 | ||
378 | sih = sih_modules; | |
1920a61e | 379 | for (i = 0; i < nr_sih_modules; i++, sih++) { |
a30d46c0 DB |
380 | u8 rxbuf[4]; |
381 | int j; | |
382 | ||
383 | /* skip USB */ | |
384 | if (!sih->bytes_ixr) | |
385 | continue; | |
386 | ||
1920a61e IK |
387 | /* Not all the SIH modules support multiple interrupt lines */ |
388 | if (sih->irq_lines <= line) | |
389 | continue; | |
390 | ||
cbcde05e FC |
391 | /* |
392 | * Clear pending interrupt status. Either the read was | |
a30d46c0 DB |
393 | * enough, or we need to write those bits. Repeat, in |
394 | * case an IRQ is pending (PENDDIS=0) ... that's not | |
395 | * uncommon with PWR_INT.PWRON. | |
396 | */ | |
397 | for (j = 0; j < 2; j++) { | |
fc7b92fc | 398 | status = twl_i2c_read(sih->module, rxbuf, |
a30d46c0 DB |
399 | sih->mask[line].isr_offset, sih->bytes_ixr); |
400 | if (status < 0) | |
401 | pr_err("twl4030: err %d initializing %s %s\n", | |
402 | status, sih->name, "ISR"); | |
403 | ||
404 | if (!sih->set_cor) | |
fc7b92fc | 405 | status = twl_i2c_write(sih->module, buf, |
a30d46c0 DB |
406 | sih->mask[line].isr_offset, |
407 | sih->bytes_ixr); | |
cbcde05e FC |
408 | /* |
409 | * else COR=1 means read sufficed. | |
a30d46c0 DB |
410 | * (for most SIH modules...) |
411 | */ | |
412 | } | |
413 | } | |
414 | ||
415 | return 0; | |
416 | } | |
417 | ||
418 | static inline void activate_irq(int irq) | |
419 | { | |
420 | #ifdef CONFIG_ARM | |
cbcde05e FC |
421 | /* |
422 | * ARM requires an extra step to clear IRQ_NOREQUEST, which it | |
a30d46c0 DB |
423 | * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE. |
424 | */ | |
425 | set_irq_flags(irq, IRQF_VALID); | |
426 | #else | |
427 | /* same effect on other architectures */ | |
d5bb1221 | 428 | irq_set_noprobe(irq); |
a30d46c0 DB |
429 | #endif |
430 | } | |
431 | ||
432 | /*----------------------------------------------------------------------*/ | |
433 | ||
a30d46c0 DB |
434 | struct sih_agent { |
435 | int irq_base; | |
436 | const struct sih *sih; | |
437 | ||
438 | u32 imr; | |
439 | bool imr_change_pending; | |
a30d46c0 DB |
440 | |
441 | u32 edge_change; | |
91e3569f FB |
442 | |
443 | struct mutex irq_lock; | |
c1e61bcf | 444 | char *irq_name; |
a30d46c0 DB |
445 | }; |
446 | ||
a30d46c0 DB |
447 | /*----------------------------------------------------------------------*/ |
448 | ||
449 | /* | |
450 | * All irq_chip methods get issued from code holding irq_desc[irq].lock, | |
451 | * which can't perform the underlying I2C operations (because they sleep). | |
452 | * So we must hand them off to a thread (workqueue) and cope with asynch | |
453 | * completion, potentially including some re-ordering, of these requests. | |
454 | */ | |
455 | ||
845aeab5 | 456 | static void twl4030_sih_mask(struct irq_data *data) |
a30d46c0 | 457 | { |
84868424 | 458 | struct sih_agent *agent = irq_data_get_irq_chip_data(data); |
a30d46c0 | 459 | |
84868424 FB |
460 | agent->imr |= BIT(data->irq - agent->irq_base); |
461 | agent->imr_change_pending = true; | |
a30d46c0 DB |
462 | } |
463 | ||
845aeab5 | 464 | static void twl4030_sih_unmask(struct irq_data *data) |
a30d46c0 | 465 | { |
84868424 | 466 | struct sih_agent *agent = irq_data_get_irq_chip_data(data); |
a30d46c0 | 467 | |
84868424 FB |
468 | agent->imr &= ~BIT(data->irq - agent->irq_base); |
469 | agent->imr_change_pending = true; | |
a30d46c0 DB |
470 | } |
471 | ||
845aeab5 | 472 | static int twl4030_sih_set_type(struct irq_data *data, unsigned trigger) |
a30d46c0 | 473 | { |
84868424 | 474 | struct sih_agent *agent = irq_data_get_irq_chip_data(data); |
a30d46c0 DB |
475 | |
476 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
477 | return -EINVAL; | |
478 | ||
2f2a7d5e | 479 | if (irqd_get_trigger_type(data) != trigger) |
84868424 | 480 | agent->edge_change |= BIT(data->irq - agent->irq_base); |
91e3569f | 481 | |
a30d46c0 DB |
482 | return 0; |
483 | } | |
484 | ||
91e3569f FB |
485 | static void twl4030_sih_bus_lock(struct irq_data *data) |
486 | { | |
84868424 | 487 | struct sih_agent *agent = irq_data_get_irq_chip_data(data); |
91e3569f | 488 | |
84868424 | 489 | mutex_lock(&agent->irq_lock); |
91e3569f FB |
490 | } |
491 | ||
492 | static void twl4030_sih_bus_sync_unlock(struct irq_data *data) | |
493 | { | |
84868424 FB |
494 | struct sih_agent *agent = irq_data_get_irq_chip_data(data); |
495 | const struct sih *sih = agent->sih; | |
496 | int status; | |
497 | ||
498 | if (agent->imr_change_pending) { | |
499 | union { | |
500 | u32 word; | |
501 | u8 bytes[4]; | |
502 | } imr; | |
503 | ||
c9531227 | 504 | /* byte[0] gets overwritten as we write ... */ |
84868424 FB |
505 | imr.word = cpu_to_le32(agent->imr << 8); |
506 | agent->imr_change_pending = false; | |
507 | ||
508 | /* write the whole mask ... simpler than subsetting it */ | |
509 | status = twl_i2c_write(sih->module, imr.bytes, | |
510 | sih->mask[irq_line].imr_offset, | |
511 | sih->bytes_ixr); | |
512 | if (status) | |
513 | pr_err("twl4030: %s, %s --> %d\n", __func__, | |
514 | "write", status); | |
515 | } | |
91e3569f | 516 | |
2f2a7d5e FB |
517 | if (agent->edge_change) { |
518 | u32 edge_change; | |
519 | u8 bytes[6]; | |
520 | ||
521 | edge_change = agent->edge_change; | |
522 | agent->edge_change = 0; | |
523 | ||
524 | /* | |
525 | * Read, reserving first byte for write scratch. Yes, this | |
526 | * could be cached for some speedup ... but be careful about | |
527 | * any processor on the other IRQ line, EDR registers are | |
528 | * shared. | |
529 | */ | |
530 | status = twl_i2c_read(sih->module, bytes + 1, | |
531 | sih->edr_offset, sih->bytes_edr); | |
532 | if (status) { | |
533 | pr_err("twl4030: %s, %s --> %d\n", __func__, | |
534 | "read", status); | |
535 | return; | |
536 | } | |
537 | ||
538 | /* Modify only the bits we know must change */ | |
539 | while (edge_change) { | |
540 | int i = fls(edge_change) - 1; | |
541 | struct irq_data *idata; | |
542 | int byte = 1 + (i >> 2); | |
543 | int off = (i & 0x3) * 2; | |
544 | unsigned int type; | |
545 | ||
546 | idata = irq_get_irq_data(i + agent->irq_base); | |
547 | ||
548 | bytes[byte] &= ~(0x03 << off); | |
549 | ||
550 | type = irqd_get_trigger_type(idata); | |
551 | if (type & IRQ_TYPE_EDGE_RISING) | |
552 | bytes[byte] |= BIT(off + 1); | |
553 | if (type & IRQ_TYPE_EDGE_FALLING) | |
554 | bytes[byte] |= BIT(off + 0); | |
555 | ||
556 | edge_change &= ~BIT(i); | |
557 | } | |
558 | ||
559 | /* Write */ | |
560 | status = twl_i2c_write(sih->module, bytes, | |
561 | sih->edr_offset, sih->bytes_edr); | |
562 | if (status) | |
563 | pr_err("twl4030: %s, %s --> %d\n", __func__, | |
564 | "write", status); | |
565 | } | |
566 | ||
84868424 | 567 | mutex_unlock(&agent->irq_lock); |
91e3569f FB |
568 | } |
569 | ||
a30d46c0 DB |
570 | static struct irq_chip twl4030_sih_irq_chip = { |
571 | .name = "twl4030", | |
8cd6af29 | 572 | .irq_mask = twl4030_sih_mask, |
845aeab5 MB |
573 | .irq_unmask = twl4030_sih_unmask, |
574 | .irq_set_type = twl4030_sih_set_type, | |
91e3569f FB |
575 | .irq_bus_lock = twl4030_sih_bus_lock, |
576 | .irq_bus_sync_unlock = twl4030_sih_bus_sync_unlock, | |
a30d46c0 DB |
577 | }; |
578 | ||
579 | /*----------------------------------------------------------------------*/ | |
580 | ||
581 | static inline int sih_read_isr(const struct sih *sih) | |
582 | { | |
583 | int status; | |
584 | union { | |
585 | u8 bytes[4]; | |
586 | u32 word; | |
587 | } isr; | |
588 | ||
589 | /* FIXME need retry-on-error ... */ | |
590 | ||
591 | isr.word = 0; | |
fc7b92fc | 592 | status = twl_i2c_read(sih->module, isr.bytes, |
a30d46c0 DB |
593 | sih->mask[irq_line].isr_offset, sih->bytes_ixr); |
594 | ||
595 | return (status < 0) ? status : le32_to_cpu(isr.word); | |
596 | } | |
597 | ||
598 | /* | |
599 | * Generic handler for SIH interrupts ... we "know" this is called | |
600 | * in task context, with IRQs enabled. | |
601 | */ | |
c1e61bcf | 602 | static irqreturn_t handle_twl4030_sih(int irq, void *data) |
a30d46c0 | 603 | { |
d5bb1221 | 604 | struct sih_agent *agent = irq_get_handler_data(irq); |
a30d46c0 DB |
605 | const struct sih *sih = agent->sih; |
606 | int isr; | |
607 | ||
608 | /* reading ISR acks the IRQs, using clear-on-read mode */ | |
a30d46c0 | 609 | isr = sih_read_isr(sih); |
a30d46c0 DB |
610 | |
611 | if (isr < 0) { | |
612 | pr_err("twl4030: %s SIH, read ISR error %d\n", | |
613 | sih->name, isr); | |
614 | /* REVISIT: recover; eventually mask it all, etc */ | |
c1e61bcf | 615 | return IRQ_HANDLED; |
a30d46c0 DB |
616 | } |
617 | ||
618 | while (isr) { | |
619 | irq = fls(isr); | |
620 | irq--; | |
621 | isr &= ~BIT(irq); | |
622 | ||
623 | if (irq < sih->bits) | |
925e853c | 624 | handle_nested_irq(agent->irq_base + irq); |
a30d46c0 DB |
625 | else |
626 | pr_err("twl4030: %s SIH, invalid ISR bit %d\n", | |
627 | sih->name, irq); | |
628 | } | |
c1e61bcf | 629 | return IRQ_HANDLED; |
a30d46c0 DB |
630 | } |
631 | ||
cbcde05e | 632 | /* returns the first IRQ used by this SIH bank, or negative errno */ |
f01b1f90 | 633 | int twl4030_sih_setup(struct device *dev, int module, int irq_base) |
a30d46c0 DB |
634 | { |
635 | int sih_mod; | |
636 | const struct sih *sih = NULL; | |
637 | struct sih_agent *agent; | |
638 | int i, irq; | |
639 | int status = -EINVAL; | |
a30d46c0 DB |
640 | |
641 | /* only support modules with standard clear-on-read for now */ | |
642 | for (sih_mod = 0, sih = sih_modules; | |
1920a61e | 643 | sih_mod < nr_sih_modules; |
a30d46c0 DB |
644 | sih_mod++, sih++) { |
645 | if (sih->module == module && sih->set_cor) { | |
f01b1f90 | 646 | status = 0; |
a30d46c0 DB |
647 | break; |
648 | } | |
649 | } | |
650 | if (status < 0) | |
651 | return status; | |
652 | ||
653 | agent = kzalloc(sizeof *agent, GFP_KERNEL); | |
654 | if (!agent) | |
655 | return -ENOMEM; | |
656 | ||
a30d46c0 DB |
657 | agent->irq_base = irq_base; |
658 | agent->sih = sih; | |
659 | agent->imr = ~0; | |
91e3569f | 660 | mutex_init(&agent->irq_lock); |
a30d46c0 DB |
661 | |
662 | for (i = 0; i < sih->bits; i++) { | |
663 | irq = irq_base + i; | |
664 | ||
91e3569f | 665 | irq_set_chip_data(irq, agent); |
d5bb1221 TG |
666 | irq_set_chip_and_handler(irq, &twl4030_sih_irq_chip, |
667 | handle_edge_irq); | |
b18d1f0f | 668 | irq_set_nested_thread(irq, 1); |
a30d46c0 DB |
669 | activate_irq(irq); |
670 | } | |
671 | ||
a30d46c0 DB |
672 | /* replace generic PIH handler (handle_simple_irq) */ |
673 | irq = sih_mod + twl4030_irq_base; | |
d5bb1221 | 674 | irq_set_handler_data(irq, agent); |
c1e61bcf N |
675 | agent->irq_name = kasprintf(GFP_KERNEL, "twl4030_%s", sih->name); |
676 | status = request_threaded_irq(irq, NULL, handle_twl4030_sih, 0, | |
677 | agent->irq_name ?: sih->name, NULL); | |
a30d46c0 DB |
678 | |
679 | pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", sih->name, | |
f01b1f90 | 680 | irq, irq_base, irq_base + i - 1); |
a30d46c0 | 681 | |
c1e61bcf | 682 | return status < 0 ? status : irq_base; |
a30d46c0 DB |
683 | } |
684 | ||
685 | /* FIXME need a call to reverse twl4030_sih_setup() ... */ | |
686 | ||
a30d46c0 DB |
687 | /*----------------------------------------------------------------------*/ |
688 | ||
689 | /* FIXME pass in which interrupt line we'll use ... */ | |
690 | #define twl_irq_line 0 | |
691 | ||
78518ffa | 692 | int twl4030_init_irq(struct device *dev, int irq_num) |
a30d46c0 DB |
693 | { |
694 | static struct irq_chip twl4030_irq_chip; | |
78518ffa BC |
695 | int irq_base, irq_end, nr_irqs; |
696 | struct device_node *node = dev->of_node; | |
a30d46c0 DB |
697 | |
698 | int status; | |
699 | int i; | |
a30d46c0 | 700 | |
78518ffa BC |
701 | /* |
702 | * TWL core and pwr interrupts must be contiguous because | |
703 | * the hwirqs numbers are defined contiguously from 1 to 15. | |
704 | * Create only one domain for both. | |
705 | */ | |
706 | nr_irqs = TWL4030_PWR_NR_IRQS + TWL4030_CORE_NR_IRQS; | |
707 | ||
708 | irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0); | |
709 | if (IS_ERR_VALUE(irq_base)) { | |
710 | dev_err(dev, "Fail to allocate IRQ descs\n"); | |
711 | return irq_base; | |
712 | } | |
713 | ||
714 | irq_domain_add_legacy(node, nr_irqs, irq_base, 0, | |
715 | &irq_domain_simple_ops, NULL); | |
716 | ||
717 | irq_end = irq_base + TWL4030_CORE_NR_IRQS; | |
718 | ||
a30d46c0 DB |
719 | /* |
720 | * Mask and clear all TWL4030 interrupts since initially we do | |
721 | * not have any TWL4030 module interrupt handlers present | |
722 | */ | |
723 | status = twl4030_init_sih_modules(twl_irq_line); | |
724 | if (status < 0) | |
725 | return status; | |
726 | ||
a30d46c0 DB |
727 | twl4030_irq_base = irq_base; |
728 | ||
cbcde05e FC |
729 | /* |
730 | * install an irq handler for each of the SIH modules; | |
a30d46c0 DB |
731 | * clone dummy irq_chip since PIH can't *do* anything |
732 | */ | |
733 | twl4030_irq_chip = dummy_irq_chip; | |
734 | twl4030_irq_chip.name = "twl4030"; | |
735 | ||
fe212213 | 736 | twl4030_sih_irq_chip.irq_ack = dummy_irq_chip.irq_ack; |
a30d46c0 DB |
737 | |
738 | for (i = irq_base; i < irq_end; i++) { | |
d5bb1221 TG |
739 | irq_set_chip_and_handler(i, &twl4030_irq_chip, |
740 | handle_simple_irq); | |
925e853c | 741 | irq_set_nested_thread(i, 1); |
a30d46c0 DB |
742 | activate_irq(i); |
743 | } | |
f01b1f90 | 744 | |
a30d46c0 | 745 | pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", "PIH", |
f01b1f90 | 746 | irq_num, irq_base, irq_end); |
a30d46c0 DB |
747 | |
748 | /* ... and the PWR_INT module ... */ | |
f01b1f90 | 749 | status = twl4030_sih_setup(dev, TWL4030_MODULE_INT, irq_end); |
a30d46c0 DB |
750 | if (status < 0) { |
751 | pr_err("twl4030: sih_setup PWR INT --> %d\n", status); | |
752 | goto fail; | |
753 | } | |
754 | ||
755 | /* install an irq handler to demultiplex the TWL4030 interrupt */ | |
286f8f3c N |
756 | status = request_threaded_irq(irq_num, NULL, handle_twl4030_pih, |
757 | IRQF_ONESHOT, | |
758 | "TWL4030-PIH", NULL); | |
1cef8e41 RK |
759 | if (status < 0) { |
760 | pr_err("twl4030: could not claim irq%d: %d\n", irq_num, status); | |
761 | goto fail_rqirq; | |
762 | } | |
763 | ||
78518ffa | 764 | return irq_base; |
1cef8e41 RK |
765 | fail_rqirq: |
766 | /* clean up twl4030_sih_setup */ | |
a30d46c0 | 767 | fail: |
925e853c FB |
768 | for (i = irq_base; i < irq_end; i++) { |
769 | irq_set_nested_thread(i, 0); | |
d5bb1221 | 770 | irq_set_chip_and_handler(i, NULL, NULL); |
925e853c | 771 | } |
2f2a7d5e | 772 | |
a30d46c0 DB |
773 | return status; |
774 | } | |
775 | ||
e8deb28c | 776 | int twl4030_exit_irq(void) |
a30d46c0 DB |
777 | { |
778 | /* FIXME undo twl_init_irq() */ | |
779 | if (twl4030_irq_base) { | |
780 | pr_err("twl4030: can't yet clean up IRQs?\n"); | |
781 | return -ENOSYS; | |
782 | } | |
783 | return 0; | |
784 | } | |
1920a61e | 785 | |
e8deb28c | 786 | int twl4030_init_chip_irq(const char *chip) |
1920a61e IK |
787 | { |
788 | if (!strcmp(chip, "twl5031")) { | |
789 | sih_modules = sih_modules_twl5031; | |
790 | nr_sih_modules = ARRAY_SIZE(sih_modules_twl5031); | |
791 | } else { | |
792 | sih_modules = sih_modules_twl4030; | |
793 | nr_sih_modules = ARRAY_SIZE(sih_modules_twl4030); | |
794 | } | |
795 | ||
796 | return 0; | |
797 | } |