Commit | Line | Data |
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e8deb28c B |
1 | /* |
2 | * twl6030-irq.c - TWL6030 irq support | |
3 | * | |
4 | * Copyright (C) 2005-2009 Texas Instruments, Inc. | |
5 | * | |
6 | * Modifications to defer interrupt handling to a kernel thread: | |
7 | * Copyright (C) 2006 MontaVista Software, Inc. | |
8 | * | |
9 | * Based on tlv320aic23.c: | |
10 | * Copyright (c) by Kai Svahn <kai.svahn@nokia.com> | |
11 | * | |
12 | * Code cleanup and modifications to IRQ handler. | |
13 | * by syed khasim <x0khasim@ti.com> | |
14 | * | |
15 | * TWL6030 specific code and IRQ handling changes by | |
16 | * Jagadeesh Bhaskar Pakaravoor <j-pakaravoor@ti.com> | |
17 | * Balaji T K <balajitk@ti.com> | |
18 | * | |
19 | * This program is free software; you can redistribute it and/or modify | |
20 | * it under the terms of the GNU General Public License as published by | |
21 | * the Free Software Foundation; either version 2 of the License, or | |
22 | * (at your option) any later version. | |
23 | * | |
24 | * This program is distributed in the hope that it will be useful, | |
25 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
26 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
27 | * GNU General Public License for more details. | |
28 | * | |
29 | * You should have received a copy of the GNU General Public License | |
30 | * along with this program; if not, write to the Free Software | |
31 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
32 | */ | |
33 | ||
34 | #include <linux/init.h> | |
5d4a357d | 35 | #include <linux/export.h> |
e8deb28c B |
36 | #include <linux/interrupt.h> |
37 | #include <linux/irq.h> | |
38 | #include <linux/kthread.h> | |
39 | #include <linux/i2c/twl.h> | |
72f2e2c7 | 40 | #include <linux/platform_device.h> |
ab2b9260 | 41 | #include <linux/suspend.h> |
e8deb28c | 42 | |
b0b4a7c2 MK |
43 | #include "twl-core.h" |
44 | ||
e8deb28c B |
45 | /* |
46 | * TWL6030 (unlike its predecessors, which had two level interrupt handling) | |
47 | * three interrupt registers INT_STS_A, INT_STS_B and INT_STS_C. | |
48 | * It exposes status bits saying who has raised an interrupt. There are | |
49 | * three mask registers that corresponds to these status registers, that | |
50 | * enables/disables these interrupts. | |
51 | * | |
52 | * We set up IRQs starting at a platform-specified base. An interrupt map table, | |
53 | * specifies mapping between interrupt number and the associated module. | |
54 | * | |
55 | */ | |
56 | ||
57 | static int twl6030_interrupt_mapping[24] = { | |
58 | PWR_INTR_OFFSET, /* Bit 0 PWRON */ | |
59 | PWR_INTR_OFFSET, /* Bit 1 RPWRON */ | |
60 | PWR_INTR_OFFSET, /* Bit 2 BAT_VLOW */ | |
61 | RTC_INTR_OFFSET, /* Bit 3 RTC_ALARM */ | |
62 | RTC_INTR_OFFSET, /* Bit 4 RTC_PERIOD */ | |
63 | HOTDIE_INTR_OFFSET, /* Bit 5 HOT_DIE */ | |
64 | SMPSLDO_INTR_OFFSET, /* Bit 6 VXXX_SHORT */ | |
65 | SMPSLDO_INTR_OFFSET, /* Bit 7 VMMC_SHORT */ | |
66 | ||
67 | SMPSLDO_INTR_OFFSET, /* Bit 8 VUSIM_SHORT */ | |
68 | BATDETECT_INTR_OFFSET, /* Bit 9 BAT */ | |
69 | SIMDETECT_INTR_OFFSET, /* Bit 10 SIM */ | |
70 | MMCDETECT_INTR_OFFSET, /* Bit 11 MMC */ | |
71 | RSV_INTR_OFFSET, /* Bit 12 Reserved */ | |
72 | MADC_INTR_OFFSET, /* Bit 13 GPADC_RT_EOC */ | |
73 | MADC_INTR_OFFSET, /* Bit 14 GPADC_SW_EOC */ | |
74 | GASGAUGE_INTR_OFFSET, /* Bit 15 CC_AUTOCAL */ | |
75 | ||
76 | USBOTG_INTR_OFFSET, /* Bit 16 ID_WKUP */ | |
77 | USBOTG_INTR_OFFSET, /* Bit 17 VBUS_WKUP */ | |
78 | USBOTG_INTR_OFFSET, /* Bit 18 ID */ | |
77b1d3fa | 79 | USB_PRES_INTR_OFFSET, /* Bit 19 VBUS */ |
e8deb28c | 80 | CHARGER_INTR_OFFSET, /* Bit 20 CHRG_CTRL */ |
6523b148 GG |
81 | CHARGERFAULT_INTR_OFFSET, /* Bit 21 EXT_CHRG */ |
82 | CHARGERFAULT_INTR_OFFSET, /* Bit 22 INT_CHRG */ | |
e8deb28c B |
83 | RSV_INTR_OFFSET, /* Bit 23 Reserved */ |
84 | }; | |
85 | /*----------------------------------------------------------------------*/ | |
86 | ||
87 | static unsigned twl6030_irq_base; | |
ab2b9260 TP |
88 | static int twl_irq; |
89 | static bool twl_irq_wake_enabled; | |
e8deb28c B |
90 | |
91 | static struct completion irq_event; | |
ab2b9260 TP |
92 | static atomic_t twl6030_wakeirqs = ATOMIC_INIT(0); |
93 | ||
94 | static int twl6030_irq_pm_notifier(struct notifier_block *notifier, | |
95 | unsigned long pm_event, void *unused) | |
96 | { | |
97 | int chained_wakeups; | |
98 | ||
99 | switch (pm_event) { | |
100 | case PM_SUSPEND_PREPARE: | |
101 | chained_wakeups = atomic_read(&twl6030_wakeirqs); | |
102 | ||
103 | if (chained_wakeups && !twl_irq_wake_enabled) { | |
104 | if (enable_irq_wake(twl_irq)) | |
105 | pr_err("twl6030 IRQ wake enable failed\n"); | |
106 | else | |
107 | twl_irq_wake_enabled = true; | |
108 | } else if (!chained_wakeups && twl_irq_wake_enabled) { | |
109 | disable_irq_wake(twl_irq); | |
110 | twl_irq_wake_enabled = false; | |
111 | } | |
112 | ||
782baa20 | 113 | disable_irq(twl_irq); |
ab2b9260 | 114 | break; |
782baa20 TP |
115 | |
116 | case PM_POST_SUSPEND: | |
117 | enable_irq(twl_irq); | |
118 | break; | |
119 | ||
ab2b9260 TP |
120 | default: |
121 | break; | |
122 | } | |
123 | ||
124 | return NOTIFY_DONE; | |
125 | } | |
126 | ||
127 | static struct notifier_block twl6030_irq_pm_notifier_block = { | |
128 | .notifier_call = twl6030_irq_pm_notifier, | |
129 | }; | |
e8deb28c B |
130 | |
131 | /* | |
132 | * This thread processes interrupts reported by the Primary Interrupt Handler. | |
133 | */ | |
134 | static int twl6030_irq_thread(void *data) | |
135 | { | |
136 | long irq = (long)data; | |
137 | static unsigned i2c_errors; | |
138 | static const unsigned max_i2c_errors = 100; | |
139 | int ret; | |
140 | ||
e8deb28c B |
141 | while (!kthread_should_stop()) { |
142 | int i; | |
143 | union { | |
144 | u8 bytes[4]; | |
145 | u32 int_sts; | |
146 | } sts; | |
147 | ||
148 | /* Wait for IRQ, then read PIH irq status (also blocking) */ | |
149 | wait_for_completion_interruptible(&irq_event); | |
150 | ||
151 | /* read INT_STS_A, B and C in one shot using a burst read */ | |
152 | ret = twl_i2c_read(TWL_MODULE_PIH, sts.bytes, | |
153 | REG_INT_STS_A, 3); | |
154 | if (ret) { | |
155 | pr_warning("twl6030: I2C error %d reading PIH ISR\n", | |
156 | ret); | |
157 | if (++i2c_errors >= max_i2c_errors) { | |
158 | printk(KERN_ERR "Maximum I2C error count" | |
159 | " exceeded. Terminating %s.\n", | |
160 | __func__); | |
161 | break; | |
162 | } | |
163 | complete(&irq_event); | |
164 | continue; | |
165 | } | |
166 | ||
167 | ||
168 | ||
169 | sts.bytes[3] = 0; /* Only 24 bits are valid*/ | |
170 | ||
77b1d3fa HH |
171 | /* |
172 | * Since VBUS status bit is not reliable for VBUS disconnect | |
173 | * use CHARGER VBUS detection status bit instead. | |
174 | */ | |
175 | if (sts.bytes[2] & 0x10) | |
176 | sts.bytes[2] |= 0x08; | |
177 | ||
e8deb28c B |
178 | for (i = 0; sts.int_sts; sts.int_sts >>= 1, i++) { |
179 | local_irq_disable(); | |
180 | if (sts.int_sts & 0x1) { | |
181 | int module_irq = twl6030_irq_base + | |
182 | twl6030_interrupt_mapping[i]; | |
c22435a3 | 183 | generic_handle_irq(module_irq); |
e8deb28c B |
184 | |
185 | } | |
186 | local_irq_enable(); | |
187 | } | |
3f8349e6 NM |
188 | |
189 | /* | |
190 | * NOTE: | |
191 | * Simulation confirms that documentation is wrong w.r.t the | |
192 | * interrupt status clear operation. A single *byte* write to | |
193 | * any one of STS_A to STS_C register results in all three | |
194 | * STS registers being reset. Since it does not matter which | |
195 | * value is written, all three registers are cleared on a | |
196 | * single byte write, so we just use 0x0 to clear. | |
197 | */ | |
198 | ret = twl_i2c_write_u8(TWL_MODULE_PIH, 0x00, REG_INT_STS_A); | |
e8deb28c B |
199 | if (ret) |
200 | pr_warning("twl6030: I2C error in clearing PIH ISR\n"); | |
201 | ||
202 | enable_irq(irq); | |
203 | } | |
204 | ||
205 | return 0; | |
206 | } | |
207 | ||
208 | /* | |
209 | * handle_twl6030_int() is the desc->handle method for the twl6030 interrupt. | |
210 | * This is a chained interrupt, so there is no desc->action method for it. | |
211 | * Now we need to query the interrupt controller in the twl6030 to determine | |
212 | * which module is generating the interrupt request. However, we can't do i2c | |
213 | * transactions in interrupt context, so we must defer that work to a kernel | |
214 | * thread. All we do here is acknowledge and mask the interrupt and wakeup | |
215 | * the kernel thread. | |
216 | */ | |
217 | static irqreturn_t handle_twl6030_pih(int irq, void *devid) | |
218 | { | |
219 | disable_irq_nosync(irq); | |
220 | complete(devid); | |
221 | return IRQ_HANDLED; | |
222 | } | |
223 | ||
224 | /*----------------------------------------------------------------------*/ | |
225 | ||
226 | static inline void activate_irq(int irq) | |
227 | { | |
228 | #ifdef CONFIG_ARM | |
229 | /* ARM requires an extra step to clear IRQ_NOREQUEST, which it | |
230 | * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE. | |
231 | */ | |
232 | set_irq_flags(irq, IRQF_VALID); | |
233 | #else | |
234 | /* same effect on other architectures */ | |
d5bb1221 | 235 | irq_set_noprobe(irq); |
e8deb28c B |
236 | #endif |
237 | } | |
238 | ||
49dcd070 SS |
239 | int twl6030_irq_set_wake(struct irq_data *d, unsigned int on) |
240 | { | |
ab2b9260 TP |
241 | if (on) |
242 | atomic_inc(&twl6030_wakeirqs); | |
243 | else | |
244 | atomic_dec(&twl6030_wakeirqs); | |
49dcd070 | 245 | |
ab2b9260 | 246 | return 0; |
49dcd070 SS |
247 | } |
248 | ||
e8deb28c B |
249 | /*----------------------------------------------------------------------*/ |
250 | ||
251 | static unsigned twl6030_irq_next; | |
252 | ||
253 | /*----------------------------------------------------------------------*/ | |
254 | int twl6030_interrupt_unmask(u8 bit_mask, u8 offset) | |
255 | { | |
256 | int ret; | |
257 | u8 unmask_value; | |
258 | ret = twl_i2c_read_u8(TWL_MODULE_PIH, &unmask_value, | |
259 | REG_INT_STS_A + offset); | |
260 | unmask_value &= (~(bit_mask)); | |
261 | ret |= twl_i2c_write_u8(TWL_MODULE_PIH, unmask_value, | |
262 | REG_INT_STS_A + offset); /* unmask INT_MSK_A/B/C */ | |
263 | return ret; | |
264 | } | |
265 | EXPORT_SYMBOL(twl6030_interrupt_unmask); | |
266 | ||
267 | int twl6030_interrupt_mask(u8 bit_mask, u8 offset) | |
268 | { | |
269 | int ret; | |
270 | u8 mask_value; | |
271 | ret = twl_i2c_read_u8(TWL_MODULE_PIH, &mask_value, | |
272 | REG_INT_STS_A + offset); | |
273 | mask_value |= (bit_mask); | |
274 | ret |= twl_i2c_write_u8(TWL_MODULE_PIH, mask_value, | |
275 | REG_INT_STS_A + offset); /* mask INT_MSK_A/B/C */ | |
276 | return ret; | |
277 | } | |
278 | EXPORT_SYMBOL(twl6030_interrupt_mask); | |
279 | ||
72f2e2c7 | 280 | int twl6030_mmc_card_detect_config(void) |
281 | { | |
282 | int ret; | |
283 | u8 reg_val = 0; | |
284 | ||
285 | /* Unmasking the Card detect Interrupt line for MMC1 from Phoenix */ | |
286 | twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK, | |
287 | REG_INT_MSK_LINE_B); | |
288 | twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK, | |
289 | REG_INT_MSK_STS_B); | |
290 | /* | |
25985edc | 291 | * Initially Configuring MMC_CTRL for receiving interrupts & |
72f2e2c7 | 292 | * Card status on TWL6030 for MMC1 |
293 | */ | |
294 | ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, ®_val, TWL6030_MMCCTRL); | |
295 | if (ret < 0) { | |
296 | pr_err("twl6030: Failed to read MMCCTRL, error %d\n", ret); | |
297 | return ret; | |
298 | } | |
299 | reg_val &= ~VMMC_AUTO_OFF; | |
300 | reg_val |= SW_FC; | |
301 | ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val, TWL6030_MMCCTRL); | |
302 | if (ret < 0) { | |
303 | pr_err("twl6030: Failed to write MMCCTRL, error %d\n", ret); | |
304 | return ret; | |
305 | } | |
306 | ||
307 | /* Configuring PullUp-PullDown register */ | |
308 | ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, ®_val, | |
309 | TWL6030_CFG_INPUT_PUPD3); | |
310 | if (ret < 0) { | |
311 | pr_err("twl6030: Failed to read CFG_INPUT_PUPD3, error %d\n", | |
312 | ret); | |
313 | return ret; | |
314 | } | |
315 | reg_val &= ~(MMC_PU | MMC_PD); | |
316 | ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val, | |
317 | TWL6030_CFG_INPUT_PUPD3); | |
318 | if (ret < 0) { | |
319 | pr_err("twl6030: Failed to write CFG_INPUT_PUPD3, error %d\n", | |
320 | ret); | |
321 | return ret; | |
322 | } | |
323 | return 0; | |
324 | } | |
325 | EXPORT_SYMBOL(twl6030_mmc_card_detect_config); | |
326 | ||
327 | int twl6030_mmc_card_detect(struct device *dev, int slot) | |
328 | { | |
329 | int ret = -EIO; | |
330 | u8 read_reg = 0; | |
331 | struct platform_device *pdev = to_platform_device(dev); | |
332 | ||
333 | if (pdev->id) { | |
334 | /* TWL6030 provide's Card detect support for | |
335 | * only MMC1 controller. | |
336 | */ | |
25985edc | 337 | pr_err("Unknown MMC controller %d in %s\n", pdev->id, __func__); |
72f2e2c7 | 338 | return ret; |
339 | } | |
340 | /* | |
341 | * BIT0 of MMC_CTRL on TWL6030 provides card status for MMC1 | |
342 | * 0 - Card not present ,1 - Card present | |
343 | */ | |
344 | ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &read_reg, | |
345 | TWL6030_MMCCTRL); | |
346 | if (ret >= 0) | |
347 | ret = read_reg & STS_MMC; | |
348 | return ret; | |
349 | } | |
350 | EXPORT_SYMBOL(twl6030_mmc_card_detect); | |
351 | ||
e8deb28c B |
352 | int twl6030_init_irq(int irq_num, unsigned irq_base, unsigned irq_end) |
353 | { | |
354 | ||
355 | int status = 0; | |
356 | int i; | |
357 | struct task_struct *task; | |
358 | int ret; | |
359 | u8 mask[4]; | |
360 | ||
361 | static struct irq_chip twl6030_irq_chip; | |
362 | mask[1] = 0xFF; | |
363 | mask[2] = 0xFF; | |
364 | mask[3] = 0xFF; | |
365 | ret = twl_i2c_write(TWL_MODULE_PIH, &mask[0], | |
366 | REG_INT_MSK_LINE_A, 3); /* MASK ALL INT LINES */ | |
367 | ret = twl_i2c_write(TWL_MODULE_PIH, &mask[0], | |
368 | REG_INT_MSK_STS_A, 3); /* MASK ALL INT STS */ | |
369 | ret = twl_i2c_write(TWL_MODULE_PIH, &mask[0], | |
370 | REG_INT_STS_A, 3); /* clear INT_STS_A,B,C */ | |
371 | ||
372 | twl6030_irq_base = irq_base; | |
373 | ||
374 | /* install an irq handler for each of the modules; | |
375 | * clone dummy irq_chip since PIH can't *do* anything | |
376 | */ | |
377 | twl6030_irq_chip = dummy_irq_chip; | |
378 | twl6030_irq_chip.name = "twl6030"; | |
c45c685c | 379 | twl6030_irq_chip.irq_set_type = NULL; |
49dcd070 | 380 | twl6030_irq_chip.irq_set_wake = twl6030_irq_set_wake; |
e8deb28c B |
381 | |
382 | for (i = irq_base; i < irq_end; i++) { | |
d5bb1221 TG |
383 | irq_set_chip_and_handler(i, &twl6030_irq_chip, |
384 | handle_simple_irq); | |
49dcd070 | 385 | irq_set_chip_data(i, (void *)irq_num); |
e8deb28c B |
386 | activate_irq(i); |
387 | } | |
388 | ||
389 | twl6030_irq_next = i; | |
390 | pr_info("twl6030: %s (irq %d) chaining IRQs %d..%d\n", "PIH", | |
391 | irq_num, irq_base, twl6030_irq_next - 1); | |
392 | ||
393 | /* install an irq handler to demultiplex the TWL6030 interrupt */ | |
394 | init_completion(&irq_event); | |
e8deb28c | 395 | |
f742b96e | 396 | status = request_irq(irq_num, handle_twl6030_pih, 0, |
e8deb28c B |
397 | "TWL6030-PIH", &irq_event); |
398 | if (status < 0) { | |
399 | pr_err("twl6030: could not claim irq%d: %d\n", irq_num, status); | |
400 | goto fail_irq; | |
401 | } | |
862de70c AL |
402 | |
403 | task = kthread_run(twl6030_irq_thread, (void *)irq_num, "twl6030-irq"); | |
404 | if (IS_ERR(task)) { | |
405 | pr_err("twl6030: could not create irq %d thread!\n", irq_num); | |
406 | status = PTR_ERR(task); | |
407 | goto fail_kthread; | |
408 | } | |
ab2b9260 TP |
409 | |
410 | twl_irq = irq_num; | |
411 | register_pm_notifier(&twl6030_irq_pm_notifier_block); | |
e8deb28c | 412 | return status; |
e8deb28c B |
413 | |
414 | fail_kthread: | |
862de70c AL |
415 | free_irq(irq_num, &irq_event); |
416 | ||
417 | fail_irq: | |
e8deb28c | 418 | for (i = irq_base; i < irq_end; i++) |
d5bb1221 | 419 | irq_set_chip_and_handler(i, NULL, NULL); |
e8deb28c B |
420 | return status; |
421 | } | |
422 | ||
423 | int twl6030_exit_irq(void) | |
424 | { | |
ab2b9260 | 425 | unregister_pm_notifier(&twl6030_irq_pm_notifier_block); |
e8deb28c B |
426 | |
427 | if (twl6030_irq_base) { | |
428 | pr_err("twl6030: can't yet clean up IRQs?\n"); | |
429 | return -ENOSYS; | |
430 | } | |
431 | return 0; | |
432 | } | |
433 |