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05c45ca9 RK |
1 | /* |
2 | * linux/drivers/mfd/ucb1x00-core.c | |
3 | * | |
4 | * Copyright (C) 2001 Russell King, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License. | |
9 | * | |
10 | * The UCB1x00 core driver provides basic services for handling IO, | |
11 | * the ADC, interrupts, and accessing registers. It is designed | |
12 | * such that everything goes through this layer, thereby providing | |
13 | * a consistent locking methodology, as well as allowing the drivers | |
14 | * to be used on other non-MCP-enabled hardware platforms. | |
15 | * | |
16 | * Note that all locks are private to this file. Nothing else may | |
17 | * touch them. | |
18 | */ | |
19 | #include <linux/config.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/slab.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/device.h> | |
27 | ||
28 | #include <asm/dma.h> | |
29 | #include <asm/hardware.h> | |
05c45ca9 RK |
30 | |
31 | #include "ucb1x00.h" | |
32 | ||
33 | static DECLARE_MUTEX(ucb1x00_sem); | |
34 | static LIST_HEAD(ucb1x00_drivers); | |
35 | static LIST_HEAD(ucb1x00_devices); | |
36 | ||
37 | /** | |
38 | * ucb1x00_io_set_dir - set IO direction | |
39 | * @ucb: UCB1x00 structure describing chip | |
40 | * @in: bitfield of IO pins to be set as inputs | |
41 | * @out: bitfield of IO pins to be set as outputs | |
42 | * | |
43 | * Set the IO direction of the ten general purpose IO pins on | |
44 | * the UCB1x00 chip. The @in bitfield has priority over the | |
45 | * @out bitfield, in that if you specify a pin as both input | |
46 | * and output, it will end up as an input. | |
47 | * | |
48 | * ucb1x00_enable must have been called to enable the comms | |
49 | * before using this function. | |
50 | * | |
51 | * This function takes a spinlock, disabling interrupts. | |
52 | */ | |
53 | void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int in, unsigned int out) | |
54 | { | |
55 | unsigned long flags; | |
56 | ||
57 | spin_lock_irqsave(&ucb->io_lock, flags); | |
58 | ucb->io_dir |= out; | |
59 | ucb->io_dir &= ~in; | |
60 | ||
61 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); | |
62 | spin_unlock_irqrestore(&ucb->io_lock, flags); | |
63 | } | |
64 | ||
65 | /** | |
66 | * ucb1x00_io_write - set or clear IO outputs | |
67 | * @ucb: UCB1x00 structure describing chip | |
68 | * @set: bitfield of IO pins to set to logic '1' | |
69 | * @clear: bitfield of IO pins to set to logic '0' | |
70 | * | |
71 | * Set the IO output state of the specified IO pins. The value | |
72 | * is retained if the pins are subsequently configured as inputs. | |
73 | * The @clear bitfield has priority over the @set bitfield - | |
74 | * outputs will be cleared. | |
75 | * | |
76 | * ucb1x00_enable must have been called to enable the comms | |
77 | * before using this function. | |
78 | * | |
79 | * This function takes a spinlock, disabling interrupts. | |
80 | */ | |
81 | void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int set, unsigned int clear) | |
82 | { | |
83 | unsigned long flags; | |
84 | ||
85 | spin_lock_irqsave(&ucb->io_lock, flags); | |
86 | ucb->io_out |= set; | |
87 | ucb->io_out &= ~clear; | |
88 | ||
89 | ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); | |
90 | spin_unlock_irqrestore(&ucb->io_lock, flags); | |
91 | } | |
92 | ||
93 | /** | |
94 | * ucb1x00_io_read - read the current state of the IO pins | |
95 | * @ucb: UCB1x00 structure describing chip | |
96 | * | |
97 | * Return a bitfield describing the logic state of the ten | |
98 | * general purpose IO pins. | |
99 | * | |
100 | * ucb1x00_enable must have been called to enable the comms | |
101 | * before using this function. | |
102 | * | |
103 | * This function does not take any semaphores or spinlocks. | |
104 | */ | |
105 | unsigned int ucb1x00_io_read(struct ucb1x00 *ucb) | |
106 | { | |
107 | return ucb1x00_reg_read(ucb, UCB_IO_DATA); | |
108 | } | |
109 | ||
110 | /* | |
111 | * UCB1300 data sheet says we must: | |
112 | * 1. enable ADC => 5us (including reference startup time) | |
113 | * 2. select input => 51*tsibclk => 4.3us | |
114 | * 3. start conversion => 102*tsibclk => 8.5us | |
115 | * (tsibclk = 1/11981000) | |
116 | * Period between SIB 128-bit frames = 10.7us | |
117 | */ | |
118 | ||
119 | /** | |
120 | * ucb1x00_adc_enable - enable the ADC converter | |
121 | * @ucb: UCB1x00 structure describing chip | |
122 | * | |
123 | * Enable the ucb1x00 and ADC converter on the UCB1x00 for use. | |
124 | * Any code wishing to use the ADC converter must call this | |
125 | * function prior to using it. | |
126 | * | |
127 | * This function takes the ADC semaphore to prevent two or more | |
128 | * concurrent uses, and therefore may sleep. As a result, it | |
129 | * can only be called from process context, not interrupt | |
130 | * context. | |
131 | * | |
132 | * You should release the ADC as soon as possible using | |
133 | * ucb1x00_adc_disable. | |
134 | */ | |
135 | void ucb1x00_adc_enable(struct ucb1x00 *ucb) | |
136 | { | |
137 | down(&ucb->adc_sem); | |
138 | ||
139 | ucb->adc_cr |= UCB_ADC_ENA; | |
140 | ||
141 | ucb1x00_enable(ucb); | |
142 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr); | |
143 | } | |
144 | ||
145 | /** | |
146 | * ucb1x00_adc_read - read the specified ADC channel | |
147 | * @ucb: UCB1x00 structure describing chip | |
148 | * @adc_channel: ADC channel mask | |
149 | * @sync: wait for syncronisation pulse. | |
150 | * | |
151 | * Start an ADC conversion and wait for the result. Note that | |
152 | * synchronised ADC conversions (via the ADCSYNC pin) must wait | |
153 | * until the trigger is asserted and the conversion is finished. | |
154 | * | |
155 | * This function currently spins waiting for the conversion to | |
156 | * complete (2 frames max without sync). | |
157 | * | |
158 | * If called for a synchronised ADC conversion, it may sleep | |
159 | * with the ADC semaphore held. | |
160 | */ | |
161 | unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync) | |
162 | { | |
163 | unsigned int val; | |
164 | ||
165 | if (sync) | |
166 | adc_channel |= UCB_ADC_SYNC_ENA; | |
167 | ||
168 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel); | |
169 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel | UCB_ADC_START); | |
170 | ||
171 | for (;;) { | |
172 | val = ucb1x00_reg_read(ucb, UCB_ADC_DATA); | |
173 | if (val & UCB_ADC_DAT_VAL) | |
174 | break; | |
175 | /* yield to other processes */ | |
176 | set_current_state(TASK_INTERRUPTIBLE); | |
177 | schedule_timeout(1); | |
178 | } | |
179 | ||
180 | return UCB_ADC_DAT(val); | |
181 | } | |
182 | ||
183 | /** | |
184 | * ucb1x00_adc_disable - disable the ADC converter | |
185 | * @ucb: UCB1x00 structure describing chip | |
186 | * | |
187 | * Disable the ADC converter and release the ADC semaphore. | |
188 | */ | |
189 | void ucb1x00_adc_disable(struct ucb1x00 *ucb) | |
190 | { | |
191 | ucb->adc_cr &= ~UCB_ADC_ENA; | |
192 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr); | |
193 | ucb1x00_disable(ucb); | |
194 | ||
195 | up(&ucb->adc_sem); | |
196 | } | |
197 | ||
198 | /* | |
199 | * UCB1x00 Interrupt handling. | |
200 | * | |
201 | * The UCB1x00 can generate interrupts when the SIBCLK is stopped. | |
202 | * Since we need to read an internal register, we must re-enable | |
203 | * SIBCLK to talk to the chip. We leave the clock running until | |
204 | * we have finished processing all interrupts from the chip. | |
205 | */ | |
206 | static irqreturn_t ucb1x00_irq(int irqnr, void *devid, struct pt_regs *regs) | |
207 | { | |
208 | struct ucb1x00 *ucb = devid; | |
209 | struct ucb1x00_irq *irq; | |
210 | unsigned int isr, i; | |
211 | ||
212 | ucb1x00_enable(ucb); | |
213 | isr = ucb1x00_reg_read(ucb, UCB_IE_STATUS); | |
214 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, isr); | |
215 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); | |
216 | ||
217 | for (i = 0, irq = ucb->irq_handler; i < 16 && isr; i++, isr >>= 1, irq++) | |
218 | if (isr & 1 && irq->fn) | |
219 | irq->fn(i, irq->devid); | |
220 | ucb1x00_disable(ucb); | |
221 | ||
222 | return IRQ_HANDLED; | |
223 | } | |
224 | ||
225 | /** | |
226 | * ucb1x00_hook_irq - hook a UCB1x00 interrupt | |
227 | * @ucb: UCB1x00 structure describing chip | |
228 | * @idx: interrupt index | |
229 | * @fn: function to call when interrupt is triggered | |
230 | * @devid: device id to pass to interrupt handler | |
231 | * | |
232 | * Hook the specified interrupt. You can only register one handler | |
233 | * for each interrupt source. The interrupt source is not enabled | |
234 | * by this function; use ucb1x00_enable_irq instead. | |
235 | * | |
236 | * Interrupt handlers will be called with other interrupts enabled. | |
237 | * | |
238 | * Returns zero on success, or one of the following errors: | |
239 | * -EINVAL if the interrupt index is invalid | |
240 | * -EBUSY if the interrupt has already been hooked | |
241 | */ | |
242 | int ucb1x00_hook_irq(struct ucb1x00 *ucb, unsigned int idx, void (*fn)(int, void *), void *devid) | |
243 | { | |
244 | struct ucb1x00_irq *irq; | |
245 | int ret = -EINVAL; | |
246 | ||
247 | if (idx < 16) { | |
248 | irq = ucb->irq_handler + idx; | |
249 | ret = -EBUSY; | |
250 | ||
251 | spin_lock_irq(&ucb->lock); | |
252 | if (irq->fn == NULL) { | |
253 | irq->devid = devid; | |
254 | irq->fn = fn; | |
255 | ret = 0; | |
256 | } | |
257 | spin_unlock_irq(&ucb->lock); | |
258 | } | |
259 | return ret; | |
260 | } | |
261 | ||
262 | /** | |
263 | * ucb1x00_enable_irq - enable an UCB1x00 interrupt source | |
264 | * @ucb: UCB1x00 structure describing chip | |
265 | * @idx: interrupt index | |
266 | * @edges: interrupt edges to enable | |
267 | * | |
268 | * Enable the specified interrupt to trigger on %UCB_RISING, | |
269 | * %UCB_FALLING or both edges. The interrupt should have been | |
270 | * hooked by ucb1x00_hook_irq. | |
271 | */ | |
272 | void ucb1x00_enable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges) | |
273 | { | |
274 | unsigned long flags; | |
275 | ||
276 | if (idx < 16) { | |
277 | spin_lock_irqsave(&ucb->lock, flags); | |
278 | ||
279 | ucb1x00_enable(ucb); | |
280 | if (edges & UCB_RISING) { | |
281 | ucb->irq_ris_enbl |= 1 << idx; | |
282 | ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl); | |
283 | } | |
284 | if (edges & UCB_FALLING) { | |
285 | ucb->irq_fal_enbl |= 1 << idx; | |
286 | ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl); | |
287 | } | |
288 | ucb1x00_disable(ucb); | |
289 | spin_unlock_irqrestore(&ucb->lock, flags); | |
290 | } | |
291 | } | |
292 | ||
293 | /** | |
294 | * ucb1x00_disable_irq - disable an UCB1x00 interrupt source | |
295 | * @ucb: UCB1x00 structure describing chip | |
296 | * @edges: interrupt edges to disable | |
297 | * | |
298 | * Disable the specified interrupt triggering on the specified | |
299 | * (%UCB_RISING, %UCB_FALLING or both) edges. | |
300 | */ | |
301 | void ucb1x00_disable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges) | |
302 | { | |
303 | unsigned long flags; | |
304 | ||
305 | if (idx < 16) { | |
306 | spin_lock_irqsave(&ucb->lock, flags); | |
307 | ||
308 | ucb1x00_enable(ucb); | |
309 | if (edges & UCB_RISING) { | |
310 | ucb->irq_ris_enbl &= ~(1 << idx); | |
311 | ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl); | |
312 | } | |
313 | if (edges & UCB_FALLING) { | |
314 | ucb->irq_fal_enbl &= ~(1 << idx); | |
315 | ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl); | |
316 | } | |
317 | ucb1x00_disable(ucb); | |
318 | spin_unlock_irqrestore(&ucb->lock, flags); | |
319 | } | |
320 | } | |
321 | ||
322 | /** | |
323 | * ucb1x00_free_irq - disable and free the specified UCB1x00 interrupt | |
324 | * @ucb: UCB1x00 structure describing chip | |
325 | * @idx: interrupt index | |
326 | * @devid: device id. | |
327 | * | |
328 | * Disable the interrupt source and remove the handler. devid must | |
329 | * match the devid passed when hooking the interrupt. | |
330 | * | |
331 | * Returns zero on success, or one of the following errors: | |
332 | * -EINVAL if the interrupt index is invalid | |
333 | * -ENOENT if devid does not match | |
334 | */ | |
335 | int ucb1x00_free_irq(struct ucb1x00 *ucb, unsigned int idx, void *devid) | |
336 | { | |
337 | struct ucb1x00_irq *irq; | |
338 | int ret; | |
339 | ||
340 | if (idx >= 16) | |
341 | goto bad; | |
342 | ||
343 | irq = ucb->irq_handler + idx; | |
344 | ret = -ENOENT; | |
345 | ||
346 | spin_lock_irq(&ucb->lock); | |
347 | if (irq->devid == devid) { | |
348 | ucb->irq_ris_enbl &= ~(1 << idx); | |
349 | ucb->irq_fal_enbl &= ~(1 << idx); | |
350 | ||
351 | ucb1x00_enable(ucb); | |
352 | ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl); | |
353 | ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl); | |
354 | ucb1x00_disable(ucb); | |
355 | ||
356 | irq->fn = NULL; | |
357 | irq->devid = NULL; | |
358 | ret = 0; | |
359 | } | |
360 | spin_unlock_irq(&ucb->lock); | |
361 | return ret; | |
362 | ||
363 | bad: | |
364 | printk(KERN_ERR "Freeing bad UCB1x00 irq %d\n", idx); | |
365 | return -EINVAL; | |
366 | } | |
367 | ||
368 | static int ucb1x00_add_dev(struct ucb1x00 *ucb, struct ucb1x00_driver *drv) | |
369 | { | |
370 | struct ucb1x00_dev *dev; | |
371 | int ret = -ENOMEM; | |
372 | ||
373 | dev = kmalloc(sizeof(struct ucb1x00_dev), GFP_KERNEL); | |
374 | if (dev) { | |
375 | dev->ucb = ucb; | |
376 | dev->drv = drv; | |
377 | ||
378 | ret = drv->add(dev); | |
379 | ||
380 | if (ret == 0) { | |
381 | list_add(&dev->dev_node, &ucb->devs); | |
382 | list_add(&dev->drv_node, &drv->devs); | |
383 | } else { | |
384 | kfree(dev); | |
385 | } | |
386 | } | |
387 | return ret; | |
388 | } | |
389 | ||
390 | static void ucb1x00_remove_dev(struct ucb1x00_dev *dev) | |
391 | { | |
392 | dev->drv->remove(dev); | |
393 | list_del(&dev->dev_node); | |
394 | list_del(&dev->drv_node); | |
395 | kfree(dev); | |
396 | } | |
397 | ||
398 | /* | |
399 | * Try to probe our interrupt, rather than relying on lots of | |
400 | * hard-coded machine dependencies. For reference, the expected | |
401 | * IRQ mappings are: | |
402 | * | |
403 | * Machine Default IRQ | |
404 | * adsbitsy IRQ_GPCIN4 | |
405 | * cerf IRQ_GPIO_UCB1200_IRQ | |
406 | * flexanet IRQ_GPIO_GUI | |
407 | * freebird IRQ_GPIO_FREEBIRD_UCB1300_IRQ | |
408 | * graphicsclient ADS_EXT_IRQ(8) | |
409 | * graphicsmaster ADS_EXT_IRQ(8) | |
410 | * lart LART_IRQ_UCB1200 | |
411 | * omnimeter IRQ_GPIO23 | |
412 | * pfs168 IRQ_GPIO_UCB1300_IRQ | |
413 | * simpad IRQ_GPIO_UCB1300_IRQ | |
414 | * shannon SHANNON_IRQ_GPIO_IRQ_CODEC | |
415 | * yopy IRQ_GPIO_UCB1200_IRQ | |
416 | */ | |
417 | static int ucb1x00_detect_irq(struct ucb1x00 *ucb) | |
418 | { | |
419 | unsigned long mask; | |
420 | ||
421 | mask = probe_irq_on(); | |
422 | if (!mask) | |
423 | return NO_IRQ; | |
424 | ||
425 | /* | |
426 | * Enable the ADC interrupt. | |
427 | */ | |
428 | ucb1x00_reg_write(ucb, UCB_IE_RIS, UCB_IE_ADC); | |
429 | ucb1x00_reg_write(ucb, UCB_IE_FAL, UCB_IE_ADC); | |
430 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff); | |
431 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); | |
432 | ||
433 | /* | |
434 | * Cause an ADC interrupt. | |
435 | */ | |
436 | ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA); | |
437 | ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | UCB_ADC_START); | |
438 | ||
439 | /* | |
440 | * Wait for the conversion to complete. | |
441 | */ | |
442 | while ((ucb1x00_reg_read(ucb, UCB_ADC_DATA) & UCB_ADC_DAT_VAL) == 0); | |
443 | ucb1x00_reg_write(ucb, UCB_ADC_CR, 0); | |
444 | ||
445 | /* | |
446 | * Disable and clear interrupt. | |
447 | */ | |
448 | ucb1x00_reg_write(ucb, UCB_IE_RIS, 0); | |
449 | ucb1x00_reg_write(ucb, UCB_IE_FAL, 0); | |
450 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff); | |
451 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); | |
452 | ||
453 | /* | |
454 | * Read triggered interrupt. | |
455 | */ | |
456 | return probe_irq_off(mask); | |
457 | } | |
458 | ||
585f5457 NP |
459 | static void ucb1x00_release(struct class_device *dev) |
460 | { | |
461 | struct ucb1x00 *ucb = classdev_to_ucb1x00(dev); | |
462 | kfree(ucb); | |
463 | } | |
464 | ||
465 | static struct class ucb1x00_class = { | |
466 | .name = "ucb1x00", | |
467 | .release = ucb1x00_release, | |
468 | }; | |
469 | ||
05c45ca9 RK |
470 | static int ucb1x00_probe(struct mcp *mcp) |
471 | { | |
472 | struct ucb1x00 *ucb; | |
473 | struct ucb1x00_driver *drv; | |
474 | unsigned int id; | |
475 | int ret = -ENODEV; | |
476 | ||
477 | mcp_enable(mcp); | |
478 | id = mcp_reg_read(mcp, UCB_ID); | |
479 | ||
480 | if (id != UCB_ID_1200 && id != UCB_ID_1300) { | |
481 | printk(KERN_WARNING "UCB1x00 ID not found: %04x\n", id); | |
482 | goto err_disable; | |
483 | } | |
484 | ||
485 | ucb = kmalloc(sizeof(struct ucb1x00), GFP_KERNEL); | |
486 | ret = -ENOMEM; | |
487 | if (!ucb) | |
488 | goto err_disable; | |
489 | ||
490 | memset(ucb, 0, sizeof(struct ucb1x00)); | |
491 | ||
492 | ucb->cdev.class = &ucb1x00_class; | |
493 | ucb->cdev.dev = &mcp->attached_device; | |
494 | strlcpy(ucb->cdev.class_id, "ucb1x00", sizeof(ucb->cdev.class_id)); | |
495 | ||
496 | spin_lock_init(&ucb->lock); | |
497 | spin_lock_init(&ucb->io_lock); | |
498 | sema_init(&ucb->adc_sem, 1); | |
499 | ||
500 | ucb->id = id; | |
501 | ucb->mcp = mcp; | |
502 | ucb->irq = ucb1x00_detect_irq(ucb); | |
503 | if (ucb->irq == NO_IRQ) { | |
504 | printk(KERN_ERR "UCB1x00: IRQ probe failed\n"); | |
505 | ret = -ENODEV; | |
506 | goto err_free; | |
507 | } | |
508 | ||
9ded96f2 RK |
509 | ret = request_irq(ucb->irq, ucb1x00_irq, SA_TRIGGER_RISING, |
510 | "UCB1x00", ucb); | |
05c45ca9 RK |
511 | if (ret) { |
512 | printk(KERN_ERR "ucb1x00: unable to grab irq%d: %d\n", | |
513 | ucb->irq, ret); | |
514 | goto err_free; | |
515 | } | |
516 | ||
05c45ca9 RK |
517 | mcp_set_drvdata(mcp, ucb); |
518 | ||
519 | ret = class_device_register(&ucb->cdev); | |
520 | if (ret) | |
521 | goto err_irq; | |
522 | ||
523 | INIT_LIST_HEAD(&ucb->devs); | |
524 | down(&ucb1x00_sem); | |
525 | list_add(&ucb->node, &ucb1x00_devices); | |
526 | list_for_each_entry(drv, &ucb1x00_drivers, node) { | |
527 | ucb1x00_add_dev(ucb, drv); | |
528 | } | |
529 | up(&ucb1x00_sem); | |
530 | goto out; | |
531 | ||
532 | err_irq: | |
533 | free_irq(ucb->irq, ucb); | |
534 | err_free: | |
535 | kfree(ucb); | |
536 | err_disable: | |
537 | mcp_disable(mcp); | |
538 | out: | |
539 | return ret; | |
540 | } | |
541 | ||
542 | static void ucb1x00_remove(struct mcp *mcp) | |
543 | { | |
544 | struct ucb1x00 *ucb = mcp_get_drvdata(mcp); | |
545 | struct list_head *l, *n; | |
546 | ||
547 | down(&ucb1x00_sem); | |
548 | list_del(&ucb->node); | |
549 | list_for_each_safe(l, n, &ucb->devs) { | |
550 | struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, dev_node); | |
551 | ucb1x00_remove_dev(dev); | |
552 | } | |
553 | up(&ucb1x00_sem); | |
554 | ||
555 | free_irq(ucb->irq, ucb); | |
556 | class_device_unregister(&ucb->cdev); | |
557 | } | |
558 | ||
05c45ca9 RK |
559 | int ucb1x00_register_driver(struct ucb1x00_driver *drv) |
560 | { | |
561 | struct ucb1x00 *ucb; | |
562 | ||
563 | INIT_LIST_HEAD(&drv->devs); | |
564 | down(&ucb1x00_sem); | |
565 | list_add(&drv->node, &ucb1x00_drivers); | |
566 | list_for_each_entry(ucb, &ucb1x00_devices, node) { | |
567 | ucb1x00_add_dev(ucb, drv); | |
568 | } | |
569 | up(&ucb1x00_sem); | |
570 | return 0; | |
571 | } | |
572 | ||
573 | void ucb1x00_unregister_driver(struct ucb1x00_driver *drv) | |
574 | { | |
575 | struct list_head *n, *l; | |
576 | ||
577 | down(&ucb1x00_sem); | |
578 | list_del(&drv->node); | |
579 | list_for_each_safe(l, n, &drv->devs) { | |
580 | struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, drv_node); | |
581 | ucb1x00_remove_dev(dev); | |
582 | } | |
583 | up(&ucb1x00_sem); | |
584 | } | |
585 | ||
586 | static int ucb1x00_suspend(struct mcp *mcp, pm_message_t state) | |
587 | { | |
588 | struct ucb1x00 *ucb = mcp_get_drvdata(mcp); | |
589 | struct ucb1x00_dev *dev; | |
590 | ||
591 | down(&ucb1x00_sem); | |
592 | list_for_each_entry(dev, &ucb->devs, dev_node) { | |
593 | if (dev->drv->suspend) | |
594 | dev->drv->suspend(dev, state); | |
595 | } | |
596 | up(&ucb1x00_sem); | |
597 | return 0; | |
598 | } | |
599 | ||
600 | static int ucb1x00_resume(struct mcp *mcp) | |
601 | { | |
602 | struct ucb1x00 *ucb = mcp_get_drvdata(mcp); | |
603 | struct ucb1x00_dev *dev; | |
604 | ||
605 | down(&ucb1x00_sem); | |
606 | list_for_each_entry(dev, &ucb->devs, dev_node) { | |
607 | if (dev->drv->resume) | |
608 | dev->drv->resume(dev); | |
609 | } | |
610 | up(&ucb1x00_sem); | |
611 | return 0; | |
612 | } | |
613 | ||
614 | static struct mcp_driver ucb1x00_driver = { | |
615 | .drv = { | |
616 | .name = "ucb1x00", | |
617 | }, | |
618 | .probe = ucb1x00_probe, | |
619 | .remove = ucb1x00_remove, | |
620 | .suspend = ucb1x00_suspend, | |
621 | .resume = ucb1x00_resume, | |
622 | }; | |
623 | ||
624 | static int __init ucb1x00_init(void) | |
625 | { | |
626 | int ret = class_register(&ucb1x00_class); | |
627 | if (ret == 0) { | |
628 | ret = mcp_driver_register(&ucb1x00_driver); | |
629 | if (ret) | |
630 | class_unregister(&ucb1x00_class); | |
631 | } | |
632 | return ret; | |
633 | } | |
634 | ||
635 | static void __exit ucb1x00_exit(void) | |
636 | { | |
637 | mcp_driver_unregister(&ucb1x00_driver); | |
638 | class_unregister(&ucb1x00_class); | |
639 | } | |
640 | ||
641 | module_init(ucb1x00_init); | |
642 | module_exit(ucb1x00_exit); | |
643 | ||
05c45ca9 RK |
644 | EXPORT_SYMBOL(ucb1x00_io_set_dir); |
645 | EXPORT_SYMBOL(ucb1x00_io_write); | |
646 | EXPORT_SYMBOL(ucb1x00_io_read); | |
647 | ||
648 | EXPORT_SYMBOL(ucb1x00_adc_enable); | |
649 | EXPORT_SYMBOL(ucb1x00_adc_read); | |
650 | EXPORT_SYMBOL(ucb1x00_adc_disable); | |
651 | ||
652 | EXPORT_SYMBOL(ucb1x00_hook_irq); | |
653 | EXPORT_SYMBOL(ucb1x00_free_irq); | |
654 | EXPORT_SYMBOL(ucb1x00_enable_irq); | |
655 | EXPORT_SYMBOL(ucb1x00_disable_irq); | |
656 | ||
657 | EXPORT_SYMBOL(ucb1x00_register_driver); | |
658 | EXPORT_SYMBOL(ucb1x00_unregister_driver); | |
659 | ||
660 | MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>"); | |
661 | MODULE_DESCRIPTION("UCB1x00 core driver"); | |
662 | MODULE_LICENSE("GPL"); |