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05c45ca9 RK |
1 | /* |
2 | * linux/drivers/mfd/ucb1x00-core.c | |
3 | * | |
4 | * Copyright (C) 2001 Russell King, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License. | |
9 | * | |
10 | * The UCB1x00 core driver provides basic services for handling IO, | |
11 | * the ADC, interrupts, and accessing registers. It is designed | |
12 | * such that everything goes through this layer, thereby providing | |
13 | * a consistent locking methodology, as well as allowing the drivers | |
14 | * to be used on other non-MCP-enabled hardware platforms. | |
15 | * | |
16 | * Note that all locks are private to this file. Nothing else may | |
17 | * touch them. | |
18 | */ | |
05c45ca9 RK |
19 | #include <linux/module.h> |
20 | #include <linux/kernel.h> | |
d43c36dc | 21 | #include <linux/sched.h> |
05c45ca9 RK |
22 | #include <linux/slab.h> |
23 | #include <linux/init.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/interrupt.h> | |
a3364409 | 26 | #include <linux/irq.h> |
05c45ca9 | 27 | #include <linux/device.h> |
a621aaed | 28 | #include <linux/mutex.h> |
c8602edf | 29 | #include <linux/mfd/ucb1x00.h> |
5a09b712 | 30 | #include <linux/pm.h> |
9ca3dc80 | 31 | #include <linux/gpio.h> |
05c45ca9 | 32 | |
a621aaed | 33 | static DEFINE_MUTEX(ucb1x00_mutex); |
05c45ca9 RK |
34 | static LIST_HEAD(ucb1x00_drivers); |
35 | static LIST_HEAD(ucb1x00_devices); | |
36 | ||
37 | /** | |
38 | * ucb1x00_io_set_dir - set IO direction | |
39 | * @ucb: UCB1x00 structure describing chip | |
40 | * @in: bitfield of IO pins to be set as inputs | |
41 | * @out: bitfield of IO pins to be set as outputs | |
42 | * | |
43 | * Set the IO direction of the ten general purpose IO pins on | |
44 | * the UCB1x00 chip. The @in bitfield has priority over the | |
45 | * @out bitfield, in that if you specify a pin as both input | |
46 | * and output, it will end up as an input. | |
47 | * | |
48 | * ucb1x00_enable must have been called to enable the comms | |
49 | * before using this function. | |
50 | * | |
51 | * This function takes a spinlock, disabling interrupts. | |
52 | */ | |
53 | void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int in, unsigned int out) | |
54 | { | |
55 | unsigned long flags; | |
56 | ||
57 | spin_lock_irqsave(&ucb->io_lock, flags); | |
58 | ucb->io_dir |= out; | |
59 | ucb->io_dir &= ~in; | |
60 | ||
61 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); | |
62 | spin_unlock_irqrestore(&ucb->io_lock, flags); | |
63 | } | |
64 | ||
65 | /** | |
66 | * ucb1x00_io_write - set or clear IO outputs | |
67 | * @ucb: UCB1x00 structure describing chip | |
68 | * @set: bitfield of IO pins to set to logic '1' | |
69 | * @clear: bitfield of IO pins to set to logic '0' | |
70 | * | |
71 | * Set the IO output state of the specified IO pins. The value | |
72 | * is retained if the pins are subsequently configured as inputs. | |
73 | * The @clear bitfield has priority over the @set bitfield - | |
74 | * outputs will be cleared. | |
75 | * | |
76 | * ucb1x00_enable must have been called to enable the comms | |
77 | * before using this function. | |
78 | * | |
79 | * This function takes a spinlock, disabling interrupts. | |
80 | */ | |
81 | void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int set, unsigned int clear) | |
82 | { | |
83 | unsigned long flags; | |
84 | ||
85 | spin_lock_irqsave(&ucb->io_lock, flags); | |
86 | ucb->io_out |= set; | |
87 | ucb->io_out &= ~clear; | |
88 | ||
89 | ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); | |
90 | spin_unlock_irqrestore(&ucb->io_lock, flags); | |
91 | } | |
92 | ||
93 | /** | |
94 | * ucb1x00_io_read - read the current state of the IO pins | |
95 | * @ucb: UCB1x00 structure describing chip | |
96 | * | |
97 | * Return a bitfield describing the logic state of the ten | |
98 | * general purpose IO pins. | |
99 | * | |
100 | * ucb1x00_enable must have been called to enable the comms | |
101 | * before using this function. | |
102 | * | |
cae15476 | 103 | * This function does not take any mutexes or spinlocks. |
05c45ca9 RK |
104 | */ |
105 | unsigned int ucb1x00_io_read(struct ucb1x00 *ucb) | |
106 | { | |
107 | return ucb1x00_reg_read(ucb, UCB_IO_DATA); | |
108 | } | |
109 | ||
9ca3dc80 TK |
110 | static void ucb1x00_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
111 | { | |
112 | struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio); | |
113 | unsigned long flags; | |
114 | ||
115 | spin_lock_irqsave(&ucb->io_lock, flags); | |
116 | if (value) | |
117 | ucb->io_out |= 1 << offset; | |
118 | else | |
119 | ucb->io_out &= ~(1 << offset); | |
120 | ||
ed442b67 | 121 | ucb1x00_enable(ucb); |
9ca3dc80 | 122 | ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); |
ed442b67 | 123 | ucb1x00_disable(ucb); |
9ca3dc80 TK |
124 | spin_unlock_irqrestore(&ucb->io_lock, flags); |
125 | } | |
126 | ||
127 | static int ucb1x00_gpio_get(struct gpio_chip *chip, unsigned offset) | |
128 | { | |
129 | struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio); | |
ed442b67 RK |
130 | unsigned val; |
131 | ||
132 | ucb1x00_enable(ucb); | |
133 | val = ucb1x00_reg_read(ucb, UCB_IO_DATA); | |
134 | ucb1x00_disable(ucb); | |
135 | ||
136 | return val & (1 << offset); | |
9ca3dc80 TK |
137 | } |
138 | ||
139 | static int ucb1x00_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
140 | { | |
141 | struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio); | |
142 | unsigned long flags; | |
143 | ||
144 | spin_lock_irqsave(&ucb->io_lock, flags); | |
145 | ucb->io_dir &= ~(1 << offset); | |
ed442b67 | 146 | ucb1x00_enable(ucb); |
9ca3dc80 | 147 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); |
ed442b67 | 148 | ucb1x00_disable(ucb); |
9ca3dc80 TK |
149 | spin_unlock_irqrestore(&ucb->io_lock, flags); |
150 | ||
151 | return 0; | |
152 | } | |
153 | ||
154 | static int ucb1x00_gpio_direction_output(struct gpio_chip *chip, unsigned offset | |
155 | , int value) | |
156 | { | |
157 | struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio); | |
158 | unsigned long flags; | |
c23bb602 | 159 | unsigned old, mask = 1 << offset; |
9ca3dc80 TK |
160 | |
161 | spin_lock_irqsave(&ucb->io_lock, flags); | |
c23bb602 | 162 | old = ucb->io_out; |
9ca3dc80 | 163 | if (value) |
c23bb602 | 164 | ucb->io_out |= mask; |
9ca3dc80 | 165 | else |
c23bb602 RK |
166 | ucb->io_out &= ~mask; |
167 | ||
ed442b67 | 168 | ucb1x00_enable(ucb); |
c23bb602 RK |
169 | if (old != ucb->io_out) |
170 | ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); | |
171 | ||
172 | if (!(ucb->io_dir & mask)) { | |
173 | ucb->io_dir |= mask; | |
174 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); | |
175 | } | |
ed442b67 | 176 | ucb1x00_disable(ucb); |
9ca3dc80 TK |
177 | spin_unlock_irqrestore(&ucb->io_lock, flags); |
178 | ||
179 | return 0; | |
180 | } | |
181 | ||
a3364409 RK |
182 | static int ucb1x00_to_irq(struct gpio_chip *chip, unsigned offset) |
183 | { | |
184 | struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio); | |
185 | ||
186 | return ucb->irq_base > 0 ? ucb->irq_base + offset : -ENXIO; | |
187 | } | |
188 | ||
05c45ca9 RK |
189 | /* |
190 | * UCB1300 data sheet says we must: | |
191 | * 1. enable ADC => 5us (including reference startup time) | |
192 | * 2. select input => 51*tsibclk => 4.3us | |
193 | * 3. start conversion => 102*tsibclk => 8.5us | |
194 | * (tsibclk = 1/11981000) | |
195 | * Period between SIB 128-bit frames = 10.7us | |
196 | */ | |
197 | ||
198 | /** | |
199 | * ucb1x00_adc_enable - enable the ADC converter | |
200 | * @ucb: UCB1x00 structure describing chip | |
201 | * | |
202 | * Enable the ucb1x00 and ADC converter on the UCB1x00 for use. | |
203 | * Any code wishing to use the ADC converter must call this | |
204 | * function prior to using it. | |
205 | * | |
cae15476 | 206 | * This function takes the ADC mutex to prevent two or more |
05c45ca9 RK |
207 | * concurrent uses, and therefore may sleep. As a result, it |
208 | * can only be called from process context, not interrupt | |
209 | * context. | |
210 | * | |
211 | * You should release the ADC as soon as possible using | |
212 | * ucb1x00_adc_disable. | |
213 | */ | |
214 | void ucb1x00_adc_enable(struct ucb1x00 *ucb) | |
215 | { | |
cae15476 | 216 | mutex_lock(&ucb->adc_mutex); |
05c45ca9 RK |
217 | |
218 | ucb->adc_cr |= UCB_ADC_ENA; | |
219 | ||
220 | ucb1x00_enable(ucb); | |
221 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr); | |
222 | } | |
223 | ||
224 | /** | |
225 | * ucb1x00_adc_read - read the specified ADC channel | |
226 | * @ucb: UCB1x00 structure describing chip | |
227 | * @adc_channel: ADC channel mask | |
228 | * @sync: wait for syncronisation pulse. | |
229 | * | |
230 | * Start an ADC conversion and wait for the result. Note that | |
231 | * synchronised ADC conversions (via the ADCSYNC pin) must wait | |
232 | * until the trigger is asserted and the conversion is finished. | |
233 | * | |
234 | * This function currently spins waiting for the conversion to | |
235 | * complete (2 frames max without sync). | |
236 | * | |
237 | * If called for a synchronised ADC conversion, it may sleep | |
cae15476 | 238 | * with the ADC mutex held. |
05c45ca9 RK |
239 | */ |
240 | unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync) | |
241 | { | |
242 | unsigned int val; | |
243 | ||
244 | if (sync) | |
245 | adc_channel |= UCB_ADC_SYNC_ENA; | |
246 | ||
247 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel); | |
248 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel | UCB_ADC_START); | |
249 | ||
250 | for (;;) { | |
251 | val = ucb1x00_reg_read(ucb, UCB_ADC_DATA); | |
252 | if (val & UCB_ADC_DAT_VAL) | |
253 | break; | |
254 | /* yield to other processes */ | |
255 | set_current_state(TASK_INTERRUPTIBLE); | |
256 | schedule_timeout(1); | |
257 | } | |
258 | ||
259 | return UCB_ADC_DAT(val); | |
260 | } | |
261 | ||
262 | /** | |
263 | * ucb1x00_adc_disable - disable the ADC converter | |
264 | * @ucb: UCB1x00 structure describing chip | |
265 | * | |
cae15476 | 266 | * Disable the ADC converter and release the ADC mutex. |
05c45ca9 RK |
267 | */ |
268 | void ucb1x00_adc_disable(struct ucb1x00 *ucb) | |
269 | { | |
270 | ucb->adc_cr &= ~UCB_ADC_ENA; | |
271 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr); | |
272 | ucb1x00_disable(ucb); | |
273 | ||
cae15476 | 274 | mutex_unlock(&ucb->adc_mutex); |
05c45ca9 RK |
275 | } |
276 | ||
277 | /* | |
278 | * UCB1x00 Interrupt handling. | |
279 | * | |
280 | * The UCB1x00 can generate interrupts when the SIBCLK is stopped. | |
281 | * Since we need to read an internal register, we must re-enable | |
282 | * SIBCLK to talk to the chip. We leave the clock running until | |
283 | * we have finished processing all interrupts from the chip. | |
284 | */ | |
a3364409 | 285 | static void ucb1x00_irq(unsigned int irq, struct irq_desc *desc) |
05c45ca9 | 286 | { |
a3364409 | 287 | struct ucb1x00 *ucb = irq_desc_get_handler_data(desc); |
05c45ca9 RK |
288 | unsigned int isr, i; |
289 | ||
290 | ucb1x00_enable(ucb); | |
291 | isr = ucb1x00_reg_read(ucb, UCB_IE_STATUS); | |
292 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, isr); | |
293 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); | |
294 | ||
a3364409 RK |
295 | for (i = 0; i < 16 && isr; i++, isr >>= 1, irq++) |
296 | if (isr & 1) | |
297 | generic_handle_irq(ucb->irq_base + i); | |
05c45ca9 | 298 | ucb1x00_disable(ucb); |
05c45ca9 RK |
299 | } |
300 | ||
a3364409 | 301 | static void ucb1x00_irq_update(struct ucb1x00 *ucb, unsigned mask) |
05c45ca9 | 302 | { |
a3364409 RK |
303 | ucb1x00_enable(ucb); |
304 | if (ucb->irq_ris_enbl & mask) | |
305 | ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl & | |
306 | ucb->irq_mask); | |
307 | if (ucb->irq_fal_enbl & mask) | |
308 | ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl & | |
309 | ucb->irq_mask); | |
310 | ucb1x00_disable(ucb); | |
05c45ca9 RK |
311 | } |
312 | ||
a3364409 | 313 | static void ucb1x00_irq_noop(struct irq_data *data) |
05c45ca9 | 314 | { |
05c45ca9 RK |
315 | } |
316 | ||
a3364409 | 317 | static void ucb1x00_irq_mask(struct irq_data *data) |
05c45ca9 | 318 | { |
a3364409 RK |
319 | struct ucb1x00 *ucb = irq_data_get_irq_chip_data(data); |
320 | unsigned mask = 1 << (data->irq - ucb->irq_base); | |
05c45ca9 | 321 | |
a3364409 RK |
322 | raw_spin_lock(&ucb->irq_lock); |
323 | ucb->irq_mask &= ~mask; | |
324 | ucb1x00_irq_update(ucb, mask); | |
325 | raw_spin_unlock(&ucb->irq_lock); | |
05c45ca9 RK |
326 | } |
327 | ||
a3364409 | 328 | static void ucb1x00_irq_unmask(struct irq_data *data) |
05c45ca9 | 329 | { |
a3364409 RK |
330 | struct ucb1x00 *ucb = irq_data_get_irq_chip_data(data); |
331 | unsigned mask = 1 << (data->irq - ucb->irq_base); | |
05c45ca9 | 332 | |
a3364409 RK |
333 | raw_spin_lock(&ucb->irq_lock); |
334 | ucb->irq_mask |= mask; | |
335 | ucb1x00_irq_update(ucb, mask); | |
336 | raw_spin_unlock(&ucb->irq_lock); | |
337 | } | |
05c45ca9 | 338 | |
a3364409 RK |
339 | static int ucb1x00_irq_set_type(struct irq_data *data, unsigned int type) |
340 | { | |
341 | struct ucb1x00 *ucb = irq_data_get_irq_chip_data(data); | |
342 | unsigned mask = 1 << (data->irq - ucb->irq_base); | |
05c45ca9 | 343 | |
a3364409 RK |
344 | raw_spin_lock(&ucb->irq_lock); |
345 | if (type & IRQ_TYPE_EDGE_RISING) | |
346 | ucb->irq_ris_enbl |= mask; | |
347 | else | |
348 | ucb->irq_ris_enbl &= ~mask; | |
05c45ca9 | 349 | |
a3364409 RK |
350 | if (type & IRQ_TYPE_EDGE_FALLING) |
351 | ucb->irq_fal_enbl |= mask; | |
352 | else | |
353 | ucb->irq_fal_enbl &= ~mask; | |
354 | if (ucb->irq_mask & mask) { | |
355 | ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl & | |
356 | ucb->irq_mask); | |
357 | ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl & | |
358 | ucb->irq_mask); | |
05c45ca9 | 359 | } |
a3364409 | 360 | raw_spin_unlock(&ucb->irq_lock); |
05c45ca9 | 361 | |
a3364409 | 362 | return 0; |
05c45ca9 RK |
363 | } |
364 | ||
a3364409 RK |
365 | static struct irq_chip ucb1x00_irqchip = { |
366 | .name = "ucb1x00", | |
367 | .irq_ack = ucb1x00_irq_noop, | |
368 | .irq_mask = ucb1x00_irq_mask, | |
369 | .irq_unmask = ucb1x00_irq_unmask, | |
370 | .irq_set_type = ucb1x00_irq_set_type, | |
371 | }; | |
372 | ||
05c45ca9 RK |
373 | static int ucb1x00_add_dev(struct ucb1x00 *ucb, struct ucb1x00_driver *drv) |
374 | { | |
375 | struct ucb1x00_dev *dev; | |
376 | int ret = -ENOMEM; | |
377 | ||
378 | dev = kmalloc(sizeof(struct ucb1x00_dev), GFP_KERNEL); | |
379 | if (dev) { | |
380 | dev->ucb = ucb; | |
381 | dev->drv = drv; | |
382 | ||
383 | ret = drv->add(dev); | |
384 | ||
385 | if (ret == 0) { | |
65b539bb RK |
386 | list_add_tail(&dev->dev_node, &ucb->devs); |
387 | list_add_tail(&dev->drv_node, &drv->devs); | |
05c45ca9 RK |
388 | } else { |
389 | kfree(dev); | |
390 | } | |
391 | } | |
392 | return ret; | |
393 | } | |
394 | ||
395 | static void ucb1x00_remove_dev(struct ucb1x00_dev *dev) | |
396 | { | |
397 | dev->drv->remove(dev); | |
398 | list_del(&dev->dev_node); | |
399 | list_del(&dev->drv_node); | |
400 | kfree(dev); | |
401 | } | |
402 | ||
403 | /* | |
404 | * Try to probe our interrupt, rather than relying on lots of | |
405 | * hard-coded machine dependencies. For reference, the expected | |
406 | * IRQ mappings are: | |
407 | * | |
408 | * Machine Default IRQ | |
409 | * adsbitsy IRQ_GPCIN4 | |
410 | * cerf IRQ_GPIO_UCB1200_IRQ | |
411 | * flexanet IRQ_GPIO_GUI | |
412 | * freebird IRQ_GPIO_FREEBIRD_UCB1300_IRQ | |
413 | * graphicsclient ADS_EXT_IRQ(8) | |
414 | * graphicsmaster ADS_EXT_IRQ(8) | |
415 | * lart LART_IRQ_UCB1200 | |
416 | * omnimeter IRQ_GPIO23 | |
417 | * pfs168 IRQ_GPIO_UCB1300_IRQ | |
418 | * simpad IRQ_GPIO_UCB1300_IRQ | |
419 | * shannon SHANNON_IRQ_GPIO_IRQ_CODEC | |
420 | * yopy IRQ_GPIO_UCB1200_IRQ | |
421 | */ | |
422 | static int ucb1x00_detect_irq(struct ucb1x00 *ucb) | |
423 | { | |
424 | unsigned long mask; | |
425 | ||
426 | mask = probe_irq_on(); | |
cfc73656 IM |
427 | if (!mask) { |
428 | probe_irq_off(mask); | |
05c45ca9 | 429 | return NO_IRQ; |
cfc73656 | 430 | } |
05c45ca9 RK |
431 | |
432 | /* | |
433 | * Enable the ADC interrupt. | |
434 | */ | |
435 | ucb1x00_reg_write(ucb, UCB_IE_RIS, UCB_IE_ADC); | |
436 | ucb1x00_reg_write(ucb, UCB_IE_FAL, UCB_IE_ADC); | |
437 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff); | |
438 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); | |
439 | ||
440 | /* | |
441 | * Cause an ADC interrupt. | |
442 | */ | |
443 | ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA); | |
444 | ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | UCB_ADC_START); | |
445 | ||
446 | /* | |
447 | * Wait for the conversion to complete. | |
448 | */ | |
449 | while ((ucb1x00_reg_read(ucb, UCB_ADC_DATA) & UCB_ADC_DAT_VAL) == 0); | |
450 | ucb1x00_reg_write(ucb, UCB_ADC_CR, 0); | |
451 | ||
452 | /* | |
453 | * Disable and clear interrupt. | |
454 | */ | |
455 | ucb1x00_reg_write(ucb, UCB_IE_RIS, 0); | |
456 | ucb1x00_reg_write(ucb, UCB_IE_FAL, 0); | |
457 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff); | |
458 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); | |
459 | ||
460 | /* | |
461 | * Read triggered interrupt. | |
462 | */ | |
463 | return probe_irq_off(mask); | |
464 | } | |
465 | ||
0c55445f | 466 | static void ucb1x00_release(struct device *dev) |
585f5457 NP |
467 | { |
468 | struct ucb1x00 *ucb = classdev_to_ucb1x00(dev); | |
469 | kfree(ucb); | |
470 | } | |
471 | ||
472 | static struct class ucb1x00_class = { | |
473 | .name = "ucb1x00", | |
0c55445f | 474 | .dev_release = ucb1x00_release, |
585f5457 NP |
475 | }; |
476 | ||
05c45ca9 RK |
477 | static int ucb1x00_probe(struct mcp *mcp) |
478 | { | |
2f7510c6 | 479 | struct ucb1x00_plat_data *pdata = mcp->attached_device.platform_data; |
05c45ca9 | 480 | struct ucb1x00_driver *drv; |
2f7510c6 | 481 | struct ucb1x00 *ucb; |
a3364409 | 482 | unsigned id, i, irq_base; |
05c45ca9 RK |
483 | int ret = -ENODEV; |
484 | ||
2f7510c6 RK |
485 | /* Tell the platform to deassert the UCB1x00 reset */ |
486 | if (pdata && pdata->reset) | |
487 | pdata->reset(UCB_RST_PROBE); | |
488 | ||
05c45ca9 RK |
489 | mcp_enable(mcp); |
490 | id = mcp_reg_read(mcp, UCB_ID); | |
2b4d9d2b | 491 | mcp_disable(mcp); |
05c45ca9 | 492 | |
65f2e753 RK |
493 | if (id != UCB_ID_1200 && id != UCB_ID_1300 && id != UCB_ID_TC35143) { |
494 | printk(KERN_WARNING "UCB1x00 ID not found: %04x\n", id); | |
2b4d9d2b | 495 | goto out; |
05c45ca9 RK |
496 | } |
497 | ||
dd00cc48 | 498 | ucb = kzalloc(sizeof(struct ucb1x00), GFP_KERNEL); |
05c45ca9 RK |
499 | ret = -ENOMEM; |
500 | if (!ucb) | |
2b4d9d2b | 501 | goto out; |
05c45ca9 | 502 | |
f5ae587f | 503 | device_initialize(&ucb->dev); |
0c55445f TJ |
504 | ucb->dev.class = &ucb1x00_class; |
505 | ucb->dev.parent = &mcp->attached_device; | |
65f2e753 | 506 | dev_set_name(&ucb->dev, "ucb1x00"); |
05c45ca9 | 507 | |
a3364409 | 508 | raw_spin_lock_init(&ucb->irq_lock); |
05c45ca9 | 509 | spin_lock_init(&ucb->io_lock); |
cae15476 | 510 | mutex_init(&ucb->adc_mutex); |
05c45ca9 | 511 | |
65f2e753 | 512 | ucb->id = id; |
05c45ca9 | 513 | ucb->mcp = mcp; |
f5ae587f RK |
514 | |
515 | ret = device_add(&ucb->dev); | |
516 | if (ret) | |
517 | goto err_dev_add; | |
518 | ||
2b4d9d2b | 519 | ucb1x00_enable(ucb); |
05c45ca9 | 520 | ucb->irq = ucb1x00_detect_irq(ucb); |
2b4d9d2b | 521 | ucb1x00_disable(ucb); |
05c45ca9 | 522 | if (ucb->irq == NO_IRQ) { |
f5ae587f | 523 | dev_err(&ucb->dev, "IRQ probe failed\n"); |
05c45ca9 | 524 | ret = -ENODEV; |
f5ae587f | 525 | goto err_no_irq; |
05c45ca9 RK |
526 | } |
527 | ||
9ca3dc80 | 528 | ucb->gpio.base = -1; |
a3364409 RK |
529 | irq_base = pdata ? pdata->irq_base : 0; |
530 | ucb->irq_base = irq_alloc_descs(-1, irq_base, 16, -1); | |
531 | if (ucb->irq_base < 0) { | |
532 | dev_err(&ucb->dev, "unable to allocate 16 irqs: %d\n", | |
533 | ucb->irq_base); | |
534 | goto err_irq_alloc; | |
535 | } | |
536 | ||
537 | for (i = 0; i < 16; i++) { | |
538 | unsigned irq = ucb->irq_base + i; | |
539 | ||
540 | irq_set_chip_and_handler(irq, &ucb1x00_irqchip, handle_edge_irq); | |
541 | irq_set_chip_data(irq, ucb); | |
542 | set_irq_flags(irq, IRQF_VALID | IRQ_NOREQUEST); | |
543 | } | |
544 | ||
545 | irq_set_irq_type(ucb->irq, IRQ_TYPE_EDGE_RISING); | |
546 | irq_set_handler_data(ucb->irq, ucb); | |
547 | irq_set_chained_handler(ucb->irq, ucb1x00_irq); | |
548 | ||
abe06082 | 549 | if (pdata && pdata->gpio_base) { |
9ca3dc80 | 550 | ucb->gpio.label = dev_name(&ucb->dev); |
7655b2ac RK |
551 | ucb->gpio.dev = &ucb->dev; |
552 | ucb->gpio.owner = THIS_MODULE; | |
abe06082 | 553 | ucb->gpio.base = pdata->gpio_base; |
9ca3dc80 TK |
554 | ucb->gpio.ngpio = 10; |
555 | ucb->gpio.set = ucb1x00_gpio_set; | |
556 | ucb->gpio.get = ucb1x00_gpio_get; | |
557 | ucb->gpio.direction_input = ucb1x00_gpio_direction_input; | |
558 | ucb->gpio.direction_output = ucb1x00_gpio_direction_output; | |
a3364409 | 559 | ucb->gpio.to_irq = ucb1x00_to_irq; |
9ca3dc80 TK |
560 | ret = gpiochip_add(&ucb->gpio); |
561 | if (ret) | |
f5ae587f | 562 | goto err_gpio_add; |
9ca3dc80 TK |
563 | } else |
564 | dev_info(&ucb->dev, "gpio_base not set so no gpiolib support"); | |
565 | ||
05c45ca9 RK |
566 | mcp_set_drvdata(mcp, ucb); |
567 | ||
05c45ca9 | 568 | INIT_LIST_HEAD(&ucb->devs); |
a621aaed | 569 | mutex_lock(&ucb1x00_mutex); |
65b539bb | 570 | list_add_tail(&ucb->node, &ucb1x00_devices); |
05c45ca9 RK |
571 | list_for_each_entry(drv, &ucb1x00_drivers, node) { |
572 | ucb1x00_add_dev(ucb, drv); | |
573 | } | |
a621aaed | 574 | mutex_unlock(&ucb1x00_mutex); |
9ca3dc80 | 575 | |
2f7510c6 | 576 | return ret; |
05c45ca9 | 577 | |
f5ae587f | 578 | err_gpio_add: |
a3364409 RK |
579 | irq_set_chained_handler(ucb->irq, NULL); |
580 | err_irq_alloc: | |
581 | if (ucb->irq_base > 0) | |
582 | irq_free_descs(ucb->irq_base, 16); | |
f5ae587f RK |
583 | err_no_irq: |
584 | device_del(&ucb->dev); | |
585 | err_dev_add: | |
586 | put_device(&ucb->dev); | |
05c45ca9 | 587 | out: |
2f7510c6 RK |
588 | if (pdata && pdata->reset) |
589 | pdata->reset(UCB_RST_PROBE_FAIL); | |
05c45ca9 RK |
590 | return ret; |
591 | } | |
592 | ||
593 | static void ucb1x00_remove(struct mcp *mcp) | |
594 | { | |
2f7510c6 | 595 | struct ucb1x00_plat_data *pdata = mcp->attached_device.platform_data; |
05c45ca9 RK |
596 | struct ucb1x00 *ucb = mcp_get_drvdata(mcp); |
597 | struct list_head *l, *n; | |
9ca3dc80 | 598 | int ret; |
05c45ca9 | 599 | |
a621aaed | 600 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
601 | list_del(&ucb->node); |
602 | list_for_each_safe(l, n, &ucb->devs) { | |
603 | struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, dev_node); | |
604 | ucb1x00_remove_dev(dev); | |
605 | } | |
a621aaed | 606 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 | 607 | |
9ca3dc80 TK |
608 | if (ucb->gpio.base != -1) { |
609 | ret = gpiochip_remove(&ucb->gpio); | |
610 | if (ret) | |
611 | dev_err(&ucb->dev, "Can't remove gpio chip: %d\n", ret); | |
612 | } | |
613 | ||
a3364409 RK |
614 | irq_set_chained_handler(ucb->irq, NULL); |
615 | irq_free_descs(ucb->irq_base, 16); | |
0c55445f | 616 | device_unregister(&ucb->dev); |
2f7510c6 RK |
617 | |
618 | if (pdata && pdata->reset) | |
619 | pdata->reset(UCB_RST_REMOVE); | |
05c45ca9 RK |
620 | } |
621 | ||
05c45ca9 RK |
622 | int ucb1x00_register_driver(struct ucb1x00_driver *drv) |
623 | { | |
624 | struct ucb1x00 *ucb; | |
625 | ||
626 | INIT_LIST_HEAD(&drv->devs); | |
a621aaed | 627 | mutex_lock(&ucb1x00_mutex); |
65b539bb | 628 | list_add_tail(&drv->node, &ucb1x00_drivers); |
05c45ca9 RK |
629 | list_for_each_entry(ucb, &ucb1x00_devices, node) { |
630 | ucb1x00_add_dev(ucb, drv); | |
631 | } | |
a621aaed | 632 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
633 | return 0; |
634 | } | |
635 | ||
636 | void ucb1x00_unregister_driver(struct ucb1x00_driver *drv) | |
637 | { | |
638 | struct list_head *n, *l; | |
639 | ||
a621aaed | 640 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
641 | list_del(&drv->node); |
642 | list_for_each_safe(l, n, &drv->devs) { | |
643 | struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, drv_node); | |
644 | ucb1x00_remove_dev(dev); | |
645 | } | |
a621aaed | 646 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
647 | } |
648 | ||
5a09b712 | 649 | static int ucb1x00_suspend(struct device *dev) |
05c45ca9 | 650 | { |
5a09b712 RK |
651 | struct ucb1x00 *ucb = dev_get_drvdata(dev); |
652 | struct ucb1x00_dev *udev; | |
05c45ca9 | 653 | |
a621aaed | 654 | mutex_lock(&ucb1x00_mutex); |
5a09b712 RK |
655 | list_for_each_entry(udev, &ucb->devs, dev_node) { |
656 | if (udev->drv->suspend) | |
657 | udev->drv->suspend(udev); | |
05c45ca9 | 658 | } |
a621aaed | 659 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
660 | return 0; |
661 | } | |
662 | ||
5a09b712 | 663 | static int ucb1x00_resume(struct device *dev) |
05c45ca9 | 664 | { |
5a09b712 RK |
665 | struct ucb1x00 *ucb = dev_get_drvdata(dev); |
666 | struct ucb1x00_dev *udev; | |
05c45ca9 | 667 | |
ed442b67 | 668 | ucb1x00_enable(ucb); |
2e95e51e | 669 | ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); |
9ca3dc80 | 670 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); |
ed442b67 | 671 | ucb1x00_disable(ucb); |
a621aaed | 672 | mutex_lock(&ucb1x00_mutex); |
5a09b712 RK |
673 | list_for_each_entry(udev, &ucb->devs, dev_node) { |
674 | if (udev->drv->resume) | |
675 | udev->drv->resume(udev); | |
05c45ca9 | 676 | } |
a621aaed | 677 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
678 | return 0; |
679 | } | |
680 | ||
5a09b712 RK |
681 | static const struct dev_pm_ops ucb1x00_pm_ops = { |
682 | SET_SYSTEM_SLEEP_PM_OPS(ucb1x00_suspend, ucb1x00_resume) | |
683 | }; | |
684 | ||
05c45ca9 RK |
685 | static struct mcp_driver ucb1x00_driver = { |
686 | .drv = { | |
687 | .name = "ucb1x00", | |
ddb1e04a | 688 | .owner = THIS_MODULE, |
5a09b712 | 689 | .pm = &ucb1x00_pm_ops, |
05c45ca9 RK |
690 | }, |
691 | .probe = ucb1x00_probe, | |
692 | .remove = ucb1x00_remove, | |
05c45ca9 RK |
693 | }; |
694 | ||
695 | static int __init ucb1x00_init(void) | |
696 | { | |
697 | int ret = class_register(&ucb1x00_class); | |
698 | if (ret == 0) { | |
699 | ret = mcp_driver_register(&ucb1x00_driver); | |
700 | if (ret) | |
701 | class_unregister(&ucb1x00_class); | |
702 | } | |
703 | return ret; | |
704 | } | |
705 | ||
706 | static void __exit ucb1x00_exit(void) | |
707 | { | |
708 | mcp_driver_unregister(&ucb1x00_driver); | |
709 | class_unregister(&ucb1x00_class); | |
710 | } | |
711 | ||
712 | module_init(ucb1x00_init); | |
713 | module_exit(ucb1x00_exit); | |
714 | ||
05c45ca9 RK |
715 | EXPORT_SYMBOL(ucb1x00_io_set_dir); |
716 | EXPORT_SYMBOL(ucb1x00_io_write); | |
717 | EXPORT_SYMBOL(ucb1x00_io_read); | |
718 | ||
719 | EXPORT_SYMBOL(ucb1x00_adc_enable); | |
720 | EXPORT_SYMBOL(ucb1x00_adc_read); | |
721 | EXPORT_SYMBOL(ucb1x00_adc_disable); | |
722 | ||
05c45ca9 RK |
723 | EXPORT_SYMBOL(ucb1x00_register_driver); |
724 | EXPORT_SYMBOL(ucb1x00_unregister_driver); | |
725 | ||
ddb1e04a | 726 | MODULE_ALIAS("mcp:ucb1x00"); |
05c45ca9 RK |
727 | MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>"); |
728 | MODULE_DESCRIPTION("UCB1x00 core driver"); | |
729 | MODULE_LICENSE("GPL"); |