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05c45ca9 RK |
1 | /* |
2 | * linux/drivers/mfd/ucb1x00-core.c | |
3 | * | |
4 | * Copyright (C) 2001 Russell King, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License. | |
9 | * | |
10 | * The UCB1x00 core driver provides basic services for handling IO, | |
11 | * the ADC, interrupts, and accessing registers. It is designed | |
12 | * such that everything goes through this layer, thereby providing | |
13 | * a consistent locking methodology, as well as allowing the drivers | |
14 | * to be used on other non-MCP-enabled hardware platforms. | |
15 | * | |
16 | * Note that all locks are private to this file. Nothing else may | |
17 | * touch them. | |
18 | */ | |
05c45ca9 RK |
19 | #include <linux/module.h> |
20 | #include <linux/kernel.h> | |
d43c36dc | 21 | #include <linux/sched.h> |
05c45ca9 RK |
22 | #include <linux/slab.h> |
23 | #include <linux/init.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/device.h> | |
a621aaed | 27 | #include <linux/mutex.h> |
c8602edf | 28 | #include <linux/mfd/ucb1x00.h> |
9ca3dc80 | 29 | #include <linux/gpio.h> |
2c08583c | 30 | #include <linux/semaphore.h> |
05c45ca9 | 31 | |
a621aaed | 32 | static DEFINE_MUTEX(ucb1x00_mutex); |
05c45ca9 RK |
33 | static LIST_HEAD(ucb1x00_drivers); |
34 | static LIST_HEAD(ucb1x00_devices); | |
35 | ||
36 | /** | |
37 | * ucb1x00_io_set_dir - set IO direction | |
38 | * @ucb: UCB1x00 structure describing chip | |
39 | * @in: bitfield of IO pins to be set as inputs | |
40 | * @out: bitfield of IO pins to be set as outputs | |
41 | * | |
42 | * Set the IO direction of the ten general purpose IO pins on | |
43 | * the UCB1x00 chip. The @in bitfield has priority over the | |
44 | * @out bitfield, in that if you specify a pin as both input | |
45 | * and output, it will end up as an input. | |
46 | * | |
47 | * ucb1x00_enable must have been called to enable the comms | |
48 | * before using this function. | |
49 | * | |
50 | * This function takes a spinlock, disabling interrupts. | |
51 | */ | |
52 | void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int in, unsigned int out) | |
53 | { | |
54 | unsigned long flags; | |
55 | ||
56 | spin_lock_irqsave(&ucb->io_lock, flags); | |
57 | ucb->io_dir |= out; | |
58 | ucb->io_dir &= ~in; | |
59 | ||
60 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); | |
61 | spin_unlock_irqrestore(&ucb->io_lock, flags); | |
62 | } | |
63 | ||
64 | /** | |
65 | * ucb1x00_io_write - set or clear IO outputs | |
66 | * @ucb: UCB1x00 structure describing chip | |
67 | * @set: bitfield of IO pins to set to logic '1' | |
68 | * @clear: bitfield of IO pins to set to logic '0' | |
69 | * | |
70 | * Set the IO output state of the specified IO pins. The value | |
71 | * is retained if the pins are subsequently configured as inputs. | |
72 | * The @clear bitfield has priority over the @set bitfield - | |
73 | * outputs will be cleared. | |
74 | * | |
75 | * ucb1x00_enable must have been called to enable the comms | |
76 | * before using this function. | |
77 | * | |
78 | * This function takes a spinlock, disabling interrupts. | |
79 | */ | |
80 | void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int set, unsigned int clear) | |
81 | { | |
82 | unsigned long flags; | |
83 | ||
84 | spin_lock_irqsave(&ucb->io_lock, flags); | |
85 | ucb->io_out |= set; | |
86 | ucb->io_out &= ~clear; | |
87 | ||
88 | ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); | |
89 | spin_unlock_irqrestore(&ucb->io_lock, flags); | |
90 | } | |
91 | ||
92 | /** | |
93 | * ucb1x00_io_read - read the current state of the IO pins | |
94 | * @ucb: UCB1x00 structure describing chip | |
95 | * | |
96 | * Return a bitfield describing the logic state of the ten | |
97 | * general purpose IO pins. | |
98 | * | |
99 | * ucb1x00_enable must have been called to enable the comms | |
100 | * before using this function. | |
101 | * | |
102 | * This function does not take any semaphores or spinlocks. | |
103 | */ | |
104 | unsigned int ucb1x00_io_read(struct ucb1x00 *ucb) | |
105 | { | |
106 | return ucb1x00_reg_read(ucb, UCB_IO_DATA); | |
107 | } | |
108 | ||
9ca3dc80 TK |
109 | static void ucb1x00_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
110 | { | |
111 | struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio); | |
112 | unsigned long flags; | |
113 | ||
114 | spin_lock_irqsave(&ucb->io_lock, flags); | |
115 | if (value) | |
116 | ucb->io_out |= 1 << offset; | |
117 | else | |
118 | ucb->io_out &= ~(1 << offset); | |
119 | ||
120 | ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); | |
121 | spin_unlock_irqrestore(&ucb->io_lock, flags); | |
122 | } | |
123 | ||
124 | static int ucb1x00_gpio_get(struct gpio_chip *chip, unsigned offset) | |
125 | { | |
126 | struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio); | |
127 | return ucb1x00_reg_read(ucb, UCB_IO_DATA) & (1 << offset); | |
128 | } | |
129 | ||
130 | static int ucb1x00_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
131 | { | |
132 | struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio); | |
133 | unsigned long flags; | |
134 | ||
135 | spin_lock_irqsave(&ucb->io_lock, flags); | |
136 | ucb->io_dir &= ~(1 << offset); | |
137 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); | |
138 | spin_unlock_irqrestore(&ucb->io_lock, flags); | |
139 | ||
140 | return 0; | |
141 | } | |
142 | ||
143 | static int ucb1x00_gpio_direction_output(struct gpio_chip *chip, unsigned offset | |
144 | , int value) | |
145 | { | |
146 | struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio); | |
147 | unsigned long flags; | |
c23bb602 | 148 | unsigned old, mask = 1 << offset; |
9ca3dc80 TK |
149 | |
150 | spin_lock_irqsave(&ucb->io_lock, flags); | |
c23bb602 | 151 | old = ucb->io_out; |
9ca3dc80 | 152 | if (value) |
c23bb602 | 153 | ucb->io_out |= mask; |
9ca3dc80 | 154 | else |
c23bb602 RK |
155 | ucb->io_out &= ~mask; |
156 | ||
157 | if (old != ucb->io_out) | |
158 | ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); | |
159 | ||
160 | if (!(ucb->io_dir & mask)) { | |
161 | ucb->io_dir |= mask; | |
162 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); | |
163 | } | |
9ca3dc80 TK |
164 | spin_unlock_irqrestore(&ucb->io_lock, flags); |
165 | ||
166 | return 0; | |
167 | } | |
168 | ||
05c45ca9 RK |
169 | /* |
170 | * UCB1300 data sheet says we must: | |
171 | * 1. enable ADC => 5us (including reference startup time) | |
172 | * 2. select input => 51*tsibclk => 4.3us | |
173 | * 3. start conversion => 102*tsibclk => 8.5us | |
174 | * (tsibclk = 1/11981000) | |
175 | * Period between SIB 128-bit frames = 10.7us | |
176 | */ | |
177 | ||
178 | /** | |
179 | * ucb1x00_adc_enable - enable the ADC converter | |
180 | * @ucb: UCB1x00 structure describing chip | |
181 | * | |
182 | * Enable the ucb1x00 and ADC converter on the UCB1x00 for use. | |
183 | * Any code wishing to use the ADC converter must call this | |
184 | * function prior to using it. | |
185 | * | |
186 | * This function takes the ADC semaphore to prevent two or more | |
187 | * concurrent uses, and therefore may sleep. As a result, it | |
188 | * can only be called from process context, not interrupt | |
189 | * context. | |
190 | * | |
191 | * You should release the ADC as soon as possible using | |
192 | * ucb1x00_adc_disable. | |
193 | */ | |
194 | void ucb1x00_adc_enable(struct ucb1x00 *ucb) | |
195 | { | |
196 | down(&ucb->adc_sem); | |
197 | ||
198 | ucb->adc_cr |= UCB_ADC_ENA; | |
199 | ||
200 | ucb1x00_enable(ucb); | |
201 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr); | |
202 | } | |
203 | ||
204 | /** | |
205 | * ucb1x00_adc_read - read the specified ADC channel | |
206 | * @ucb: UCB1x00 structure describing chip | |
207 | * @adc_channel: ADC channel mask | |
208 | * @sync: wait for syncronisation pulse. | |
209 | * | |
210 | * Start an ADC conversion and wait for the result. Note that | |
211 | * synchronised ADC conversions (via the ADCSYNC pin) must wait | |
212 | * until the trigger is asserted and the conversion is finished. | |
213 | * | |
214 | * This function currently spins waiting for the conversion to | |
215 | * complete (2 frames max without sync). | |
216 | * | |
217 | * If called for a synchronised ADC conversion, it may sleep | |
218 | * with the ADC semaphore held. | |
219 | */ | |
220 | unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync) | |
221 | { | |
222 | unsigned int val; | |
223 | ||
224 | if (sync) | |
225 | adc_channel |= UCB_ADC_SYNC_ENA; | |
226 | ||
227 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel); | |
228 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel | UCB_ADC_START); | |
229 | ||
230 | for (;;) { | |
231 | val = ucb1x00_reg_read(ucb, UCB_ADC_DATA); | |
232 | if (val & UCB_ADC_DAT_VAL) | |
233 | break; | |
234 | /* yield to other processes */ | |
235 | set_current_state(TASK_INTERRUPTIBLE); | |
236 | schedule_timeout(1); | |
237 | } | |
238 | ||
239 | return UCB_ADC_DAT(val); | |
240 | } | |
241 | ||
242 | /** | |
243 | * ucb1x00_adc_disable - disable the ADC converter | |
244 | * @ucb: UCB1x00 structure describing chip | |
245 | * | |
246 | * Disable the ADC converter and release the ADC semaphore. | |
247 | */ | |
248 | void ucb1x00_adc_disable(struct ucb1x00 *ucb) | |
249 | { | |
250 | ucb->adc_cr &= ~UCB_ADC_ENA; | |
251 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr); | |
252 | ucb1x00_disable(ucb); | |
253 | ||
254 | up(&ucb->adc_sem); | |
255 | } | |
256 | ||
257 | /* | |
258 | * UCB1x00 Interrupt handling. | |
259 | * | |
260 | * The UCB1x00 can generate interrupts when the SIBCLK is stopped. | |
261 | * Since we need to read an internal register, we must re-enable | |
262 | * SIBCLK to talk to the chip. We leave the clock running until | |
263 | * we have finished processing all interrupts from the chip. | |
264 | */ | |
7d12e780 | 265 | static irqreturn_t ucb1x00_irq(int irqnr, void *devid) |
05c45ca9 RK |
266 | { |
267 | struct ucb1x00 *ucb = devid; | |
268 | struct ucb1x00_irq *irq; | |
269 | unsigned int isr, i; | |
270 | ||
271 | ucb1x00_enable(ucb); | |
272 | isr = ucb1x00_reg_read(ucb, UCB_IE_STATUS); | |
273 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, isr); | |
274 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); | |
275 | ||
276 | for (i = 0, irq = ucb->irq_handler; i < 16 && isr; i++, isr >>= 1, irq++) | |
277 | if (isr & 1 && irq->fn) | |
278 | irq->fn(i, irq->devid); | |
279 | ucb1x00_disable(ucb); | |
280 | ||
281 | return IRQ_HANDLED; | |
282 | } | |
283 | ||
284 | /** | |
285 | * ucb1x00_hook_irq - hook a UCB1x00 interrupt | |
286 | * @ucb: UCB1x00 structure describing chip | |
287 | * @idx: interrupt index | |
288 | * @fn: function to call when interrupt is triggered | |
289 | * @devid: device id to pass to interrupt handler | |
290 | * | |
291 | * Hook the specified interrupt. You can only register one handler | |
292 | * for each interrupt source. The interrupt source is not enabled | |
293 | * by this function; use ucb1x00_enable_irq instead. | |
294 | * | |
295 | * Interrupt handlers will be called with other interrupts enabled. | |
296 | * | |
297 | * Returns zero on success, or one of the following errors: | |
298 | * -EINVAL if the interrupt index is invalid | |
299 | * -EBUSY if the interrupt has already been hooked | |
300 | */ | |
301 | int ucb1x00_hook_irq(struct ucb1x00 *ucb, unsigned int idx, void (*fn)(int, void *), void *devid) | |
302 | { | |
303 | struct ucb1x00_irq *irq; | |
304 | int ret = -EINVAL; | |
305 | ||
306 | if (idx < 16) { | |
307 | irq = ucb->irq_handler + idx; | |
308 | ret = -EBUSY; | |
309 | ||
310 | spin_lock_irq(&ucb->lock); | |
311 | if (irq->fn == NULL) { | |
312 | irq->devid = devid; | |
313 | irq->fn = fn; | |
314 | ret = 0; | |
315 | } | |
316 | spin_unlock_irq(&ucb->lock); | |
317 | } | |
318 | return ret; | |
319 | } | |
320 | ||
321 | /** | |
322 | * ucb1x00_enable_irq - enable an UCB1x00 interrupt source | |
323 | * @ucb: UCB1x00 structure describing chip | |
324 | * @idx: interrupt index | |
325 | * @edges: interrupt edges to enable | |
326 | * | |
327 | * Enable the specified interrupt to trigger on %UCB_RISING, | |
328 | * %UCB_FALLING or both edges. The interrupt should have been | |
329 | * hooked by ucb1x00_hook_irq. | |
330 | */ | |
331 | void ucb1x00_enable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges) | |
332 | { | |
333 | unsigned long flags; | |
334 | ||
335 | if (idx < 16) { | |
336 | spin_lock_irqsave(&ucb->lock, flags); | |
337 | ||
338 | ucb1x00_enable(ucb); | |
339 | if (edges & UCB_RISING) { | |
340 | ucb->irq_ris_enbl |= 1 << idx; | |
341 | ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl); | |
342 | } | |
343 | if (edges & UCB_FALLING) { | |
344 | ucb->irq_fal_enbl |= 1 << idx; | |
345 | ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl); | |
346 | } | |
347 | ucb1x00_disable(ucb); | |
348 | spin_unlock_irqrestore(&ucb->lock, flags); | |
349 | } | |
350 | } | |
351 | ||
352 | /** | |
353 | * ucb1x00_disable_irq - disable an UCB1x00 interrupt source | |
354 | * @ucb: UCB1x00 structure describing chip | |
355 | * @edges: interrupt edges to disable | |
356 | * | |
357 | * Disable the specified interrupt triggering on the specified | |
358 | * (%UCB_RISING, %UCB_FALLING or both) edges. | |
359 | */ | |
360 | void ucb1x00_disable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges) | |
361 | { | |
362 | unsigned long flags; | |
363 | ||
364 | if (idx < 16) { | |
365 | spin_lock_irqsave(&ucb->lock, flags); | |
366 | ||
367 | ucb1x00_enable(ucb); | |
368 | if (edges & UCB_RISING) { | |
369 | ucb->irq_ris_enbl &= ~(1 << idx); | |
370 | ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl); | |
371 | } | |
372 | if (edges & UCB_FALLING) { | |
373 | ucb->irq_fal_enbl &= ~(1 << idx); | |
374 | ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl); | |
375 | } | |
376 | ucb1x00_disable(ucb); | |
377 | spin_unlock_irqrestore(&ucb->lock, flags); | |
378 | } | |
379 | } | |
380 | ||
381 | /** | |
382 | * ucb1x00_free_irq - disable and free the specified UCB1x00 interrupt | |
383 | * @ucb: UCB1x00 structure describing chip | |
384 | * @idx: interrupt index | |
385 | * @devid: device id. | |
386 | * | |
387 | * Disable the interrupt source and remove the handler. devid must | |
388 | * match the devid passed when hooking the interrupt. | |
389 | * | |
390 | * Returns zero on success, or one of the following errors: | |
391 | * -EINVAL if the interrupt index is invalid | |
392 | * -ENOENT if devid does not match | |
393 | */ | |
394 | int ucb1x00_free_irq(struct ucb1x00 *ucb, unsigned int idx, void *devid) | |
395 | { | |
396 | struct ucb1x00_irq *irq; | |
397 | int ret; | |
398 | ||
399 | if (idx >= 16) | |
400 | goto bad; | |
401 | ||
402 | irq = ucb->irq_handler + idx; | |
403 | ret = -ENOENT; | |
404 | ||
405 | spin_lock_irq(&ucb->lock); | |
406 | if (irq->devid == devid) { | |
407 | ucb->irq_ris_enbl &= ~(1 << idx); | |
408 | ucb->irq_fal_enbl &= ~(1 << idx); | |
409 | ||
410 | ucb1x00_enable(ucb); | |
411 | ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl); | |
412 | ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl); | |
413 | ucb1x00_disable(ucb); | |
414 | ||
415 | irq->fn = NULL; | |
416 | irq->devid = NULL; | |
417 | ret = 0; | |
418 | } | |
419 | spin_unlock_irq(&ucb->lock); | |
420 | return ret; | |
421 | ||
422 | bad: | |
423 | printk(KERN_ERR "Freeing bad UCB1x00 irq %d\n", idx); | |
424 | return -EINVAL; | |
425 | } | |
426 | ||
427 | static int ucb1x00_add_dev(struct ucb1x00 *ucb, struct ucb1x00_driver *drv) | |
428 | { | |
429 | struct ucb1x00_dev *dev; | |
430 | int ret = -ENOMEM; | |
431 | ||
432 | dev = kmalloc(sizeof(struct ucb1x00_dev), GFP_KERNEL); | |
433 | if (dev) { | |
434 | dev->ucb = ucb; | |
435 | dev->drv = drv; | |
436 | ||
437 | ret = drv->add(dev); | |
438 | ||
439 | if (ret == 0) { | |
440 | list_add(&dev->dev_node, &ucb->devs); | |
441 | list_add(&dev->drv_node, &drv->devs); | |
442 | } else { | |
443 | kfree(dev); | |
444 | } | |
445 | } | |
446 | return ret; | |
447 | } | |
448 | ||
449 | static void ucb1x00_remove_dev(struct ucb1x00_dev *dev) | |
450 | { | |
451 | dev->drv->remove(dev); | |
452 | list_del(&dev->dev_node); | |
453 | list_del(&dev->drv_node); | |
454 | kfree(dev); | |
455 | } | |
456 | ||
457 | /* | |
458 | * Try to probe our interrupt, rather than relying on lots of | |
459 | * hard-coded machine dependencies. For reference, the expected | |
460 | * IRQ mappings are: | |
461 | * | |
462 | * Machine Default IRQ | |
463 | * adsbitsy IRQ_GPCIN4 | |
464 | * cerf IRQ_GPIO_UCB1200_IRQ | |
465 | * flexanet IRQ_GPIO_GUI | |
466 | * freebird IRQ_GPIO_FREEBIRD_UCB1300_IRQ | |
467 | * graphicsclient ADS_EXT_IRQ(8) | |
468 | * graphicsmaster ADS_EXT_IRQ(8) | |
469 | * lart LART_IRQ_UCB1200 | |
470 | * omnimeter IRQ_GPIO23 | |
471 | * pfs168 IRQ_GPIO_UCB1300_IRQ | |
472 | * simpad IRQ_GPIO_UCB1300_IRQ | |
473 | * shannon SHANNON_IRQ_GPIO_IRQ_CODEC | |
474 | * yopy IRQ_GPIO_UCB1200_IRQ | |
475 | */ | |
476 | static int ucb1x00_detect_irq(struct ucb1x00 *ucb) | |
477 | { | |
478 | unsigned long mask; | |
479 | ||
480 | mask = probe_irq_on(); | |
cfc73656 IM |
481 | if (!mask) { |
482 | probe_irq_off(mask); | |
05c45ca9 | 483 | return NO_IRQ; |
cfc73656 | 484 | } |
05c45ca9 RK |
485 | |
486 | /* | |
487 | * Enable the ADC interrupt. | |
488 | */ | |
489 | ucb1x00_reg_write(ucb, UCB_IE_RIS, UCB_IE_ADC); | |
490 | ucb1x00_reg_write(ucb, UCB_IE_FAL, UCB_IE_ADC); | |
491 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff); | |
492 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); | |
493 | ||
494 | /* | |
495 | * Cause an ADC interrupt. | |
496 | */ | |
497 | ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA); | |
498 | ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | UCB_ADC_START); | |
499 | ||
500 | /* | |
501 | * Wait for the conversion to complete. | |
502 | */ | |
503 | while ((ucb1x00_reg_read(ucb, UCB_ADC_DATA) & UCB_ADC_DAT_VAL) == 0); | |
504 | ucb1x00_reg_write(ucb, UCB_ADC_CR, 0); | |
505 | ||
506 | /* | |
507 | * Disable and clear interrupt. | |
508 | */ | |
509 | ucb1x00_reg_write(ucb, UCB_IE_RIS, 0); | |
510 | ucb1x00_reg_write(ucb, UCB_IE_FAL, 0); | |
511 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff); | |
512 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); | |
513 | ||
514 | /* | |
515 | * Read triggered interrupt. | |
516 | */ | |
517 | return probe_irq_off(mask); | |
518 | } | |
519 | ||
0c55445f | 520 | static void ucb1x00_release(struct device *dev) |
585f5457 NP |
521 | { |
522 | struct ucb1x00 *ucb = classdev_to_ucb1x00(dev); | |
523 | kfree(ucb); | |
524 | } | |
525 | ||
526 | static struct class ucb1x00_class = { | |
527 | .name = "ucb1x00", | |
0c55445f | 528 | .dev_release = ucb1x00_release, |
585f5457 NP |
529 | }; |
530 | ||
05c45ca9 RK |
531 | static int ucb1x00_probe(struct mcp *mcp) |
532 | { | |
533 | struct ucb1x00 *ucb; | |
534 | struct ucb1x00_driver *drv; | |
abe06082 | 535 | struct ucb1x00_plat_data *pdata; |
05c45ca9 RK |
536 | unsigned int id; |
537 | int ret = -ENODEV; | |
9ca3dc80 | 538 | int temp; |
05c45ca9 RK |
539 | |
540 | mcp_enable(mcp); | |
541 | id = mcp_reg_read(mcp, UCB_ID); | |
542 | ||
65f2e753 RK |
543 | if (id != UCB_ID_1200 && id != UCB_ID_1300 && id != UCB_ID_TC35143) { |
544 | printk(KERN_WARNING "UCB1x00 ID not found: %04x\n", id); | |
05c45ca9 RK |
545 | goto err_disable; |
546 | } | |
547 | ||
dd00cc48 | 548 | ucb = kzalloc(sizeof(struct ucb1x00), GFP_KERNEL); |
05c45ca9 RK |
549 | ret = -ENOMEM; |
550 | if (!ucb) | |
551 | goto err_disable; | |
552 | ||
abe06082 | 553 | pdata = mcp->attached_device.platform_data; |
0c55445f TJ |
554 | ucb->dev.class = &ucb1x00_class; |
555 | ucb->dev.parent = &mcp->attached_device; | |
65f2e753 | 556 | dev_set_name(&ucb->dev, "ucb1x00"); |
05c45ca9 RK |
557 | |
558 | spin_lock_init(&ucb->lock); | |
559 | spin_lock_init(&ucb->io_lock); | |
560 | sema_init(&ucb->adc_sem, 1); | |
561 | ||
65f2e753 | 562 | ucb->id = id; |
05c45ca9 RK |
563 | ucb->mcp = mcp; |
564 | ucb->irq = ucb1x00_detect_irq(ucb); | |
565 | if (ucb->irq == NO_IRQ) { | |
65f2e753 | 566 | printk(KERN_ERR "UCB1x00: IRQ probe failed\n"); |
05c45ca9 RK |
567 | ret = -ENODEV; |
568 | goto err_free; | |
569 | } | |
570 | ||
9ca3dc80 | 571 | ucb->gpio.base = -1; |
abe06082 | 572 | if (pdata && pdata->gpio_base) { |
9ca3dc80 | 573 | ucb->gpio.label = dev_name(&ucb->dev); |
abe06082 | 574 | ucb->gpio.base = pdata->gpio_base; |
9ca3dc80 TK |
575 | ucb->gpio.ngpio = 10; |
576 | ucb->gpio.set = ucb1x00_gpio_set; | |
577 | ucb->gpio.get = ucb1x00_gpio_get; | |
578 | ucb->gpio.direction_input = ucb1x00_gpio_direction_input; | |
579 | ucb->gpio.direction_output = ucb1x00_gpio_direction_output; | |
580 | ret = gpiochip_add(&ucb->gpio); | |
581 | if (ret) | |
582 | goto err_free; | |
583 | } else | |
584 | dev_info(&ucb->dev, "gpio_base not set so no gpiolib support"); | |
585 | ||
dace1453 | 586 | ret = request_irq(ucb->irq, ucb1x00_irq, IRQF_TRIGGER_RISING, |
65f2e753 | 587 | "UCB1x00", ucb); |
05c45ca9 | 588 | if (ret) { |
65f2e753 RK |
589 | printk(KERN_ERR "ucb1x00: unable to grab irq%d: %d\n", |
590 | ucb->irq, ret); | |
9ca3dc80 | 591 | goto err_gpio; |
05c45ca9 RK |
592 | } |
593 | ||
05c45ca9 RK |
594 | mcp_set_drvdata(mcp, ucb); |
595 | ||
0c55445f | 596 | ret = device_register(&ucb->dev); |
05c45ca9 RK |
597 | if (ret) |
598 | goto err_irq; | |
599 | ||
9ca3dc80 | 600 | |
05c45ca9 | 601 | INIT_LIST_HEAD(&ucb->devs); |
a621aaed | 602 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
603 | list_add(&ucb->node, &ucb1x00_devices); |
604 | list_for_each_entry(drv, &ucb1x00_drivers, node) { | |
605 | ucb1x00_add_dev(ucb, drv); | |
606 | } | |
a621aaed | 607 | mutex_unlock(&ucb1x00_mutex); |
9ca3dc80 | 608 | |
05c45ca9 RK |
609 | goto out; |
610 | ||
611 | err_irq: | |
612 | free_irq(ucb->irq, ucb); | |
9ca3dc80 TK |
613 | err_gpio: |
614 | if (ucb->gpio.base != -1) | |
615 | temp = gpiochip_remove(&ucb->gpio); | |
05c45ca9 RK |
616 | err_free: |
617 | kfree(ucb); | |
618 | err_disable: | |
619 | mcp_disable(mcp); | |
620 | out: | |
621 | return ret; | |
622 | } | |
623 | ||
624 | static void ucb1x00_remove(struct mcp *mcp) | |
625 | { | |
626 | struct ucb1x00 *ucb = mcp_get_drvdata(mcp); | |
627 | struct list_head *l, *n; | |
9ca3dc80 | 628 | int ret; |
05c45ca9 | 629 | |
a621aaed | 630 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
631 | list_del(&ucb->node); |
632 | list_for_each_safe(l, n, &ucb->devs) { | |
633 | struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, dev_node); | |
634 | ucb1x00_remove_dev(dev); | |
635 | } | |
a621aaed | 636 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 | 637 | |
9ca3dc80 TK |
638 | if (ucb->gpio.base != -1) { |
639 | ret = gpiochip_remove(&ucb->gpio); | |
640 | if (ret) | |
641 | dev_err(&ucb->dev, "Can't remove gpio chip: %d\n", ret); | |
642 | } | |
643 | ||
05c45ca9 | 644 | free_irq(ucb->irq, ucb); |
0c55445f | 645 | device_unregister(&ucb->dev); |
05c45ca9 RK |
646 | } |
647 | ||
05c45ca9 RK |
648 | int ucb1x00_register_driver(struct ucb1x00_driver *drv) |
649 | { | |
650 | struct ucb1x00 *ucb; | |
651 | ||
652 | INIT_LIST_HEAD(&drv->devs); | |
a621aaed | 653 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
654 | list_add(&drv->node, &ucb1x00_drivers); |
655 | list_for_each_entry(ucb, &ucb1x00_devices, node) { | |
656 | ucb1x00_add_dev(ucb, drv); | |
657 | } | |
a621aaed | 658 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
659 | return 0; |
660 | } | |
661 | ||
662 | void ucb1x00_unregister_driver(struct ucb1x00_driver *drv) | |
663 | { | |
664 | struct list_head *n, *l; | |
665 | ||
a621aaed | 666 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
667 | list_del(&drv->node); |
668 | list_for_each_safe(l, n, &drv->devs) { | |
669 | struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, drv_node); | |
670 | ucb1x00_remove_dev(dev); | |
671 | } | |
a621aaed | 672 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
673 | } |
674 | ||
675 | static int ucb1x00_suspend(struct mcp *mcp, pm_message_t state) | |
676 | { | |
677 | struct ucb1x00 *ucb = mcp_get_drvdata(mcp); | |
678 | struct ucb1x00_dev *dev; | |
679 | ||
a621aaed | 680 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
681 | list_for_each_entry(dev, &ucb->devs, dev_node) { |
682 | if (dev->drv->suspend) | |
683 | dev->drv->suspend(dev, state); | |
684 | } | |
a621aaed | 685 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
686 | return 0; |
687 | } | |
688 | ||
689 | static int ucb1x00_resume(struct mcp *mcp) | |
690 | { | |
691 | struct ucb1x00 *ucb = mcp_get_drvdata(mcp); | |
692 | struct ucb1x00_dev *dev; | |
693 | ||
2e95e51e | 694 | ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); |
9ca3dc80 | 695 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); |
a621aaed | 696 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
697 | list_for_each_entry(dev, &ucb->devs, dev_node) { |
698 | if (dev->drv->resume) | |
699 | dev->drv->resume(dev); | |
700 | } | |
a621aaed | 701 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
702 | return 0; |
703 | } | |
704 | ||
705 | static struct mcp_driver ucb1x00_driver = { | |
706 | .drv = { | |
707 | .name = "ucb1x00", | |
708 | }, | |
709 | .probe = ucb1x00_probe, | |
710 | .remove = ucb1x00_remove, | |
711 | .suspend = ucb1x00_suspend, | |
712 | .resume = ucb1x00_resume, | |
713 | }; | |
714 | ||
715 | static int __init ucb1x00_init(void) | |
716 | { | |
717 | int ret = class_register(&ucb1x00_class); | |
718 | if (ret == 0) { | |
719 | ret = mcp_driver_register(&ucb1x00_driver); | |
720 | if (ret) | |
721 | class_unregister(&ucb1x00_class); | |
722 | } | |
723 | return ret; | |
724 | } | |
725 | ||
726 | static void __exit ucb1x00_exit(void) | |
727 | { | |
728 | mcp_driver_unregister(&ucb1x00_driver); | |
729 | class_unregister(&ucb1x00_class); | |
730 | } | |
731 | ||
732 | module_init(ucb1x00_init); | |
733 | module_exit(ucb1x00_exit); | |
734 | ||
05c45ca9 RK |
735 | EXPORT_SYMBOL(ucb1x00_io_set_dir); |
736 | EXPORT_SYMBOL(ucb1x00_io_write); | |
737 | EXPORT_SYMBOL(ucb1x00_io_read); | |
738 | ||
739 | EXPORT_SYMBOL(ucb1x00_adc_enable); | |
740 | EXPORT_SYMBOL(ucb1x00_adc_read); | |
741 | EXPORT_SYMBOL(ucb1x00_adc_disable); | |
742 | ||
743 | EXPORT_SYMBOL(ucb1x00_hook_irq); | |
744 | EXPORT_SYMBOL(ucb1x00_free_irq); | |
745 | EXPORT_SYMBOL(ucb1x00_enable_irq); | |
746 | EXPORT_SYMBOL(ucb1x00_disable_irq); | |
747 | ||
748 | EXPORT_SYMBOL(ucb1x00_register_driver); | |
749 | EXPORT_SYMBOL(ucb1x00_unregister_driver); | |
750 | ||
751 | MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>"); | |
752 | MODULE_DESCRIPTION("UCB1x00 core driver"); | |
753 | MODULE_LICENSE("GPL"); |