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05c45ca9 RK |
1 | /* |
2 | * linux/drivers/mfd/ucb1x00-core.c | |
3 | * | |
4 | * Copyright (C) 2001 Russell King, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License. | |
9 | * | |
10 | * The UCB1x00 core driver provides basic services for handling IO, | |
11 | * the ADC, interrupts, and accessing registers. It is designed | |
12 | * such that everything goes through this layer, thereby providing | |
13 | * a consistent locking methodology, as well as allowing the drivers | |
14 | * to be used on other non-MCP-enabled hardware platforms. | |
15 | * | |
16 | * Note that all locks are private to this file. Nothing else may | |
17 | * touch them. | |
18 | */ | |
05c45ca9 RK |
19 | #include <linux/module.h> |
20 | #include <linux/kernel.h> | |
d43c36dc | 21 | #include <linux/sched.h> |
05c45ca9 RK |
22 | #include <linux/slab.h> |
23 | #include <linux/init.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/device.h> | |
a621aaed | 27 | #include <linux/mutex.h> |
c8602edf | 28 | #include <linux/mfd/ucb1x00.h> |
9ca3dc80 | 29 | #include <linux/gpio.h> |
05c45ca9 | 30 | |
a621aaed | 31 | static DEFINE_MUTEX(ucb1x00_mutex); |
05c45ca9 RK |
32 | static LIST_HEAD(ucb1x00_drivers); |
33 | static LIST_HEAD(ucb1x00_devices); | |
34 | ||
35 | /** | |
36 | * ucb1x00_io_set_dir - set IO direction | |
37 | * @ucb: UCB1x00 structure describing chip | |
38 | * @in: bitfield of IO pins to be set as inputs | |
39 | * @out: bitfield of IO pins to be set as outputs | |
40 | * | |
41 | * Set the IO direction of the ten general purpose IO pins on | |
42 | * the UCB1x00 chip. The @in bitfield has priority over the | |
43 | * @out bitfield, in that if you specify a pin as both input | |
44 | * and output, it will end up as an input. | |
45 | * | |
46 | * ucb1x00_enable must have been called to enable the comms | |
47 | * before using this function. | |
48 | * | |
49 | * This function takes a spinlock, disabling interrupts. | |
50 | */ | |
51 | void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int in, unsigned int out) | |
52 | { | |
53 | unsigned long flags; | |
54 | ||
55 | spin_lock_irqsave(&ucb->io_lock, flags); | |
56 | ucb->io_dir |= out; | |
57 | ucb->io_dir &= ~in; | |
58 | ||
59 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); | |
60 | spin_unlock_irqrestore(&ucb->io_lock, flags); | |
61 | } | |
62 | ||
63 | /** | |
64 | * ucb1x00_io_write - set or clear IO outputs | |
65 | * @ucb: UCB1x00 structure describing chip | |
66 | * @set: bitfield of IO pins to set to logic '1' | |
67 | * @clear: bitfield of IO pins to set to logic '0' | |
68 | * | |
69 | * Set the IO output state of the specified IO pins. The value | |
70 | * is retained if the pins are subsequently configured as inputs. | |
71 | * The @clear bitfield has priority over the @set bitfield - | |
72 | * outputs will be cleared. | |
73 | * | |
74 | * ucb1x00_enable must have been called to enable the comms | |
75 | * before using this function. | |
76 | * | |
77 | * This function takes a spinlock, disabling interrupts. | |
78 | */ | |
79 | void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int set, unsigned int clear) | |
80 | { | |
81 | unsigned long flags; | |
82 | ||
83 | spin_lock_irqsave(&ucb->io_lock, flags); | |
84 | ucb->io_out |= set; | |
85 | ucb->io_out &= ~clear; | |
86 | ||
87 | ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); | |
88 | spin_unlock_irqrestore(&ucb->io_lock, flags); | |
89 | } | |
90 | ||
91 | /** | |
92 | * ucb1x00_io_read - read the current state of the IO pins | |
93 | * @ucb: UCB1x00 structure describing chip | |
94 | * | |
95 | * Return a bitfield describing the logic state of the ten | |
96 | * general purpose IO pins. | |
97 | * | |
98 | * ucb1x00_enable must have been called to enable the comms | |
99 | * before using this function. | |
100 | * | |
cae15476 | 101 | * This function does not take any mutexes or spinlocks. |
05c45ca9 RK |
102 | */ |
103 | unsigned int ucb1x00_io_read(struct ucb1x00 *ucb) | |
104 | { | |
105 | return ucb1x00_reg_read(ucb, UCB_IO_DATA); | |
106 | } | |
107 | ||
9ca3dc80 TK |
108 | static void ucb1x00_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
109 | { | |
110 | struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio); | |
111 | unsigned long flags; | |
112 | ||
113 | spin_lock_irqsave(&ucb->io_lock, flags); | |
114 | if (value) | |
115 | ucb->io_out |= 1 << offset; | |
116 | else | |
117 | ucb->io_out &= ~(1 << offset); | |
118 | ||
ed442b67 | 119 | ucb1x00_enable(ucb); |
9ca3dc80 | 120 | ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); |
ed442b67 | 121 | ucb1x00_disable(ucb); |
9ca3dc80 TK |
122 | spin_unlock_irqrestore(&ucb->io_lock, flags); |
123 | } | |
124 | ||
125 | static int ucb1x00_gpio_get(struct gpio_chip *chip, unsigned offset) | |
126 | { | |
127 | struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio); | |
ed442b67 RK |
128 | unsigned val; |
129 | ||
130 | ucb1x00_enable(ucb); | |
131 | val = ucb1x00_reg_read(ucb, UCB_IO_DATA); | |
132 | ucb1x00_disable(ucb); | |
133 | ||
134 | return val & (1 << offset); | |
9ca3dc80 TK |
135 | } |
136 | ||
137 | static int ucb1x00_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
138 | { | |
139 | struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio); | |
140 | unsigned long flags; | |
141 | ||
142 | spin_lock_irqsave(&ucb->io_lock, flags); | |
143 | ucb->io_dir &= ~(1 << offset); | |
ed442b67 | 144 | ucb1x00_enable(ucb); |
9ca3dc80 | 145 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); |
ed442b67 | 146 | ucb1x00_disable(ucb); |
9ca3dc80 TK |
147 | spin_unlock_irqrestore(&ucb->io_lock, flags); |
148 | ||
149 | return 0; | |
150 | } | |
151 | ||
152 | static int ucb1x00_gpio_direction_output(struct gpio_chip *chip, unsigned offset | |
153 | , int value) | |
154 | { | |
155 | struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio); | |
156 | unsigned long flags; | |
c23bb602 | 157 | unsigned old, mask = 1 << offset; |
9ca3dc80 TK |
158 | |
159 | spin_lock_irqsave(&ucb->io_lock, flags); | |
c23bb602 | 160 | old = ucb->io_out; |
9ca3dc80 | 161 | if (value) |
c23bb602 | 162 | ucb->io_out |= mask; |
9ca3dc80 | 163 | else |
c23bb602 RK |
164 | ucb->io_out &= ~mask; |
165 | ||
ed442b67 | 166 | ucb1x00_enable(ucb); |
c23bb602 RK |
167 | if (old != ucb->io_out) |
168 | ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); | |
169 | ||
170 | if (!(ucb->io_dir & mask)) { | |
171 | ucb->io_dir |= mask; | |
172 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); | |
173 | } | |
ed442b67 | 174 | ucb1x00_disable(ucb); |
9ca3dc80 TK |
175 | spin_unlock_irqrestore(&ucb->io_lock, flags); |
176 | ||
177 | return 0; | |
178 | } | |
179 | ||
05c45ca9 RK |
180 | /* |
181 | * UCB1300 data sheet says we must: | |
182 | * 1. enable ADC => 5us (including reference startup time) | |
183 | * 2. select input => 51*tsibclk => 4.3us | |
184 | * 3. start conversion => 102*tsibclk => 8.5us | |
185 | * (tsibclk = 1/11981000) | |
186 | * Period between SIB 128-bit frames = 10.7us | |
187 | */ | |
188 | ||
189 | /** | |
190 | * ucb1x00_adc_enable - enable the ADC converter | |
191 | * @ucb: UCB1x00 structure describing chip | |
192 | * | |
193 | * Enable the ucb1x00 and ADC converter on the UCB1x00 for use. | |
194 | * Any code wishing to use the ADC converter must call this | |
195 | * function prior to using it. | |
196 | * | |
cae15476 | 197 | * This function takes the ADC mutex to prevent two or more |
05c45ca9 RK |
198 | * concurrent uses, and therefore may sleep. As a result, it |
199 | * can only be called from process context, not interrupt | |
200 | * context. | |
201 | * | |
202 | * You should release the ADC as soon as possible using | |
203 | * ucb1x00_adc_disable. | |
204 | */ | |
205 | void ucb1x00_adc_enable(struct ucb1x00 *ucb) | |
206 | { | |
cae15476 | 207 | mutex_lock(&ucb->adc_mutex); |
05c45ca9 RK |
208 | |
209 | ucb->adc_cr |= UCB_ADC_ENA; | |
210 | ||
211 | ucb1x00_enable(ucb); | |
212 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr); | |
213 | } | |
214 | ||
215 | /** | |
216 | * ucb1x00_adc_read - read the specified ADC channel | |
217 | * @ucb: UCB1x00 structure describing chip | |
218 | * @adc_channel: ADC channel mask | |
219 | * @sync: wait for syncronisation pulse. | |
220 | * | |
221 | * Start an ADC conversion and wait for the result. Note that | |
222 | * synchronised ADC conversions (via the ADCSYNC pin) must wait | |
223 | * until the trigger is asserted and the conversion is finished. | |
224 | * | |
225 | * This function currently spins waiting for the conversion to | |
226 | * complete (2 frames max without sync). | |
227 | * | |
228 | * If called for a synchronised ADC conversion, it may sleep | |
cae15476 | 229 | * with the ADC mutex held. |
05c45ca9 RK |
230 | */ |
231 | unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync) | |
232 | { | |
233 | unsigned int val; | |
234 | ||
235 | if (sync) | |
236 | adc_channel |= UCB_ADC_SYNC_ENA; | |
237 | ||
238 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel); | |
239 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel | UCB_ADC_START); | |
240 | ||
241 | for (;;) { | |
242 | val = ucb1x00_reg_read(ucb, UCB_ADC_DATA); | |
243 | if (val & UCB_ADC_DAT_VAL) | |
244 | break; | |
245 | /* yield to other processes */ | |
246 | set_current_state(TASK_INTERRUPTIBLE); | |
247 | schedule_timeout(1); | |
248 | } | |
249 | ||
250 | return UCB_ADC_DAT(val); | |
251 | } | |
252 | ||
253 | /** | |
254 | * ucb1x00_adc_disable - disable the ADC converter | |
255 | * @ucb: UCB1x00 structure describing chip | |
256 | * | |
cae15476 | 257 | * Disable the ADC converter and release the ADC mutex. |
05c45ca9 RK |
258 | */ |
259 | void ucb1x00_adc_disable(struct ucb1x00 *ucb) | |
260 | { | |
261 | ucb->adc_cr &= ~UCB_ADC_ENA; | |
262 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr); | |
263 | ucb1x00_disable(ucb); | |
264 | ||
cae15476 | 265 | mutex_unlock(&ucb->adc_mutex); |
05c45ca9 RK |
266 | } |
267 | ||
268 | /* | |
269 | * UCB1x00 Interrupt handling. | |
270 | * | |
271 | * The UCB1x00 can generate interrupts when the SIBCLK is stopped. | |
272 | * Since we need to read an internal register, we must re-enable | |
273 | * SIBCLK to talk to the chip. We leave the clock running until | |
274 | * we have finished processing all interrupts from the chip. | |
275 | */ | |
7d12e780 | 276 | static irqreturn_t ucb1x00_irq(int irqnr, void *devid) |
05c45ca9 RK |
277 | { |
278 | struct ucb1x00 *ucb = devid; | |
279 | struct ucb1x00_irq *irq; | |
280 | unsigned int isr, i; | |
281 | ||
282 | ucb1x00_enable(ucb); | |
283 | isr = ucb1x00_reg_read(ucb, UCB_IE_STATUS); | |
284 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, isr); | |
285 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); | |
286 | ||
287 | for (i = 0, irq = ucb->irq_handler; i < 16 && isr; i++, isr >>= 1, irq++) | |
288 | if (isr & 1 && irq->fn) | |
289 | irq->fn(i, irq->devid); | |
290 | ucb1x00_disable(ucb); | |
291 | ||
292 | return IRQ_HANDLED; | |
293 | } | |
294 | ||
295 | /** | |
296 | * ucb1x00_hook_irq - hook a UCB1x00 interrupt | |
297 | * @ucb: UCB1x00 structure describing chip | |
298 | * @idx: interrupt index | |
299 | * @fn: function to call when interrupt is triggered | |
300 | * @devid: device id to pass to interrupt handler | |
301 | * | |
302 | * Hook the specified interrupt. You can only register one handler | |
303 | * for each interrupt source. The interrupt source is not enabled | |
304 | * by this function; use ucb1x00_enable_irq instead. | |
305 | * | |
306 | * Interrupt handlers will be called with other interrupts enabled. | |
307 | * | |
308 | * Returns zero on success, or one of the following errors: | |
309 | * -EINVAL if the interrupt index is invalid | |
310 | * -EBUSY if the interrupt has already been hooked | |
311 | */ | |
312 | int ucb1x00_hook_irq(struct ucb1x00 *ucb, unsigned int idx, void (*fn)(int, void *), void *devid) | |
313 | { | |
314 | struct ucb1x00_irq *irq; | |
315 | int ret = -EINVAL; | |
316 | ||
317 | if (idx < 16) { | |
318 | irq = ucb->irq_handler + idx; | |
319 | ret = -EBUSY; | |
320 | ||
321 | spin_lock_irq(&ucb->lock); | |
322 | if (irq->fn == NULL) { | |
323 | irq->devid = devid; | |
324 | irq->fn = fn; | |
325 | ret = 0; | |
326 | } | |
327 | spin_unlock_irq(&ucb->lock); | |
328 | } | |
329 | return ret; | |
330 | } | |
331 | ||
332 | /** | |
333 | * ucb1x00_enable_irq - enable an UCB1x00 interrupt source | |
334 | * @ucb: UCB1x00 structure describing chip | |
335 | * @idx: interrupt index | |
336 | * @edges: interrupt edges to enable | |
337 | * | |
338 | * Enable the specified interrupt to trigger on %UCB_RISING, | |
339 | * %UCB_FALLING or both edges. The interrupt should have been | |
340 | * hooked by ucb1x00_hook_irq. | |
341 | */ | |
342 | void ucb1x00_enable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges) | |
343 | { | |
344 | unsigned long flags; | |
345 | ||
346 | if (idx < 16) { | |
347 | spin_lock_irqsave(&ucb->lock, flags); | |
348 | ||
349 | ucb1x00_enable(ucb); | |
350 | if (edges & UCB_RISING) { | |
351 | ucb->irq_ris_enbl |= 1 << idx; | |
352 | ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl); | |
353 | } | |
354 | if (edges & UCB_FALLING) { | |
355 | ucb->irq_fal_enbl |= 1 << idx; | |
356 | ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl); | |
357 | } | |
358 | ucb1x00_disable(ucb); | |
359 | spin_unlock_irqrestore(&ucb->lock, flags); | |
360 | } | |
361 | } | |
362 | ||
363 | /** | |
364 | * ucb1x00_disable_irq - disable an UCB1x00 interrupt source | |
365 | * @ucb: UCB1x00 structure describing chip | |
366 | * @edges: interrupt edges to disable | |
367 | * | |
368 | * Disable the specified interrupt triggering on the specified | |
369 | * (%UCB_RISING, %UCB_FALLING or both) edges. | |
370 | */ | |
371 | void ucb1x00_disable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges) | |
372 | { | |
373 | unsigned long flags; | |
374 | ||
375 | if (idx < 16) { | |
376 | spin_lock_irqsave(&ucb->lock, flags); | |
377 | ||
378 | ucb1x00_enable(ucb); | |
379 | if (edges & UCB_RISING) { | |
380 | ucb->irq_ris_enbl &= ~(1 << idx); | |
381 | ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl); | |
382 | } | |
383 | if (edges & UCB_FALLING) { | |
384 | ucb->irq_fal_enbl &= ~(1 << idx); | |
385 | ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl); | |
386 | } | |
387 | ucb1x00_disable(ucb); | |
388 | spin_unlock_irqrestore(&ucb->lock, flags); | |
389 | } | |
390 | } | |
391 | ||
392 | /** | |
393 | * ucb1x00_free_irq - disable and free the specified UCB1x00 interrupt | |
394 | * @ucb: UCB1x00 structure describing chip | |
395 | * @idx: interrupt index | |
396 | * @devid: device id. | |
397 | * | |
398 | * Disable the interrupt source and remove the handler. devid must | |
399 | * match the devid passed when hooking the interrupt. | |
400 | * | |
401 | * Returns zero on success, or one of the following errors: | |
402 | * -EINVAL if the interrupt index is invalid | |
403 | * -ENOENT if devid does not match | |
404 | */ | |
405 | int ucb1x00_free_irq(struct ucb1x00 *ucb, unsigned int idx, void *devid) | |
406 | { | |
407 | struct ucb1x00_irq *irq; | |
408 | int ret; | |
409 | ||
410 | if (idx >= 16) | |
411 | goto bad; | |
412 | ||
413 | irq = ucb->irq_handler + idx; | |
414 | ret = -ENOENT; | |
415 | ||
416 | spin_lock_irq(&ucb->lock); | |
417 | if (irq->devid == devid) { | |
418 | ucb->irq_ris_enbl &= ~(1 << idx); | |
419 | ucb->irq_fal_enbl &= ~(1 << idx); | |
420 | ||
421 | ucb1x00_enable(ucb); | |
422 | ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl); | |
423 | ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl); | |
424 | ucb1x00_disable(ucb); | |
425 | ||
426 | irq->fn = NULL; | |
427 | irq->devid = NULL; | |
428 | ret = 0; | |
429 | } | |
430 | spin_unlock_irq(&ucb->lock); | |
431 | return ret; | |
432 | ||
433 | bad: | |
434 | printk(KERN_ERR "Freeing bad UCB1x00 irq %d\n", idx); | |
435 | return -EINVAL; | |
436 | } | |
437 | ||
438 | static int ucb1x00_add_dev(struct ucb1x00 *ucb, struct ucb1x00_driver *drv) | |
439 | { | |
440 | struct ucb1x00_dev *dev; | |
441 | int ret = -ENOMEM; | |
442 | ||
443 | dev = kmalloc(sizeof(struct ucb1x00_dev), GFP_KERNEL); | |
444 | if (dev) { | |
445 | dev->ucb = ucb; | |
446 | dev->drv = drv; | |
447 | ||
448 | ret = drv->add(dev); | |
449 | ||
450 | if (ret == 0) { | |
65b539bb RK |
451 | list_add_tail(&dev->dev_node, &ucb->devs); |
452 | list_add_tail(&dev->drv_node, &drv->devs); | |
05c45ca9 RK |
453 | } else { |
454 | kfree(dev); | |
455 | } | |
456 | } | |
457 | return ret; | |
458 | } | |
459 | ||
460 | static void ucb1x00_remove_dev(struct ucb1x00_dev *dev) | |
461 | { | |
462 | dev->drv->remove(dev); | |
463 | list_del(&dev->dev_node); | |
464 | list_del(&dev->drv_node); | |
465 | kfree(dev); | |
466 | } | |
467 | ||
468 | /* | |
469 | * Try to probe our interrupt, rather than relying on lots of | |
470 | * hard-coded machine dependencies. For reference, the expected | |
471 | * IRQ mappings are: | |
472 | * | |
473 | * Machine Default IRQ | |
474 | * adsbitsy IRQ_GPCIN4 | |
475 | * cerf IRQ_GPIO_UCB1200_IRQ | |
476 | * flexanet IRQ_GPIO_GUI | |
477 | * freebird IRQ_GPIO_FREEBIRD_UCB1300_IRQ | |
478 | * graphicsclient ADS_EXT_IRQ(8) | |
479 | * graphicsmaster ADS_EXT_IRQ(8) | |
480 | * lart LART_IRQ_UCB1200 | |
481 | * omnimeter IRQ_GPIO23 | |
482 | * pfs168 IRQ_GPIO_UCB1300_IRQ | |
483 | * simpad IRQ_GPIO_UCB1300_IRQ | |
484 | * shannon SHANNON_IRQ_GPIO_IRQ_CODEC | |
485 | * yopy IRQ_GPIO_UCB1200_IRQ | |
486 | */ | |
487 | static int ucb1x00_detect_irq(struct ucb1x00 *ucb) | |
488 | { | |
489 | unsigned long mask; | |
490 | ||
491 | mask = probe_irq_on(); | |
cfc73656 IM |
492 | if (!mask) { |
493 | probe_irq_off(mask); | |
05c45ca9 | 494 | return NO_IRQ; |
cfc73656 | 495 | } |
05c45ca9 RK |
496 | |
497 | /* | |
498 | * Enable the ADC interrupt. | |
499 | */ | |
500 | ucb1x00_reg_write(ucb, UCB_IE_RIS, UCB_IE_ADC); | |
501 | ucb1x00_reg_write(ucb, UCB_IE_FAL, UCB_IE_ADC); | |
502 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff); | |
503 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); | |
504 | ||
505 | /* | |
506 | * Cause an ADC interrupt. | |
507 | */ | |
508 | ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA); | |
509 | ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | UCB_ADC_START); | |
510 | ||
511 | /* | |
512 | * Wait for the conversion to complete. | |
513 | */ | |
514 | while ((ucb1x00_reg_read(ucb, UCB_ADC_DATA) & UCB_ADC_DAT_VAL) == 0); | |
515 | ucb1x00_reg_write(ucb, UCB_ADC_CR, 0); | |
516 | ||
517 | /* | |
518 | * Disable and clear interrupt. | |
519 | */ | |
520 | ucb1x00_reg_write(ucb, UCB_IE_RIS, 0); | |
521 | ucb1x00_reg_write(ucb, UCB_IE_FAL, 0); | |
522 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff); | |
523 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); | |
524 | ||
525 | /* | |
526 | * Read triggered interrupt. | |
527 | */ | |
528 | return probe_irq_off(mask); | |
529 | } | |
530 | ||
0c55445f | 531 | static void ucb1x00_release(struct device *dev) |
585f5457 NP |
532 | { |
533 | struct ucb1x00 *ucb = classdev_to_ucb1x00(dev); | |
534 | kfree(ucb); | |
535 | } | |
536 | ||
537 | static struct class ucb1x00_class = { | |
538 | .name = "ucb1x00", | |
0c55445f | 539 | .dev_release = ucb1x00_release, |
585f5457 NP |
540 | }; |
541 | ||
05c45ca9 RK |
542 | static int ucb1x00_probe(struct mcp *mcp) |
543 | { | |
2f7510c6 | 544 | struct ucb1x00_plat_data *pdata = mcp->attached_device.platform_data; |
05c45ca9 | 545 | struct ucb1x00_driver *drv; |
2f7510c6 | 546 | struct ucb1x00 *ucb; |
05c45ca9 RK |
547 | unsigned int id; |
548 | int ret = -ENODEV; | |
9ca3dc80 | 549 | int temp; |
05c45ca9 | 550 | |
2f7510c6 RK |
551 | /* Tell the platform to deassert the UCB1x00 reset */ |
552 | if (pdata && pdata->reset) | |
553 | pdata->reset(UCB_RST_PROBE); | |
554 | ||
05c45ca9 RK |
555 | mcp_enable(mcp); |
556 | id = mcp_reg_read(mcp, UCB_ID); | |
557 | ||
65f2e753 RK |
558 | if (id != UCB_ID_1200 && id != UCB_ID_1300 && id != UCB_ID_TC35143) { |
559 | printk(KERN_WARNING "UCB1x00 ID not found: %04x\n", id); | |
05c45ca9 RK |
560 | goto err_disable; |
561 | } | |
562 | ||
dd00cc48 | 563 | ucb = kzalloc(sizeof(struct ucb1x00), GFP_KERNEL); |
05c45ca9 RK |
564 | ret = -ENOMEM; |
565 | if (!ucb) | |
566 | goto err_disable; | |
567 | ||
f5ae587f | 568 | device_initialize(&ucb->dev); |
0c55445f TJ |
569 | ucb->dev.class = &ucb1x00_class; |
570 | ucb->dev.parent = &mcp->attached_device; | |
65f2e753 | 571 | dev_set_name(&ucb->dev, "ucb1x00"); |
05c45ca9 RK |
572 | |
573 | spin_lock_init(&ucb->lock); | |
574 | spin_lock_init(&ucb->io_lock); | |
cae15476 | 575 | mutex_init(&ucb->adc_mutex); |
05c45ca9 | 576 | |
65f2e753 | 577 | ucb->id = id; |
05c45ca9 | 578 | ucb->mcp = mcp; |
f5ae587f RK |
579 | |
580 | ret = device_add(&ucb->dev); | |
581 | if (ret) | |
582 | goto err_dev_add; | |
583 | ||
05c45ca9 RK |
584 | ucb->irq = ucb1x00_detect_irq(ucb); |
585 | if (ucb->irq == NO_IRQ) { | |
f5ae587f | 586 | dev_err(&ucb->dev, "IRQ probe failed\n"); |
05c45ca9 | 587 | ret = -ENODEV; |
f5ae587f | 588 | goto err_no_irq; |
05c45ca9 RK |
589 | } |
590 | ||
9ca3dc80 | 591 | ucb->gpio.base = -1; |
abe06082 | 592 | if (pdata && pdata->gpio_base) { |
9ca3dc80 | 593 | ucb->gpio.label = dev_name(&ucb->dev); |
7655b2ac RK |
594 | ucb->gpio.dev = &ucb->dev; |
595 | ucb->gpio.owner = THIS_MODULE; | |
abe06082 | 596 | ucb->gpio.base = pdata->gpio_base; |
9ca3dc80 TK |
597 | ucb->gpio.ngpio = 10; |
598 | ucb->gpio.set = ucb1x00_gpio_set; | |
599 | ucb->gpio.get = ucb1x00_gpio_get; | |
600 | ucb->gpio.direction_input = ucb1x00_gpio_direction_input; | |
601 | ucb->gpio.direction_output = ucb1x00_gpio_direction_output; | |
602 | ret = gpiochip_add(&ucb->gpio); | |
603 | if (ret) | |
f5ae587f | 604 | goto err_gpio_add; |
9ca3dc80 TK |
605 | } else |
606 | dev_info(&ucb->dev, "gpio_base not set so no gpiolib support"); | |
607 | ||
dace1453 | 608 | ret = request_irq(ucb->irq, ucb1x00_irq, IRQF_TRIGGER_RISING, |
65f2e753 | 609 | "UCB1x00", ucb); |
05c45ca9 | 610 | if (ret) { |
f5ae587f | 611 | dev_err(&ucb->dev, "ucb1x00: unable to grab irq%d: %d\n", |
65f2e753 | 612 | ucb->irq, ret); |
f5ae587f | 613 | goto err_irq; |
05c45ca9 RK |
614 | } |
615 | ||
05c45ca9 RK |
616 | mcp_set_drvdata(mcp, ucb); |
617 | ||
05c45ca9 | 618 | INIT_LIST_HEAD(&ucb->devs); |
a621aaed | 619 | mutex_lock(&ucb1x00_mutex); |
65b539bb | 620 | list_add_tail(&ucb->node, &ucb1x00_devices); |
05c45ca9 RK |
621 | list_for_each_entry(drv, &ucb1x00_drivers, node) { |
622 | ucb1x00_add_dev(ucb, drv); | |
623 | } | |
a621aaed | 624 | mutex_unlock(&ucb1x00_mutex); |
9ca3dc80 | 625 | |
2f7510c6 | 626 | return ret; |
05c45ca9 RK |
627 | |
628 | err_irq: | |
9ca3dc80 TK |
629 | if (ucb->gpio.base != -1) |
630 | temp = gpiochip_remove(&ucb->gpio); | |
f5ae587f RK |
631 | err_gpio_add: |
632 | err_no_irq: | |
633 | device_del(&ucb->dev); | |
634 | err_dev_add: | |
635 | put_device(&ucb->dev); | |
05c45ca9 RK |
636 | err_disable: |
637 | mcp_disable(mcp); | |
638 | out: | |
2f7510c6 RK |
639 | if (pdata && pdata->reset) |
640 | pdata->reset(UCB_RST_PROBE_FAIL); | |
05c45ca9 RK |
641 | return ret; |
642 | } | |
643 | ||
644 | static void ucb1x00_remove(struct mcp *mcp) | |
645 | { | |
2f7510c6 | 646 | struct ucb1x00_plat_data *pdata = mcp->attached_device.platform_data; |
05c45ca9 RK |
647 | struct ucb1x00 *ucb = mcp_get_drvdata(mcp); |
648 | struct list_head *l, *n; | |
9ca3dc80 | 649 | int ret; |
05c45ca9 | 650 | |
a621aaed | 651 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
652 | list_del(&ucb->node); |
653 | list_for_each_safe(l, n, &ucb->devs) { | |
654 | struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, dev_node); | |
655 | ucb1x00_remove_dev(dev); | |
656 | } | |
a621aaed | 657 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 | 658 | |
9ca3dc80 TK |
659 | if (ucb->gpio.base != -1) { |
660 | ret = gpiochip_remove(&ucb->gpio); | |
661 | if (ret) | |
662 | dev_err(&ucb->dev, "Can't remove gpio chip: %d\n", ret); | |
663 | } | |
664 | ||
05c45ca9 | 665 | free_irq(ucb->irq, ucb); |
0c55445f | 666 | device_unregister(&ucb->dev); |
2f7510c6 RK |
667 | |
668 | if (pdata && pdata->reset) | |
669 | pdata->reset(UCB_RST_REMOVE); | |
05c45ca9 RK |
670 | } |
671 | ||
05c45ca9 RK |
672 | int ucb1x00_register_driver(struct ucb1x00_driver *drv) |
673 | { | |
674 | struct ucb1x00 *ucb; | |
675 | ||
676 | INIT_LIST_HEAD(&drv->devs); | |
a621aaed | 677 | mutex_lock(&ucb1x00_mutex); |
65b539bb | 678 | list_add_tail(&drv->node, &ucb1x00_drivers); |
05c45ca9 RK |
679 | list_for_each_entry(ucb, &ucb1x00_devices, node) { |
680 | ucb1x00_add_dev(ucb, drv); | |
681 | } | |
a621aaed | 682 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
683 | return 0; |
684 | } | |
685 | ||
686 | void ucb1x00_unregister_driver(struct ucb1x00_driver *drv) | |
687 | { | |
688 | struct list_head *n, *l; | |
689 | ||
a621aaed | 690 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
691 | list_del(&drv->node); |
692 | list_for_each_safe(l, n, &drv->devs) { | |
693 | struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, drv_node); | |
694 | ucb1x00_remove_dev(dev); | |
695 | } | |
a621aaed | 696 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
697 | } |
698 | ||
699 | static int ucb1x00_suspend(struct mcp *mcp, pm_message_t state) | |
700 | { | |
701 | struct ucb1x00 *ucb = mcp_get_drvdata(mcp); | |
702 | struct ucb1x00_dev *dev; | |
703 | ||
a621aaed | 704 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
705 | list_for_each_entry(dev, &ucb->devs, dev_node) { |
706 | if (dev->drv->suspend) | |
707 | dev->drv->suspend(dev, state); | |
708 | } | |
a621aaed | 709 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
710 | return 0; |
711 | } | |
712 | ||
713 | static int ucb1x00_resume(struct mcp *mcp) | |
714 | { | |
715 | struct ucb1x00 *ucb = mcp_get_drvdata(mcp); | |
716 | struct ucb1x00_dev *dev; | |
717 | ||
ed442b67 | 718 | ucb1x00_enable(ucb); |
2e95e51e | 719 | ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); |
9ca3dc80 | 720 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); |
ed442b67 | 721 | ucb1x00_disable(ucb); |
a621aaed | 722 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
723 | list_for_each_entry(dev, &ucb->devs, dev_node) { |
724 | if (dev->drv->resume) | |
725 | dev->drv->resume(dev); | |
726 | } | |
a621aaed | 727 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
728 | return 0; |
729 | } | |
730 | ||
731 | static struct mcp_driver ucb1x00_driver = { | |
732 | .drv = { | |
733 | .name = "ucb1x00", | |
ddb1e04a | 734 | .owner = THIS_MODULE, |
05c45ca9 RK |
735 | }, |
736 | .probe = ucb1x00_probe, | |
737 | .remove = ucb1x00_remove, | |
738 | .suspend = ucb1x00_suspend, | |
739 | .resume = ucb1x00_resume, | |
740 | }; | |
741 | ||
742 | static int __init ucb1x00_init(void) | |
743 | { | |
744 | int ret = class_register(&ucb1x00_class); | |
745 | if (ret == 0) { | |
746 | ret = mcp_driver_register(&ucb1x00_driver); | |
747 | if (ret) | |
748 | class_unregister(&ucb1x00_class); | |
749 | } | |
750 | return ret; | |
751 | } | |
752 | ||
753 | static void __exit ucb1x00_exit(void) | |
754 | { | |
755 | mcp_driver_unregister(&ucb1x00_driver); | |
756 | class_unregister(&ucb1x00_class); | |
757 | } | |
758 | ||
759 | module_init(ucb1x00_init); | |
760 | module_exit(ucb1x00_exit); | |
761 | ||
05c45ca9 RK |
762 | EXPORT_SYMBOL(ucb1x00_io_set_dir); |
763 | EXPORT_SYMBOL(ucb1x00_io_write); | |
764 | EXPORT_SYMBOL(ucb1x00_io_read); | |
765 | ||
766 | EXPORT_SYMBOL(ucb1x00_adc_enable); | |
767 | EXPORT_SYMBOL(ucb1x00_adc_read); | |
768 | EXPORT_SYMBOL(ucb1x00_adc_disable); | |
769 | ||
770 | EXPORT_SYMBOL(ucb1x00_hook_irq); | |
771 | EXPORT_SYMBOL(ucb1x00_free_irq); | |
772 | EXPORT_SYMBOL(ucb1x00_enable_irq); | |
773 | EXPORT_SYMBOL(ucb1x00_disable_irq); | |
774 | ||
775 | EXPORT_SYMBOL(ucb1x00_register_driver); | |
776 | EXPORT_SYMBOL(ucb1x00_unregister_driver); | |
777 | ||
ddb1e04a | 778 | MODULE_ALIAS("mcp:ucb1x00"); |
05c45ca9 RK |
779 | MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>"); |
780 | MODULE_DESCRIPTION("UCB1x00 core driver"); | |
781 | MODULE_LICENSE("GPL"); |