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mfd: Add regmap cache support for wm8350
[deliverable/linux.git] / drivers / mfd / wm8350-core.c
CommitLineData
89b4012b
MB		 1/*
2 * wm8350-core.c -- Device access for Wolfson WM8350
3 *
4 * Copyright 2007, 2008 Wolfson Microelectronics PLC.
5 *
6 * Author: Liam Girdwood, Mark Brown
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/init.h>
5a0e3ad6 18#include <linux/slab.h>
ebccec0f 19#include <linux/bug.h>
89b4012b
MB		 20#include <linux/device.h>
21#include <linux/delay.h>
22#include <linux/interrupt.h>
b7b142d9 23#include <linux/regmap.h>
ebccec0f 24#include <linux/workqueue.h>
89b4012b
MB		 25
26#include <linux/mfd/wm8350/core.h>
27#include <linux/mfd/wm8350/audio.h>
ebccec0f 28#include <linux/mfd/wm8350/comparator.h>
89b4012b
MB		 29#include <linux/mfd/wm8350/gpio.h>
30#include <linux/mfd/wm8350/pmic.h>
ebccec0f 31#include <linux/mfd/wm8350/rtc.h>
89b4012b 32#include <linux/mfd/wm8350/supply.h>
ebccec0f 33#include <linux/mfd/wm8350/wdt.h>
89b4012b 34
89b4012b
MB		 35#define WM8350_CLOCK_CONTROL_1 0x28
36#define WM8350_AIF_TEST 0x74
37
38/* debug */
39#define WM8350_BUS_DEBUG 0
40#if WM8350_BUS_DEBUG
41#define dump(regs, src) do { \
42 int i_; \
43 u16 *src_ = src; \
44 printk(KERN_DEBUG); \
45 for (i_ = 0; i_ < regs; i_++) \
46 printk(" 0x%4.4x", *src_++); \
47 printk("\n"); \
48} while (0);
49#else
50#define dump(bytes, src)
51#endif
52
53#define WM8350_LOCK_DEBUG 0
54#if WM8350_LOCK_DEBUG
55#define ldbg(format, arg...) printk(format, ## arg)
56#else
57#define ldbg(format, arg...)
58#endif
59
60/*
61 * WM8350 Device IO
62 */
63static DEFINE_MUTEX(io_mutex);
64static DEFINE_MUTEX(reg_lock_mutex);
89b4012b
MB		 65
66/* Perform a physical read from the device.
67 */
68static int wm8350_phys_read(struct wm8350 *wm8350, u8 reg, int num_regs,
69 u16 *dest)
70{
71 int i, ret;
72 int bytes = num_regs * 2;
73
74 dev_dbg(wm8350->dev, "volatile read\n");
b7b142d9 75 ret = regmap_raw_read(wm8350->regmap, reg, dest, bytes);
89b4012b
MB		 76
77 for (i = reg; i < reg + num_regs; i++) {
78 /* Cache is CPU endian */
79 dest[i - reg] = be16_to_cpu(dest[i - reg]);
80
89b4012b
MB		 81 /* Mask out non-readable bits */
82 dest[i - reg] &= wm8350_reg_io_map[i].readable;
83 }
84
85 dump(num_regs, dest);
86
87 return ret;
88}
89
90static int wm8350_read(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *dest)
91{
92 int i;
93 int end = reg + num_regs;
94 int ret = 0;
95 int bytes = num_regs * 2;
96
89b4012b
MB		 97 if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) {
98 dev_err(wm8350->dev, "invalid reg %x\n",
99 reg + num_regs - 1);
100 return -EINVAL;
101 }
102
103 dev_dbg(wm8350->dev,
104 "%s R%d(0x%2.2x) %d regs\n", __func__, reg, reg, num_regs);
105
106#if WM8350_BUS_DEBUG
107 /* we can _safely_ read any register, but warn if read not supported */
108 for (i = reg; i < end; i++) {
109 if (!wm8350_reg_io_map[i].readable)
110 dev_warn(wm8350->dev,
111 "reg R%d is not readable\n", i);
112 }
113#endif
114
115 /* if any volatile registers are required, then read back all */
116 for (i = reg; i < end; i++)
117 if (wm8350_reg_io_map[i].vol)
118 return wm8350_phys_read(wm8350, reg, num_regs, dest);
119
120 /* no volatiles, then cache is good */
121 dev_dbg(wm8350->dev, "cache read\n");
122 memcpy(dest, &wm8350->reg_cache[reg], bytes);
123 dump(num_regs, dest);
124 return ret;
125}
126
127static inline int is_reg_locked(struct wm8350 *wm8350, u8 reg)
128{
129 if (reg == WM8350_SECURITY ||
130 wm8350->reg_cache[WM8350_SECURITY] == WM8350_UNLOCK_KEY)
131 return 0;
132
8e6ba2df 133 if ((reg >= WM8350_GPIO_FUNCTION_SELECT_1 &&
89b4012b
MB		 134 reg <= WM8350_GPIO_FUNCTION_SELECT_4) ||
135 (reg >= WM8350_BATTERY_CHARGER_CONTROL_1 &&
136 reg <= WM8350_BATTERY_CHARGER_CONTROL_3))
137 return 1;
138 return 0;
139}
140
141static int wm8350_write(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *src)
142{
143 int i;
144 int end = reg + num_regs;
145 int bytes = num_regs * 2;
146
89b4012b
MB		 147 if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) {
148 dev_err(wm8350->dev, "invalid reg %x\n",
149 reg + num_regs - 1);
150 return -EINVAL;
151 }
152
153 /* it's generally not a good idea to write to RO or locked registers */
154 for (i = reg; i < end; i++) {
155 if (!wm8350_reg_io_map[i].writable) {
156 dev_err(wm8350->dev,
157 "attempted write to read only reg R%d\n", i);
158 return -EINVAL;
159 }
160
161 if (is_reg_locked(wm8350, i)) {
162 dev_err(wm8350->dev,
163 "attempted write to locked reg R%d\n", i);
164 return -EINVAL;
165 }
166
167 src[i - reg] &= wm8350_reg_io_map[i].writable;
168
169 wm8350->reg_cache[i] =
170 (wm8350->reg_cache[i] & ~wm8350_reg_io_map[i].writable)
171 | src[i - reg];
172
173 src[i - reg] = cpu_to_be16(src[i - reg]);
174 }
175
176 /* Actually write it out */
b7b142d9 177 return regmap_raw_write(wm8350->regmap, reg, src, bytes);
89b4012b
MB		 178}
179
180/*
181 * Safe read, modify, write methods
182 */
183int wm8350_clear_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
184{
185 u16 data;
186 int err;
187
188 mutex_lock(&io_mutex);
189 err = wm8350_read(wm8350, reg, 1, &data);
190 if (err) {
191 dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
192 goto out;
193 }
194
195 data &= ~mask;
196 err = wm8350_write(wm8350, reg, 1, &data);
197 if (err)
198 dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
199out:
200 mutex_unlock(&io_mutex);
201 return err;
202}
203EXPORT_SYMBOL_GPL(wm8350_clear_bits);
204
205int wm8350_set_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
206{
207 u16 data;
208 int err;
209
210 mutex_lock(&io_mutex);
211 err = wm8350_read(wm8350, reg, 1, &data);
212 if (err) {
213 dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
214 goto out;
215 }
216
217 data |= mask;
218 err = wm8350_write(wm8350, reg, 1, &data);
219 if (err)
220 dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
221out:
222 mutex_unlock(&io_mutex);
223 return err;
224}
225EXPORT_SYMBOL_GPL(wm8350_set_bits);
226
227u16 wm8350_reg_read(struct wm8350 *wm8350, int reg)
228{
229 u16 data;
230 int err;
231
232 mutex_lock(&io_mutex);
233 err = wm8350_read(wm8350, reg, 1, &data);
234 if (err)
235 dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
236
237 mutex_unlock(&io_mutex);
238 return data;
239}
240EXPORT_SYMBOL_GPL(wm8350_reg_read);
241
242int wm8350_reg_write(struct wm8350 *wm8350, int reg, u16 val)
243{
244 int ret;
245 u16 data = val;
246
247 mutex_lock(&io_mutex);
248 ret = wm8350_write(wm8350, reg, 1, &data);
249 if (ret)
250 dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
251 mutex_unlock(&io_mutex);
252 return ret;
253}
254EXPORT_SYMBOL_GPL(wm8350_reg_write);
255
256int wm8350_block_read(struct wm8350 *wm8350, int start_reg, int regs,
257 u16 *dest)
258{
259 int err = 0;
260
261 mutex_lock(&io_mutex);
262 err = wm8350_read(wm8350, start_reg, regs, dest);
263 if (err)
264 dev_err(wm8350->dev, "block read starting from R%d failed\n",
265 start_reg);
266 mutex_unlock(&io_mutex);
267 return err;
268}
269EXPORT_SYMBOL_GPL(wm8350_block_read);
270
271int wm8350_block_write(struct wm8350 *wm8350, int start_reg, int regs,
272 u16 *src)
273{
274 int ret = 0;
275
276 mutex_lock(&io_mutex);
277 ret = wm8350_write(wm8350, start_reg, regs, src);
278 if (ret)
279 dev_err(wm8350->dev, "block write starting at R%d failed\n",
280 start_reg);
281 mutex_unlock(&io_mutex);
282 return ret;
283}
284EXPORT_SYMBOL_GPL(wm8350_block_write);
285
858e6744
MB		 286/**
287 * wm8350_reg_lock()
288 *
289 * The WM8350 has a hardware lock which can be used to prevent writes to
290 * some registers (generally those which can cause particularly serious
291 * problems if misused). This function enables that lock.
292 */
89b4012b
MB		 293int wm8350_reg_lock(struct wm8350 *wm8350)
294{
89b4012b
MB		 295 int ret;
296
52b461b8
MB		 297 mutex_lock(&reg_lock_mutex);
298
89b4012b 299 ldbg(__func__);
52b461b8
MB		 300
301 ret = wm8350_reg_write(wm8350, WM8350_SECURITY, WM8350_LOCK_KEY);
89b4012b
MB		 302 if (ret)
303 dev_err(wm8350->dev, "lock failed\n");
52b461b8
MB		 304
305 wm8350->unlocked = false;
306
307 mutex_unlock(&reg_lock_mutex);
308
89b4012b
MB		 309 return ret;
310}
311EXPORT_SYMBOL_GPL(wm8350_reg_lock);
312
858e6744
MB		 313/**
314 * wm8350_reg_unlock()
315 *
316 * The WM8350 has a hardware lock which can be used to prevent writes to
317 * some registers (generally those which can cause particularly serious
318 * problems if misused). This function disables that lock so updates
319 * can be performed. For maximum safety this should be done only when
320 * required.
321 */
89b4012b
MB		 322int wm8350_reg_unlock(struct wm8350 *wm8350)
323{
89b4012b
MB		 324 int ret;
325
52b461b8
MB		 326 mutex_lock(&reg_lock_mutex);
327
89b4012b 328 ldbg(__func__);
52b461b8
MB		 329
330 ret = wm8350_reg_write(wm8350, WM8350_SECURITY, WM8350_UNLOCK_KEY);
89b4012b
MB		 331 if (ret)
332 dev_err(wm8350->dev, "unlock failed\n");
52b461b8
MB		 333
334 wm8350->unlocked = true;
335
336 mutex_unlock(&reg_lock_mutex);
337
89b4012b
MB		 338 return ret;
339}
340EXPORT_SYMBOL_GPL(wm8350_reg_unlock);
341
67488526
MB		 342int wm8350_read_auxadc(struct wm8350 *wm8350, int channel, int scale, int vref)
343{
344 u16 reg, result = 0;
67488526
MB		 345
346 if (channel < WM8350_AUXADC_AUX1 || channel > WM8350_AUXADC_TEMP)
347 return -EINVAL;
348 if (channel >= WM8350_AUXADC_USB && channel <= WM8350_AUXADC_TEMP
349 && (scale != 0 || vref != 0))
350 return -EINVAL;
351
352 mutex_lock(&wm8350->auxadc_mutex);
353
354 /* Turn on the ADC */
355 reg = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_5);
356 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_5, reg | WM8350_AUXADC_ENA);
357
358 if (scale || vref) {
359 reg = scale << 13;
360 reg |= vref << 12;
361 wm8350_reg_write(wm8350, WM8350_AUX1_READBACK + channel, reg);
362 }
363
364 reg = wm8350_reg_read(wm8350, WM8350_DIGITISER_CONTROL_1);
365 reg |= 1 << channel | WM8350_AUXADC_POLL;
366 wm8350_reg_write(wm8350, WM8350_DIGITISER_CONTROL_1, reg);
367
5051d411
MB		 368 /* If a late IRQ left the completion signalled then consume
369 * the completion. */
370 try_wait_for_completion(&wm8350->auxadc_done);
371
d19663ac
MB		 372 /* We ignore the result of the completion and just check for a
373 * conversion result, allowing us to soldier on if the IRQ
374 * infrastructure is not set up for the chip. */
375 wait_for_completion_timeout(&wm8350->auxadc_done, msecs_to_jiffies(5));
67488526 376
d19663ac
MB		 377 reg = wm8350_reg_read(wm8350, WM8350_DIGITISER_CONTROL_1);
378 if (reg & WM8350_AUXADC_POLL)
67488526
MB		 379 dev_err(wm8350->dev, "adc chn %d read timeout\n", channel);
380 else
381 result = wm8350_reg_read(wm8350,
382 WM8350_AUX1_READBACK + channel);
383
384 /* Turn off the ADC */
385 reg = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_5);
386 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_5,
387 reg & ~WM8350_AUXADC_ENA);
388
389 mutex_unlock(&wm8350->auxadc_mutex);
390
391 return result & WM8350_AUXADC_DATA1_MASK;
392}
393EXPORT_SYMBOL_GPL(wm8350_read_auxadc);
394
d19663ac
MB		 395static irqreturn_t wm8350_auxadc_irq(int irq, void *irq_data)
396{
397 struct wm8350 *wm8350 = irq_data;
398
399 complete(&wm8350->auxadc_done);
400
401 return IRQ_HANDLED;
402}
403
89b4012b
MB		 404/*
405 * Cache is always host endian.
406 */
96920630 407static int wm8350_create_cache(struct wm8350 *wm8350, int type, int mode)
89b4012b
MB		 408{
409 int i, ret = 0;
410 u16 value;
411 const u16 *reg_map;
412
96920630 413 switch (type) {
89b4012b 414 case 0:
96920630
MB		 415 switch (mode) {
416#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_0
417 case 0:
418 reg_map = wm8350_mode0_defaults;
419 break;
89b4012b
MB		 420#endif
421#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_1
96920630
MB		 422 case 1:
423 reg_map = wm8350_mode1_defaults;
424 break;
89b4012b
MB		 425#endif
426#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_2
96920630
MB		 427 case 2:
428 reg_map = wm8350_mode2_defaults;
429 break;
89b4012b
MB		 430#endif
431#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_3
96920630
MB		 432 case 3:
433 reg_map = wm8350_mode3_defaults;
434 break;
89b4012b 435#endif
96920630
MB		 436 default:
437 dev_err(wm8350->dev,
438 "WM8350 configuration mode %d not supported\n",
439 mode);
440 return -EINVAL;
441 }
4331bb32 442 break;
96920630 443
ca23f8c1
MB		 444 case 1:
445 switch (mode) {
446#ifdef CONFIG_MFD_WM8351_CONFIG_MODE_0
447 case 0:
448 reg_map = wm8351_mode0_defaults;
449 break;
450#endif
451#ifdef CONFIG_MFD_WM8351_CONFIG_MODE_1
452 case 1:
453 reg_map = wm8351_mode1_defaults;
454 break;
455#endif
456#ifdef CONFIG_MFD_WM8351_CONFIG_MODE_2
457 case 2:
458 reg_map = wm8351_mode2_defaults;
459 break;
460#endif
461#ifdef CONFIG_MFD_WM8351_CONFIG_MODE_3
462 case 3:
463 reg_map = wm8351_mode3_defaults;
464 break;
465#endif
466 default:
467 dev_err(wm8350->dev,
468 "WM8351 configuration mode %d not supported\n",
469 mode);
470 return -EINVAL;
471 }
472 break;
473
96920630
MB		 474 case 2:
475 switch (mode) {
476#ifdef CONFIG_MFD_WM8352_CONFIG_MODE_0
477 case 0:
478 reg_map = wm8352_mode0_defaults;
479 break;
480#endif
481#ifdef CONFIG_MFD_WM8352_CONFIG_MODE_1
482 case 1:
483 reg_map = wm8352_mode1_defaults;
484 break;
485#endif
486#ifdef CONFIG_MFD_WM8352_CONFIG_MODE_2
487 case 2:
488 reg_map = wm8352_mode2_defaults;
489 break;
490#endif
491#ifdef CONFIG_MFD_WM8352_CONFIG_MODE_3
492 case 3:
493 reg_map = wm8352_mode3_defaults;
494 break;
495#endif
496 default:
497 dev_err(wm8350->dev,
498 "WM8352 configuration mode %d not supported\n",
499 mode);
500 return -EINVAL;
501 }
502 break;
503
89b4012b 504 default:
96920630
MB		 505 dev_err(wm8350->dev,
506 "WM835x configuration mode %d not supported\n",
89b4012b
MB		 507 mode);
508 return -EINVAL;
509 }
510
511 wm8350->reg_cache =
9dfd3381 512 kmalloc(sizeof(u16) * (WM8350_MAX_REGISTER + 1), GFP_KERNEL);
89b4012b
MB		 513 if (wm8350->reg_cache == NULL)
514 return -ENOMEM;
515
516 /* Read the initial cache state back from the device - this is
517 * a PMIC so the device many not be in a virgin state and we
518 * can't rely on the silicon values.
519 */
b7b142d9
MB		 520 ret = regmap_raw_read(wm8350->regmap, 0, wm8350->reg_cache,
521 sizeof(u16) * (WM8350_MAX_REGISTER + 1));
9dfd3381
MB		 522 if (ret < 0) {
523 dev_err(wm8350->dev,
524 "failed to read initial cache values\n");
525 goto out;
526 }
527
528 /* Mask out uncacheable/unreadable bits and the audio. */
89b4012b 529 for (i = 0; i < WM8350_MAX_REGISTER; i++) {
89b4012b
MB		 530 if (wm8350_reg_io_map[i].readable &&
531 (i < WM8350_CLOCK_CONTROL_1 || i > WM8350_AIF_TEST)) {
9dfd3381 532 value = be16_to_cpu(wm8350->reg_cache[i]);
89b4012b
MB		 533 value &= wm8350_reg_io_map[i].readable;
534 wm8350->reg_cache[i] = value;
535 } else
536 wm8350->reg_cache[i] = reg_map[i];
537 }
538
539out:
8c46cf30 540 kfree(wm8350->reg_cache);
89b4012b
MB		 541 return ret;
542}
89b4012b 543
9201d38b
MB		 544/*
545 * Register a client device. This is non-fatal since there is no need to
546 * fail the entire device init due to a single platform device failing.
547 */
548static void wm8350_client_dev_register(struct wm8350 *wm8350,
549 const char *name,
550 struct platform_device **pdev)
551{
552 int ret;
553
554 *pdev = platform_device_alloc(name, -1);
cb9b2245 555 if (*pdev == NULL) {
9201d38b
MB		 556 dev_err(wm8350->dev, "Failed to allocate %s\n", name);
557 return;
558 }
559
560 (*pdev)->dev.parent = wm8350->dev;
561 platform_set_drvdata(*pdev, wm8350);
562 ret = platform_device_add(*pdev);
563 if (ret != 0) {
564 dev_err(wm8350->dev, "Failed to register %s: %d\n", name, ret);
565 platform_device_put(*pdev);
566 *pdev = NULL;
567 }
568}
569
ebccec0f 570int wm8350_device_init(struct wm8350 *wm8350, int irq,
bcdd4efc 571 struct wm8350_platform_data *pdata)
89b4012b 572{
85c93ea7 573 int ret;
b7b142d9
MB		 574 unsigned int id1, id2, mask_rev;
575 unsigned int cust_id, mode, chip_rev;
89b4012b 576
18bf50a3
MB		 577 dev_set_drvdata(wm8350->dev, wm8350);
578
89b4012b 579 /* get WM8350 revision and config mode */
b7b142d9 580 ret = regmap_read(wm8350->regmap, WM8350_RESET_ID, &id1);
85c93ea7
MB		 581 if (ret != 0) {
582 dev_err(wm8350->dev, "Failed to read ID: %d\n", ret);
583 goto err;
584 }
585
b7b142d9 586 ret = regmap_read(wm8350->regmap, WM8350_ID, &id2);
85c93ea7
MB		 587 if (ret != 0) {
588 dev_err(wm8350->dev, "Failed to read ID: %d\n", ret);
589 goto err;
590 }
591
b7b142d9 592 ret = regmap_read(wm8350->regmap, WM8350_REVISION, &mask_rev);
85c93ea7
MB		 593 if (ret != 0) {
594 dev_err(wm8350->dev, "Failed to read revision: %d\n", ret);
595 goto err;
596 }
89b4012b 597
b797a555
MB		 598 if (id1 != 0x6143) {
599 dev_err(wm8350->dev,
600 "Device with ID %x is not a WM8350\n", id1);
601 ret = -ENODEV;
602 goto err;
603 }
604
605 mode = id2 & WM8350_CONF_STS_MASK >> 10;
606 cust_id = id2 & WM8350_CUST_ID_MASK;
607 chip_rev = (id2 & WM8350_CHIP_REV_MASK) >> 12;
608 dev_info(wm8350->dev,
609 "CONF_STS %d, CUST_ID %d, MASK_REV %d, CHIP_REV %d\n",
610 mode, cust_id, mask_rev, chip_rev);
611
612 if (cust_id != 0) {
613 dev_err(wm8350->dev, "Unsupported CUST_ID\n");
614 ret = -ENODEV;
615 goto err;
616 }
617
618 switch (mask_rev) {
619 case 0:
645524a9
MB		 620 wm8350->pmic.max_dcdc = WM8350_DCDC_6;
621 wm8350->pmic.max_isink = WM8350_ISINK_B;
622
b797a555 623 switch (chip_rev) {
89b4012b 624 case WM8350_REV_E:
b797a555 625 dev_info(wm8350->dev, "WM8350 Rev E\n");
89b4012b
MB		 626 break;
627 case WM8350_REV_F:
b797a555 628 dev_info(wm8350->dev, "WM8350 Rev F\n");
89b4012b
MB		 629 break;
630 case WM8350_REV_G:
b797a555 631 dev_info(wm8350->dev, "WM8350 Rev G\n");
d756f4a4 632 wm8350->power.rev_g_coeff = 1;
89b4012b 633 break;
0c8a6016 634 case WM8350_REV_H:
b797a555 635 dev_info(wm8350->dev, "WM8350 Rev H\n");
d756f4a4 636 wm8350->power.rev_g_coeff = 1;
0c8a6016 637 break;
89b4012b
MB		 638 default:
639 /* For safety we refuse to run on unknown hardware */
b797a555 640 dev_err(wm8350->dev, "Unknown WM8350 CHIP_REV\n");
89b4012b
MB		 641 ret = -ENODEV;
642 goto err;
643 }
b797a555
MB		 644 break;
645
ca23f8c1
MB		 646 case 1:
647 wm8350->pmic.max_dcdc = WM8350_DCDC_4;
648 wm8350->pmic.max_isink = WM8350_ISINK_A;
649
650 switch (chip_rev) {
651 case 0:
652 dev_info(wm8350->dev, "WM8351 Rev A\n");
653 wm8350->power.rev_g_coeff = 1;
654 break;
655
02d46e07
MB		 656 case 1:
657 dev_info(wm8350->dev, "WM8351 Rev B\n");
658 wm8350->power.rev_g_coeff = 1;
659 break;
660
ca23f8c1
MB		 661 default:
662 dev_err(wm8350->dev, "Unknown WM8351 CHIP_REV\n");
663 ret = -ENODEV;
664 goto err;
665 }
666 break;
667
96920630 668 case 2:
645524a9
MB		 669 wm8350->pmic.max_dcdc = WM8350_DCDC_6;
670 wm8350->pmic.max_isink = WM8350_ISINK_B;
671
96920630
MB		 672 switch (chip_rev) {
673 case 0:
674 dev_info(wm8350->dev, "WM8352 Rev A\n");
675 wm8350->power.rev_g_coeff = 1;
676 break;
677
678 default:
679 dev_err(wm8350->dev, "Unknown WM8352 CHIP_REV\n");
680 ret = -ENODEV;
681 goto err;
682 }
683 break;
684
b797a555
MB		 685 default:
686 dev_err(wm8350->dev, "Unknown MASK_REV\n");
89b4012b
MB		 687 ret = -ENODEV;
688 goto err;
689 }
690
96920630 691 ret = wm8350_create_cache(wm8350, mask_rev, mode);
89b4012b 692 if (ret < 0) {
b797a555 693 dev_err(wm8350->dev, "Failed to create register cache\n");
89b4012b
MB		 694 return ret;
695 }
696
67488526 697 mutex_init(&wm8350->auxadc_mutex);
d19663ac 698 init_completion(&wm8350->auxadc_done);
32064503 699
e0a3389a
MB		 700 ret = wm8350_irq_init(wm8350, irq, pdata);
701 if (ret < 0)
8c46cf30 702 goto err_free;
ebccec0f 703
d19663ac
MB		 704 if (wm8350->irq_base) {
705 ret = request_threaded_irq(wm8350->irq_base +
706 WM8350_IRQ_AUXADC_DATARDY,
707 NULL, wm8350_auxadc_irq, 0,
708 "auxadc", wm8350);
709 if (ret < 0)
710 dev_warn(wm8350->dev,
711 "Failed to request AUXADC IRQ: %d\n", ret);
712 }
713
62571c29
MB		 714 if (pdata && pdata->init) {
715 ret = pdata->init(wm8350);
716 if (ret != 0) {
717 dev_err(wm8350->dev, "Platform init() failed: %d\n",
718 ret);
e0a3389a 719 goto err_irq;
62571c29
MB		 720 }
721 }
722
ebccec0f
MB		 723 wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0x0);
724
add41cb4
MB		 725 wm8350_client_dev_register(wm8350, "wm8350-codec",
726 &(wm8350->codec.pdev));
727 wm8350_client_dev_register(wm8350, "wm8350-gpio",
728 &(wm8350->gpio.pdev));
fb6c023a
MB		 729 wm8350_client_dev_register(wm8350, "wm8350-hwmon",
730 &(wm8350->hwmon.pdev));
add41cb4
MB		 731 wm8350_client_dev_register(wm8350, "wm8350-power",
732 &(wm8350->power.pdev));
733 wm8350_client_dev_register(wm8350, "wm8350-rtc", &(wm8350->rtc.pdev));
734 wm8350_client_dev_register(wm8350, "wm8350-wdt", &(wm8350->wdt.pdev));
735
89b4012b
MB		 736 return 0;
737
e0a3389a
MB		 738err_irq:
739 wm8350_irq_exit(wm8350);
8c46cf30 740err_free:
89b4012b 741 kfree(wm8350->reg_cache);
8c46cf30 742err:
89b4012b
MB		 743 return ret;
744}
745EXPORT_SYMBOL_GPL(wm8350_device_init);
746
747void wm8350_device_exit(struct wm8350 *wm8350)
748{
da09155a
MB		 749 int i;
750
0081e802
MB		 751 for (i = 0; i < ARRAY_SIZE(wm8350->pmic.led); i++)
752 platform_device_unregister(wm8350->pmic.led[i].pdev);
753
da09155a 754 for (i = 0; i < ARRAY_SIZE(wm8350->pmic.pdev); i++)
add41cb4
MB		 755 platform_device_unregister(wm8350->pmic.pdev[i]);
756
757 platform_device_unregister(wm8350->wdt.pdev);
758 platform_device_unregister(wm8350->rtc.pdev);
759 platform_device_unregister(wm8350->power.pdev);
fb6c023a 760 platform_device_unregister(wm8350->hwmon.pdev);
add41cb4
MB		 761 platform_device_unregister(wm8350->gpio.pdev);
762 platform_device_unregister(wm8350->codec.pdev);
da09155a 763
d19663ac
MB		 764 if (wm8350->irq_base)
765 free_irq(wm8350->irq_base + WM8350_IRQ_AUXADC_DATARDY, wm8350);
766
e0a3389a
MB		 767 wm8350_irq_exit(wm8350);
768
89b4012b
MB		 769 kfree(wm8350->reg_cache);
770}
771EXPORT_SYMBOL_GPL(wm8350_device_exit);
772
ebccec0f 773MODULE_DESCRIPTION("WM8350 AudioPlus PMIC core driver");
89b4012b 774MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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