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c9fbf7e0 MB |
1 | /* |
2 | * wm8994-irq.c -- Interrupt controller support for Wolfson WM8994 | |
3 | * | |
4 | * Copyright 2010 Wolfson Microelectronics PLC. | |
5 | * | |
6 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | */ | |
14 | ||
15 | #include <linux/kernel.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/irq.h> | |
19 | #include <linux/mfd/core.h> | |
20 | #include <linux/interrupt.h> | |
8ab30691 | 21 | #include <linux/regmap.h> |
c9fbf7e0 MB |
22 | |
23 | #include <linux/mfd/wm8994/core.h> | |
b0ab907d | 24 | #include <linux/mfd/wm8994/pdata.h> |
c9fbf7e0 MB |
25 | #include <linux/mfd/wm8994/registers.h> |
26 | ||
27 | #include <linux/delay.h> | |
28 | ||
8ab30691 | 29 | static struct regmap_irq wm8994_irqs[] = { |
c9fbf7e0 | 30 | [WM8994_IRQ_TEMP_SHUT] = { |
8ab30691 | 31 | .reg_offset = 1, |
c9fbf7e0 MB |
32 | .mask = WM8994_TEMP_SHUT_EINT, |
33 | }, | |
34 | [WM8994_IRQ_MIC1_DET] = { | |
8ab30691 | 35 | .reg_offset = 1, |
c9fbf7e0 MB |
36 | .mask = WM8994_MIC1_DET_EINT, |
37 | }, | |
38 | [WM8994_IRQ_MIC1_SHRT] = { | |
8ab30691 | 39 | .reg_offset = 1, |
c9fbf7e0 MB |
40 | .mask = WM8994_MIC1_SHRT_EINT, |
41 | }, | |
42 | [WM8994_IRQ_MIC2_DET] = { | |
8ab30691 | 43 | .reg_offset = 1, |
c9fbf7e0 MB |
44 | .mask = WM8994_MIC2_DET_EINT, |
45 | }, | |
46 | [WM8994_IRQ_MIC2_SHRT] = { | |
8ab30691 | 47 | .reg_offset = 1, |
c9fbf7e0 MB |
48 | .mask = WM8994_MIC2_SHRT_EINT, |
49 | }, | |
50 | [WM8994_IRQ_FLL1_LOCK] = { | |
8ab30691 | 51 | .reg_offset = 1, |
c9fbf7e0 MB |
52 | .mask = WM8994_FLL1_LOCK_EINT, |
53 | }, | |
54 | [WM8994_IRQ_FLL2_LOCK] = { | |
8ab30691 | 55 | .reg_offset = 1, |
c9fbf7e0 MB |
56 | .mask = WM8994_FLL2_LOCK_EINT, |
57 | }, | |
58 | [WM8994_IRQ_SRC1_LOCK] = { | |
8ab30691 | 59 | .reg_offset = 1, |
c9fbf7e0 MB |
60 | .mask = WM8994_SRC1_LOCK_EINT, |
61 | }, | |
62 | [WM8994_IRQ_SRC2_LOCK] = { | |
8ab30691 | 63 | .reg_offset = 1, |
c9fbf7e0 MB |
64 | .mask = WM8994_SRC2_LOCK_EINT, |
65 | }, | |
66 | [WM8994_IRQ_AIF1DRC1_SIG_DET] = { | |
8ab30691 | 67 | .reg_offset = 1, |
c9fbf7e0 MB |
68 | .mask = WM8994_AIF1DRC1_SIG_DET, |
69 | }, | |
70 | [WM8994_IRQ_AIF1DRC2_SIG_DET] = { | |
8ab30691 | 71 | .reg_offset = 1, |
c9fbf7e0 MB |
72 | .mask = WM8994_AIF1DRC2_SIG_DET_EINT, |
73 | }, | |
74 | [WM8994_IRQ_AIF2DRC_SIG_DET] = { | |
8ab30691 | 75 | .reg_offset = 1, |
c9fbf7e0 MB |
76 | .mask = WM8994_AIF2DRC_SIG_DET_EINT, |
77 | }, | |
78 | [WM8994_IRQ_FIFOS_ERR] = { | |
8ab30691 | 79 | .reg_offset = 1, |
c9fbf7e0 MB |
80 | .mask = WM8994_FIFOS_ERR_EINT, |
81 | }, | |
82 | [WM8994_IRQ_WSEQ_DONE] = { | |
8ab30691 | 83 | .reg_offset = 1, |
c9fbf7e0 MB |
84 | .mask = WM8994_WSEQ_DONE_EINT, |
85 | }, | |
86 | [WM8994_IRQ_DCS_DONE] = { | |
8ab30691 | 87 | .reg_offset = 1, |
c9fbf7e0 MB |
88 | .mask = WM8994_DCS_DONE_EINT, |
89 | }, | |
90 | [WM8994_IRQ_TEMP_WARN] = { | |
8ab30691 | 91 | .reg_offset = 1, |
c9fbf7e0 MB |
92 | .mask = WM8994_TEMP_WARN_EINT, |
93 | }, | |
94 | [WM8994_IRQ_GPIO(1)] = { | |
c9fbf7e0 MB |
95 | .mask = WM8994_GP1_EINT, |
96 | }, | |
97 | [WM8994_IRQ_GPIO(2)] = { | |
c9fbf7e0 MB |
98 | .mask = WM8994_GP2_EINT, |
99 | }, | |
100 | [WM8994_IRQ_GPIO(3)] = { | |
c9fbf7e0 MB |
101 | .mask = WM8994_GP3_EINT, |
102 | }, | |
103 | [WM8994_IRQ_GPIO(4)] = { | |
c9fbf7e0 MB |
104 | .mask = WM8994_GP4_EINT, |
105 | }, | |
106 | [WM8994_IRQ_GPIO(5)] = { | |
c9fbf7e0 MB |
107 | .mask = WM8994_GP5_EINT, |
108 | }, | |
109 | [WM8994_IRQ_GPIO(6)] = { | |
c9fbf7e0 MB |
110 | .mask = WM8994_GP6_EINT, |
111 | }, | |
112 | [WM8994_IRQ_GPIO(7)] = { | |
c9fbf7e0 MB |
113 | .mask = WM8994_GP7_EINT, |
114 | }, | |
115 | [WM8994_IRQ_GPIO(8)] = { | |
c9fbf7e0 MB |
116 | .mask = WM8994_GP8_EINT, |
117 | }, | |
118 | [WM8994_IRQ_GPIO(9)] = { | |
c9fbf7e0 MB |
119 | .mask = WM8994_GP8_EINT, |
120 | }, | |
121 | [WM8994_IRQ_GPIO(10)] = { | |
c9fbf7e0 MB |
122 | .mask = WM8994_GP10_EINT, |
123 | }, | |
124 | [WM8994_IRQ_GPIO(11)] = { | |
c9fbf7e0 MB |
125 | .mask = WM8994_GP11_EINT, |
126 | }, | |
127 | }; | |
128 | ||
8ab30691 MB |
129 | static struct regmap_irq_chip wm8994_irq_chip = { |
130 | .name = "wm8994", | |
131 | .irqs = wm8994_irqs, | |
132 | .num_irqs = ARRAY_SIZE(wm8994_irqs), | |
c9fbf7e0 | 133 | |
8ab30691 MB |
134 | .num_regs = 2, |
135 | .status_base = WM8994_INTERRUPT_STATUS_1, | |
136 | .mask_base = WM8994_INTERRUPT_STATUS_1_MASK, | |
137 | .ack_base = WM8994_INTERRUPT_STATUS_1, | |
7a976379 | 138 | .runtime_pm = true, |
c9fbf7e0 MB |
139 | }; |
140 | ||
c9fbf7e0 MB |
141 | int wm8994_irq_init(struct wm8994 *wm8994) |
142 | { | |
8ab30691 | 143 | int ret; |
b0ab907d MB |
144 | unsigned long irqflags; |
145 | struct wm8994_pdata *pdata = wm8994->dev->platform_data; | |
c9fbf7e0 MB |
146 | |
147 | if (!wm8994->irq) { | |
148 | dev_warn(wm8994->dev, | |
149 | "No interrupt specified, no interrupts\n"); | |
150 | wm8994->irq_base = 0; | |
151 | return 0; | |
152 | } | |
153 | ||
b0ab907d MB |
154 | /* select user or default irq flags */ |
155 | irqflags = IRQF_TRIGGER_HIGH | IRQF_ONESHOT; | |
156 | if (pdata->irq_flags) | |
157 | irqflags = pdata->irq_flags; | |
158 | ||
8ab30691 | 159 | ret = regmap_add_irq_chip(wm8994->regmap, wm8994->irq, |
b0ab907d | 160 | irqflags, |
8ab30691 MB |
161 | wm8994->irq_base, &wm8994_irq_chip, |
162 | &wm8994->irq_data); | |
c9fbf7e0 | 163 | if (ret != 0) { |
8ab30691 | 164 | dev_err(wm8994->dev, "Failed to register IRQ chip: %d\n", ret); |
c9fbf7e0 MB |
165 | return ret; |
166 | } | |
167 | ||
168 | /* Enable top level interrupt if it was masked */ | |
169 | wm8994_reg_write(wm8994, WM8994_INTERRUPT_CONTROL, 0); | |
170 | ||
171 | return 0; | |
172 | } | |
173 | ||
174 | void wm8994_irq_exit(struct wm8994 *wm8994) | |
175 | { | |
8ab30691 | 176 | regmap_del_irq_chip(wm8994->irq, wm8994->irq_data); |
c9fbf7e0 | 177 | } |